18th week of 2011 patent applcation highlights part 19 |
Patent application number | Title | Published |
20110101476 | ELECTRONIC DEVICE, MEMORY DEVICE, AND METHOD OF FABRICATING THE SAME - Provided are an electronic device, a memory device, and a method of fabricating the devices for preventing physical distortion of functional elements from generating and improving electric contact properties between the functional elements and electric elements connecting to the functional elements. At least two grooves are formed in a substrate, and a conductive material is filled in the grooves to obtain electric elements having a surface at the same height as that of the substrate. In addition, a functional material layer (functional layer) is formed on an entire upper surface of the substrate and is patterned so as to obtain a functional element having both bottom surfaces contacting the electric elements. | 2011-05-05 |
20110101477 | Method for manufacturing magnetic field detection devices and devices therefrom - A method for manufacturing magnetic field detection devices comprises the operations of manufacturing a magneto-resistive element comprising regions with metallic conduction and regions with semi-conductive conduction. The method comprises the following operations: forming metallic nano-particles to obtain regions with metallic conduction; providing a semiconductor substrate; and applying metallic nano-particles to the porous semiconductor substrate to obtain a disordered mesoscopic structure. A magnetic device comprises a spin valve, which comprises a plurality of layers arranged in a stack which in turn comprises at least one free magnetic layer able to be associated to a temporary magnetisation (MT), a spacer layer and a permanent magnetic layer associated to a permanent magnetisation (MP). The spacer element is obtained by means of a mesoscopic structure of nanoparticles in a metallic matrix produced in accordance with the inventive method for manufacturing magneto-resistive elements. | 2011-05-05 |
20110101478 | High density spin-transfer torque MRAM process - A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden. | 2011-05-05 |
20110101479 | PHOTOVOLTAIC DEVICE INCLUDING SEMICONDUCTOR NANOCRYSTALS - A photovoltaic device includes a semiconductor nanocrystal and a charge transporting layer that includes an inorganic material. The charge transporting layer can be a hole or electron transporting layer. The inorganic material can be an inorganic semiconductor. | 2011-05-05 |
20110101480 | COMPACT CAMERA MODULE AND METHOD FOR FABRICATING THE SAME - A compact camera module (CCM) includes an image sensor, a lens unit and a specific filter glass unit. The image sensor is used for sensing an image. The lens unit is used for guiding light beams toward the image sensor. The specific filter glass unit is implemented external to the lens unit and has the image sensor and the lens unit disposed on opposite sides of the specific filter glass unit, for filtering out a specific light of the light beams. | 2011-05-05 |
20110101481 | Photodetector Array Having Array of Discrete Electron Repulsive Elements - Photodetector arrays, image sensors, and other apparatus are disclosed. In one aspect, an apparatus may include a surface to receive light, a plurality of photosensitive regions disposed within a substrate, and a material coupled between the surface and the plurality of photosensitive regions. The material may receive the light. At least some of the light may free electrons in the material. The apparatus may also include a plurality of discrete electron repulsive elements. The discrete electron repulsive elements may be coupled between the surface and the material. Each of the discrete electron repulsive elements may correspond to a different photosensitive region. Each of the discrete electron repulsive elements may repel electrons in the material toward a corresponding photosensitive region. Other apparatus are also disclosed, as are methods of use, methods of fabrication, and systems incorporating such apparatus. | 2011-05-05 |
20110101482 | METHOD OF MANUFACTURE OF A BACKSIDE ILLUMINATED IMAGE SENSOR - A method of manufacturing a backside illuminated image sensor includes providing a start material that has a layer of semiconductor material on a substrate. The layer of semiconductor material has a first face and a second, backside, face. The layer of semiconductor material is processed to form semiconductor devices in the layer adjacent the first face. At least a part of the substrate is removed to leave an exposed face. A passivation layer is formed on the exposed face, the passivation layer having negative fixed charges. The passivation layer can be Al2O3 (Sapphire). The passivation layer can have a thickness less than 5 μm, advantageously less than 1 μm, and more advantageously in the range 1 nm-150 nm. Another layer, or layers, can be provided on the passivation layer, including: an anti-reflective layer, a layer to improve passivation, a layer including a color filter pattern, a layer comprising a microlens. | 2011-05-05 |
20110101483 | TWO COLOUR PHOTON DETECTOR - A two-colour radiation detector ( | 2011-05-05 |
20110101484 | LIGHT-RECEIVING DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a device including at least one light-receiving unit | 2011-05-05 |
20110101485 | Detector for Plastic Optical Fiber Networks - An apparatus comprises a substrate having a type of conductivity, an intrinsic region above the substrate, and a metal layer on a portion of the surface of the intrinsic region. The intrinsic region has a surface. The metal layer may have a thickness that is configured to allow a plurality of photons to pass through the metal layer into the intrinsic region and form a rectifying contact with the intrinsic region. | 2011-05-05 |
20110101486 | BIPOLAR TRANSISTOR - A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation. | 2011-05-05 |
20110101487 | CRACK RESISTANT CIRCUIT UNDER PAD STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A circuit under pad structure includes a substrate, a pad electrode, wiring layers interlayer insulation layers alternately disposed between the pad electrode and the substrate, and at least one circuit pattern integral with the substrate, disposed beneath the lowermost wiring layer and spanned by the pad electrode. The width of each wiring layer is smaller than the width of the wiring layer beneath it, i.e., closer to the substrate. The structure is fabricated such that it resists cracking, which maximizes its production yield, and possesses a minimal footprint. | 2011-05-05 |
20110101488 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device includes: providing a substrate; forming a plurality of trenches by etching the substrate; forming a first isolation layer by filling the plurality of the trenches with a first insulation layer; recessing the first insulation layer filling a first group of the plurality of the trenches to a predetermined depth; forming a liner layer over the first group of the trenches with the first insulation layer recessed to the predetermined depth; and forming a second isolation layer by filling the first group of the trenches, where the liner layer is formed, with a second insulation layer. | 2011-05-05 |
20110101489 | SiCOH DIELECTRIC MATERIAL WITH IMPROVED TOUGHNESS AND IMPROVED Si-C BONDING, SEMICONDUCTOR DEVICE CONTAINING THE SAME, AND METHOD TO MAKE THE SAME - A low-k dielectric material with increased cohesive strength for use in electronic structures including interconnect and sensing structures is provided that includes atoms of Si, C, O, and H in which a fraction of the C atoms are bonded as Si—CH | 2011-05-05 |
20110101490 | CONTOURED INSULATOR LAYER OF SILICON-ON-INSULATOR WAFERS AND PROCESS OF MANUFACTURE - A silicon-on-insulator wafer. The SOI wafer comprises a top silicon layer, a silicon substrate, and an oxide insulator layer disposed across the wafer and between the silicon substrate and the top silicon layer. The oxide insulator layer has at least one of a contoured top surface and a contoured bottom surface. Also provided are processes for manufacturing such a SOI wafer. | 2011-05-05 |
20110101491 | INTEGRATED CIRCUIT PACKAGES INCLUDING HIGH DENSITY BUMP-LESS BUILD UP LAYERS AND A LESSER DENSITY CORE OR CORELESS SUBSTRATE - In some embodiments, integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate are presented. In this regard, an apparatus is introduced having a first element including a microelectronic die having an active surface and at least one side, an encapsulation material adjacent said at least one microelectronic die side, wherein said encapsulation material includes at least one surface substantially planar to said microelectronic die active surface, a first dielectric material layer disposed on at least a portion of said microelectronic die active surface and said encapsulation material surface, a plurality of build-up layers disposed on said first dielectric material layer, and a plurality of conductive traces disposed on said first dielectric material layer and said build-up layers and in electrical contact with said microelectronic die active surface; and a second element coupled to the first element, the second element including a substrate having a plurality of dielectric material layers and conductive traces to conductively couple conductive contacts on a top surface with conductive contacts on a bottom surface, said conductive contacts on said top surface conductively coupled with said conductive traces of said first element. Other embodiments are also disclosed and claimed. | 2011-05-05 |
20110101492 | SEMICONDUCTOR DEVICE HAVING THERMALLY FORMED AIR GAP IN WIRING LAYER AND METHOD OF FABRICATING SAME - A semiconductor device is provided. A unit wiring level of the semiconductor device includes; first and second wiring layers spaced apart from each other on a support layer, a large space formed adjacent to the first wiring layer and including a first air gap of predetermined width as measured from a sidewall of the first wiring layer, and a portion of a thermally degradable material layer formed on the support layer, small space formed between the first and second wiring layers, wherein the small space is smaller than the large space, and a second air gap at least partially fills the small space, and a porous insulating layer formed on the first and second air gaps. | 2011-05-05 |
20110101493 | Electrical Fuse Structure and Method of Formation - An embodiment is a fuse structure. In accordance with an embodiment, a fuse structure comprises an anode, a cathode, a fuse link interposed between the anode and the cathode, and cathode connectors coupled to the cathode. The cathode connectors are each equivalent to or larger than about two times a minimum feature size of a contact that couples to an active device. | 2011-05-05 |
20110101494 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a first bit line contact pattern coupled to a region of a word line conductive layer; a first bit line conductive pattern coupled to the first bit line contact pattern; a first metal interconnection contact pattern coupled to the first bit line conductive pattern; a fuse having a side coupled to the first metal interconnection contact pattern; a second bit line contact pattern coupled to another region of the word line conductive layer; a second bit line conductive pattern coupled to the second bit line contact pattern; a second metal interconnection contact pattern coupled to the second bit line conductive pattern; and a first guard ring metal layer disposed on the same layer as the first and second metal interconnection contact patterns and between the first and second metal interconnection contact patterns and disposed as a layer surrounding the fuse. | 2011-05-05 |
20110101495 | FUSE BOX FOR SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME - A fuse box for a semiconductor device is disclosed and includes a first fuse group comprising a plurality of first fuses, arranged in a first direction and having a first cutting axis, each first fuse comprising a first portion having a first fuse pitch, a second portion having a second fuse pitch smaller than the first fuse pitch, and a third portion connecting the first and second portions, a second fuse group comprising a plurality of second fuses, arranged in the first direction and having a second cutting axis, each second fuse comprising a first portion having a first fuse pitch, a second portion having a second fuse pitch smaller than the first fuse pitch, and a third portion connecting the first portion and the second portion, and a third fuse group comprising a plurality of third fuses, wherein each third fuse has either the first cutting axis or the second cutting axis, comprises a first pattern arranged in the first direction and having a first fuse pitch, and a second pattern arranged in a second direction and having a second fuse pitch smaller than the first fuse pitch, and is arranged to bypass the first fuse or the second fuse. | 2011-05-05 |
20110101496 | FOUR-TERMINAL ANTIFUSE STRUCTURE HAVING INTEGRATED HEATING ELEMENTS FOR A PROGRAMMABLE CIRCUIT - The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming. | 2011-05-05 |
20110101497 | METHOD FOR FABRICATING A FLIP-BONDED DUAL-SUBSTRATE INDUCTOR, FLIP-BONDED DUAL-SUBSTRATE INDUCTOR, AND INTEGRATED PASSIVE DEVICE INCLUDING A FLIP-BONDED DUAL-SUBSTRATE INDUCTOR - A flip-bonded dual-substrate inductor includes a base substrate, a first inductor body portion provided on a surface of the base substrate, a cover substrate, a second inductor body portion provided on a surface of a cover substrate, and a nanoparticle bonding material provided between the base substrate surface and the cover substrate surface to electrically connect the first inductor body portion and the second inductor body portion. A method for fabricating a flip-bonded dual-substrate inductor including forming a first inductor body portion on a surface of a base substrate, forming a second inductor body portion on a surface of a cover substrate, and attaching the base substrate surface to the cover substrate surface using a nanoparticle bonding material that electrically connects the first inductor body portion and the second inductor body portion. | 2011-05-05 |
20110101498 | SEMICONDUCTOR DEVICE AND ARRANGEMENT METHOD THEREOF - An arrangement method of a semiconductor device including external connection terminals and inductors, the terminals being arranged at a predetermined pitch in a lattice pattern is provided. The method includes determining the arrangement of the terminals, determining a maximum width of air-core portions of the inductors, drawing first virtual lines passing a central position between two adjacent ones of the terminals in a first direction, drawing second virtual lines passing a central position between two adjacent ones of the terminals in a direction orthogonal to the first direction, determining a permissible range of distances between the first and second virtual lines nearest to each inductor and the inductor center, and arranging the inductors such that at least one of a distance between the nearest first virtual line and the inductor center and a distance between the nearest second virtual line and the inductor center falls within the permissible range. | 2011-05-05 |
20110101499 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating a semiconductor device are provided. The method for fabricating a semiconductor device includes forming an isolation layer over a semiconductor substrate defining first and second regions, etching the isolation layer at an edge of the first region to form a guard ring pattern, forming a buried guard ring filling the guard ring pattern, selectively etching the isolation layer of the first region to form a plurality of patterns, forming a plurality of conductive patterns in the respective patterns, and completely removing the isolation layer of the first region through a dip-out process. | 2011-05-05 |
20110101500 | JUNCTION FIELD EFFECT TRANSISTOR - A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitted from an intrinsic region of the transistor. | 2011-05-05 |
20110101501 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR ZONES AND MANUFACTURING METHOD - A semiconductor device includes first semiconductor zones of a first conductivity type having a first dopant species of the first conductivity type and a second dopant species of a second conductivity type different from the first conductivity type. The semiconductor device also includes second semiconductor zones of the second conductivity type including the second dopant species. The first and second semiconductor zones are alternately arranged in contact with each other along a lateral direction extending in parallel to a surface of a semiconductor body. One of the first and second semiconductor zones constitute drift zones and a diffusion coefficient of the second dopant species is at least twice as large as the diffusion coefficient of the first dopant species. A concentration profile of the first dopant species along a vertical direction perpendicular to the surface of the semiconductor body includes at least two maxima. | 2011-05-05 |
20110101502 | COMPOSITE WAFERS AND SUBSTRATES FOR III-NITRIDE EPITAXY AND DEVICES AND METHODS THEREFOR - A composite wafer comprises a single crystal substrate having first and second sides; a first III-nitride single crystal layer disposed on the first side of the substrate and being defined by a thickness; and a second III-nitride single crystal layer disposed on the second side of the single crystal substrate and being defined by a thickness. The thickness of each III-nitride single crystal layer is substantially the same. The composite wafer may be used in the manufacture of a semiconductor device or a freestanding wafer. | 2011-05-05 |
20110101503 | HYPERBRANCHED POLYMER SYNTHESIZING METHOD, HYPERBRANCHED POLYMER, RESIST COMPOSITION, SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION METHOD - A hyperbranched polymer synthesizing method employs living radical polymerization of a monomer in the presence of a metal catalyst. The method includes forming a shell portion by introducing an acid-decomposable group to a core portion formed of a hyperbranched polymer synthesized by living radical polymerization; forming an acid group by partially decomposing the acid-decomposable group by an acid catalyst; precipitating a core-shell hyperbranched polymer contained in a first solution and having the acid group, by mixing the first solution with ultrapure water; and extracting, from a mixed solution into an organic solvent by liquid-liquid extraction, the core-shell hyperbranched polymer having the acid group, wherein the mixed solution contains a second solution containing the core-shell hyperbranched polymer precipitated at the precipitating and dissolved into the organic solvent, and the ultrapure water of an amount yielding a prescribed ratio of the ultrapure water relative to the organic solvent in the second solution. | 2011-05-05 |
20110101504 | Methods of Grinding Semiconductor Wafers Having Improved Nanotopology - Methods for holding a workpiece with a hydrostatic pad are disclosed herein. The pad includes hydrostatic pockets formed in a face of the body directly opposed to the wafer. The pockets are adapted for receiving fluid through the body and into the pockets to provide a barrier between the body face and the workpiece while still applying pressure to hold the workpiece during grinding. The hydrostatic pads allow the wafer to rotate relative to the pads about their common axis. The pockets are oriented to reduce hydrostatic bending moments that are produced in the wafer when the grinding wheels shift or tilt relative to the hydrostatic pads, helping prevent nanotopology degradation of surfaces of the wafer commonly caused by shift and tilt of the grinding wheels. | 2011-05-05 |
20110101505 | Semiconductor Die Separation Method - According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets. Subsequent to the first cutting procedure, and prior to the second cutting procedure, additional die preparation procedures that are sensitive to die shift may be carried out. | 2011-05-05 |
20110101506 | Stress Memorization Technique Using Silicon Spacer - A structure for memorizing tensile stress in a semiconductor device includes a gate electrode of the semiconductor device; a silicon spacer adjacent to the gate electrode; and a capping layer encapsulating the gate electrode and the silicon spacer, wherein the silicon spacer and capping layer are configured to cause a tensile stress to be memorized in the gate electrode during an annealing process. A method for memorizing tensile stress in a semiconductor device includes forming a silicon spacer adjacent to a gate electrode of the semiconductor device; forming a capping layer over the silicon spacer and the gate electrode; and annealing the semiconductor device, wherein the silicon spacer and capping layer cause a tensile stress to be memorized in the gate electrode during annealing. A disposable silicon spacer is configured to induce a tensile stress in a semiconductor device during a stress memorization technique process. | 2011-05-05 |
20110101507 | METHOD AND STRUCTURE FOR REWORKING ANTIREFLECTIVE COATING OVER SEMICONDUCTOR SUBSTRATE - A method and a structure for reworking an antireflective coating (ARC) layer over a semiconductor substrate. The method includes providing a substrate having a material layer, forming a planarization layer on the material layer, forming an organic solvent soluble layer on the planarization layer, forming an ARC layer on the organic solvent soluble layer, forming a pattern in the ARC layer, and removing the organic solvent soluble layer and the ARC layer with an organic solvent while leaving the planarization layer unremoved. The structure includes a substrate having a material layer, a planarization layer on the material layer, an organic solvent soluble layer on the planarization layer, and an ARC layer on the organic solvent soluble layer. | 2011-05-05 |
20110101508 | RESIST PATTERN THICKENING MATERIAL, SEMICONDUCTOR DEVICE, AND PRODUCTION METHOD THEREOF - A resist pattern thickening material containing a resin, a cyclic compound expressed by the general formula 1, at least one of compounds expressed by the general formulae 2 to 3, respectively, and water: | 2011-05-05 |
20110101509 | Wafer Integrated With Permanent Carrier and Method Therefor - A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer that exposes the conductive layer, a second via formed in the carrier wafer that exposes the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second insulation layers are deposited over the first and second metal layers respectively. The first or second insulation layer has an etched portion to expose a portion of the first or second metal layer. | 2011-05-05 |
20110101510 | BOARD ON CHIP PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF - A single-layer board on chip package substrate and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the substrate includes an insulator, a first pad and a second pad, which are provided on an upper surface of the insulator, a through-hole, which is formed in the insulator such that a lower surface of the first pad is exposed, and a solder resist layer, which is formed on the upper surface of the insulator such that at least a portion of the second pad is exposed. | 2011-05-05 |
20110101511 | POWER SEMICONDUCTOR PACKAGE - The present invention features a power semiconductor package and a method of forming the same that includes forming, in the body, a stress relief region disposed between a pair of mounting regions and attaching a semiconductor die in each of the mounting regions. The semiconductor die has first and second sets of electrical contacts with the first set being on a first surface of the semiconductor die and the second set being disposed upon a second surface of the semiconductor die opposite to the first surface. The first set is in electrical communication with the mounting region. Walls are formed on outer sides of the pair of mounting regions, defining a shaped body, with the shaped body and walls defining an electrically conductive path that extends from the first set and terminates on side of the package common with the second set. | 2011-05-05 |
20110101512 | Semiconductor Package and Method of Mounting Semiconductor Die to Opposite Sides of TSV Substrate - A semiconductor package has a first conductive via formed through a substrate. The substrate with first conductive via is mounted to a first carrier. A first semiconductor die is mounted to a first surface of the substrate. A first encapsulant is deposited over the first die and first carrier. The first carrier is removed. The first die and substrate with the first encapsulant is mounted to a second carrier. A second semiconductor die is mounted to a second surface of the substrate opposite the first surface of the substrate. A second encapsulant is deposited over the second die. The second carrier is removed. A bump is formed over the second surface of the substrate. A conductive layer can be mounted over the first die. A second conductive via can be formed through the first encapsulant and electrically connected to the first conductive via. The semiconductor packages are stackable. | 2011-05-05 |
20110101513 | CHIP ON FILM TYPE SEMICONDUCTOR PACKAGE - A chip on film type semiconductor package includes a film, a plurality of leads formed over the film, a chip formed over the plurality of leads, an under-fill layer filled an space between the chip and the plurality of leads and an insulating heating sheet formed on an opposite side of the film contacting to the plurality of leads, wherein the insulating heating sheet is formed of a compound based on a glass fiber. | 2011-05-05 |
20110101514 | VERTICAL SURFACE MOUNT ASSEMBLY AND METHODS - A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradeable. | 2011-05-05 |
20110101515 | POWER MODULE ASSEMBLY WITH REDUCED INDUCTANCE - A device is provided that includes a first conductive substrate and a second conductive substrate. A first power semiconductor component having a first thickness can be electrically coupled to the first conductive substrate. A second power semiconductor component having a second thickness can be electrically coupled to the second conductive substrate. A positive terminal can also be electrically coupled to the first conductive substrate, while a negative terminal can be electrically coupled to the second power semiconductor component, and an output terminal may be electrically coupled to the first power semiconductor component and the second conductive substrate. The terminals, the power semiconductor components, and the conductive substrates may thereby be incorporated into a common circuit loop, and may together be configured such that a width of the circuit loop in at least one direction is defined by at least one of the first thickness or the second thickness. | 2011-05-05 |
20110101516 | Microelectronic package and method of manufacturing same - A microelectronic package includes a first substrate ( | 2011-05-05 |
20110101517 | MOLDED SEMICONDUCTOR PACKAGE HAVING A FILLER MATERIAL - An integrated circuit is attached to a package substrate. The integrated circuit is electrically connected to the package substrate using a plurality of bond wires connected between a plurality of bond posts and a plurality of bond pads. A first plurality of the bond pads are along a first side of the integrated circuit and coupled to a first plurality of the bond posts with a first plurality of the bond wires. A second plurality of the bond pads are along a second side of the integrated circuit and coupled to a second plurality of the bond posts with a second plurality of the bond wires. Mold compound is injected through a plurality of openings in the package substrate. A first opening is between the first plurality of bond posts and the first side. A second opening is between the second plurality of bond posts and the second side. | 2011-05-05 |
20110101518 | Semiconductor Device and Method of Forming Column Interconnect Structure to Reduce Wafer Stress - An interconnect pad is formed over a first substrate. A photoresist layer is formed over the first substrate and interconnect pad. A portion of the photoresist layer is removed to form a channel and expose a perimeter of the interconnect pad while leaving the photoresist layer covering a central area of the interconnect pad. A first conductive material is deposited in the channel of the photoresist layer to form a column of conductive material. The remainder of the photoresist layer is removed. A masking layer is formed around the column of conductive material while exposing the interconnect pad within the column of conductive material. A second conductive material is deposited over the first conductive layer. The second conductive material extends above the column of conductive material. The masking layer is removed. The second conductive material is reflowed to form a column interconnect structure over the semiconductor device. | 2011-05-05 |
20110101519 | Robust Joint Structure for Flip-Chip Bonding - An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a copper bump at a main surface of the first work piece and having a first dimension; and a nickel-containing barrier layer over and adjoining the copper bump. The second work piece is bonded to the first work piece and includes a bond pad at a main surface of the second work piece; and a solder mask at the main surface of the second work piece and having a solder resist opening with a second dimension exposing a portion of the bond pad. A ratio of the first dimension to the second dimension is greater than about 1. Further, a solder region electrically connects the copper bump to the bond pad, with a vertical distance between the bond pad and the copper bump being greater than about 30 μm. | 2011-05-05 |
20110101520 | Semiconductor Die Contact Structure and Method - A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact. | 2011-05-05 |
20110101521 | POST PASSIVATION INTERCONNECT WITH OXIDATION PREVENTION LAYER - A copper interconnect line formed on a passivation layer is protected by a copper-containing material layer including a group III element, a group IV element, a group V element or combinations thereof. | 2011-05-05 |
20110101522 | Multichip semiconductor device, chip therefor and method of formation thereof - A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug. | 2011-05-05 |
20110101523 | PILLAR BUMP WITH BARRIER LAYER - A copper pillar bump has a surface covered with by a barrier layer formed of a copper-containing material layer including a group III element, a group IV element, a group V element or combinations thereof. The barrier layer depresses the copper diffusion and reaction with solder to reduce the thickness of intermetallic compound between the pillar pump and solder. | 2011-05-05 |
20110101524 | Semiconductor Device with Bump Interconnection - A semiconductor device includes a semiconductor die having contact pads disposed over a surface of the semiconductor die, a die attach adhesive layer disposed under the semiconductor die, and an encapsulant material disposed around and over the semiconductor die. The semiconductor device further includes bumps disposed in the encapsulant material around a perimeter of the semiconductor die. The bumps are partially enclosed by the encapsulant material. The semiconductor device further comprises first vias disposed in the encapsulant. The first vias expose surfaces of the contact pads. The semiconductor device further includes a first redistribution layer (RDL) disposed over the encapsulant and in the first vias, and a second RDL disposed under the encapsulant material and the die attach adhesive layer. The first RDL electrically connects each contact pad of the semiconductor die to one of the bumps, and the second RDL is electrically connected to one of the bumps. | 2011-05-05 |
20110101525 | SEMICONDUCTOR DEVICE WITH TRENCH-LIKE FEED-THROUGHS - A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated. | 2011-05-05 |
20110101526 | Copper Bump Joint Structures with Improved Crack Resistance - An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a semiconductor substrate, and a copper bump over the semiconductor substrate. The second work piece includes a bond pad. A solder is between and adjoining the first work piece and the second work piece, wherein the solder electrically connects the copper bump to the bond pad. The solder includes palladium. | 2011-05-05 |
20110101527 | MECHANISMS FOR FORMING COPPER PILLAR BUMPS - The mechanism of forming a metal bump structure described above resolves the delamination issues between a conductive layer on a substrate and a metal bump connected to the conductive layer. The conductive layer can be a metal pad, a post passivation interconnect (PPI) layer, or a top metal layer. By performing an in-situ deposition of a protective conductive layer over the conductive layer (or base conductive layer), the under bump metallurgy (UBM) layer of the metal bump adheres better to the conductive layer and reduces the occurrence of interfacial delamination. In some embodiments, a copper diffusion barrier sub-layer in the UBM layer can be removed. In some other embodiments, the UBM layer is not needed if the metal bump is deposited by a non-plating process and the metal bump is not made of copper. | 2011-05-05 |
20110101528 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a substrate; a wiring provided above the substrate and including a graphene nanoribbon layer comprising a plurality of laminated graphene nanoribbon sheets; and a wiring connecting member penetrating at least one of the plurality of graphene nanoribbon sheets for connecting the wiring and a conductive member above or below the wiring. | 2011-05-05 |
20110101529 | BARRIER LAYER FOR COPPER INTERCONNECT - A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide. | 2011-05-05 |
20110101530 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF - A seal ring is provided between a region where a circuit is formed on a semiconductor substrate and a dicing region. The seal ring has a portion where sealing layers of which the cross sectional form is in T-shape are layered and a portion where sealing layers of which the cross sectional form is rectangular are layered. | 2011-05-05 |
20110101531 | THERMO-MECHANICAL STRESS IN SEMICONDUCTOR WAFERS - An apparatus for restricting the thermo-mechanical stress in semiconductor wafers both during manufacture, and during the operating lifetime of the semiconductor devices and systems formed on the wafer. An electrically conductive track | 2011-05-05 |
20110101532 | DEVICE FABRICATED USING AN ELECTROPLATING PROCESS - A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer. | 2011-05-05 |
20110101533 | INTEGRATED (MULTILAYER) CIRCUITS AND PROCESS OF PRODUCING THE SAME - A process of forming a semiconductor integrated circuit that includes the steps of: forming at least a first element having a first pattern of conductive material and including a polymer layer surrounding the conductive material, forming at least a second element having a second pattern of conductive material and including a polymer layer surrounding the conductive material, positioning the first element relative to the second element, and bonding the polymer layer of the first and second elements at a temperature below a melting temperature of the conductive materials of the first and second elements wherein the conductive material of the first element contacts the conductive material of the second element and is maintained in position by the bonded polymer layers. | 2011-05-05 |
20110101534 | AUTOMATED SHORT LENGTH WIRE SHAPE STRAPPING AND METHODS OF FABRICTING THE SAME - An automatic short length wire shape generation and strapping and method of fabricating such wires is provided. The method of manufacturing includes breaking of a wiring into adjacent short length wires which are below a maximum short length effect length. The adjacent short length wires are formed in a same wiring level of an integrated circuit. The method further includes forming a conductive strap in a single deposition process which overlaps and is in contact with the adjacent short length wires. | 2011-05-05 |
20110101535 | MICROELECTRONIC ASSEMBLY WITH IMPEDANCE CONTROLLED WIREBOND AND CONDUCTIVE REFERENCE ELEMENT - A microelectronic assembly can include a microelectronic device having device contacts exposed at a surface thereof and an interconnection element having element contacts and having a face adjacent to the microelectronic device. Conductive elements, e.g., wirebonds connect the device contacts with the element contacts and have portions extending in runs above the surface of the microelectronic device. A conductive layer has a conductive surface disposed at least a substantially uniform distance above or below the plurality of the runs of the conductive elements. In some cases, the conductive material can have first and second dimensions in first and second horizontal directions which are smaller than first and second corresponding dimensions of the microelectronic device. The conductive material is connectable to a source of reference potential so as to achieve a desired impedance for the conductive elements. | 2011-05-05 |
20110101536 | Methods For Discretized Formation of Masking and Capping Layers on a Substrate - The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate. | 2011-05-05 |
20110101537 | HYBRID BONDING INTERFACE FOR 3-DIMENSIONAL CHIP INTEGRATION - Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions. | 2011-05-05 |
20110101538 | CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS - Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided. | 2011-05-05 |
20110101539 | Semiconductor device and manufacturing method of semiconductor device - Disclosed herein is a semiconductor device including a semiconductor substrate, a wiring layer formed above the semiconductor substrate, a through-hole electrode extending from the bottom surface of the semiconductor substrate to the wiring layer, a bottom surface wiring provided at the bottom surface of the semiconductor substrate such that the bottom surface wiring is connected to the through-hole electrode, and an external terminal connected to the bottom surface wiring. The bottom surface wiring has a greater film thickness than a film thickness of the through-hole electrode at least a portion of the bottom surface wiring including a connection part between the bottom surface wiring and the external terminal. | 2011-05-05 |
20110101540 | INTEGRATED CHIP CARRIER WITH COMPLIANT INTERCONNECTS - A silicon chip includes a silicon substrate, a plurality of pads, and a plurality of through vias to connect back-end-of-line wiring to the plurality of pads. The silicon substrate includes a layer of active devices and the back-end-of-line wiring connected to the active devices. | 2011-05-05 |
20110101541 | SEMICONDUCTOR DEVICE - A falling off of a through electrode is inhibited without decreasing a reliability of a semiconductor device including a through electrode. A semiconductor device | 2011-05-05 |
20110101542 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED INTEGRATED CIRCUIT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed. | 2011-05-05 |
20110101543 | CONNECTING MATERIAL AND SEMICONDUCTOR DEVICE - The invention provides a connecting material comprising metallic particles with an oxygen state ratio of less than 15% as measured by X-ray photoelectron spectroscopy, and especially a connecting material comprising metallic particles that have been subjected to treatment for removal of the surface oxide film and to surface treatment with a surface protective material, for the purpose of providing a connecting material having a high coefficient of thermal conductivity even when joined at a curing temperature of up to 200° C. without application of a load, and that has sufficient bonding strength even when the cured product has been heated at 260° C., as well as a semiconductor device employing it. | 2011-05-05 |
20110101544 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package. | 2011-05-05 |
20110101545 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH BOND PAD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a semiconductor substrate; forming a core region on the semiconductor substrate with the core region having a core side; forming an inner bond pad on the semiconductor substrate with the inner bond pad having an inner core pad and an inner probe pad with the inner probe pad further from the core region than the inner core pad; and forming an outer bond pad on the semiconductor substrate and adjacent the inner bond pad with the outer bond pad having an outer core pad and an outer probe pad with the outer probe pad closer to the core region than the outer core pad, and the inner probe pad and the outer probe pad aligned parallel to the core side. | 2011-05-05 |
20110101546 | System and Method for Directional Grinding on Backside of a Semiconductor Wafer - A semiconductor device includes a backing plate, a semiconductor wafer, and integrated devices. The semiconductor wafer includes a plurality of semiconductor die having edges oriented along a reference line, a front surface facing the backing plate, and a backside surface. The backside surface is formed opposite the front surface and includes linear grind marks oriented along the reference line and diagonal with respect to the edges of the plurality of semiconductor die. The linear grind marks are formed by a linear motion of an abrasive surface, such as by a cylinder or wheel having an abrasive surface, and in one embodiment are oriented at 45 degrees with respect to the reference line. The linear grind marks increase a strength of the plurality of semiconductor die to resist cracking. Integrated devices are formed on the front surface of the semiconductor wafer. | 2011-05-05 |
20110101547 | FLUIDIZATION AERATION MIXING APPARATUS - The present invention relates to fluidization aeration mixing apparatus comprising a centrifugal ventilator ( | 2011-05-05 |
20110101548 | DIFFUSER FOR AERATION - Disclosed is a diffuser installation structure capable of improving uniformity of air bubbles discharged from air bubble discharge holes, restricting the formation of dead zone air bubble discharge holes, and having the tolerance against design deviation. In the installation structure for a diffuser comprising at least one air feeding port and an air bubble discharge wall having a plurality of air bubble discharge holes, the air bubble discharge wall is inclined upward in the direction of increasing distance relative to the air feeding port. | 2011-05-05 |
20110101549 | HUMIDITY CONTROL DEVICE - A humidity control device is for controlling the humidity of air in a target space, and the humidity control device comprises: a processor for controlling the humidity of air in the target space by passing air through a hygroscopic liquid L; a regenerator for regenerating the hygroscopic liquid L used for the process by the processor; a hygroscopic-liquid pipe path ( | 2011-05-05 |
20110101550 | MOLDS FOR PRODUCING CONTACT LENSES - This invention describes molds made from alicyclic co-polymers that are useful in the production of contact lenses and methods for their use. | 2011-05-05 |
20110101551 | Method for manufacturing lens used in camera module - The present invention provides a method for manufacturing a lens used in a camera module including the steps of: preparing a preform for manufacturing a lens; forming a front lens on a front surface of the preform; and forming an array lens by forming a rear lens on a rear surface of the preform during the formation of the front lens. | 2011-05-05 |
20110101552 | METHOD FOR MAKING A COLORED CONTACT LENS - The present invention relates to a method for the manufacture of a contact lens with a printed image thereon, in particular a silicone hydrogel contact lens with a printed image thereon, comprising applying one or more ink drops to at least a portion of at least one molding surface of a lens mold, wherein each ink drop is sufficiently flat, that the forces exerted by the mold surface to the ink drop surface in the area where they make contact, are higher than the forces exerted by the flowing lens forming material to the facing surface of the ink drop, and wherein the ink material and the lens forming material are sufficiently immiscible or not miscible at all. | 2011-05-05 |
20110101553 | METHOD AND DEVICE FOR CONTINUOUSLY PREPARING MICROSPHERES, AND COLLECTION UNIT THEREOF - A method and a device for continuously preparing microspheres, and a collection unit thereof are provided. The collection unit for collecting microspheres in the solution comprises a tank and a first plate. The first plate is removably disposed in the tank. The first plate, when lay across the tank, has its two ends came in contact with the sidewall of the tank so as to divide the tank into a first chamber and a second chamber. The tank has an outlet located in the second chamber. After the solution with microspheres are input to the first chamber of the tank, the microspheres are deposited around the first plate, and the solution is caused to pass through or over the first plate to the second chamber and output from the outlet. | 2011-05-05 |
20110101554 | Compression Processes for Graphene Sheets - Processes for preparing or handling graphene sheets wherein low bulk density graphene sheets are compressed. The graphene sheets may be produced by a thermal treatment such as exfoliation of precursor or reduction or annealing of previously existing graphene sheets and conveyed in a closed system to a compression apparatus. | 2011-05-05 |
20110101555 | METHODS FOR FORMING INJECTED MOLDED PARTS AND IN-MOLD SENSORS THEREFOR - A method for use in forming a molded part includes providing a mold having a cavity and a movable pin, injecting a moldable material into the cavity, biasing the movable pin to maintain an end of the movable pin in contact with the moldable material in the cavity during the curing of the moldable material and until the moldable material is cured, and monitoring movement of the biased movable pin during curing of the moldable material in the mold. Also disclosed is a sensor engageable with an end of a movable pin of a mold for monitoring the forming of a moldable part, and systems employing the same. | 2011-05-05 |
20110101556 | METHOD AND HEATING DEVICE FOR THERMOFORMING - The present invention relates to a method and a heating device for thermoforming thermoplastic semi-finished products. According to the method locally different thermoforming behaviour during shaping to give a three-dimensional moulded part is achieved by locally different heating of the semi-finished product ( | 2011-05-05 |
20110101557 | VEHICLE SEAT WITH IMPROVED CRAFTSMANSHIP - A process for improving vehicle seat craftsmanship by camouflaging a receiving surface on a predetermined vehicle component (e.g., a foam seat cushion) is described. The camouflaging conceals the vehicle component from observation. One example of the process includes designating a receiving surface area on the vehicle component and providing a covering material having an opaque characteristic. The covering material includes an opaque dye that bonds with the polyurethane foam that is poured into a mold with deionized water for solidification. Another example of the process further includes spraying the covering material according to a surface of the mold cavity which corresponds to the designated receiving surface area on the vehicle component. | 2011-05-05 |
20110101558 | METHOD FOR MANUFACTURING MOLDED FOAM - An object of the invention is to provide a method for manufacturing a molded foam which is lightweight and excellent in strength. According to the invention, a method for manufacturing a molded foam from a foamed parison includes: an extruding step of extruding a resin blend containing a foaming agent and a thermoplastic resin to form a foamed parison; an attaching step of closely attaching facing portions of an inner wall surface of the foamed parison to each other to form a foamed parison laminated body; a mold clamping step of sealing and mold clamping the foamed parison laminated body by clamping the foamed parison laminated body by split mold blocks; and a sucking step of sucking air between the split mold blocks to reduce a pressure between the split mold blocks, after the attaching step and the mold clamping step. | 2011-05-05 |
20110101559 | METHOD OF MAKING A LAMP STAND OR CRAFTWORK - A method of making a lamp stand or other craftwork. The method begins by mixing materials with the following weight ratios: 1-10 kilograms of powdered Magnesia Usta; 1-10 kilograms of liquid magnesium chloride; 1-5 kilograms of glass quartz sand; 7-10 milliliters of activator; 5-50 milliliters of retarder; glass fiber and a paint for tinting. Next, the mixed materials are poured into a molded blowing die of the lamp stand and left within the die to solidify for approximately 3 to 5 hours. Next, the molded lamp stand is removed from the die. French chalk and de-foaming agent may be added to the mixed materials. | 2011-05-05 |
20110101560 | SUBSTRATE AND METHOD OF MANUFACTURING POLYGON FLAKES - A method of forming pigment flakes includes using a deposition substrate having a plurality of regions; some of the regions are raised or lowered so that there is a level difference between each two adjacent regions. A coating deposited onto this substrate breaks along region borders when it is separated from the substrate. In one embodiment, the substrate includes first and second regions, wherein each of the first regions is in an abutting relationship with at least one of the second regions. All the first regions are at a first level and all the second regions are at a second level, and the difference between the first and second levels is greater than a predetermined value. The first and second regions are preferably square-shaped regions for manufacturing square flakes with practically no debris. | 2011-05-05 |
20110101561 | METHOD FOR FORMING RESIN MOLDED ARTICLES - A method for forming a resin molded article includes a step of extruding a thermoplastic resin intermittently at a predetermined speed from an extrusion slit, such that the resin droops downward in a shape of a sheet. The method further includes the steps of: feeding the extruded sheet-shaped resin downward by a pair of rollers; and forming the sheet-shaped resin with a mold. In the step of feeding the sheet-shaped resin, one of the rollers is pressed against the other, but not to the extent of crushing the sheet-shaped resin, regardless of the thickness of the sheet-shaped resin. In addition, a surface temperature of each of the rollers is set lower than a temperature of the sheet-shaped resin and within a predetermined temperature range. This method can prevent sliding contact between the rollers and the sheet, while preventing the sheet from being wound around the rollers. | 2011-05-05 |
20110101562 | TUBULAR MEMBER EXTRUSION METHOD AND TUBULAR MEMBER EXTRUSION APPARATUS - According to a fabrication method, an extruded tubular member HA is formed, using an extrusion die | 2011-05-05 |
20110101563 | METHOD OF MAKING A PISTON FOR A DISPENSER - A dispenser for dispensing a liquid onto a substrate includes a dispenser body having an output and a reservoir in fluid communication with the output, the reservoir being defined by a wall and adapted to hold a supply of liquid to be dispensed. A piston is disposed in the reservoir and adapted to pressurize the liquid so that an amount of liquid is dispensed from the output of the dispenser. The piston includes a base portion having an outer periphery and having a first hardness, and a skirt portion integrally molded to the outer periphery of the base portion and having a second hardness lower than the first hardness. A two-shot molding operation may be used to form the piston with the base portion being, for example, formed in the first shot of the molding operation and the skirt portion being formed in the second shot of the molding operation. | 2011-05-05 |
20110101564 | METHOD FOR ENCAPSULATING THE EDGE OF A FLEXIBLE SHEET - The present invention is premised upon an inventive method of producing an over-molded edge portion on a flexible substrate, wherein the edge portion is void of open areas due to support devices in the mold cavity. | 2011-05-05 |
20110101565 | METHOD OF RAPIDLY HEATING MOLD APPARATUS - The present invention relates to a method of rapidly heating a mold. The method of rapidly heating a mold according to the present invention includes a heater unit coupling step S | 2011-05-05 |
20110101566 | FLAME-RETARDANT RESIN COMPOSITION, PROCESS FOR PRODUCING THE SAME, METHOD OF MOLDING THE SAME - A flame-retardant composition is obtained wherein at least one resin selected from a biodegradable resin and a plant-based resin or a PS resin is flame retarded by using a non-halogen-based flame retardancy-imparting component. At least one catalyst selected from a catalyst for purifying hydrocarbon, a catalyst for cracking hydrocarbon, a catalyst for synthesizing hydrocarbon and a catalyst for reforming hydrocarbon is used as a component conferring flame retardancy and this catalyst is kneaded with a biodegradable resin or a plant based resin such as polylactic acid and polybutylene succinate or the PS resin so as to give a resin composition. Further, the resin composition is injection-molded to give an exterior body of electric home appliance. Particularly the silica-magnesia catalyst as a flame-retardant component provides a resin composition with excellent flame-retardant characteristics, as a non-halogen-based material, in the case where polylactic acid or the PS resin is made flame retardant. | 2011-05-05 |
20110101567 | INJECTION MOLD - Disclosed, amongst other things, is a molding apparatus and an injection molding process. The molding apparatus includes a positioner that is configured to regulate, in use, a relative position between a gate member and a nozzle of a melt distribution apparatus between a retracted position and an extended position for adjusting a volume of a nozzle melt reservoir that is definable between the gate member and the nozzle between a reduced volume and an expanded volume, respectively. The injection molding process includes regulating a relative position between a gate member and a nozzle of a melt distribution apparatus, with a positioner, into one of a retracted position and an extended position for adjusting a volume of a nozzle melt reservoir that is definable between the gate member and the nozzle between a reduced volume and an expanded volume, respectively. | 2011-05-05 |
20110101568 | AUTOMATIC DE-MOLDING DEVICE FOR FLAT RUBBER TREADS - A method of automatically de-molding a tread from a mold is provided utilizing an automatic de-molding apparatus. The automatic de-molding device utilizes at least one anchor member that is inserted into the mold and automatically secures the tread to the de-molding apparatus wherein the mold is mechanically removed from the mold. | 2011-05-05 |
20110101569 | THREE-DIMENSIONAL STEREOLITHOGRAPHY APPARATUS, THREE-DIMENSIONAL STEREOLITHOGRAPHY METHOD, AND THREE-DIMENSIONAL OBJECT - A three-dimensional stereolithography apparatus includes a stage, a support mechanism to support a film so that the film is opposed to the stage, a pressing mechanism, a supply mechanism, an irradiation unit, a movement mechanism, and a control mechanism. The pressing mechanism presses at least a linear area of the film so that the linear area closest to the stage is formed in the film. The supply mechanism supplies a light-curing material into a slit area formed between the stage and the linear area. The irradiation unit irradiates the light-curing material supplied into the slit area with laser light through the pressing mechanism and the film. The movement mechanism moves the stage and the pressing mechanism relatively to the film, to form one cured layer of the light-curing material. The control mechanism controls a distance between the stage and the linear area of the film, to stack the cured layer. | 2011-05-05 |
20110101570 | Device and Method for Producing a Three-Dimensional Object by Means of Mask Exposure - The invention describes device and method for producing a three-dimensional object by solidifying a solidifiable material under an action of electromagnetic radiation by means of energy input via an imaging unit comprising a predetermined number of discrete imaging elements (pixels). The energy input related to a specific cross-sectional area of the three-dimensional object is controlled by exposure by means of multiple successive raster masks (bitmaps; e.g. bitmap | 2011-05-05 |
20110101571 | METHOD OF MAKING COILED AND BUCKLED ELECTROSPUN FIBER STRUCTURES - An apparatus and method for making coiled and buckled electrospun fiber including (a) providing a solution of a polymer in an organic solvent and a device for electrospinning fiber; b) subjecting the polymer solution to an electric field such that at least one fiber is electrospun; (c) subjecting the so formed fiber to electrical bending and mechanical buckling instability to hereby form a coiled and buckled fiber; (d) collecting the at least one fiber on a collector, such that a fiber structure is produced. | 2011-05-05 |
20110101572 | METHOD OF MANUFACTURING CHARGING ROLLER FOR ELECTROPHOTOGRAPHIC IMAGE FORMING APPARATUS, AND CHARGING ROLLER MANUFACTURED BY THE SAME METHOD - Disclosed is a method of manufacturing a charging roller useable in an electrophotographic image forming apparatus and a charging roller manufactured according to the method. The method includes introducing a conductive agent and a mixture of a rubber-based material and polyolefin-based resin into an extruder, extruding the conductive agent and the mixture to obtain an extrudate, crosslinking the extrudate by electron beam irradiation, and polishing the crosslinked extrudate. The method results in an environmentally friendly and simplified manufacturing processes, and/or in the reduction of the manufacturing costs. | 2011-05-05 |
20110101573 | HOLLOW CONTAINER AND PROCESS FOR PRODUCING THE SAME - There is provided a multilayer hollow container having a laminar structure including a PGA resin and a co-laminated resin, such as an aromatic polyester resin, that takes advantage of the gas-barrier property of the PGA resin layer to the utmost and is suitable for bottles of a small volume required to exhibit a higher level of gas-barrier property. The multilayer hollow container has a co-stretched multilayer wall structure including a layer of a polyglycolic acid resin comprising at least 60 wt. % of recurring unit represented by a formula of —(O.CH | 2011-05-05 |
20110101574 | METHOD OF FORMING AN ARTICLE FROM NON-MELT PROCESSIBLE POLYMERS AND ARTICLES FORMED THEREBY - A method of preparing an article includes compressing a polymeric material to form a body and hot isostatic pressing (HIP) the body in an inert atmosphere at a pressure of at least 3 ksi without an encapsulant. The body may optionally be sintered prior to hot isostatic pressing (HIP). The body may have a porosity of not greater than 8% prior to hot isostatic pressing (HIP). The polymer material may be a non-melt processible polymer. | 2011-05-05 |
20110101575 | PREFORM FOR COMPOSITE MATERIAL AND PROCESS FOR PRODUCING THE SAME - A preform for a composite material which has high strength and excellent air permeability and hence is applicable to a high-speed die casting method and which is capable of forming a metal composite material having excellent mechanical properties by a high-speed die casting method. Also provided is a process for producing such a preform. Ceramic fibers or/and ceramic particles are mixed with a silica sol and calcium carbonate and sintered at a predetermined temperature to form a calcium/silicon sinter obtained from the silica sol and calcium carbonate. The calcium/silicon sinter coats the ceramic fibers or/and ceramic particles so that a preform having the fibers or/and the particles bound to each other by the calcium/silicon sinter is obtained. The preform for a composite material has high strength and excellent air permeability and is applicable to the high-speed die casting method capable of attaining high productivity. | 2011-05-05 |