| 18th week of 2009 patent applcation highlights part 64 |
| Patent application number | Title | Published |
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| 20090113172 | NETWORK TOPOLOGY FOR A SCALABLE MULTIPROCESSOR SYSTEM - A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters. | 2009-04-30 |
| 20090113173 | COMPUTER SYSTEM AND METHOD THAT ELIMINATES THE NEED FOR AN OPERATING SYSTEM - A hardware/firmware layer comprising a Device Manager, an Information Manager, a Memory Manager, and a Process Manager contained in one or more semiconductor chips is disclosed. The hardware/firmware layer eliminates the need for an operating system. Each of the Managers comprises a microcontroller associated with a firmware embedded in ROM or Flash memory that contains instruction sets that cause the microcontroller to provide a designated task of device management, information management, memory management and process management. In another aspect of the invention, devices connected to the computer system are “smart devices,” each device having a device microcontroller and embedded device drivers in a ROM or Flash memory. The hardware/firmware of the present invention does not need to search for available devices, provide diagnostic tests or obtain device drivers to communicate with the devices. Instead, the device microcontroller uses the embedded device driver to perform configuration and self diagnostic test as well as device operations. If the device is operational, the device microcontroller sends an identification signal to the hardware/firmware layer of the present to indicate availability of the device. | 2009-04-30 |
| 20090113174 | Sign Operation Instructions and Circuitry - A co-processor for efficiently decoding codewords encoded according to a Low Density Parity Check (LDPC) code, and arranged to efficiently execute an instruction to multiply the value of one operand with the sign of another operand, is disclosed. Logic circuitry is included in the co-processor to select between the value of a second operand, and an arithmetic inverse of the second operand value, in response to the sign bit of the first operand. This logic circuitry is arranged to operate according to | 2009-04-30 |
| 20090113175 | Processor architecture for concurrently fetching data and instructions - In one embodiment, a processor architecture for concurrently fetching data and patched instructions includes a microprocessor, an instruction patch, a dedicated instruction memory, a patch memory, and a dedicated data memory. The instruction patch is coupled to the microprocessor by an instruction bus, and is also coupled to the dedicated instruction memory and the patch memory. The patch memory and the dedicated data memory are coupled to the microprocessor by a data bus separate from the instruction bus. In one embodiment, the instruction patch has a number of comparators that can be individually enabled by respective enable signals. Each comparator that is enabled compares every bit on an instruction address with a corresponding bit of a patched instruction address to detect a patch condition. When a patch condition is detected, patched instructions are fetched from the patch memory, while the microprocessor can concurrently fetch data from the dedicated data memory. | 2009-04-30 |
| 20090113176 | Method of reducing data path width restrictions on instruction sets - A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers. | 2009-04-30 |
| 20090113177 | INTEGRATED CIRCUIT WITH DMA MODULE FOR LOADING PORTIONS OF CODE TO A CODE MEMORY FOR EXECUTION BY A HOST PROCESSOR THAT CONTROLS A VIDEO DECODER - A system, method, and apparatus for dynamically booting processor code memory with a wait instruction is presented herein. A wait instruction precedes the transfer of a new code portion to the code memory. The wait instruction causes the processor to temporarily cease using the code memory. When the processor ceases using the code memory, the processor signals a direct memory access (DMA) module to transfer a new code portion to the code memory. The DMA module transfers the new code portion to the code memory and transmits a signal to the processor when the transfer is completed. The signal causes the processor to resume. When the processor resumes, the processor begins executing the instructions at the next code address. | 2009-04-30 |
| 20090113178 | Microprocessor based on event-processing instruction set and event-processing method using the same - Provided are a microprocessor based on event-processing instruction set and an event-processing method using the same. The microprocessor includes an event register controlling an event according to an event-processing instruction set provided in an instruction set architecture (ISA) and an event controller transmitting externally generated events into the microprocessor. Therefore, the microprocessor may be useful to reduce its unnecessary power consumption by suspending the execution of its program when an instruction decoded to execute the program is an event-processing instruction, and also to cut off its unnecessary power consumption that is caused for an interrupt delay period since the program of the microprocessor may be executed again by immediately re-running the microprocessor with the operation of the event register and the event controller when external events are generated. | 2009-04-30 |
| 20090113179 | OPERATIONAL PROCESSING APPARATUS, PROCESSOR, PROGRAM CONVERTING APPARATUS AND PROGRAM - The present invention provides an operational processing apparatus which can guarantee a period for executing instructions in the shortest cycle when the operational processing apparatus synchronizes with a hardware accelerator. A processor in the present invention simultaneously issues and executes instructions including instruction groups having a simultaneously issueable instruction. The processor executes a program including a specific instruction. The specific instruction instructs to exclude an instruction subsequent to the specific instruction out of the instruction groups including the specific instruction, and to suspend issuing the instruction subsequent to the specific instruction only during a predetermined period immediately after the specific instruction is issued. | 2009-04-30 |
| 20090113180 | Fetch Director Employing Barrel-Incrementer-Based Round-Robin Apparatus For Use In Multithreading Microprocessor - A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a given selection cycle, some of the threads may not be requesting to fetch instructions. The fetch director includes a circuit for selecting one of threads in a round-robin fashion to provide its fetch address to the instruction cache. The circuit 1-bit left rotatively increments a first addend by a second addend to generate a sum that is ANDed with the inverse of the first addend to generate a 1-hot vector indicating which of the threads is selected next. The first addend is an N-bit vector where each bit is false if the corresponding thread is requesting to fetch instructions from the instruction cache. The second addend is a 1-hot vector indicating the last selected thread. In one embodiment threads with an empty instruction buffer are selected at highest priority; a last dispatched but not fetched thread at middle priority; all other threads at lowest priority. The threads are selected round-robin within the highest and lowest priorities. | 2009-04-30 |
| 20090113181 | Method and Apparatus for Executing Instructions - A method and apparatus for executing instructions in a processor are provided. In one embodiment of the invention, the method includes receiving a plurality of instructions. The plurality of instructions includes first instructions in a first thread and second instructions in a second thread. The method further includes forming a common issue group including an instruction of a first instruction type and an instruction of a second instruction type. The method also includes issuing the common issue group to a first execution unit and a second execution unit. The instruction of the first instruction type is issued to the first execution unit and the instruction of the second instruction type is issued to the second execution unit. | 2009-04-30 |
| 20090113182 | System and Method for Issuing Load-Dependent Instructions from an Issue Queue in a Processing Unit - A system and method for issuing load-dependent instructions from an issue queue in a processing unit in a data processing system. In response to a LSU determining that a load request from a load instruction missed a first level in a memory hierarchy, a LMQ allocates a load-miss queue entry corresponding to the load instruction. The LMQ associates at least one instruction dependent on the load request with the load-miss queue entry. Once data associated with the load request is retrieved, the LMQ selects at least one instruction dependent on the load request for execution on the next cycle. At least one instruction dependent on the load request is executed and a result is outputted. | 2009-04-30 |
| 20090113183 | METHOD OF CONTROLLING A DEVICE AND A DEVICE CONTROLLED THEREBY - A method of controlling at least one device is disclosed. The method includes providing the device with at least one constraint for carrying out an operation. The device determines if the constraint can be met. If it is determined that the constraint can be met, the device determines on its own accord a manner to get into a state wherein the constraint will be met. The device then goes into the state in the determined manner. A device that is controlled by the method and a system including such a device are also disclosed. | 2009-04-30 |
| 20090113184 | Method, Apparatus, and Program for Pinning Internal Slack Nodes to Improve Instruction Scheduling - A scheduling algorithm is provided for selecting the placement of instructions with internal slack into a schedule of instructions within a loop. The algorithm achieves this by pinning nodes with internal slack to corresponding nodes on the critical path of the code that have similar properties in terms of the data dependency graph, such as earliest time and latest time. The effect is that nodes with internal slack are more often optimally placed in the schedule, reducing the need for rotating registers or register copy instructions. The benefit of the present invention can primarily be seen when performing instruction scheduling or software pipelining on loop code, but can also apply to other forms of instruction scheduling when greater control of placement of nodes with internal slack is desired. | 2009-04-30 |
| 20090113185 | Processor for executing multiply matrix and convolve extract instructions requiring wide operands - A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers. | 2009-04-30 |
| 20090113186 | MICROCONTROLLER AND CONTROLLING SYSTEM - A microcontroller and a controlling system having the same are provided, in which the increase in the program code for performing floating-point arithmetic, in particular, the increase in the amount of code due to a variable are suppressed, and the processing overhead for converting fixed-point data into floating-point data is reduced. The microcontroller includes a floating-point converter which inputs integer data and corresponding decimal point position data as fixed-point data and which converts the input data into floating-point data by acquiring a fraction part, an exponent part, and a sign of the floating type from the input data, and a floating-point arithmetic logic unit which receives the output of the floating-point converter and calculates the floating-point data. The floating-point converter acquires the exponent part by performing addition and subtraction of the decimal point position data and the shift amount of the fraction part to the integer data. | 2009-04-30 |
| 20090113187 | Processor architecture for executing instructions using wide operands - A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers. | 2009-04-30 |
| 20090113188 | COORDINATOR SERVER, DATABASE SERVER, AND PIPELINE PROCESSING CONTROL METHOD - A first transmitting unit transmits a processing command to a plurality of parallelized database servers. A second transmitting unit integrates data sets transmitted from the database servers in response to the processing command, and transmits an integrated data set to a client. An integrating unit integrates data sets buffered in a buffer unit. A determining unit determines a transmission start or a transmission suspend of the data sets based on a data size in the buffer unit. A third transmitting unit transmits a control command for the transmission start or the transmission suspend to the database servers based on a result of determination by the first determining unit. | 2009-04-30 |
| 20090113189 | Method and System for Hiding Information in the Instruction Processing Pipeline - A system, article of manufacture and method is provided for transferring secret information from a first location to a second location. The secret information is encoded and stalls in executable code are located. The executable code is configured to perform a predetermined function when executed on a pipeline processor. The encoded information is inserted into a plurality of instructions and the instructions are inserted into the executable code at the stalls. There is no net effect of all of the inserted instructions on the predetermined function of the executable code. The executable code is transferred to the second location. The location of the stalls in the transferred code is identified. The encoded information is extracted from the instructions located at the stalls. The encoded information may then be decoding information to generate the information at the second location. | 2009-04-30 |
| 20090113190 | GATHERING OPERATIONAL METRICS WITHIN A GRID ENVIRONMENT USING GHOST AGENTS - A method for gathering operational metrics can include the step of identifying a host within a grid environment, wherein the host can be a software object. A ghost agent can be associated with the host. The ghost agent can replicate actions of the host. Operational metrics for at least a portion of the replicated actions can be determined. The operational metrics can be recorded. The host can move within the grid environment. The ghost agent can responsively move in accordance with movement of the host. | 2009-04-30 |
| 20090113191 | Apparatus and Method for Improving Efficiency of Short Loop Instruction Fetch - A method, system and computer program product for instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. Instructions are stored in the modified instruction buffers for the length of the loop cycle. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycle, rather than from the instruction cache. | 2009-04-30 |
| 20090113192 | DESIGN STRUCTURE FOR IMPROVING EFFICIENCY OF SHORT LOOP INSTRUCTION FETCH - A design structure provides instruction fetching within a processor instruction unit, utilizing a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. During instruction fetch, modified instruction buffers coupled to an instruction cache (I-cache) temporarily store instructions from a single branch, backwards short loop. The modified instruction buffers may be a loop buffer, one or more virtual loop buffers, and/or an instruction buffer. Instructions are stored in the modified instruction buffers for the length of the loop cycle. The instruction fetch within the instruction unit of a processor retrieves the instructions for the short loop from the modified buffers during the loop cycle, rather than from the instruction cache. | 2009-04-30 |
| 20090113193 | ON-SITE CONFIGURATION OF A HARDWARE DEVICE MODULE OF A SECURITY SYSTEM - A security system is provided. The security system comprises a plurality of hardware device modules and a plurality of sensor detection devices. At least one of the hardware device modules has a microcontroller coupled to a memory element that stores a configuration map for on-site configuration comprising configuration option information available for the at least one hardware device module. The plurality of sensor detection devices are capable of sending at least a signal to one or more of the hardware device modules. | 2009-04-30 |
| 20090113194 | Persisting value relevant to debugging of computer system during reset of computer system - The last value of an element of a computing system is continually stored within a first register. The element is cleared during any restart or reset of the computing system. The last value is relevant to debugging of the computing system when the computing system fails to perform as expected and/or as desired. Upon receiving an instruction to reset the computing system via a first reset signal corresponding to pressing of a reset button or a second reset signal corresponding to a baseboard management controller issuing a reset command, the last value of the element as stored within the first register is copied to a second register. The computing system is then reset. The last value of the element as stored within the second register persists within the second register during this type of reset, but is cleared during any other reset or restart of the computing system. | 2009-04-30 |
| 20090113195 | System and Method for Extension of the BIOS Boot Specification - A system and method is disclosed for extending the BIOS Boot Specification. The specification is extended to accommodate the identification of a greater number of bootable devices. The specification is also extended so that the identifier for each bootable device identifies the default boot order of the device. The specification is also extended to provide additional information about the type of each bootable device and whether each bootable device is an onboard or add-in device. The extension of the BIOS Boot Specification also allows for the designation of certain entries as placeholders for devices that that are supported by the computer system, but not present in the computer system. | 2009-04-30 |
| 20090113196 | Method and systems for advanced reprogrammable boot codes and in-application programming of embedded microprocessor systems - This invention relates to an advanced system and method of reprogrammable boot codes and In Application Programming (IAP) of embedded systems by booting up with boot loader to shadow program codes on to an internal high speed SRAM and extending contiguously to external higher space memory for runtime applications, and supporting on-line IAP to update run-time firmware or boot loader driver through network communication by utilizing advanced address remapping scheme as well as supporting In System Programming (ISP) to program initial Flash memory via ISP adaptor. | 2009-04-30 |
| 20090113197 | EXPEDIENT PREPARATION OF MEMORY FOR VIDEO EXECUTION - A computer system that initializes a fraction of the computer system's memory for execution of video during booting of the computer system is provided. The computer system can include a first portion of BIOS code on a ROM device, wherein the first portion includes instructions for initializing the fraction. The computer system further can include a second portion of BIOS code that copies itself to the fraction upon completion of initialization of the fraction, wherein the second portion executes on the fraction and wherein the second portion initializes system memory and initializes a video buffer. The computer system further can include a copy of the second portion located on the ROM device, wherein the copy of the second portion executes until video buffer initialization is completed but before all of the system memory is initialized. Further, the video buffer displays video before all of the computer system's memory is initialized. | 2009-04-30 |
| 20090113198 | Methods, Systems and Media for Configuring Boot Options - Implementations described herein generally provide methods of configuring boot options. One method may generally include receiving on a remote management information handling system (IHS), boot information relating to a remotely configured HIS, using the boot information on the remote management IHS to create boot options and sending the boot options from the remote management IHS to the remotely configured IHS. | 2009-04-30 |
| 20090113199 | METHOD FOR AUTOMATIC INTEGRATION AND PERSISTENT STORAGE OF A PRIORI VOLATILE PERSONALIZING PARAMETERS. - The invention concerns a method for persistent storage of personalizing parameter values of at least one logical process of management of a priori volatile data characterized in that it consists in creating in a first step one or more insertions into one or more loading and/or initializing sequences of said logical processes of management of data to be personalized, of at least one logical sub-process of data management which reads the personalizing parameter values previously saved, each of the insertions being arranged in chronological order after the corresponding previously saved personalizing parameter values are accessible for reading, each of the insertions being arranged in chronological order before said values are integrated by said logical processes of management of data to be personalized, the logical sub-processes being capable of efficiently saving the personalizing parameter values which they process on non volatile data media, so as to integrate the modifications of said values upon subsequent readings. | 2009-04-30 |
| 20090113200 | STEGANOGRAPHIC TECHNIQUES FOR SECURELY DELIVERING ELECTRONIC DIGITAL RIGHTS MANAGEMENT CONTROL INFORMATION OVER INSECURE COMMUNICATION CHANNELS - Electronic steganographic techniques can be used to encode a rights management control signal onto an information signal carried over an insecure communications channel. Steganographic techniques ensure that the digital control information is substantially invisibly and substantially indelibly carried by the information signal. These techniques can provide end-to-end rights management protection of an information signal irrespective of transformations between analog and digital. An electronic appliance can recover the control information and use it for electronic rights management to provide compatibility with a Virtual Distribution Environment. In one example, the system encodes low data rate pointers within high bandwidth time periods of the content signal to improve overall control information read/seek times. | 2009-04-30 |
| 20090113201 | SCALEABLE ARCHITECTURE TO SUPPORT HIGH ASSURANCE INTERNET PROTOCOL ENCRYPTION (HAIPE) - A scalable internet protocol (IP) encryption system includes a cryptographic unit that processes sensitive data for packet encryption/decryption and data authentication. A first processing unit with an optional IP Layer hardware accelerator includes a data processing subsystem that processes sensitive data and forwards the data to the cryptographic unit for encryption and data authentication. A management subsystem is operative with the cryptographic unit for configuring IP networking functions and distributing network configuration information to the data processing subsystem through the cryptographic unit. Data processing is separated from management and control functions at the data processing and management subsystems. A second processing unit with an optional IP Layer hardware accelerator receives the encrypted data from the cryptographic unit and processes the encrypted data for IP packet routing, fragmentation and reassembly and receives network configuration information from the management subsystem via the cryptographic unit. | 2009-04-30 |
| 20090113202 | System and method for providing secure network communications - A method includes receiving a data message, from a first embedded node, in a first end point device. The first data message is addressed to a second embedded node. The method also includes encrypting the first data message to produce an encrypted data message, where the encryption is transparent to the first embedded node. The method further includes transmitting the encrypted data message to a second end point device. An apparatus includes a plurality of embedded node ports each configured to communicate with an embedded node. The apparatus also includes an encrypted communications link port configured to communicate with an end point device. The apparatus further includes a controller connected to communicate with the embedded node ports and the encrypted communications link port. In addition, the apparatus includes a storage connected to be read from and written to by the controller. | 2009-04-30 |
| 20090113203 | Network System - An encryption communication module on the side of a service providing server reports a global IP address allocated to an NAPT router on the service providing server side and a port number of an outside UDP header used on the global side to an authentication/key exchange server. When receiving an encryption packet from an encryption communication module on the user terminal side, the encryption communication module on the service providing server side overwrite a source/destination IP address of an inside IP header by a source/destination IP address of an outside IP header. The encryption communication module further changes a source port number of an inside TCP•UDP header to a unique value for each communication session in the encryption communication having the same source IP address in the outside IP header. The inverse header change is made when the packet is transmitted to the encryption communication module of the user terminal side. | 2009-04-30 |
| 20090113204 | Secure Messaging - A method for secure communication of a message. The method includes providing a message including a plurality of message packets, providing a nodal network including a plurality of nodes, where nodal operations are capable of execution on the message packets at the nodes, gaining, by a first node of the network, a first message packet, processing the first message packet by the first node, relinquishing the first message packet as processed by the first node, gaining, by any other node of the network, at least one other message packet, processing the other message packet by the other node, relinquishing the other message packet as processed by the other node, receiving, by a message destination node of the network, a first message packet, receiving, by the message destination node, at least a second message packet, and processing the first message packet and the second message packet to provide a reproduced message. | 2009-04-30 |
| 20090113205 | METHOD AND APPARATUS FOR THE SECURE IDENTIFICATION OF THE OWNER OF A PORTABLE DEVICE - An authentication system is provided that includes a portable device and a decryption node. An individual uses the portable device, such as a portable device like a cell phone to compute a challenge and a response. The challenge and response is sent to a decryption node. In response, the decryption node computes a presumed response and compares the presumed response to the response of the portable device, in order to authenticate the individual associated with the portable device. | 2009-04-30 |
| 20090113206 | Revocation List Improvement - A method for enforcing use of certificate revocation lists in validating certificates, the lists being associated with a series of list generation indices such that each list is assigned one index which advances according to a time of generation of the list, the lists and the indices being cryptographically signed, the method including receiving one of the lists and an associated index as an identifier of the one list, checking the certificates against the list, associating each of the certificates, which have been checked against the list, with the index, receiving an enforcement generation index (EGI) associated with a latest list in use, storing the EGI as a last known EGI, and refusing performance of an action associated with a certificate if the one index of the one certificate is earlier in the series than the last known EGI. Related apparatus and methods are also included. | 2009-04-30 |
| 20090113207 | SECURE OVERLAY MANAGER PROTECTION - A method for protection of data includes maintaining a control parameter indicative of a current version of the data. The data is partitioned into multiple segments. Respective signatures of the segments are computed, responsively to the control parameter, the segments and respective signatures forming respective signed input segments, which are stored in a memory. After the signed input segments are stored, a signed output segment is fetched from the memory. The signature of the signed output segment is verified responsively to the control parameter, and the data in the signed output segment is processed responsively to verifying the signature. | 2009-04-30 |
| 20090113208 | WIRELESS NETWORK HAVING MULTIPLE COMMUNICATION ALLOWANCES - Multiple levels of wireless network resource granting. A user who has an authorized key, e.g., an encryption key or a key indicating that they have paid for service, gets a first, better level of access to the network resources. One without the key is granted lesser access, e.g., less total bandwidth, less bandwidth speed, no access to files or the like. | 2009-04-30 |
| 20090113209 | BIOMETRIC AUTHENTICATION METHOD - Provided is a biometric authentication method. A biometric authentication method in accordance with an aspect of the present invention includes generating a first one-time authentication template from biometric information using one-time transform information, and requesting authentication, comparing the first one-time authentication template with a one-time registration template, updating the one-time registration template and the one-time transform information when authentication is achieved according to a result of the comparison, wherein the updated one-time transform information is used to generate a second one-time authentication template to be authenticated according to the result of the comparison with the updated one-time registration template when successive authentication is requested. | 2009-04-30 |
| 20090113210 | Program and operation verification - A security module may be used to verify integrity of an executable program and may also be used to verify execution of the executable program on a computer. The security module may directly read a computer memory by asserting bus master control of a system bus. The executable program may be directly verified by calculating a hash or may be indirectly verified by an intermediate program that calculates the hash and passes it to the security module. To verify operation, the executable program may cause an interrupt to be generated when the executable program is in a known state. An interrupt service routine may trigger the security module to read registers in the computer processor via a debug port. If either the verification of the executable program fails or the register values are inconsistent with operation of the executable program, the security module may interrupt operation of the computer. | 2009-04-30 |
| 20090113211 | PROCESSING UNIT INCLUDING A WIRELESS MODULE AND METHOD THEREOF - A processing unit includes a processing core and a wireless module directly connected to the processing core, wherein the wireless module is for providing wireless communications to the processing core. A multi-processor system includes a first processing unit having a first processing core and a first wireless module directly connected to the first processing core, the first wireless module for providing wireless communications to the first processing core; a second processing unit having a second processing core and a second wireless module directly connected to the second processing core, the second wireless module for providing wireless communications to the second processing core; and a wireless link between the first and second wireless modules; wherein the first processing unit is for communicating with the second processing unit via the wireless link. | 2009-04-30 |
| 20090113212 | Multiprocessor electronic circuit including a plurality of processors and electronic data processing system - A multiprocessor electronic circuit and an electronic data processing system comprising such circuit are disclosed for reducing the power consumption and the chip area consumption of a multiprocessor system having cryptographic functionality. In one embodiment, the multiprocessor electronic circuit comprises a plurality of processors, a single cryptographic processing unit that comprises a plurality of input/output buffer pairs and two cryptographic engines, a cipher engine and a hash engine, and associated control logic. | 2009-04-30 |
| 20090113213 | SYSTEM AND METHOD FOR SEARCHING ENCRYPTED NUMERICAL DATA - A system for searching encrypted numerical data according to an embodiment of the present invention includes: a key generator that generates a key for encryption; an index generator that generates an index for documents from a plurality of documents including numerical data and the generated key, on the basis of individual digits of the numerical data and the positions of the digits; a trapdoor generator that generates a trapdoor including search information on the individual digits of the numerical data and the positions of the digits, using the generated key; and a document searching unit that receives numerical data for search, searches the index using the trapdoor, and outputs document information including the numerical data for search. | 2009-04-30 |
| 20090113214 | SOFTWARE PROTECTION AGAINST FAULT ATTACKS - A method for protecting information in a device includes providing a device with a non-secure hardware domain, a processor having a software-controlled mode of operation, and a secure hardware domain having a secure memory that is inaccessible by the processor when the processor is operating in the software-controlled mode of operation. Data from the non-secure hardware domain is established in the secure hardware domain. Computing operations are executed on the data in the secure hardware domain to produce a result. The secure hardware domain is purged, while retaining the result therein. The result is thereafter returned from the secure hardware domain into the non-secure hardware domain. | 2009-04-30 |
| 20090113215 | FAST UPDATE FOR HIERARCHICAL INTEGRITY SCHEMES - A method for data integrity protection includes arranging data in a plurality of data blocks. A respective block signature is computed over each of the data blocks, thereby generating multiple block signatures. The data blocks and the block signatures in an integrity hierarchy are stored in a storage medium, the hierarchy comprising multiple levels of signature blocks containing signatures computed over lower levels in the hierarchy, culminating in a top-level block containing a top-level signature computed over all of the hierarchy. A modification is made in the data stored in a given data block within the hierarchy. The respective block signature of the given data block is recomputed in response to the modification, and the recomputed block signature is stored in the top-level block for use in verifying a subsequent requests to read data from the given data block. | 2009-04-30 |
| 20090113216 | CRYPTOGRAPHIC MULTI-SHADOWING WITH INTEGRITY VERIFICATION - A virtual-machine-based system that may protect the privacy and integrity of application data, even in the event of a total operating system compromise. An application is presented with a normal view of its resources, but the operating system is presented with an encrypted view. This allows the operating system to carry out the complex task of managing an application's resources, without allowing it to read or modify them. Different views of “physical” memory are presented, depending on a context performing the access. An additional dimension of protection beyond the hierarchical protection domains implemented by traditional operating systems and processors is provided. | 2009-04-30 |
| 20090113217 | MEMORY RANDOMIZATION FOR PROTECTION AGAINST SIDE CHANNEL ATTACKS - Side channel attacks against a computing device are prevented by combinations of scrambling data to be stored in memory and scrambling the memory addresses of the data using software routines to execute scrambling and descrambling functions. Encrypted versions of variables, data and lookup tables, commonly employed in cryptographic algorithms, are thus dispersed into pseudorandom locations. Data and cryptographic primitives that require data-dependent memory accesses are thus shielded from attacks that could reveal memory access patterns and compromise cryptographic keys. | 2009-04-30 |
| 20090113218 | SECURE DATA PROCESSING FOR UNALIGNED DATA - A method for data cryptography includes accepting input data, which contains a section that is to undergo a cryptographic operation and starts at an offset with respect to a beginning of the input data, by a Direct Memory Access (DMA) module. The input data is aligned by the DMA module to cancel out the offset. The aligned input data is read out of the DMA module, and the cryptographic operation is performed on the section. | 2009-04-30 |
| 20090113219 | OPTIMIZED HIERARCHICAL INTEGRITY PROTECTION FOR STORED DATA - A method for data integrity protection includes receiving items of data for storage in a storage medium. The items are grouped into multiple groups, such that at least some of the groups include respective pluralities of the items. A respective group signature is computed over each of the groups, thereby generating multiple group signatures. An upper-level signature is computed over the group signatures. Groups of the items, the group signatures, and the upper-level signature are stored in respective locations in the storage medium. | 2009-04-30 |
| 20090113220 | ENCRYPTED BACKUP DATA STORAGE DEVICE AND STORAGE SYSTEM USING THE SAME - An encrypted backup data storage device and a storage system using the same are provided. A backup memory stores at least one of plain-text data and a secret key. A leakage current blocking circuit includes at least one inverter and a complementary metal oxide semiconductor (CMOS) NAND gate circuit and cuts off leakage current paths formed by the lines connected to the battery backup memory. | 2009-04-30 |
| 20090113221 | COLLABORATIVE POWER SHARING BETWEEN COMPUTING DEVICES - A plurality of power budgets are sent to a corresponding plurality of power consumers by a power management point, wherein a total power budget managed by the power management point includes a sum of the plurality of power budgets and an available power budget not assigned to the plurality of power consumers. An additional power request having a power increase amount is received from a first power consumer of the plurality of power consumers. The additional power request is approved when the power increase amount does not exceed the available power budget. The available power budget is decreased by the power increase amount. An approval of the additional power request is sent to the first power consumer. | 2009-04-30 |
| 20090113222 | TERMINAL HAVING REAL TIME CLOCK (RTC) OPERATOR AND METHOD OF RTC OPERATION USING THE SAME - A method of operating a Real Time Clock (RTC) in a terminal is provided. The method includes detecting a clock signal transmitted to an RTC block when the main power supply is switched off, and supplying a power to the RTC block for its operation by charging and discharging the power periodically supplied from the backup battery according to the detected clock signal. A DC/DC converter connected to a backup battery is periodically switched on and off, and a capacitor is charged and discharged using the power of the backup battery, thereby avoiding supplying power from a backup battery continuously to an RTC block. Therefore, power consumption is reduced and a duration of time for maintaining RTC data is extended. | 2009-04-30 |
| 20090113223 | APPARATUS AND METHOD FOR POWER SAVING - An apparatus and method for power savings are provided. The apparatus includes a register analysis unit and a register change unit. The register analysis unit determines if registers among bit-switching targeted registers are one of changeable and unchangeable. The register change unit searches for a register pair having a minimum bit switching frequency among registers determined to be changeable, and changes at least one register. | 2009-04-30 |
| 20090113224 | Method of operation of a portable computer apparatus with thermal enhancements and multiple modes of operation - A portable computer adapted for electrical connection to a docking station having multiple power modes of operation is described. The portable computer has one or more CPU chips which have at least two power modes of operation, a low power mode and a high power mode. When the portable computer is operated as a stand-alone computer, it operates in the low power mode. When the portable computer is operated while electrically connected to the docking station, it operates in a high power mode. The docking station has greater cooling capacity than the portable computer alone to provide enhanced cooling of the high power mode of operation. | 2009-04-30 |
| 20090113225 | Method of operations of a portable computer apparatus with thermal enhancements and multiple modes of operation - A portable computer adapted for electrical connection to a docking station having multiple power modes of operation is described. The portable computer has one or more CPU chips which have at least two power modes of operation, a low power mode and a high power mode. When the portable computer is operated as a stand-alone computer, it operates in the low power mode. When the portable computer is operated while electrically connected to the docking station, it operates in a high power mode. The docking station has greater cooling capacity than the portable computer alone to provide enhanced cooling of the high power mode of operation. | 2009-04-30 |
| 20090113226 | Portable computer apparatus with thermal enhancements and multiple modes of operation - A portable computer adapted for electrical connection to a docking station having multiple power modes of operation is described. The portable computer has one or more CPU chips which have at least two power modes of operation, a low power mode and a high power mode. When the portable computer is operated as a stand-alone computer, it operates in the low power mode. When the portable computer is operated while electrically connected to the docking station, it operates in a high power mode. The docking station has greater cooling capacity than the portable computer alone to provide enhanced cooling of the high power mode of operation. | 2009-04-30 |
| 20090113227 | Method of operation of a portable computer apparatus with thermal enhancements and multiple modes of operation - A portable computer adapted for electrical connection to a docking station having multiple power modes of operation is described. The portable computer has one or more CPU chips which have at least two power modes of operation, a low power mode and a high power mode. When the portable computer is operated as a stand-alone computer, it operates in the low power mode. When the portable computer is operated while electrically connected to the docking station, it operates in a high power mode. The docking station has greater cooling capacity than the portable computer alone to provide enhanced cooling of the high power mode of operation. | 2009-04-30 |
| 20090113228 | Portable computer systems with thermal enhancements and multiple power modes of operation - A portable computer adapted for electrical connection to a docking station having multiple power modes of operation is described. The portable computer has one or more CPU chips which have at least two power modes of operation, a low power mode and a high power mode. When the portable computer is operated as a stand-alone computer, it operates in the low power mode. When the portable computer is operated while electrically connected to the docking station, it operates in a high power mode. The docking station has greater cooling capacity than the portable computer alone to provide enhanced cooling of the high power mode of operation. | 2009-04-30 |
| 20090113229 | METHOD AND A SYSTEM FOR SYNCHRONISING RESPECTIVE STATE TRANSITIONS IN A GROUP OF DEVICES - A method of synchronizing respective state transitions in a group of devices including at least one responding device is disclosed. The group of devices is communicatively coupled to an initiating device via a communication network. The method includes the at least one responding device receiving a trigger message from the initiating device. The trigger message includes a state transition time or a time from which a state transition time is obtainable. The method further includes the at least one responding device jointly making a respective state transition at the state transition time. A responding device, and a system including the initiating device and the responding device are also disclosed. | 2009-04-30 |
| 20090113230 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A scan chain group structure in which a group of scan chains formed for each clock tree system in an LSI is subjected to a reconnection process so that the scan chain group is not present across a plurality of clock distribution regions obtained by dividing the clock-supplied region of the clock tree of one system and that the connection distance thereof in the distribution region becomes short, a test clock input mechanism in which test clocks to be input to the distribution regions are independent sub-clock phases, and an on/off mechanism of the clocks to be input to the distribution regions are realized. Further, the scan-in/out and scan test performed at the same time are limited in one region or between single regions, and tests in all regions and between all regions are carried out by a plurality of times of test steps. | 2009-04-30 |
| 20090113231 | DATA PROCESSING DEVICE AND MOBILE DEVICE - A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card. | 2009-04-30 |
| 20090113232 | APPARATUS AND METHOD FOR MANAGING WIRELESS SENSOR NETWORK - An apparatus for managing a plurality of wireless sensor networks selects a configuring policy according to a characteristic of each wireless sensor network and configures a network with the selected configuring policy for management. When an error occurs in the wireless sensor network, the apparatus performs error diagnosis based on a configuring policy applied to the error-detected wireless sensor network, infers a cause of the error, and provides an error recovery method corresponding to the inferred cause of the error to the error-detected wireless sensor network. | 2009-04-30 |
| 20090113233 | Testing Disaster Recovery Elements - Testing disaster recovery elements can be performed by configuring a disaster recovery site with network addresses to disaster recovery elements at an application layer. End-to-end operation of the disaster recovery site is verified using the network addresses at the application layer. The disaster recovery site is verified while an associated production site is operating. | 2009-04-30 |
| 20090113234 | VIRTUALIZATION SWITCH AND METHOD FOR CONTROLLING A VIRTUALIZATION SWITCH - A virtualization switch includes first communication line connection terminals which can be connected to a host computer, a physical storage apparatus or a plurality of physical storage apparatuses, and another virtualization switch, a second communication line connection terminal which can be connected to a single line concentrator or a plurality of line concentrators connected to a manager computer by a second communication line a storage virtualization unit, a first communication unit which can communicate with an other virtualization switch through a first communication line, second communication unit which can communicate with the other virtualization switch through an second communication line, second communication line monitor unit which test communication between the virtualization switch, and abnormal state coping unit which executes a closing process and causes the first communication unit to output a failover designation instruction. | 2009-04-30 |
| 20090113235 | RAID WITH REDUNDANT PARITY - Methods and apparatus of the present invention include storing redundant parity information in storage devices that are configured in a RAID array. Conventional hard disk drives are configured to store data in RAID 3 or RAID 4 data layouts. A storage controller is configured to generate the parity information for the data written to the hard disk drives. One or more of the devices storing the parity information may be a flash storage device. | 2009-04-30 |
| 20090113236 | DISK MANAGEMENT METHOD, DISK MANAGEMENT DEVICE AND STORAGE SYSTEM - A disk management method for managing a disk management device for writing and reading data to and from a disk drive in which a recording medium is managed in a first control unit. The disk management method includes an error checking operation for checking an error on the recording medium in the first control unit, an error correction operation for correcting the error detected in the error, an error correcting operation for correcting the error detected in the error checking operation after converting data including the error to the second control unit, a data loss registration operation for registering a region in which data are lost due to an inconsistency between the first control unit and second control unit in a data loss region table, and a data loss recovery operation for recovering the loss of data with reference to the data loss region table. | 2009-04-30 |
| 20090113237 | STORAGE CONTROL DEVICE, STORAGE CONTROL METHOD AND STORAGE CONTROL PROGRAM - A storage control device includes a first rebuilding unit rebuilding information stored in one of a plurality of storages that fails by using information stored in the plurality of storages excluding said failed storage and storing rebuilt information in a spare storage replaced with the failed storage, a second rebuilding unit rebuilding information stored in two of said plurality of storages that fail by using information stored in said plurality of storages excluding the two failed storages and storing rebuilt information in two spare storages replaced with the two failed storages, and a rebuilding control unit for controlling said first rebuilding unit and second rebuilding unit where one of said spare storages fails during rebuilding the data stored in said two failed storages to replace the failed spare storage with other spare storage whereby said second rebuilding unit continues rebuilding the data. | 2009-04-30 |
| 20090113238 | POWER FAILURE MANAGEMENT FOR RESPIRATORY SYSTEM HEATER UNIT - A heater unit includes power failure management to detect disruptions in the electrical power supply, such as the AC supply, for the unit. The heater unit emits an audible alarm in response to detection of such a disruption, and may shut down the heater(s) and visuals display(s). The heater unit advantageously includes a power storage device, such as a super-capacitor, to temporarily power the electronic circuitry of the heater unit. Operating parameters, such as of a processor of the electronic circuitry, may be stored in a non-volatile memory response to the disruption, and recalled if the disruption terminates before the level of power has gotten too low to sustain reliable operation of the processor. | 2009-04-30 |
| 20090113239 | METHOD AND APPARATUS FOR INSTRUCTION TRACE REGISTERS - A computer implemented method, apparatus, and computer usable program product for utilizing instruction trace registers. In one embodiment, a value in a target processor register in a plurality of processor registers is updated in response to executing an instruction associated with program code. In response to updating the value in the target processor register, an address for the instruction is copied from an instruction address register into an instruction trace register associated with the target processor register. The instruction trace register holds the address of the instruction that updated the value stored in the target processor register. | 2009-04-30 |
| 20090113240 | Detecting Soft Errors Via Selective Re-Execution - In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed. | 2009-04-30 |
| 20090113241 | METHOD, SYSTEM, AND APPARATUS FOR PROVIDING ALERT SYNTHESIS IN A DATA PROTECTION SYSTEM - A method for diagnosing problems with protection of a data source and recovery of the same. The method includes diagnosing a copy of data located at the storage location and diagnosing a temporal version of the copy of data. Based on the diagnosis it is determined whether an error or a warning was detected. If either were detected a response is provided with a suggested solution. | 2009-04-30 |
| 20090113242 | Dynamic Partitioning of Event Patterns for Determining Symptoms - Events experienced by resources are locally processed by secondary autonomic managers into consolidated events. These consolidated events are then transmitted to a primary autonomic manager, which recognizes symptoms of conditions found in a computer system that utilizes the resources. The primary autonomic manager is thus able to leverage information in a symptom catalog to process the consolidated events to recognize such symptoms. | 2009-04-30 |
| 20090113243 | Method, Apparatus and Computer Program Product for Rule-Based Directed Problem Resolution for Servers with Scalable Proactive Monitoring - Method, apparatus and computer program product are configured to perform computer monitoring activities; to collect information regarding computer system status during the computer monitoring activities; to detect a problem in dependence on the information collected during the computer monitoring activities; and to determine whether to launch a diagnostic probe when the problem is detected. The monitoring activities may be performed on a periodic or event-driven basis. The determination whether to launch a diagnostic probe is based on a rule included in a hierarchy of rules. The hierarchy of rules is based on problem tickets; system logs; and computer system configuration information. | 2009-04-30 |
| 20090113244 | Diagnostic Functionality for Wireless Client Connectivity Problems in Wireless Networks - A troubleshooting system. In particular implementations, a method includes collecting, from a first wireless network element, PEM state associated with a wireless client having a connection problem, and collecting log data associated with the wireless client from the first wireless network elements and one or more other wireless network elements. The method further includes correlating the PEM state and log data based on a network security protocol employed by the wireless client, where the network security protocol corresponds to an expected sequence of events. The correlating includes correlating events and messages collected based on the expected sequence of events, and comparing the correlated sequence of events to a data store of diagnostic information to identify one or more possible causes of the connection problem. | 2009-04-30 |
| 20090113245 | PROTOCOL AWARE DIGITAL CHANNEL APPARATUS - In one embodiment, provided is a protocol specific circuit for simulating a functional operational environment into which a device-under-test is placed for functional testing. The protocol specific circuit includes a protocol aware circuit constructed to receive a non-deterministic signal communicated by a device-under-test and to control a transfer of the test stimulus signal to the device-under-test in response to the a non-deterministic signal. | 2009-04-30 |
| 20090113246 | Apparatus for and Method of Implementing system Log Message Ranking via System Behavior Analysis - A novel and useful method for enabling system logs to be effectively and efficiently monitored by ranking the system log messages by their estimated value to administrators and generating a log view that displays the most important messages. The ranking process uses a dataset of system logs from many computer systems to score messages. For better scoring, unsupervised clustering is used to identify sets of systems that behave similarly. The expected distribution of messages in a given system is estimated using the resulting clusters, and log messages are scored using this estimation. | 2009-04-30 |
| 20090113247 | FAILURE DIAGNOSIS DEVICE, PROGRAM AND STORAGE MEDIUM - A failure diagnosis device, program and storage medium are provided, which are capable of automatically generating FTA and/or FMEA from MFM. An FTA generating section generates an FTA knowledge by reading out, from an HD, an MFM knowledge systematically and organically representing goals, functions, relations between the functions, relations between the functions and goals, and relations between the functions and components realizing the functions; an MFM attendant knowledge including a component behavior knowledge representing relations between failures and behaviors of components when failure occurs in the component; and an influence-repercussion rule defining the influence exerting when the function is changed. An FMEA generating section generates an FMEA knowledge by reading out the MFM knowledge, the MFM attendant knowledge, and the influence-repercussion rule from the HD. | 2009-04-30 |
| 20090113248 | COLLABORATIVE TROUBLESHOOTING COMPUTER SYSTEMS USING FAULT TREE ANALYSIS - Embodiments of the invention provide techniques for troubleshooting of computer systems using a fault tree analysis. In one embodiment, data parameters describing a status of a system may be monitored to determine the existence of a fault. In the event of a fault, fault tree analysis metadata may be evaluated to attempt to determine a root cause of the fault. If a root cause can be automatically determined, it may be presented to a user in a troubleshooting console, or may be used to trigger an automated corrective action. Alternatively, if a root cause cannot be automatically determined, the user may be presented with additional fault tree analysis metadata and any relevant data parameters in the troubleshooting console, so that the user may determine the root cause of the fault event. | 2009-04-30 |
| 20090113249 | Stress testing method of file system - A stress testing method of a file system includes traversing local or network storage devices with a drive letter; detecting a network mapping path of the network storage devices; calculating an absolute path of all the storage devices through a mounted point and a system volume; collecting the above information to update the path information of the file system; and then calling a corresponding test algorithm and stressing strategy according to different types of storage devices, so as to perform the stress test. The stress testing method can make the file system display storage devices without a drive letter, and call appropriate testing methods and stressing strategies for different types of storage devices, so the depth and scope of the stress testing for file system are expanded, the accuracy of the test is enhanced, and the problem of occupying too many system resources is avoided. | 2009-04-30 |
| 20090113250 | SERVICE TESTING - Communication symmetry is leveraged to facilitate testing of network services. To identify, isolate, understand, and resolve problems a test client is employed. In accordance with one aspect, a service can be provided for execution on a service consumer while the test client resides on a service provider. Roles are reversed to provide more testing freedom on the provider side and less intrusion on the consumer side. Additionally or alternatively, a service and/or test client can be shipped to consumers to aid testing in a real execution environment | 2009-04-30 |
| 20090113251 | REAL-TIME ANALYSIS OF PERFORMANCE DATA OF A VIDEO GAME - A method for analyzing the performance of a video game uses a diagnostic tool that is associated with application code of the video game. The diagnostic tool is activated when the video game is in operation, and real-time performance data is captured and displayed. A warning is generated when a performance metric violates a pre-set condition. The warning may be displayed on a display screen that is used to provide information for rectifying the violation. | 2009-04-30 |
| 20090113252 | FAULT DETECTION IN EXPONENTIATION AND POINT MULTIPLICATION OPERATIONS USING A MONTGOMERY LADDER - A system and method are provided enabling implicit redundancies such as constant differences and points that should be on the same curve, to be checked at the beginning, end and intermittently throughout the computation to thwart fault injection attacks. This can be implemented by checking the constant difference in point pairs during point multiplication, by checking constant scalings in exponentiation pairs, and by checking that any intermediate point is on the curve and/or in the correct subgroup of the curve. | 2009-04-30 |
| 20090113253 | SYSTEM AND APPARATUS FOR DELIVERING MEDIA AND METHOD FOR PLAYING STREAMING MEDIA - A media delivery system includes a media manager (MM) a central server that supports peer to peer (P2P) technology (CS-P), a request routing system that supports P2P technology (RRS-P), and an edge server that supports P2P technology (ES-P) and multiple P2P clients. A method for playing streaming media based on the above media delivery system includes: the MM publishes a live channel notification to the CS-P, RRS-P, and ES-P; the CS-P obtains streaming data packets from a live source and parses and slices the packets to generate slice data; the ES-P obtains the slice data from the CS-P and/or other ES-Ps that are able to provide slice data and caches the slice data; and the P2P client obtains the slice data from the ES-P or other P2P clients and delivers the data, or the data is played by a local player after an assembly operation by the P2P client. With the P2P technology, the present invention improves the prior media delivery network and realizes the playing of streaming media to a large number of clients. | 2009-04-30 |
| 20090113254 | System management apparatus and method for multi-shelf modular computing system - The invention provides a system management apparatus for a multi-shelf modular computing system. The system management apparatus receives and parses an alert information in response to an abnormal parameter/state relative to a component of the multi-shelf modular computing system sent from a shelf management device of the multi-shelf modular computing system, and stores the parsed alert information into a storage module. Then, the system management apparatus periodically retrieves the parsed alert information, if any, from the storage module and generates a visual alert information indicating the abnormal parameter/state. Thereby, a user can view the visual alert information to perceive the abnormal parameter/state rapidly and intuitively, so as to take corresponding measures. | 2009-04-30 |
| 20090113255 | Software Fault Detection Using Progress Tracker - The invention provides for software fault detection. A software process tracks its own progress. In the event the timer times out, a handler checks the progress. If the progress meets a fault criterion, a fault response is executed. | 2009-04-30 |
| 20090113256 | Method, computer program product, apparatus and device providing scalable structured high throughput LDPC decoding - The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Decoding is performed in a pipelined manner using a layered belief propagation technique and scalable resources, which are configurable to accommodate at least two codeword lengths and at least two code rates. A computer program product, apparatus and device are also described. | 2009-04-30 |
| 20090113257 | DEVICE AND METHOD FOR TESTING SAS CHANNELS - A device and a method for testing SAS channels which are applied to a plurality of pairs of SAS interfaces. The testing device includes a control terminal, a PCI-E microprocessor, a PCI-E-to-SAS adaptor, and a signal feedback module. The control terminal is used for selecting SAS channels and sending a control command; the PCI-E microprocessor is used for receiving the control command and sending a test signal to a PCI-E channel according to the control command; the PCI-E-to-SAS adaptor is used for converting a transmission signal between the PCI-E channel and the SAS channels; and the signal feedback module is used for connecting a first SAS interface to a second SAS interface in the SAS back plate. The PCI-E microprocessor compares whether the test signal sent to the first SAS channel is consistent with the test signal received from the second SAS interface. | 2009-04-30 |
| 20090113258 | Method and system for testing devices using loop-back pseudo random datat - There is provided a method of testing a first device using a tester. The method comprises receiving test data having a pattern by the first device from the tester; detecting the pattern of the test data by the first device; generating first data, by the first device, according to the pattern detected by the detecting; comparing the test data with the pattern detected by the detecting; determining errors in the test data, by the first device, based on the comparing; inserting the errors into the first data to generate error-inserted first data; and transmitting the error-inserted first data by the first device to the tester. The method may further comprise generating a first clock at the first device; wherein the transmitting uses the first clock for transmitting the error-inserted first data. | 2009-04-30 |
| 20090113259 | MEMORY CELL PROGRAMMING - Embodiments of the present disclosure provide methods, devices, and systems for performing a programming operation on an array of non-volatile memory cells. One method includes programming a number of cells to a number of final data states. The method includes performing, prior to completion of, e.g., finishing, the programming operation, an erase state check on a subset of the number of cells, which were to be programmed to an erased state. | 2009-04-30 |
| 20090113260 | TEST SYSTEM - A test system for testing a plurality of devices under test is disclosed. The test system includes a tester and a plurality of processors. The tester is used for providing a plurality of control signals and determining a plurality of test results for the devices under test according to a plurality of measurement results. Each processor coupled to the tester is used for generating a plurality of test signals according to the plurality of control signals. The plurality of devices under test respectively generates the plurality of test results according to the plurality of test signals. | 2009-04-30 |
| 20090113261 | CONVERSION DEVICE, CONVERSION METHOD, PROGRAM, AND RECORDING MEDIUM - Provided are a conversion device and the like for converting a initial test pattern given in advance into a test pattern of a bit constitution of different logic values, without losing the fault coverage of transition delay fault which can be detected by the constitution element of the initial test pattern. The conversion device converts an initial test pattern | 2009-04-30 |
| 20090113262 | SYSTEM AND METHOD FOR CONDITIONING AND IDENTIFYING BAD BLOCKS IN INTEGRATED CIRCUITS - An electronic system of an Integrated circuit (IC) for conditioning and identification of bad blocks in the IC is disclosed. The electronic system includes at least one cyclic scan chain and at least one multiplexer. A cyclic scan chain includes a plurality of flip-flops, which are connected in a cascaded manner. A multiplexer is connected between two adjacent flip-flops of the cyclic shift register. The multiplexer has a first input pin connected to output of a first flip-flop, a second input pin connected to a user pin and an output pin connected to an input of a second flip-flop. The multiplexer is configured to condition the plurality of flip-flops through the user pin by programming logic bits in the plurality of flip-flop. The output of the first flip-flop is configured to read the logic bits in the plurality of flip-flops to identify a bad block in the IC. | 2009-04-30 |
| 20090113263 | METHODS FOR ANALYZING SCAN CHAINS, AND FOR DETERMINING NUMBERS OR LOCATIONS OF HOLD TIME FAULTS IN SCAN CHAINS - In a method for determining a number of possible hold time faults in a scan chain of a DUT, an environmental variable of the scan chain is set to a value believed to cause a hold time fault in the scan chain, and then a pattern is shifted through the scan chain. The pattern has a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is a length of the scan chain. The number of possible hold time faults in the scan chain can be determined as a difference between i) a clock cycle when the at least one bit is expected to cause a transition at an output of the scan chain, and ii) a clock cycle when the at least one bit actually causes a transition at the output of the scan chain. If a value of the environmental variable at which the scan chain operates correctly can be determined, the location of one or more hold time faults can also be determined. | 2009-04-30 |
| 20090113264 | BUILT IN SELF TEST FOR INPUT/OUTPUT CHARACTERIZATION - A test system in an integrated circuit includes at least one boundary scan cell. The boundary scan cell includes a first storage element and a second storage element connected in series with the first storage element. The boundary scan cell also includes test logic configured to provide a test completion signal indicative of completion of a respective test based on a comparison of an output of the first storage element relative to test value (TVALUE). The output of the first storage element is provided to the input of the second storage element unchanged during a first operating state and, depending on the test completion signal, an inverted version of the output of the first storage element can be provided to the input of the second storage element during a second operating state. A bi-directional element is connected to receive the output of the second storage element and to feed the output of the second storage element back to an input of the first storage element. | 2009-04-30 |
| 20090113265 | LOCATING HOLD TIME VIOLATIONS IN SCAN CHAINS BY GENERATING PATTERNS ON ATE - A method for determining that failures in semiconductor test are due to a defect potentially causing a hold time violation in a scan cell in a scan chain, counting the number of potential defects, and, if possible, localizing, and ameliorating hold time defects in a scan chain. | 2009-04-30 |
| 20090113266 | COMPRESSION AND DECOMPRESSION OF STIMULUS AND RESPONSE WAVEFORMS IN AUTOMATED TEST SYSTEMS - An automated test system for a device under test (DUT) compresses the stimulus waveform before transferring it to a storage device or over a data transfer interface. The compressed stimulus waveform data are decompressed, and if required converted to analog form, then applied as a stimulus to the DUT. In response, the DUT produces a response waveform. The response waveform is compressed before transferring it to a storage device or over a data transfer interface. If the response waveform is analog, it is converted to digital before compression. The compressed waveform is decompressed for further analysis or display by a host computer. Features of the response waveform can be calculated from the compressed or uncompressed waveform data. Several configurations that include compression and decompression of stimulus and/or response waveforms in test systems are described. | 2009-04-30 |
| 20090113267 | Error detection method and apparatus - To identify errored bits in a binary data set, an ordered plurality of modulo-2 summations of respective selections of the data-set bits are compared with a target syndrome. The selections of data-set bits are defined by the connection of sum nodes to variable nodes in a logical network of nodes and edges where each variable node is associated with a respective data-set bit and each sum node corresponds to a respective modulo-2 summation. Any sum node for which the corresponding summation of selected data-set bits is found to be inconsistent with the target syndrome is identified as errored. Predetermined patterns of errored sum nodes are then looked for to identify one or more associated errored data-set bits. The identified errored data-set bits can then be flipped to correct them | 2009-04-30 |
| 20090113268 | Joint channel code for data non-associated control signalling type | 2009-04-30 |
| 20090113269 | DATA DESCRAMBLING APPARATUS AND DATA DESCRAMBLING METHOD - When performing data descrambling for data including errors, a countermeasure against an error in a seed value that is required for the descrambling is realized in a system having no CPU. | 2009-04-30 |
| 20090113270 | Data processing method of decoding coded data and data processor for the same - For the coded data that was transmitted via a communication channel, a known code portion thereof that is a code portion corresponding to known data is detected. When the known code portion is not detected from the coded data, the coded data will be decoded. When the known code portion is detected from the coded data, at least a part thereof will be replaced with normal data, and the decoding will be performed on the coded data after the substitution. | 2009-04-30 |
| 20090113271 | Method and apparatus for parallel structured latin square interleaving in communication system - A method and apparatus for parallel structured Latin square interleaving in a communication system are provided. The method includes dividing input information bits into sub-blocks according to a parallel processing order, generating a first Latin square matrix or a second Latin square matrix by comparing the parallel processing order with a predetermined threshold, and interleaving by reading out the information bits divided into the sub-blocks according to the generated Latin square matrix. | 2009-04-30 |
