| 18th week of 2009 patent applcation highlights part 44 |
| Patent application number | Title | Published |
|---|
| 20090111172 | MURINE CALICIVIRUS - The invention disclosed herein relates to a newly discovered murine norovirus, and compositions and methods related thereto. | 2009-04-30 |
| 20090111173 | Micro-Organism Test Apparatus and Methods of Using the Same - A micro-organism testing apparatus comprising a multi-compartment resealable container provided with or adapted to receive a growth medium ( | 2009-04-30 |
| 20090111174 | Biomolecule analyzing system - A biomolecule analyzing system ( | 2009-04-30 |
| 20090111175 | NUCLEIC ACID ENCODING A NOVEL RIBONUCLEASE HAVING AN AMINO ACID SEQUENCE MADE UP OF THE AMINO ACID SEQUENCE OF A KNOWN RIBONUCLEASE AND AN N-TERMINAL LEADER SEQUENCE - A nucleic acid encodes a novel RNase. The RNase has an amino acid sequence in which an amino acid sequence disclosed in U.S. Pat. No. 6,239,257 B1 is preceded by a leader sequence. | 2009-04-30 |
| 20090111176 | Trehalose transporter gene and method of introducing trehalose into cells - There are provided trehalose transporter gene and a method of introducing trehalose into cells by using the gene. Candidates for the trehalose transporter genes were searched in | 2009-04-30 |
| 20090111177 | Maintenance of Embryonic Stem Cells by the GSK-3 Inhibitor 6-Bromoindirubin-3'-Oxime - The present invention relates to methods for maintaining the undifferentiated state of embryonic stem cells without the use of a feeder layer by activating the Wnt signal transduction pathway or by inhibiting glycogen synthase kinase-3 activity by contacting the cell with, inter alia, 6-bromoindirubin-3′-oxime. The present invention also relates to embryonic stem cell lines and cells derived therefrom that have been isolated and cultured in the absence of a feeder layer. | 2009-04-30 |
| 20090111178 | GENE REPORTER ASSAY, KIT, AND CELLS FOR DETERMINING THE PRESENCE AND/OR THE LEVEL OF A MOLECULE THAT ACTIVATES SIGNAL TRANSDUCTION ACTIVITY OF A CELL SURFACE PROTEIN - The present invention relates to a commercializable cell and to a gene reporter assay method and a kit which use this cell to determine the presence and/or the level of a molecule that activates signal transduction activity of a cell surface protein. This cell is treated in such a manner that it will have a sufficiently long shelf life for its intended purpose, whereupon at the end of its useful shelf life or at the end of its use, i.e., in an assay, the cell undergoes cellular death. | 2009-04-30 |
| 20090111179 | Cell Culture Shaking Device and Shaking Culture Method as Cell Culture Method - The invention intends to provide a cell culture shaking device which is able to improve the efficiency of cell culture while preventing the cells from becoming damaged. The shaking devices used in cell culture apparatuses for culturing cells in flexible culture bags for storing culture suspension having cells inoculated therein includes: shaking mechanisms having operating panels for pressing the culture bags repeatedly, so that the culture suspension in the culture bags is stirred by being pressed by a plurality of projections projecting for the operating panels. | 2009-04-30 |
| 20090111180 | BIOREACTOR SYSTEM FOR THREE-DIMENSIONAL TISSUE STIMULATOR - A bioreactor system for growing and conditioning tissue for research and implantation in a human or animal body is disclosed which includes one or more tissue growth chambers for growing and conditioning tissue, each chamber being defined by a housing and providing a fluid culture media cavity which can act as a reservoir. A construct for growing three-dimensional tissues is housed in each tissue growth chamber. Each chamber is connected to a source of pressurized air for applying a controlled pressure to the chamber media cavity. The tissue growth chambers can be mounted on an agitation device such as a shaker system which enhances mass transport within the chamber media cavity. A control system is provided to control the pressure and temperature of the pressurized gas delivered to the chamber media cavity and subsequently to the tissue construct. | 2009-04-30 |
| 20090111181 | APPARATUS FOR PREPARING A BIOCOMPATIBLE MATRIX - An apparatus and method of using the apparatus to prepare a biocompatible biodegradable matrix capable of supporting cells to form an implantable or engraftable surgical device. A matrix-forming fluid is contained within a chamber defined by top and bottom surfaces of a thermally conductive material and spacers defining the thickness of the matrix. The chamber is then cooled to freeze the solution at a controlled rate, resulting in a matrix with a desired and uniform thickness having symmetric and uniform reticulations. The apparatus and method reproducibly forms such a matrix, which may be populated with cells for transplantation and engraftment into a wound. | 2009-04-30 |
| 20090111182 | Method for Propagation of Plant - A novel method is provided, which makes it possible to perform mass propagation of a plant of the family Araceae, the family Bromeliaceae, or the family Marantaceae. Specifically, a method for producing an embryogenic callus, comprising culturing a leaf sheath or a part thereof of a plant selected from the group consisting of the family Araceae, the family Bromeliaceae, and the family Marantaceae as an explant and then inducing an embryogenic callus and a propagation method comprising regenerating a plant through induction of a somatic embryo from the embryogenic callus obtained by the above method are also provided herein. | 2009-04-30 |
| 20090111183 | Ketone Ligands for Modulating the Expression of Exogenous Genes Via An Ecdysone Receptor Complex - This invention relates to a method to modulate exogenous gene expression in which an ecdysone receptor complex comprising: a DNA binding domain; a ligand binding domain; a transactivation domain; and a ligand is contacted with a DNA construct comprising: the exogenous gene and a response element; wherein the exogenous gene is under the control of the response element and binding of the DNA binding domain to the response element in the presence of the ligand results in activation or suppression of the gene. The ligands comprise a class of ketones. | 2009-04-30 |
| 20090111184 | Chromosome selection - Systems, methods, compositions and apparatus relating to genome, chromosome, and mitochondria selection are disclosed. | 2009-04-30 |
| 20090111185 | Female genome selection - Systems, methods, compositions and apparatus relating to genome, chromosome, and mitochondria selection are disclosed. | 2009-04-30 |
| 20090111186 | PROMOTER AND VECTORS FOR PLANT TRANSFORMATION AND METHODS OF USING SAME - The invention is directed to a promoter, designated MuB, sequences which hybridize to same and functional fragments thereof. The regulatory element of the invention provide improved expression in plants of operably linked nucleotide sequences. Expression vectors with the regulatory element is the subject of the invention, which may further include an operably linked nucleotide sequence. The invention is further directed to transformed plant tissue including the nucleotide sequence and to transformed plants and seeds thereof. The regulatory element is useful for driving gene or antisense expression or the like for the purpose of imparting agronomically useful traits such as, but not limited to, increase in yield, disease resistance, insect resistance, herbicide tolerance, drought tolerance and salt tolerance in plants. | 2009-04-30 |
| 20090111187 | Moss Expressing Promotion Regions - Disclosed are isolated nucleic acid molecules encoding wild type nucleus derived moss expression promoting regions (MEPRs) as well as a method for producing recombinant polypeptides using such MEPRs. | 2009-04-30 |
| 20090111188 | Optimized non-canonical zinc finger proteins - Disclosed herein are zinc fingers comprising CCHC zinc coordinating residues. Also described are zinc finger proteins and fusion proteins comprising these CCHC zinc fingers as well as polynucleotides encoding these proteins. Methods of using these proteins for gene editing and gene regulation are also described. | 2009-04-30 |
| 20090111189 | ORGANIC AND INORGANIC MERCURY DETECTION - An apparatus and method for the detection and quantitation of metals and metalloids in a sample by derivatization are provided. In particular, the apparatus and method relates to analysis of mercury in a sample by derivatization of the inorganic and organic mercury species into elemental mercury and organo-mercury hydrides using sodium borohydride. | 2009-04-30 |
| 20090111190 | Meander - A centrifugal based microfluidic device that comprises a microchannel structure in which there is a detection microcavity which in the upstream direction is attached to an inlet microconduit for transport of liquid (transport microconduit) to the detection microcavity and which is used for detecting the result of a reaction taking place in the detection microcavity or in a reaction microcavity positioned upstream of the detection microcavity. The detection microcavity comprises a detection microconduit having an inlet part and an outlet part and therebetween an upward or a downward meander. | 2009-04-30 |
| 20090111191 | GAS ANALYZER CASSETTE SYSTEM - A highly sensitive fluid composition analyzer where a fluid may be placed in contact with a very small area on a material sensitized to change color in the presence of a specific type of compound, to be impinged with light. The light reflected, transmitted and/or scattered by the material may serve as input for the analyzer electronics. The fluid may be pre-concentrated prior to being brought in contact with the material. The area on the material may be a spot having an outside dimension of less than one millimeter. | 2009-04-30 |
| 20090111192 | BIOGENIC SUBSTANCE DETECTOR AND BIOGENIC SUBSTANCE DETECTION METHOD - A biogenic substance detector with high reaction efficiency and detection sensitivity is obtained. | 2009-04-30 |
| 20090111193 | Sample preparation device - A sample preparation device is disclosed. The sample preparation device includes a housing defining a passage way between a first opening and a second opening; and a sample filter occupying a section of said passage way. The sample filter contains a monolith adsorbent that specifically binds to nucleic acids. Also disclosed are sample filters containing glass frit is coated with an capture agent that binds specifically to an analyte of interest, sample filters containing a hydrophilic matrix with impregnated chemicals that lyses cell membranes, a cartridge base and an integrated sample preparation cartridge. | 2009-04-30 |
| 20090111194 | Methods and device for the detection of occult blood - The present invention relates generally to detection of occult blood. In particular, the present invention provides a device and methods for the simultaneous detection of hemoglobin and transferrin in fecal samples, which permit a more sensitive diagnosis of occult blood in fecal sample and a differential diagnosis of bleeding of the upper GI tract versus the lower GI tract. | 2009-04-30 |
| 20090111195 | CHEMICAL REAGENTS AND METHODS FOR DETECTION AND QUANTIFICATION OF PROTEINS IN COMPLEX MIXTURES - The invention provides a reagent comprising an affinity tag, a detectable moiety, a linker, an isotope tag and a reactive group. The invention also provides methods of using a reagent of the invention. The methods can be used to label a polypeptide in a sample by contacting a sample with a reagent of the invention under conditions allowing the reactive group to bind to one or more polypeptides in the sample. The invention additionally provides methods of isolating, identifying and quantifying a polypeptide in a sample. The invention further provides methods of diagnosing a disease using a reagent of the invention. | 2009-04-30 |
| 20090111196 | Immunochromatography method - A object of the present invention is to provide an immunochromatography method that makes it possible to rapidly detect an ultratrace amount of an analyte that has been impossible to analyze by conventional immunochromatography methods. The present invention provides an immunochromatography method, which comprises developing an analyte and a labeling substance which is modified with a first binding substance against the analyte in a mixed state on a porous carrier and capturing the analyte and the label at a reaction site on the porous carrier having a second binding substance against the analyte or a substance capable of binding to the first binding substance against the analyte, so as to detect the analyte, wherein the labeling substance having an average particle size of 1 μm or more and 20 μm or less is detected. | 2009-04-30 |
| 20090111197 | HYBRID DEVICE - A hybrid device ( | 2009-04-30 |
| 20090111198 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A manufacturing method of the present invention includes a process using a first multi-tone mask, in which a first conductive layer in which a transparent conductive layer and a metal layer are stacked over a substrate, a gate electrode formed of a first conductive layer, and a pixel electrode formed of a single layer of the transparent conductive layer are formed, a process using a second multi-tone mask, in which a contact hole to the pixel electrode, and an island of an i-type semiconductor layer and an n | 2009-04-30 |
| 20090111199 | Method of manufacturing flat panel display - The present invention relates to a method for manufacturing a flat panel display. Herein, the same mask is used to form contact holes and pixel electrodes in the display substrate. Hence, the number of masks needed for manufacturing the flat panel display can be reduced to decrease the manufacturing cost. | 2009-04-30 |
| 20090111200 | Method for Fabricating Electronic and Photonic Devices on a Semiconductor Substrate - A method for fabricating photonic and electronic devices on a substrate is disclosed. Multiple slabs are initially patterned and etched on a layer of a substrate. An electronic device is fabricated on a first one of the slabs and a photonic device is fabricated on a second one of the slabs, such that the electronic device and the photonic device are formed on the same layer of the substrate. | 2009-04-30 |
| 20090111201 | Ridge and mesa optical waveguides - Apparatus including: a substrate layer having a substantially planar top surface; an optically conductive peak located and elongated on, and spanning a first thickness measured in a direction generally away from, the top surface; the optically conductive peak having first and second lateral walls each including distal and proximal lateral wall portions, the proximal lateral wall portions intersecting the top surface; and first and second sidewall layers located on the distal lateral wall portions, the sidewall layers not intersecting the top surface and spanning a second thickness that is less than the first thickness measured in the same direction. | 2009-04-30 |
| 20090111202 | Method for self bonding epitaxy - A method for self bonding epitaxy includes forming a passivation layer on a substrate surface of a semiconductor lighting element; etching to form recesses and protrusive portions with the passivation layer located thereon; starting forming epitaxy on the bottom surface of the recesses; filling the recesses with an Epi layer; then covering the protrusive portions and starting self bonding upwards the epitaxy to finish the Epi layer structure. Such a self bonding epitaxy growing technique can prevent cavity generation caused by parameter errors of the epitaxy and reduce defect density, and improve the quality of the Epi layer and increase internal quantum efficiency. | 2009-04-30 |
| 20090111203 | METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - A laminated structure having light-emitting units is formed on a single-crystal wafer. Electrode patterns are formed on the single-crystal wafer opposite the light-emitting units. Dummy patterns are formed on the single-crystal wafer at a location spaced apart from a location opposite the light-emitting units, and offset from a desired cleavage line intersecting the light-emitting units. A scratch is formed on the desired cleavage line. The wafer is cleaved, originating on the scratch, along the cleavage line orientation, in the direction from the dummy pattern, toward the light-emitting units. | 2009-04-30 |
| 20090111204 | Vertically Aligned Mode Liquid Crystal Display - A plurality of gate lines and a plurality of data lines intersecting each other are formed on a first insulating substrate having a plurality of first cutouts are formed on the respective pixel areas defined by the data lines and the gate lines. A thin film transistor is connected to each pixel electrode. A reference electrode having a plurality of second cutouts is formed on a second substrate opposite the first substrate. The first cutouts and the second cutouts in the adjacent two pixel areas opposite each other with respect to one data line have an inversion symmetry with respect to the data line. | 2009-04-30 |
| 20090111205 | Method of seperating two material systems - An embodiment of this invention discloses a method of separating two material systems, which comprises steps of providing a bulk sapphire; forming a nitride system on the bulk sapphire; forming at least two channels between the bulk sapphire and the nitride system; etching at least one inner surface of the channel; and separating the bulk sapphire and the nitride system. | 2009-04-30 |
| 20090111206 | Collector grid, electrode structures and interrconnect structures for photovoltaic arrays and methods of manufacture - The invention teaches novel structure and methods for producing electrical current collectors and electrical interconnection structure. Such articles find particular use in facile production of modular arrays of photovoltaic cells. The current collector and interconnecting structures may be initially produced separately from the photovoltaic cells thereby allowing the use of unique materials and manufacture. Subsequent combination of the structures with photovoltaic cells allows facile and efficient completion of modular arrays. Methods for combining the collector and interconnection structures with cells and final interconnecting into modular arrays are taught | 2009-04-30 |
| 20090111207 | METHOD OF FABRICATING AN INTEGRATED DETECTION BIOSENSOR - A method of fabricating an integrated detection biosensor, the biosensor comprising an assembly ( | 2009-04-30 |
| 20090111208 | COLORS ONLY PROCESS TO REDUCE PACKAGE YIELD LOSS - Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon. A transparent encapsulant is deposited to planarize the color filter layer and completes the solid-state color image-forming device without conventional convex microlenses. | 2009-04-30 |
| 20090111209 | METHOD FOR PATTERNING MO LAYER IN A PHOTOVOLTAIC DEVICE COMPRISING CIGS MATERIAL USING AN ETCH PROCESS - A processing method described herein provides a method of patterning a MoSe | 2009-04-30 |
| 20090111210 | Method for Organic Semiconductor Material Thin-Film Formation and Process for Producing Organic Thin Film Transistor - A method for the formation of an organic semiconductor material film having improved mobility on a substrate, and a process for producing an organic thin film transistor which can develop high performance by utilizing the method. The production process of an organic thin film transistor utilizes the method for organic semiconductor material film formation, comprising coating an organic semiconductor material-containing liquid onto a surface of a substrate to form a semiconductor material thin film. The method for organic semiconductor material thin film formation is characterized in that, when the surface free energy of the surface of the substrate is γ | 2009-04-30 |
| 20090111211 | FLAT PANEL DISPLAY AND MANUFACTURING METHOD OF FLAT PANEL DISPLAY - The present disclosure relates to a display device comprising an insulating substrate; a source electrode and a drain electrode on the insulating substrate and separated by a channel area; an organic semiconductor layer formed in the channel area and on at least a portion of the source electrode and at least a portion of the drain electrode; and a self-assembly monolayer having a first portion disposed between the organic semiconductor layer and the source electrode and a second portion disposed between the organic semiconductor layer and the drain electrode to reduce contact resistance between the electrodes and the organic semiconductor layer. Thus, embodiments of present invention provide a display device including a TFT that is enhanced in its performance. | 2009-04-30 |
| 20090111212 | Method and apparatus for chalcogenide device formation - Chalcogenide devices are delineated and sidewalls of the devices are sealed, in an anaerobic and/or anhydrous environment environment. Throughout the delineation and sealing steps, and any intervening steps, the sidewalls are not exposed to oxygen or water. In an illustrative embodiment, a cluster tool includes an etching tool and a sealing/deposition tool configured to etch and seal the chalcogenide devices and to maintain the devices in an anaerobic and/or anhydrous environment throughout the process. | 2009-04-30 |
| 20090111213 | High-Density Fine Line Structure And Method Of Manufacturing The Same - A high-density fine line structure mainly includes: two boards with similar structures and a dielectric film for combing the two boards. Semiconductor devices respectively in two boards are opposite to each other after the two boards are combined. The two boards each include a fine line circuit, an insulated layer on the same surface, and the semiconductor device installed above the fine line circuit. The surface of the circuit, which is not covered by a solder mask, is made into a pad. The pad is filled with the tin balls for electrically connecting with another semiconductor device. Electroplating rather than the etching method is used for forming the fine line circuit layer, and a carrier and a metal barrier layer, which are needed during or at the end of the manufacturing process, are removed to increase the wiring density for realizing the object of high-density. | 2009-04-30 |
| 20090111214 | Method for Improved Power Distribution in a Three Dimensional Vertical Integrated Circuit - A first through via is electrically insulated from surrounding wafer substrate material. A second through via is not electrically insulated from the surrounding wafer substrate material. This configuration is advantageous when the non-insulated via serves as the path for either Vdd or GND. By not insulating the through via, a first supply voltage (Vdd or GND) is allowed to flow through the surrounding wafer substrate material thereby decreasing the resistance of the first supply voltage path. | 2009-04-30 |
| 20090111215 | Modular Chip Integration Techniques - Modular chip integration and operation techniques are provided. In one aspect, a method of integrating chips, chip macros or at least one chip in combination with at least one chip macro is provided. The method comprises the following steps. The chips, chip macros or at least one chip in combination with at least one chip macro are assembled on a single carrier platform. One or more signal inputs and outputs are provided to each of the chips, chip macros or at least one chip in combination with at least one chip macro. One or more power and ground inputs and outputs are provided to each of the chips, chip macros or at least one chip in combination with at least one chip macro. The power and ground inputs and outputs to one or more of the chips, chip macros or at least one chip in combination with at least one chip macro are segmented from the power and ground inputs and outputs to at least one other of the chips, chip macros or at least one chip in combination with at least one chip macro so as to form a plurality of voltage islands. | 2009-04-30 |
| 20090111216 | APPLICATION OF HIPIMS TO THROUGH SILICON VIA METALLIZATION IN THREE-DIMENSIONAL WAFER PACKAGING - A method of magnetically enhanced sputtering an electrically-conductive material onto interior surfaces of a trench described herein includes providing a magnetic field adjacent to a target formed at least in part from the electrically-conductive material, and applying a DC voltage between an anode and the target as a plurality of pulses. A high-frequency signal is applied to the pedestal supporting the semiconductor substrate to generate a self-bias field adjacent to the semiconductor substrate. The high-frequency signal is applied to the pedestal in pulses, during periods of time that overlap with the periods during which the DC voltage pulses are applied. The periods of time that the high-frequency signals are applied include a duration that extends beyond termination of the DC voltage pulse applied between the anode and the target. During each DC voltage pulse the electrically-conductive material is sputter deposited onto the side walls of the trench formed in the semiconductor substrate. | 2009-04-30 |
| 20090111217 | Method of manufacturing chip-on-chip semiconductor device - Provided is a method of fabricating a chip-on-chip (COC) semiconductor device. The method of fabricating a chip-on-chip (COC) semiconductor device may include preparing a first semiconductor device with a metal wiring having at least one discontinuous spot formed therein, preparing a second semiconductor device with at least one bump formed on a surface of the second semiconductor device corresponding to the at least one discontinuous spot, aligning the first semiconductor device onto the second semiconductor device, and connecting the at least one bump of the second semiconductor device to the at least one discontinuous spot formed in the metal wiring of the first semiconductor device. | 2009-04-30 |
| 20090111218 | STACK MCP AND MANUFACTURING METHOD THEREOF - A semiconductor chip having an adhesive layer previously formed on an element forming surface thereof and having a bump exposed from the surface of the adhesive layer is wire-bonded to a printed circuit board. Another semiconductor chip is stacked on the above semiconductor chip with the adhesive layer disposed therebetween and is wire-bonded to the printed circuit board by wire bonding. Likewise, at least one semiconductor chip is sequentially stacked on the thus attained semiconductor structure to form a stack MCP. | 2009-04-30 |
| 20090111219 | WAFER-LEVEL CHIP SCALE PACKAGE AND METHOD FOR FABRICATING AND USING THE SAME - A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e., interface) to the printed circuit board for any small die. | 2009-04-30 |
| 20090111220 | COATED LEAD FRAME - A lead frame having a coating of organic compounds on its lead fingers prevents tin and flux from contaminating the lead fingers after die attach. The coating is removed prior to wire bonding. The coating allows for reliable second bonds (bond between wires and lead fingers) to be formed, decreasing the likelihood of non-stick and improving wire peel strength. | 2009-04-30 |
| 20090111221 | Fabrication method of semiconductor device - A fabrication method of semiconductor device includes providing a substrate which has a plurality of electrical connection pads and is covered with an insulative layer, wherein the insulative layer has an opening formed for exposing the electrical connection pads; forming a filling material on the insulative layer of the substrate and compressing a semiconductor chip to the substrate through a plurality of bumps, the bumps electrically connecting the electrical connection pads and the filling material filling spacing between the semiconductor chip and the substrate so as to form a filling layer. By replacing the conventional underfilling process with the preprinting process of the filling material, the fabrication cost of the semiconductor device is reduced and the fabrication process is simplified. | 2009-04-30 |
| 20090111222 | SEMICONDUCTOR CHIP MOUNTING METHOD, SEMICONDUCTOR MOUNTING WIRING BOARD PRODUCING METHOD AND SEMICONDUCTOR MOUNTING WIRING BOARD - A method of producing a wiring board on which a semiconductor chip is to be mounted, includes: adhering an aluminum foil to one surface of a resin substrate; providing a heat-hardening resin layer having a predetermined shape on the aluminum foil; removing a part of the aluminum foil which is exposed from the heat-hardening resin layer to form a wiring circuit; and providing a thermoplastic resin layer on the wiring circuit. The heat-hardening resin layer has strength that enables the wiring board to prevent short between the semiconductor chip and the wiring circuit and has a crosslinking degree that is so reduced as to enable the bump to remove the heat-hardening resin layer to reach the wiring circuit, when the heat is applied to the wiring board and the bump to which the ultrasonic wave is applied is pressed to the wiring board. | 2009-04-30 |
| 20090111223 | SOI DEVICE HAVING A SUBSTRATE DIODE FORMED BY REDUCED IMPLANTATION ENERGY - By removing material during the formation of trench openings of isolation structures in an SOI device, the subsequent implantation process for defining the well region for a substrate diode may be performed on the basis of moderately low implantation energies, thereby increasing process uniformity and significantly reducing cycle time of the implantation process. Thus, enhanced reliability and stability of the substrate diode may be accomplished while also providing a high degree of compatibility with conventional manufacturing techniques. | 2009-04-30 |
| 20090111224 | FUSI INTEGRATION METHOD USING SOG AS A SACRIFICIAL PLANARIZATION LAYER - A method for making a transistor | 2009-04-30 |
| 20090111225 | CMOS STRUCTURE AND METHOD INCLUDING MULTIPLE CRYSTALLOGRAPHIC PLANES - A complementary metal oxide semiconductor (CMOS) structure includes a semiconductor substrate having first mesa having a first ratio of channel effective horizontal surface area to channel effective vertical surface area. The CMOS structure also includes a second mesa having a second ratio of the same surface areas that is greater than the first ratio. A first device having a first polarity uses the first mesa as a channel and benefits from the enhanced vertical crystallographic orientation. A second device having a second polarity different from the first polarity uses the second mesa as a channel and benefits from the enhanced horizontal crystallographic orientation. | 2009-04-30 |
| 20090111226 | METHOD FOR INTEGRATING NVM CIRCUITRY WITH LOGIC CIRCUITRY - A method for integrating Non-Volatile Memory (NVM) circuitry with logic circuitry is provided. The method includes depositing a first layer of gate material over the NVM area and the logic area of the substrate. The method further includes depositing multiple adjoining sacrificial layers comprising nitride, oxide and nitride (ARC layer) overlying each other. The multiple adjoining sacrificial layers are used to pattern select gate and control gate of memory transistor in the NVM area, and the ARC layer of the multiple adjoining sacrificial layers is used to pattern gate of logic transistor in the logic area. | 2009-04-30 |
| 20090111227 | Method for Forming Trench Gate Field Effect Transistor with Recessed Mesas Using Spacers - A method for forming a field effect transistor with an active area and a termination region surrounding the active area includes forming a well region in a first silicon region, where the well region and the first silicon region are of opposite conductivity type. Gate trenches extending through the well region and terminating within the first silicon region are formed. A recessed gate is formed in each gate trench. A dielectric cap is formed over each recessed gate. The well region is recessed between adjacent trenches to expose upper sidewalls of each dielectric cap. A blanket source implant is carried out to form a second silicon region in an upper portion of the recessed well region between every two adjacent trenches. A dielectric spacer is formed along each exposed upper sidewall of the dielectric cap, with every two adjacent dielectric spacers located between every two adjacent gate trenches forming an opening over the second silicon region. The second silicon region is recessed through the opening between every two adjacent dielectric spacers so that only portions of the second silicon region directly below the dielectric spacers remain. The remaining portions of the second silicon region form source regions. | 2009-04-30 |
| 20090111228 | SELF ALIGNED RING ELECTRODES - The present invention in one embodiment provides a method of manufacturing an electrode that includes providing at least one metal stud positioned in a via extending into a first dielectric layer, wherein an electrically conductive liner is positioned between at least a sidewall of the via and the at least one metal stud; recessing an upper surface of the at least one metal stud below an upper surface of the first dielectric layer to provide at least one recessed metal stud; and forming a second dielectric atop the at least one recessed metal stud, wherein an upper surface of the electrically conductive liner is exposed. | 2009-04-30 |
| 20090111229 | METHOD OF FORMING A SPLIT GATE NON-VOLATILE MEMORY CELL - A method forms a split gate memory cell by providing a semiconductor substrate and forming an overlying select gate. The select gate has a predetermined height and is electrically insulated from the semiconductor substrate. A charge storing layer is subsequently formed overlying and adjacent to the select gate. A control gate is subsequently formed adjacent to and separated from the select gate by the charge storing layer. The charge storing layer is also positioned between the control gate and the semiconductor substrate. The control gate initially has a height greater than the predetermined height of the select gate. The control gate is recessed to a control gate height that is less than the predetermined height of the select gate. A source and a drain are formed in the semiconductor substrate. | 2009-04-30 |
| 20090111230 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | 2009-04-30 |
| 20090111231 | Method for Forming Shielded Gate Field Effect Transistor Using Spacers - A trench is formed in a semiconductor region. A dielectric layer lining sidewalls and bottom surface of the trench is formed. The dielectric layer is thicker along lower sidewalls and the bottom surface than along upper sidewalls of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. Dielectric spacers are formed along the upper trench sidewalls. After forming the dielectric spacers, an inter-electrode dielectric (IED) is formed in the trench over the shield electrode. After forming the IED, the dielectric spacers are removed. | 2009-04-30 |
| 20090111232 | SEMICONDUCTOR DEVICE HAVING DECOUPLING CAPACITOR AND METHOD OF FABRICATING THE SAME - A semiconductor device having a decoupling capacitor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a cell region, a first peripheral circuit region, and a second peripheral circuit region. At least one channel trench is disposed in the cell region of the semiconductor substrate. At least one first capacitor trench is disposed in the first peripheral circuit region of the semiconductor substrate, and at least one second capacitor trench is disposed in the second peripheral circuit region of the semiconductor substrate. A gate electrode is disposed in the cell region of the semiconductor substrate and fills the channel trench. A first upper electrode is disposed in the first peripheral circuit region of the semiconductor substrate and fills at least the first capacitor trench. A second upper electrode is disposed in the second peripheral circuit region of the semiconductor substrate and fills at least the second capacitor trench. A gate dielectric layer is interposed between the channel trench and the gate electrode. A first dielectric layer is interposed between the semiconductor substrate of the first peripheral circuit region having the first capacitor trench and the first upper electrode and has the same thickness as the gate dielectric layer. A second dielectric layer is interposed between the semiconductor substrate of the second peripheral circuit region having the second capacitor trench and the second upper electrode and has a different thickness from the first dielectric layer. | 2009-04-30 |
| 20090111233 | METHOD OF FORMING JUNCTION OF SEMICONDUCTOR DEVICE - The present invention relates to a method of forming junctions of a semiconductor device. According to the method of forming junctions of a semiconductor device in accordance with an aspect of the present invention, there is provided a semiconductor substrate in which a transistor including the junctions are formed. A first thermal treatment process for forming a passivation layer over the semiconductor substrate including the junctions is performed. Here, the passivation layer functions to prevent impurities within the junctions from being drained. A pre-metal dielectric layer is formed over the semiconductor substrate including the passivation layer. | 2009-04-30 |
| 20090111234 | Method for forming min capacitor in a copper damascene interconnect - A method for forming a metal-insulator-metal capacitor in a multilevel semiconductor device utilizes the copper interconnect levels of the semiconductor device as parts of the capacitor. A lower capacitor plate consists of a copper interconnect level and a first metal layer formed on the copper interconnect level by selective deposition methods. The upper capacitor plate includes the same pattern as the capacitor dielectric, the pattern having an area less than the area of the lower capacitor plate. The upper capacitor plate is formed of a second metal layer. The first and second metal layers may each be formed of cobalt, tungsten, nickel, molybdenum, or a combinations of one of the aforementioned elements with boron and/or phosphorus. Conductive vias provide contact from the upper capacitor plate and lower capacitor plate, to interconnect levels. | 2009-04-30 |
| 20090111235 | Semiconductor Integrated Circuit Devices Having High-Q Wafer Back-Side Capacitors - Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit. | 2009-04-30 |
| 20090111236 | METHOD FOR MANUFACTURING SOI SUBSTRATE - An object is to reduce occurrence of defective bonding between a base substrate and a semiconductor substrate even when a silicon nitride film or the like is used as a bonding layer. Another object is to provide a method for manufacturing an SOI substrate by which an increase in the number of steps can be suppressed. A semiconductor substrate and a base substrate are prepared; an oxide film is formed over the semiconductor substrate; the semiconductor substrate is irradiated with accelerated ions through the oxide film to form a separation layer at a predetermined depth from a surface of the semiconductor substrate; a nitrogen-containing layer is formed over the oxide film after the ion irradiation; the semiconductor substrate and the base substrate are disposed opposite to each other to bond a surface of the nitrogen-containing layer and a surface of the base substrate to each other; and the semiconductor substrate is heated to cause separation along the separation layer, thereby forming a single crystal semiconductor layer over the base substrate with the oxide film and the nitrogen-containing layer interposed therebetween. | 2009-04-30 |
| 20090111237 | Method for manufacturing semiconductor substrate - A consistent reduction in temperature in an SOI substrate manufacturing process is achieved. | 2009-04-30 |
| 20090111238 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE CAPABLE OF INCREASING CURRENT DRIVABILITY OF PMOS TRANSISTOR - A semiconductor device capable of selectively applying different stresses for increasing current drivability of PMOS transistor is made by defining trenches in a semiconductor substrate having a PMOS region; forming selectively a buffer layer on sidewalls of the trenches; forming an insulation layer to fill the trenches; annealing the semiconductor substrate such that compressive stress is applied in a channel length direction of a PMOS transistor by oxidizing the buffer layer; removing portions of the insulation layer and thereby forming an isolation layer; and forming the PMOS transistor on the PMOS region of the semiconductor substrate. | 2009-04-30 |
| 20090111239 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes determining an active region in a semiconductor substrate, forming a recess in a gate region crossing over the active region, annealing an oxide layer formed in the recess to oxidize the active region in the gate region, and etching the active region by using the oxidized active region as an etch mask. | 2009-04-30 |
| 20090111240 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a mask including a first silicon nitride film over a semiconductor substrate, forming a trench in a surface of the semiconductor substrate using the mask, forming a silicon oxide film over the mask to embed the silicon oxide film in the trench, performing a first nitriding treatment to selectively convert a portion of the silicon oxide film above the trench into an oxynitride film, performing a second nitriding treatment of the silicon oxide and oxynitride film to form a second silicon nitride film, and planarizing the first silicon nitride film and second silicon nitride film. | 2009-04-30 |
| 20090111241 | WAFER BONDING METHOD - A method includes steps of providing first and second substrates, and forming a bonding interface between them using a conductive bonding region. A portion of the second substrate is removed to form a mesa structure. A vertically oriented semiconductor device is formed with the mesa structure. A portion of the conductive bonding region is removed to form a contact. The vertically oriented semiconductor device is carried by the contact. | 2009-04-30 |
| 20090111242 | Method for producing semiconductor substrate - An object of the present invention is to provide a method by which bonding at a low temperature is possible and an amount of metal contaminants in an SOI film is decreased. An embodiment of the present invention is realized in the following manner. A single crystal silicon substrate | 2009-04-30 |
| 20090111243 | SOI SUBSTRATES WITH A FINE BURIED INSULATING LAYER - A method of producing a semiconductor structure having a buried insulating layer having a thickness between 2 and 25 nm, by: forming at least one insulating layer on a surface of a first or second substrate, or both, wherein the surfaces are free from an insulator or presenting a native oxide layer resulting from exposure of the substrates to ambient conditions; assembling the first and second substrates; and thinning down the first substrate, in order to obtain the semiconductor structure. In this method, the insulating layer forming stage is a plasma activation based on an oxidizing or nitriding gas. | 2009-04-30 |
| 20090111244 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A single crystal semiconductor substrate is irradiated with ions that are generated by exciting a hydrogen gas and are accelerated with an ion doping apparatus, thereby forming a damaged region that contains a large amount of hydrogen. After the single crystal semiconductor substrate and a supporting substrate are bonded, the single crystal semiconductor substrate is heated to be separated along the damaged region. While a single crystal semiconductor layer separated from the single crystal semiconductor substrate is heated, this single crystal semiconductor layer is irradiated with a laser beam. The single crystal semiconductor layer undergoes re-single-crystallization by being melted through laser beam irradiation, thereby recovering its crystallinity and planarizing the surface of the single crystal semiconductor layer. | 2009-04-30 |
| 20090111245 | Method for manufacturing bonded wafer - The present invention provides a method for manufacturing a bonded wafer comprising steps of forming an oxide film on at least a surface of a base wafer or a surface of a bond wafer; bringing the base wafer and the bond wafer into close contact via the oxide film; subjecting these wafers to a heat treatment under an oxidizing atmosphere to bond the wafers together; grinding and removing the outer periphery of the bond wafer so that the outer periphery has a predetermined thickness; subsequently removing an unbonded portion of the outer periphery of the bond wafer by etching; and then thinning the bond wafer so that the bond wafer has a desired thickness, wherein the etching is conducted by using a mixed acid at 30° C. or less at least comprising hydrofluoric acid, nitric acid, and acetic acid. Thus there is provided a method for manufacturing a bonded wafer by which unbonded portions of the outer periphery of the bond wafer are removed with a high selectivity ratio (R | 2009-04-30 |
| 20090111246 | INHIBITORS FOR SELECTIVE DEPOSITION OF SILICON CONTAINING FILMS - A method for depositing a single crystalline silicon film comprises: providing a substrate disposed within a chamber; introducing to the chamber under chemical vapor deposition conditions a silicon precursor, a chlorine-containing etchant and an inhibitor source for decelerating reactions between the silicon precursor and the chlorine-containing etchant; and selectively depositing a doped crystalline Si-containing film onto the substrate. | 2009-04-30 |
| 20090111247 | FORMATION METHOD OF SINGLE CRYSTAL SEMICONDUCTOR LAYER, FORMATION METHOD OF CRYSTALLINE SEMICONDUCTOR LAYER, FORMATION METHOD OF POLYCRYSTALLINE LAYER, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for forming a single crystal semiconductor layer in which a first porous layer and a second porous layer are formed over a single crystal semiconductor ingot, a groove is formed in a part of the second porous layer and a single crystal semiconductor layer is formed over the second porous layer, the single crystal semiconductor ingot is attached onto a large insulating substrate, water jet is directed to the interface between the first porous layer and the second porous layer, and the single crystal semiconductor layer is attached to the large insulating substrate, or a method for forming a crystalline semiconductor layer in which a crystalline semiconductor ingot is irradiated with hydrogen ions to form a hydrogen ion irradiation region in the crystalline semiconductor ingot, the crystalline semiconductor ingot is rolled over the large insulating substrate while being heated, the crystalline semiconductor layer is separated from the hydrogen ion irradiation region, and the crystalline semiconductor layer is attached to the large insulating substrate. | 2009-04-30 |
| 20090111248 | MANUFACTURING METHOD OF SOI SUBSTRATE - A damaged region is formed by generation of plasma by excitation of a source gas, and by addition of ion species contained in the plasma from one of surfaces of a single crystal semiconductor substrate; an insulating layer is formed over the other surface of the single crystal semiconductor substrate; a supporting substrate is firmly attached to the single crystal semiconductor substrate so as to face the single crystal semiconductor substrate with the insulating layer interposed therebetween; separation is performed at the damaged region into the supporting substrate to which a single crystal semiconductor layer is attached and part of the single crystal semiconductor substrate by heating of the single crystal semiconductor substrate; dry etching is performed on a surface of the single crystal semiconductor layer attached to the supporting substrate; the single crystal semiconductor layer is recrystallized by irradiation of the single crystal semiconductor layer with a laser beam to melt at least part of the single crystal semiconductor layer. | 2009-04-30 |
| 20090111249 | Multilevel Phase Change Memory - A multilevel phase change memory may be formed of a chalcogenide material formed between a pair of spaced electrodes. The cross-sectional area of the chalcogenide material may decrease as the material extends from one electrode to another. As a result, the current density decreases from one electrode to the other. This means that a higher current is necessary to convert the material that has the largest cross-sectional area. As a result, different current levels may be utilized to convert different amounts of the chalcogenide material to the amorphous or reset state. A distinguishable resistance may be associated with each of those different amounts of amorphous material, providing the opportunity to engineer a number of different current selectable programmable states. | 2009-04-30 |
| 20090111250 | METHOD FOR PREPARING COMPOUND SEMICONDUCTOR SUBSTRATE - Provided is a method for preparing a compound semiconductor substrate. The method includes coating a plurality of spherical balls on a substrate, growing a compound semiconductor epitaxial layer on the substrate coated with the spherical balls while allowing voids to be formed under the spherical balls, and cooling the substrate on which the compound semiconductor epitaxial layer is grown so that the substrate and the compound semiconductor epitaxial layer are self-separated along the voids. The spherical ball treatment can reduce dislocation generations. In addition, because the substrate and the compound semiconductor epitaxial layer are separated through the self-separation, there is no need for laser lift-off process. | 2009-04-30 |
| 20090111251 | EXPOSURE MASK AND METHOD FOR FABRICATING THIN-FILM TRANSISTOR - An exposure mask includes a transparent substrate; a first pattern portion formed on the transparent substrate using at least one light-shielding pattern having a predetermined shape; and a translucent layer which is formed at a section including a first pattern region having the first pattern portion, which allows exposure light to pass therethrough, and which has a transmittance greater than that of the light-shielding pattern. | 2009-04-30 |
| 20090111252 | METHOD FOR FORMING DEEP WELL REGION OF HIGH VOLTAGE DEVICE - A method of fabricating a deep well region of a high voltage device is provided. The method includes designating a deep well region that includes a designated highly doped region and a designed scarcely doped region in a substrate. A mask layer, which covers a periphery of the designated deep well region, is formed over the substrate, wherein the mask layer includes a plurality of shielding parts to cover a portion of the designated scarcely doped region. Using the mask layer as an implantation mask, an ion implantation process is performed to implant dopants into the substrate exposed by the mask and to form a plurality of undoped regions in the designated scarcely doped region covered by the shielding parts. The dopants in the designated scarcely doped region are then induced to diffuse to the undoped regions. | 2009-04-30 |
| 20090111253 | METHOD FOR PRODUCING A TRANSISTOR GATE WITH SUB-PHOTOLITHOGRAPHIC DIMENSIONS - Methods of fabricating compound semiconductor devices are described. | 2009-04-30 |
| 20090111254 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming an insulation layer over a substrate including a pattern for forming a multi-plane channel, forming a columnar polysilicon layer over the insulation layer and filling in the pattern, and performing a thermal treatment process. | 2009-04-30 |
| 20090111255 | METHOD FOR FABRICATING TRANSISTOR IN SEMICONDUCTOR DEVICE - Provided is a method for fabricating a transistor in a semiconductor device. The method includes forming an etch stop layer pattern over a semiconductor substrate; forming a semiconductor layer for covering the etch stop layer pattern; forming a recess trench that exposes an upper surface of the etch stop layer pattern by etching the semiconductor layer pattern; removing the etch stop layer pattern exposed in the recess trench; and forming a gate that fills the recess trench. | 2009-04-30 |
| 20090111256 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a pattern including a first layer including tungsten, performing a gas flowing process on the pattern in a gas ambience including nitrogen, and forming a second layer over the pattern using a source gas including nitrogen, wherein the purge is performed at a given temperature for a given period of time in a manner that a reaction between the first layer and the nitrogen used when forming the second layer is controlled. | 2009-04-30 |
| 20090111257 | Techniques for Impeding Reverse Engineering - Anti-reverse engineering techniques are provided. In one aspect, a method for forming at least one feature in an insulating layer is provided. The method comprises the following steps. Ions are selectively implanted in the insulating layer so as to form at least one implant region within the insulating layer, the implanted ions being configured to alter an etch rate through the insulating layer within the implant region. The insulating layer is etched to, at the same time, form at least one void both within the implant region and outside of the implant region, wherein the etch rate through the insulating layer within the implant region is different from an etch rate through the insulating layer outside of the implant region. The void is filled with at least one conductor material to form the feature in the insulating layer. | 2009-04-30 |
| 20090111258 | Method for Manufacturing a Semiconductor Device - A manufacturing method of a semiconductor device wherein a metal pad is etched to form a trench in which a central part is concave in form, or to form a trench in the shape of a cylinder or a parallelepiped on the edge part of a metal pad. Accordingly, the contact area between a polymide isoindro quirazorindione (PIQ) or similar curable layer and the metal pad is increased and the bondability is improved. Accordingly, the technology of improving the characteristic of device by preventing the problem that the metal pad is excessively opened in a subsequent curing process and the layer of a lower portion of the metal pad is attacked is disclosed. | 2009-04-30 |
| 20090111259 | METHODS FOR FORMING CONNECTIVE ELEMENTS ON INTEGRATED CIRCUITS FOR PACKAGING APPLICATIONS - Methods for forming connective elements on integrated circuits for packaging applications are provided herein. In some embodiments, a method of forming connective elements on an integrated circuit for flipchip packaging may include providing a resist layer on the integrated circuit; forming a plurality of holes through the resist layer; filling the plurality of holes with conductive material; and stripping at least a portion of the resist layer using a stripping solution containing acetic anhydride and ozone to expose the connective elements. | 2009-04-30 |
| 20090111260 | ELECTRONIC COMPONENT, SEMICONDUCTOR DEVICE, METHODS OF MANUFACTURING THE SAME, CIRCUIT BOARD, AND ELECTRONIC INSTRUMENT - The present invention is a method of manufacturing a semiconductor device, by forming a wiring on or above a wafer so that the wiring is electrically connected to a first electrode disposed on a first surface of the wafer, forming a first resin layer on or above the wafer such that the wiring is disposed between the wafer and the first resin layer, forming an opening in the first resin layer such that the opening overlaps the wiring, forming a conductive member in the opening such that the conductive member being electrically connected to the wiring, forming a second electrode on the conductive member such that the second electrode is electrically connected to the wiring via the conductive member, and separating the wafer into individual elements after the forming of the first resin layer. | 2009-04-30 |
| 20090111261 | Over-passivation process of forming polymer layer over IC chip - A method for forming a semiconductor chip or wafer includes following steps. A semiconductor substrate is provided, and then a polymer layer is deposited over the semiconductor substrate, wherein the polymer layer comprises polyimide. The polymer layer with a temperature profile having a peak temperature between 200 and 320 degrees Celsius. Alternatively, the temperature profile may comprises a period of time with a temperature higher than 320 degree Celsius, wherein the period of time is shorter than 45 minutes. | 2009-04-30 |
| 20090111262 | MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION - A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated. | 2009-04-30 |
| 20090111263 | Method of Forming Programmable Via Devices - A device is formed by providing a contact via in a dielectric layer, providing a capping layer overlying at least a portion of the contact via, and forming a conductive element in physical contact with the capping layer. The conductive element is formed using a masked deposition process. This process comprises forming a seed layer overlying the capping layer and at least a portion of an uppermost surface of the dielectric layer, forming a masking layer on the seed layer, the masking layer defining an opening exposing a portion of the seed layer that overlies the capping layer, and selectively depositing a conductive material onto the exposed portion of the seed layer. | 2009-04-30 |
| 20090111264 | PLASMA-ENHANCED CYCLIC LAYER DEPOSITION PROCESS FOR BARRIER LAYERS - In one embodiment, a method for depositing materials on a substrate is provided which includes forming a titanium nitride barrier layer on the substrate by sequentially exposing the substrate to a titanium precursor containing a titanium organic compound and a nitrogen plasma formed from a mixture of nitrogen gas and hydrogen gas. In another embodiment, the method includes exposing the substrate to the deposition gas containing the titanium organic compound to form a titanium-containing layer on the substrate, and exposing the titanium-containing layer disposed on the substrate to a nitrogen plasma formed from a mixture of nitrogen gas and hydrogen gas. The method further provides depositing a conductive material containing tungsten or copper over the substrate during a vapor deposition process. In some examples, the titanium organic compound may contain methylamido or ethylamido, such as tetrakis(dimethylamido)titanium, tetrakis(diethylamido)titanium, or derivatives thereof. | 2009-04-30 |
| 20090111265 | SELECTIVE SILICIDE FORMATION USING RESIST ETCHBACK - Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device. | 2009-04-30 |
| 20090111266 | Method of Forming Gate of Semiconductor Device - A method of forming a gate of a semiconductor device comprising providing a semiconductor substrate over which a gate insulating layer, a first conductive layer, a dielectric layer, and a second conductive layer are sequentially formed, the semiconductor substrate defining gate line regions; removing he second conductive layer between gate line regions; removing the dielectric layer so that a top surface of the first conductive layer between the gate line regions is exposed; performing a first etch process in order to lower a height of the first conductive layer between the gate line region; removing he dielectric layer between the gate line regions; and, performing a second etch process in order to remove the first conductive layer between the gate line regions. | 2009-04-30 |
| 20090111267 | METHOD OF ANTI-STICTION DIMPLE FORMATION UNDER MEMS - A method for making a MEMS structure comprises patterning recesses in a dielectric layer overlying a substrate, each recess being disposed between adjacent mesas of dielectric material. A conformal layer of semiconductor material is formed overlying the recesses and mesas. The conformal layer is chemical mechanically polished to form a chemical mechanical polished surface, wherein the chemical mechanical polishing is sufficient to create dished portions of semiconductor material within the plurality of recesses. Each dished portion has a depth proximate a central portion thereof that is less than a thickness of the semiconductor material proximate an outer portion thereof. A semiconductor wafer is then bonded to the chemical mechanical polished surface. The bonded semiconductor wafer is patterned with openings according to the requirements of a desired MEMS transducer. Lastly, the MEMS transducer is released. Releasing advantageously exposes anti-stiction features formed from outer edges of the dished portion of semiconductor material. | 2009-04-30 |
| 20090111268 | REWORKING METHOD FOR INTEGRATED CIRCUIT DEVICES - A reworking method for integrated circuit devices includes the following: providing a substrate having a first base layer and a first dielectric layer formed thereon, performing a first dry etching process to remove the first dielectric layer, performing a CMP process to remove the first base layer, and sequentially reforming a second base layer and a second dielectric layer on the substrate. When certain layers on the IC device have hailed an inspection or when quality defects are found, the defective layer is removed according to the provided reworking method. | 2009-04-30 |
| 20090111269 | SILICON WAFER RECLAMATION PROCESS - By exposing a process control wafer having a porous low-k-dielectric layer thereon in an HF-based low-k dielectric etching solvent comprising a dilating additive and a passivating additive, the pores in the low-k dielectric layer are dilated some of which connect with one another to form one or more continuous channels extending through the thickness of the dielectric layer and allowing the HF-based solvent to reach down to the substrate. Then the passivating additive component of the HF-based etching solvent forms a passivation layer at the dielectric layer and the substrate interface that protects substrate from the HF-based etchant. | 2009-04-30 |
| 20090111270 | Method for Forming Patterns in Semiconductor Memory Device - A method for forming patterns in a semiconductor memory device, wherein first spacers arranged at a first spacing and second spacers arranged at a second spacing are formed on a target layer which is formed on a semiconductor substrate. A mask pattern is formed to cover a portion of the target layer defined by the two adjacent second spacers. At least two first patterns and at least one second pattern is formed by patterning the target layer using the first spacers, the second spacers and the mask pattern as an etch mask. Here, the second pattern is wider than the first pattern. | 2009-04-30 |
| 20090111271 | ISOTROPIC SILICON ETCH USING ANISOTROPIC ETCHANTS - Methods for isotropically etching a monocrystalline silicon wafer. An example method includes applying a layer of material at least one of onto a first side or into a first side of the monocrystalline silicon wafer and isotropically etching a non-linear pit into the monocrystalline silicon wafer using an anisotropic etchant. The applied layer of material has a faster etch rate than the monocrystalline silicon wafer. | 2009-04-30 |
