18th week of 2009 patent applcation highlights part 29 |
Patent application number | Title | Published |
20090109676 | LOOP LED LIGHT - A Light-Emitting Diode (“LED”) light includes a ring-shaped housing wish a cross section, a transparent section and a non-transparent section. The ring-shaped housing defines a horizontal plane relative to a midpoint of the cross section, and a board is fitted within the ring-shaped housing at an angle between about ten to sixty degrees relative to the horizontal plane with LEDs mounted thereon the board to emit light through the transparent section. In one aspect, the board is a printed circuit board. In one aspect, the LEDs are mounted approximately perpendicularly onto the board. | 2009-04-30 |
20090109677 | CHAMBERED WATERPROOF LAMP ASSEMBLY HAVING A TRANSPARENT COVER SWITCH ACTIVATOR - A waterproof portable lamp ( | 2009-04-30 |
20090109678 | LIGHT SOURCE ASSEMBLY - In one embodiment, an exemplary light source assembly includes a light source device, a optical component, and a light pervious filling layer interposed between the light source and the optical component. The light source includes a light pervious cover. The light pervious filling layer can reduce a refraction loss and reflection loss of light. | 2009-04-30 |
20090109679 | ADJUSTABLE UTILITY LIGHT AND METHODS OF USE THEREOF - An adjustable utility light having a body section, two independently movable hooks, a pivoting lamp section having fluorescent tubes and/or light emitting diodes, a component retention tray, at least one keyhole mounting slot, and a movable reflector, wherein the pivoting lamp section and the movable reflector pivot about the same pivot axis. | 2009-04-30 |
20090109680 | Selectable Gobo Animation for a Multiparameter Light - A multiparameter lighting apparatus is disclosed that allows an operator of a central controller to remotely choose a first rotation of a selected gobo of the multiparameter lighting apparatus. The first rotation is typically a substantially smooth rotation. A second rotation can also be chosen, wherein the second rotation causes an animation of the selected gobo. | 2009-04-30 |
20090109681 | Magnetic quick-change gobo changer system - For lighting equipment for illumination of theatre and show stages and platforms there is designed an equipment for change of rotary gobos comprising a carrier disc supporting interchangeable segments with the gobos. The individual segments ( | 2009-04-30 |
20090109682 | Illumination Sources And Subjects Having Distinctly Matched And Mismatched Narrow Spectral Bands - A light source is configured to emit narrow peaks at discrete spectral bands, especially primary color wavelengths, added to simulate the effect of a broadband light source. A subject is provided with a pigment, examples being certain rare earth lanthanides, with a strong absorption peak at a corresponding narrow spectral band. The pigment has a nominal hue under true broadband light. When illuminated by the narrow band source, the absorption peak eliminates the contribution of one of the primary colors, producing a distinct shift in hue of the pigmented subject. The change in hue cannot be anticipated from the appearance of illuminated subjects that lack the pigment, which remain normal. The narrow absorption peak is not noticeable under unmatched light sources or true broadband light sources, e.g., sunlight. The hue shift effect is useful for security authentication, informational and decorative applications. | 2009-04-30 |
20090109683 | LIGHT GUIDE PLATE FOR DISPLAY DEVICE - A light guide plate according to the present invention includes an incident plane into which a light flux from a light source is incident, and a plurality of prisms having reflection planes reflecting the light flux incident from the incident plane, wherein the reflection planes of the plurality of prisms are extended to cross in a direction in which the light flux from the light source incident into the incident plane travels, and of the reflection planes of the plurality of prisms, the reflection plane of at least one prism closest to the incident plane is formed in a recess shape with respect to the incident plane. Thereby nonuniformity of backlight illumination can be improved and a display device can be uniformly and efficiently illuminated. | 2009-04-30 |
20090109684 | ENERGY SAVING LIGHT STRUCTURE - An energy saving light structure includes a socket and an energy saving bulb mounted in the socket. The socket is provided with an oval spherical multi-reflector on the inner wall of the socket. The multi-reflector has a number of rectangular reflecting plates connected in series. The multi-reflector is formed with a concave oval spherical reflecting section. The inner wall of the reflecting section is formed with a corrugated reflecting surface to enhance the illumination effect and save energy. | 2009-04-30 |
20090109685 | Lighting Apparatus - A lighting apparatus includes a reflector, a light source, and a lens unit. The reflector has an open side, and a reflective surface that extends from a periphery of the open side and that defines a compartment. The light source is disposed in the compartment and emits light toward the reflective surface. The reflective surface reflects the light from the light source towards the open side. The lens unit is disposed to close the open side and permits passage of the light reflected by the reflective surface therethrough. The lens unit includes a central lens portion, and first and second side lens portions respectively disposed on two sides of the central lens portion. The central lens portion and the first and second side lens portions are Fresnel lenses, and are configured to redirect the light passing therethrough to result in rectangularly-distributed illumination outwardly of the lighting apparatus. | 2009-04-30 |
20090109686 | LAMPSHADE AND ILLUMINATION LAMP HAVING THE SAME - An illumination lamp ( | 2009-04-30 |
20090109687 | VARIABLE SPOT SIZE LENSES AND LIGHTING SYSTEMS - Improved lighting devices and methods are provided. In many embodiments, the devices and methods provide the capability to change a spot of light projected onto a target surface. In other embodiments, the devices and methods are fixed-focus. In one embodiment a lens can have a lens body with anterior and posterior surfaces. The anterior surface can be adapted to receive light from a light source. The posterior surface can have a central portion and a peripheral portion. Some of the light from the light source can pass through the lens body and exit the central portion of the posterior surface via refraction. Some of the light from the light source can pass through the lens body and exit the peripheral portion of the posterior surface via both refraction and reflection at various surfaces of the lens. | 2009-04-30 |
20090109688 | Photoelectronic device - A photoelectronic device including a carrier, a light-emitting component mounted on the carrier; a patterned structure deposited on the carrier and around the light-emitting component; and a transparent sealing structure formed above the light-emitting component. The patterned structure mentioned above can cause the transparent sealing structure to be focused above the light-emitting component, and restrained in the patterned structure. The transparent sealing structure with predetermined proportional configuration is obtained by controlling the quantity of the transparent sealing structure. Therefore light efficiency of the photoelectronic device can be greatly improved. | 2009-04-30 |
20090109689 | REFLECTOR - A metallic reflector device having one or an array of individual reflector elements for positioning over a corresponding one or array of light sources, preferably comprising one or more light emitting diodes (LEDs). The metallic reflector device includes a planar base and a plurality of the reflector elements. The planar base has one or a plurality of apertures, each aperture having an edge that defines a proximal rim of the reflector element. Each reflector element includes an annular sidewall having an inner surface that extends from the proximal annular rim to a distal annular rim. The proximal annular rim defines a first opening through which direct and reflected light from a light source is emitted. The distal annular rim defines a second opening through which the light source is disposed. The inner surface of the annular sidewall is formed from the material of the planar sheet by mechanically deforming the planar sheet, such as by stamping or drawing. | 2009-04-30 |
20090109690 | Light distribution board - A light distribution board used as an illuminating cover for a lamp set and having on a transparent board of it saw toothed light gratings, each saw toothed light grating is composed of a convex lens surface and a bevel plane lens surface the saw toothed light gratings are arranged at two lateral sides of a central line of the transparent board to form mirror images one side to the other side, the bevel plane lens surfaces are arranged to face respectively to two lateral sides of the transparent board, while the convex lens surfaces are arranged to face to the central line; the top surface is a light receiving surface of the lamp set. The bottom surface of the transparent board is formed thereon a plurality of convex-lens strip like light gratings and the bottom surface is an illuminating surface of the lamp set. With this structure, light beams can be uniformly distributed and can avoid the phenomenon of Gauss distribution that makes the area below the lamp especially bright, and avoid the phenomenon of dazzling of eyes during looking at the light emitting member in the lamp set, and the light beams become more tender under the condition that lose of brightness is minimum. | 2009-04-30 |
20090109691 | BENT FIXING STRUCTURE FOR LIGHT EMITTING COMPONENT - A bent fixing structure for fixing at least one pin of a light emitting component, such as a light emitting diode (LED). The bent fixing structure has a fixing part and a bent installation part. The fixing part is connected to the pin, and is used for fixing the light emitting component on the bent fixing structure. The bent installation part is connected to the fixing part, and an included angle between the fixing part and the bent installation part is unequal to 180 degrees. | 2009-04-30 |
20090109692 | Light Fixture with Removable Lamp Housing - A lighting fixture having a socket housing and a removable lamp housing. The socket housing includes a socket for receiving a lamp and for connecting the lamp to a power supply. The lamp housing has a first end for emitting light from the lamp and a second end that is removably coupled to the socket housing. The lamp housing least partially encloses the lamp when connected to the socket housing. The second end of the lamp housing is wider than the lamp, so as to allow the lamp housing to be removed from the socket housing without first removing the lamp from the socket. Removing the lamp housing from said socket housing substantially exposes the socket to view and allows for installation of a lamp into the socket without having to re-position or re-aim the track light fixture. | 2009-04-30 |
20090109693 | Lamp holder with improved structure - A lamp holder with improved structure includes an upper plate and a lower plate mounted to a ceiling; the upper plate has a top and a bottom with each disposed with multiple reinforcement ribs; a circular wall is disposed to the bottom; two accommodation spaces are defined by the circular wall and those reinforcement ribs on the bottom with each accommodation space disposed with a conduction reed secured in place by an elastic member; two sockets are provided to the lower plate for insertion by pins from an energy saving lamp and to constitute a conducted circuit with the conduction reed. | 2009-04-30 |
20090109694 | Light Fixture with Lamp Adjustment Assembly - A lamp adjustment assembly for a light fixture includes a socket platform having a base and hollow neck. A socket mounts to the base. The interior of the hollow neck includes at least three spaced-apart cam followers. A cam having spiral grooves includes a first portion that fits at least partially within the interior of the hollow neck. The cam followers mate with the grooves. An adjustment knob is coupled to a second portion of the cam and rotatably coupled to a socket housing that at least partially encloses the lamp adjustment assembly. Alignment wings extend from the base of the socket platform and are sized to fit within slots in the interior of the socket housing. The slots prevent the socket platform from rotating and limit the linear range of motion of the socket platform. A spring applies force to the base and the adjustment knob. | 2009-04-30 |
20090109695 | WIRE FIXING FRAME AND BACKLIGHT MODULE - A wire fixing frame for fixing at least one wire on a substrate is described. The wire fixing frame includes a main part, a first fixing part, a second fixing part, and an extending part. A wire outlet is defined between the extending part and the first fixed part, and a wire inlet is opposite to the wire outlet. A wire hold space is defined among the main part, the first fixing part, the second fixing part, and the substrate. The wire passes from the wire inlet to the wire outlet through the wire hold space, and the wire is fixed at a position by a round corner of the first fixing part and the extending part. | 2009-04-30 |
20090109696 | Modular Vehicle Lighting System - A modular vehicle lighting system capable of taking any desired configuration for providing illumination to cargo areas of any size and configuration of accessories comprising at least one light bar having a body defining at least one opening to allow light to allow light to pass from the body to the surrounding vehicle, the light bar also having at least one connection end and at least one connector configured to mate with the light bar connection end whereby an electrical connection between the light bar and the connector is established and at least one bracket for mounting the light bar to a cargo area. | 2009-04-30 |
20090109697 | LAMP SHIELD DRIVING DEVICE AND HEADLAMP ASSEMBLY INCLUDING THE SAME - A headlamp assembly for providing various beam patterns for a vehicle is provided, which includes a lamp shield driving device. The device comprises a first shield including at least one shield projection formed on a circumference thereof, a second shield to shield at least a part of beam irradiation in a close range, and a shield driving unit to drive the first shield and the second shield in a sequential order to thereby generate a certain beam pattern. | 2009-04-30 |
20090109698 | Lighting apparatus - Provided is a lighting apparatus capable of uniformly and efficiently lighting a spatial light modulator. The lighting apparatus includes: a light source for outputting laser light; a multimode optical fiber in which the laser light outputted from the light source propagates through an internal core whose lateral cross section is a substantially polygonal outer diameter shape; and spatial light modulator for producing an image with illumination light from the multimode optical fiber. In the lighting apparatus, the laser light is outputted from the light source and is propagated to the multimode optical fiber in which an outer diameter shape of the lateral cross section of the core is a substantially polygonal shape, whereby the spatial light modulator can be uniformly and efficiently lighted. | 2009-04-30 |
20090109699 | LIGHT SOURCE - A light source, such as for a projection system, having a plurality of semiconductor chips and at least two different, electromagnetic-radiation-emitting chip types with different emission spectra, each semiconductor chip having a chip coupling-out area through which radiation is coupled out. Furthermore, the light source has a plurality of primary optical elements, each semiconductor chip being assigned a primary optical element, which in each case has a light input and a light output and reduces the divergence of at least part of the radiation emitted by the semiconductor chip during the operation thereof. The semiconductor chips with the primary optical elements are arranged in at least two groups that are spatially separate from one another, with the result that the groups emit separate light cones during operation of the semiconductor chips. The separate light cones of the groups are superposed by means of a secondary optical arrangement to form a common light cone. | 2009-04-30 |
20090109700 | LIGHT PIPE MOUNTING INTERFACE - In an example embodiment, a light pipe mounting interface may include a support strip and at least one light pipe projecting from the support strip. The light pipe is to extend through a housing. A hook projects from the support strip to engage with the housing, and a cantilever snap head projects from an extension of the support strip to engage with the housing. The cantilever snap head and the hook lock the light pipe in a predetermined position with respect to the housing. | 2009-04-30 |
20090109701 | ILLUMINANT BUSINESS CARD - An illuminant business card includes a light guiding card body, at least a light emitting diode and a power source. The light guiding card body includes a front surface with display information arranged thereon, a rear surface opposite to the front surface, and a plurality of side surfaces interconnecting the front and rear surfaces. The at least a light emitting diode couples to the light guiding card body optically. The power source is electrically connected to the at least a light emitting diode to supply an electric current to the at least a light emitting diode to illuminate the display information of the light guiding card body. | 2009-04-30 |
20090109702 | BACKLIGHT UNIT AND DISPLAY APPARATUS - A backlight unit includes a light guide panel to guide entering light, a light source disposed on at least one side of the light guide panel to emit light, and a reflecting sheet disposed on a surface of the light guide panel to reflect the entering light toward a light emitting plane of the light guide panel, and includes a plurality of reflecting areas which have different reflectance, where a reflecting area of the plurality of reflecting areas which encounters a relatively large amount of the entering light has a higher reflectance than that of a reflecting area of the plurality of reflecting areas which encounters a relatively small amount of the entering light. | 2009-04-30 |
20090109703 | Light guide plate and side-emitting backlight module having the same - A light guide plate and a side-emitting backlight module having the same are disclosed. The light guide plate includes a transparent substrate, a plurality of prisms and a plurality of condensing lenses. The prisms are arranged side by side on one surface of the transparent substrate. The condensing lenses are disposed between two adjacent prisms, and distributed from sparsely to densely along a direction of a crest line of each of the prisms. | 2009-04-30 |
20090109704 | LIGHT GUIDE PLATE - The wedge-shaped light guide plate has a number of reflection structures with gaps therebetween arranged along the light reflection plane. Each reflection structure from a previous gap contains sequentially a slant surface extended away from the light emission surface, a second reflection surface further slanting away from the light emission plane, and a first reflection surface slanting towards the light emission plane to connect to a next gap. The second and first reflection surfaces form a prism element. In one embodiment of the present invention, the reflection structures are more densely arranged as they are more distant from the light source. In an alternative embodiment of the present invention, the reflection structures are arranged uniformly. | 2009-04-30 |
20090109705 | Back-light assembly - A back-light assembly for uniformly illuminating large area displays. The back-light assembly includes a uniformly thin waveguide, a reflector and a plurality of light sources evenly distributed along the display area between the waveguide and the reflector. Prismatic facets are provided along the lower surface of the waveguide for effectively coupling light emitted from light sources into the waveguide. | 2009-04-30 |
20090109706 | OPTICAL GUIDING DEVICE AND BACKLIGHT MODULE USING SAME - An exemplary optical guiding device for optically coupling a plurality of light beams having at least one laser beam, includes a light coupling lens, a light collimating lens, and an optical fiber. The light coupling lens and the light collimating lens are positioned apart along an optical path. The optical fiber is optically coupled to the light couple lens. External laser beam introduced by the optical fiber are optically coupled by the light coupling lens for collimating and mixing the light beams, then collimated by the at least one light collimating lens, and finally emitting out. A backlight module using the optical guiding device with colored semiconductor lasers and light transferring device are also provided. The backlight module has a good color performance, such as high color saturation. | 2009-04-30 |
20090109707 | Push button release for luminaires in a track lighting system - The invention provides an apparatus for engaging and disengaging a track lighting assembly with respect to a track in a track lighting system. The apparatus includes a track engaging apparatus that includes a housing. The housing includes a rotation inhibitor that has a protruding end that protrudes from the housing for engaging with the track and preventing the track engaging apparatus from rotating with respect to the track. The rotation inhibitor further includes a receiving member for translating a force in a first direction into motion of the rotation inhibitor in a second direction substantially orthogonal to the first direction. The apparatus further includes an actuator for applying the force in the first direction to the receiving member. | 2009-04-30 |
20090109708 | RADIANCE LIGHTING SYSTEM AND METHOD - A lighting system includes a wiring system and a plurality of light source modules adapted for connection to and disconnection from the wiring system Each light source module includes at least one light source unit including a plurality of light emitting diodes, wherein each of the light emitting diodes is independently connected with the wiring system The lighting system of the invention may be modular, allowing use of a suitable number and arrangement of light source modules for illuminating a given space or surface The lighting system may be adapted for being mounted, e g, to structures such as walls, ceilings, and the like, via a mounting assembly The lighting system may be suitable for, but not limited to, shedding visible light directly or indirectly to a space or a surface | 2009-04-30 |
20090109709 | SWITCHING POWER SUPPLY - The first choke coil and the third choke coil are not magnetically coupled to the second choke coil and the fourth choke coil. Therefore, even in a case where a structure for increasing the heat radiation area is adopted, a pair of the first and third choke coils and a pair of the second and fourth choke coils located between the two ends of the capacitor maintain a state of equilibrium so as to be inversely proportional to mutual loss without affecting one another, and the output therefore stabilizes. Accordingly, the output of the switching power supply, that is, the rectified and smoothed output across the two ends of the capacitor stabilizes. | 2009-04-30 |
20090109710 | Switching power supply unit - A switching power supply unit is provided, in which circuit efficiency can be effectively improved compared with a usual case. Secondary windings of a transformer are configured of two sheet metals. Rectifier diodes in a rectifier circuit are connected between the two sheet metals. Inductance of a line between the rectifier elements and the secondary windings is reduced compared with the usual case where rectifier elements are connected between secondary windings and a wiring area, and consequently surge voltage to the rectifier elements is effectively suppressed. A plurality of diode chips configuring the rectifier diodes are preferably disposed at equal spaces along a winding direction of each of the sheet metals. | 2009-04-30 |
20090109711 | Three-pin integrated synchronous rectifier and a flyback synchronous rectifying circuit - A three-pin integrated synchronous rectifier is the synchronous rectifier chip where the quantity of connection pins is the smallest possible quantity. The three-pin integrated synchronous rectifier uses a control pin to receive a control signal used as a power bias voltage and a synchronous pulse to make the synchronous rectifier chip operate normally. The control signal is obtained from the output pin of an auxiliary winding via a diode. The other pins are respectively the drain pin and the source pin of an internal power transistor and are connected with the output winding and the voltage output terminal for transmitting the power of the transformer to supply current for the loading. | 2009-04-30 |
20090109712 | Capacitor based energy storage - An electrical storage device comprises a capacitor or capacitor bank capable of storing significant quantities of electricity. An inverter in circuit with the capacitor converts direct energy of the capacitor into alternating current. A variable ratio transformer is in circuit with the output of the inverter to produce an alternating current output of controlled voltage. The impedance of the transformer acts to prolong discharge of the capacitor over a significant time period. To further control the rate of discharge of the energy storage capacitor, an additional capacitor may be provided in the transformer circuit. | 2009-04-30 |
20090109713 | Variable speed drive - Systems and methods for improved Variable Speed Drives are provided. One embodiment relates to apparatus for common mode and differential mode filtering for motor or compressor bearing protection when operating with Variable Speed Drives, including conducted EMI/RFI input power mains mitigation. Another embodiment relates to a method to extend the synchronous operation of an Active Converter to the AC mains voltage during complete line dropout. Another embodiment relates to an Active Converter-based Variable Speed Drive system with Improved Full Speed Efficiency. Another embodiment relates to a liquid- or refrigerant-cooled inductor. The liquid- or refrigerant-cooled inductor may be used in any application where liquid or refrigerant cooling is available and a reduction in size and weight of a magnetic component is desired. | 2009-04-30 |
20090109714 | POWER SUPPLY MODULE ADAPTED TO POWER A CONTROL CIRCUIT OF A SWITCHING MODE POWER SUPPLY - A power supply module to power the control circuit of a switching mode power supply is provided. Based on the determination of whether the switching mode power supply is under a light or open load condition, the power supply module can dynamically provide the power to the control circuit of the switching mode power supply. Therefore, the performance of the power supply can be increased and the power loss can be decreased when the switching mode power supply is under a light or open load. | 2009-04-30 |
20090109715 | SYNCHRONOUS RECTIFYING FOR SOFT SWITCHING POWER CONVERTERS - An synchronous rectifying apparatus or synchronous rectifying circuit of a soft switching power converter is provided to improve the efficiency. The integrated synchronous rectifying circuit includes: a power transistor connected from a transformer to the output of the power converter for rectifying; a controller having a latch circuit generates a drive signal to control the power transistor in response to a switching signal generated by a winding of the transformer in response to the switching of the transformer. The controller turns off the power transistor when the switching signal is lower than a low-threshold. The power transistor is turned on when the switching signal is higher than a high-threshold. Furthermore, a maximum-on-time circuit provided in the controller is applied to generate a maximum-on-time signal for limiting the maximum on time of the power transistor. | 2009-04-30 |
20090109716 | Method and Apparatus for Supplying and Switching Power - An exemplary embodiment of an apparatus for supplying and switching power may include a power source, a transformer, a full bridge rectifier and a control switch. The transformer has a first winding and a second winding, the first winding being connected to the power source, the second winding having a first tap and a second tap, with the first tap being connected to a first load output. The full bridge rectifier includes four nodes, the first being connected to the second tap of the second winding, the second being connected to a second load output, the third being connected to a reference voltage source. The control switch is connected between a fourth of the four nodes and the reference voltage source. | 2009-04-30 |
20090109717 | POWER FACTOR CORRECTED CIRCUIT HAVING INTEGRATED COIL - There is provided a power factor corrected circuit having an integrated coil in which a plurality of inductors that have been separately used for circuits are wound around one core. The power factor corrected circuit includes a rectifying unit for rectifying a common AC power supply; a coil unit for controlling the change in electric current of the rectified power supply from the rectifying unit according to the switching operation; and a switching unit for complementarily switching the power supply from the coil unit, wherein the coil unit has a core including first and second coils electrically coupled to each other; and first, second and third legs magnetically coupled to each other, and the first coil is wound around the first leg, the second coil is wound around the second leg, and the third leg is combined with the first and the second leg to form magnetic flux paths, respectively. | 2009-04-30 |
20090109718 | INTEGRATED CIRCUIT INCLUDING A CONTROLLER FOR REGULATING A POWER SUPPLY - An integrated circuit includes a controller configured to regulate an output of a power supply based on a first signal. The integrated circuit includes an input configured to receive the first signal and to be coupled to an external capacitor that sets an adjustable blanking time for the power supply. | 2009-04-30 |
20090109719 | System and Method for Providing Content-Addressable Magnetoresistive Random Access Memory Cells - A content-addressable random access memory having magnetic tunnel junction-based memory cells and methods for making and using same. The magnetic tunnel junction has first and second magnetic layers and can act as a data store and a data sense. Within each cell, registered data is written by setting a magnetic orientation of the first magnetic layer in the magnetic tunnel junction via current pulses in one or more current lines. Input data for comparison with the registered data can be similarly set through the magnetic orientation of the second magnetic layer via the current lines. The data sense is performed by measuring cell resistance, which depends upon the relative magnetic orientation of the magnetic layers. Since data storage, data input, and data sense are integrated into one cell, the memory combines higher densities with non-volatility. The memory can support high speed, reduced power consumption, and data masking. | 2009-04-30 |
20090109720 | Memory Structure - The subject matter of this specification can be embodied in, among other things, a method for manufacturing and a structure of a byte-addressable electrically erasable programmable read-only memory (EEPROM). In a first aspect, a byte-addressable EEPROM integrated circuit includes isolation means, in each of a plurality of memory bytes, for electrically isolating the EEPROM byte select transistor from an EEPROM memory bit disposed closest to the byte select transistor. In one example, the isolation means precludes the need to use a wide STI oxide for isolation, and thereby avoids the process variation of active area of memory bits. | 2009-04-30 |
20090109721 | NONVOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI LEVEL CELLS WITHIN SAID ARCHITECTURE. - An apparatus comprising a two or three dimensional array of a plurality of pairs of non-volatile memory (“NVM”) cells coupled to enable program and erase of the NVM cells. The plurality of pairs of NVM cells is electrically connected to word lines and bit lines. Each pair of NVM cells comprises a first memory cell and a second memory cell. The first and second memory cells comprise a first source/drain, a second source/drain, and a control gate. The first source/drain of the first memory cell is connected to one of the bit lines. The second source/drain of the first memory cell is connected to the first source/drain of the second memory cell. The second source/drain of the second memory cell is connected to another one of the bit lines. The control gates of the first and second memory cells are connected to different word lines. | 2009-04-30 |
20090109722 | REPROGRAMMABLE ELECTRICAL FUSE - The present invention provides a reprogrammable electrically blowable fuse and associated design structure. The electrically blowable fuse is programmed using an electro-migration effect and is reprogrammed using a reverse electro-migration effect. The state (i.e., “opened” or “closed”) of the electrically blowable fuse is determined by a sensing system which compares a resistance of the electrically blowable fuse to a reference resistance. | 2009-04-30 |
20090109723 | Quad SRAM Based One Time Programmable Memory - A quad SRAM based one time programmable memory cell is provided. Prior to programming, the memory cell operates as an SRAM memory cell. After programming, the memory cell operates as a one-time programmable non-volatile memory cell. The memory cell includes a storage element coupled at a first side to a first upper fuse and a first lower fuse and coupled at a second side to a second upper fuse and a second lower fuse. When the first upper fuse and second lower fuse are programmed, the storage element outputs a first value. When the second upper fuse and first lower fuse are programmed, the storage element outputs a second value. After programming the upper fuse acts as a pull-up fuse and the lower fuse acts as a pull-down fuse hold the state of the cell. | 2009-04-30 |
20090109724 | Differential Latch-Based One Time Programmable Memory - A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse. | 2009-04-30 |
20090109725 | Data storage in circuit elements with changed resistance - A method of storing data in an array of circuit elements, said method comprising injecting a current into selected circuit elements, said current causing a persistent change in a resistance of said selected circuit elements from a first resistance to a second higher resistance indicative of a binary data bit, wherein said current does not break an electrical circuit in which said circuit element is disposed. | 2009-04-30 |
20090109726 | NON-LINEAR CONDUCTOR MEMORY - A high-speed, low-power memory device comprises an array of non-linear conductors wherein the storage, address decoding, and output detection are all accomplished with diodes or other non-linear conductors. In various embodiments, the row and column resistors are switchable between a high resistance when connected to a row or column that is non-selected, and a low resistance when connected to the selected row and column. | 2009-04-30 |
20090109727 | Erase, programming and leakage characteristics of a resistive memory device - The present method provides annealing of a resistive memory device so as to provide that the device in its erased state has a greatly increased resistance as compared to a prior art approach. The annealing also provides that the device may be erased by application of any of a plurality of electrical potentials within an increased range of electrical potentials as compared to the prior art. | 2009-04-30 |
20090109728 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device including memory cells arranged, the memory cell having a stable state with a high resistance value and storing in a non-volatile manner such multi-level data that at least three resistance values, R | 2009-04-30 |
20090109729 | RESISTANCE CHANGE MEMORY DEVICE AND METHOD FOR ERASING THE SAME - A resistance change memory device including a cell array with memory cells arranged therein to store a resistance value as data in a non-volatile manner, and an erase circuit configured to set the memory cells in the cell array in a reset state prior to data writing, wherein the erase circuit includes: an erase current generating circuit configured to output erase current of the cell array; multiple switch devices so disposed on current paths between the erase current generating circuit and the respective divided areas defined in the cell array as to supply the erase current to the divided areas; and a control circuit configured to sequentially turn on the switch devices. | 2009-04-30 |
20090109730 | RESISTANCE MEMORY ELEMENT - A resistance memory element includes an elementary body and opposing electrodes separated by at least a portion of the elementary body. The elementary body is preferably made of a strontium titanate-based semiconductor ceramic expressed by the formula: (Sr | 2009-04-30 |
20090109731 | DIELECTRIC LAYERS AND MEMORY CELLS INCLUDING METAL-DOPED ALUMINA - A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process. | 2009-04-30 |
20090109732 | ASYMMETRICAL SRAM CELL WITH SEPARATE WORD LINES - An integrated circuit includes a memory array having a plurality of SRAM memory cells arranged in a plurality of rows and columns, the array also having a plurality of word lines for accessing rows of cells and a plurality bit lines for accessing columns of cells. The plurality of memory cells include a plurality of asymmetric cells, each of the asymmetric cells configured with a strong side including a first inverter having a strong side latch node, and a strong side pass transistor coupled to the strong side latch node, and a weak side including a second inverter cross-coupled with the first inverter having a weak side latch node and a weak side pass transistor coupled to the weak side latch node. Separate ones of the plurality of word lines are coupled to a gate of the strong side pass transistor and a gate of the weak side pass transistor. | 2009-04-30 |
20090109733 | Design structure for sram active write assist for improved operational margins - A design structure embodied in a machine-readable medium used in a design process is provided. The design structure comprises a static random access memory (“SRAM”), including a plurality of cells arranged in an SRAM having a plurality of columns; and a voltage control circuit operable to temporarily raise a voltage level of a low voltage reference to cells belonging to a column selected for writing from the plurality of columns, wherein the voltage control circuit includes a first n-type field effect transistor (“NFET”) and a second NFET, the first NFET having a conduction path connected between ground and the low voltage reference, the second NFET having a conduction path connected between a power supply and the low voltage reference. | 2009-04-30 |
20090109734 | NON-VOLATILE SRAM CELL - Methods, devices and systems for non-volatile static random access memory (SRAM) are provided. One method embodiment for operating an SRAM includes transferring data from a pair of static storage nodes of the SRAM to a pair of non-volatile storage nodes when the SRAM is placed in a standby mode. The method further includes transferring data from the pair of non-volatile storage nodes to the pair of static storage nodes when the SRAM exits the standby mode. | 2009-04-30 |
20090109735 | DESIGN STRUCTURE FOR INITIALIZING REFERENCE CELLS OF A TOGGLE SWITCHED MRAM DEVICE - A design structure embodied in a machine readable medium used in a design process includes an apparatus for initializing a reference cell in a toggle switched MRAM device, with a first sense amplifier configured for performing a first read operation of the reference cell by comparing current through the reference cell with the average current passing through a pair of data cells; a first latch for storing the result of the first read operation; a second latch for storing the result of a second read operation by the first sense amplifier, wherein the second read operation is performed following the first read operation and the inversion of the value of one of the pair of the data cells; a third latch for storing the result of a third read operation by the first sense amplifier, wherein the third read operation is performed following the second read operation and the inversion of the value of the other of the pair of the data cells; and a majority compare device configured to compare of the results of the first, second and third operations respectively stored in the first, second and third latches, wherein an output of the majority compare operation is the initial state of the reference cell. | 2009-04-30 |
20090109736 | MAGNETIC RANDOM ACCESS MEMORY AND OPERATION METHOD THEREOF - The MRAM includes: a memory cell | 2009-04-30 |
20090109737 | Method of restoring variable resistance memory device - Methods of programming a phase-change memory device that remedy device failure. The methods includes applying a sequence of two or more electrical energy pulses to the device, where the sequence of pulses includes positive polarity pulses and negative polarity pulses. In one method, two or more pulses of an initial polarity are applied and are followed by one or more pulses having opposite polarity. In another method, pulses of an initial polarity are repeatedly applied until the device fails and one or more pulses of opposite polarity are subsequently applied to restore the device to its initial performance. The pulses may be set pulses, reset pulses, or pulses that produce programmed states having a resistance intermediate between the set resistance and reset resistance of the device. | 2009-04-30 |
20090109738 | PHASE-CHANGE MEMORY DEVICE WITH ERROR CORRECTION CAPABILITY - A phase-change memory device includes a plurality of data PCM cells for storing data bits; data decoding circuits for selectively addressing sets of data PCM cells; and data read/program circuits for reading and programming the selected data PCM cells. The device further includes a plurality of parity PCM cells for storing parity bits associated with data bits stored in the data PCM cells; parity decoding circuits for selectively addressing sets of parity PCM cells; and parity read/program circuits for reading and programming the selected parity PCM cells. | 2009-04-30 |
20090109739 | LOW CURRENT SWITCHING MAGNETIC TUNNEL JUNCTION DESIGN FOR MAGNETIC MEMORY USING DOMAIN WALL MOTION - A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall. | 2009-04-30 |
20090109740 | Semiconductor device using magnetic domain wall movement - Provided may be a semiconductor device using magnetic domain wall movement. The semiconductor device may include a magnetic track having a plurality of magnetic domains and a thermal conductive insulating layer configured to contact the magnetic track. The thermal conductive insulating layer may prevent or reduce the magnetic track from being heated due to a current supplied to the magnetic track. | 2009-04-30 |
20090109741 | DETERMINING HISTORY STATE OF DATA IN DATA RETAINING DEVICE BASED ON STATE OF PARTIALLY DEPLETED SILICON-ON-INSULATOR - An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a partially depleted silicon-on-insulator (PD SOI) device electrically coupled to the data retaining device; and a measurement device coupled to the PD SOI device for measuring a state of the PD SOI device indicating a body voltage thereof, the measuring device being communicatively coupled to a calculating means which determines a history state of a data in the data retaining device based on the measured state of the PD SOI device. | 2009-04-30 |
20090109742 | CONTROL OF TEMPERATURE SLOPE FOR BAND GAP REFERENCE VOLTAGE IN A MEMORY DEVICE - Systems and/or methods are presented that can facilitate regulating performance of operations in a memory device based on controlling an operating temperature slope associated with the memory device. A regulator component can facilitate controlling the operating temperature slope level and controlling a reference voltage(s) associated with a word-line(s) and/or bit-line(s) to facilitate execution of operations in a memory, while also controlling a respective current level(s) associated with the reference voltage to minimize errors in the memory or harm to the memory. The reference voltage can be controlled based on a first resistance and the current level can be controlled based on a second resistance that can be based on the first resistance. An analyzer component can facilitate determining a desired operating temperature slope level. Trim bits can be employed to facilitate setting the first resistance and/or the second resistance. | 2009-04-30 |
20090109743 | MULTILEVEL MEMORY CELL OPERATION - One or more embodiments of the present disclosure provide methods, devices, and systems for operating non-volatile multilevel memory cells. One method embodiment includes programming a memory cell to one of a number of different threshold voltage (Vt) levels, each level corresponding to a program state. The method includes programming a reference cell to a Vt level at least as great as an uppermost Vt level of the number of different Vt levels, performing a read operation on the reference cell, and determining a number of read reference voltages used to determine a particular program state of the memory cell based on the read operation performed on the reference cell. | 2009-04-30 |
20090109744 | SENSING MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes programming at least one of the memory cells to one of a number of states. The method also includes programming at least another one of the memory cells, which is adjacent to the programmed at least one of the memory cells, to one of a different number of states. The method further includes sensing non-erased states of the memory cells using at least one common voltage level. | 2009-04-30 |
20090109745 | NON-VOLATILE MULTILEVEL MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes assigning, to a first cell coupled to a row select line, a first number of program states to which the first cell can be programmed. The method includes assigning, to a second cell coupled to the row select line, a second number of program states to which the second cell can be programmed, wherein the second number of program states is greater than the first number of program states. The method includes programming the first cell to one of the first number of program states prior to programming the second cell to one of the second number of program states. | 2009-04-30 |
20090109746 | MEMORY CELL PROGRAMMING - One or more embodiments include programming, in parallel, a first cell to one of a first number of states and a second cell to one of a second number of states. Such embodiments include programming, separately, the first cell to one of a third number of states based, at least in part, on the one of the first number of states and the second cell to one of a fourth number of states based, at least in part, on the one of the second number of states. | 2009-04-30 |
20090109747 | FRACTIONAL BITS IN MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for programming memory cells. One method embodiment includes storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. The method also includes storing a charge in a cell of the set, where the charge corresponds to a programmed state, where the programmed state represents a fractional number of bits, and where the programmed state denotes a digit of the data state as expressed by a number in base N, where N is equal to 2 | 2009-04-30 |
20090109748 | Apparatus and method of multi-bit programming - Multi-bit programming apparatuses and/or methods are provided. A multi-bit programming apparatus may include: a first control unit that allocates any one of 2 | 2009-04-30 |
20090109749 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a nonvolatile memory including a first area which stores data for every n bits (n is a natural number of not less than 2), and a second area which stores data for every 1 bit, each of the first area and the second area including a plurality of memory cells each configured to store n-bit data on the basis of a threshold voltage, and a controller which sets 2 | 2009-04-30 |
20090109750 | SEMICONDUCTOR MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE FUNCTIONALITY AND METHOD OF OPERATING - Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping latter for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory, as non-volatile memory when power to the device is interrupted. | 2009-04-30 |
20090109751 | NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING - Embodiments of the present disclosure provide methods, devices, modules, and systems for programming an array of non-volatile multilevel memory cells to a number of threshold voltage ranges. One method includes programming a lower page of a first wordline cell to increase a threshold voltage (Vt) of the first wordline cell to a first Vt within a lowermost Vt range. The method includes programming a lower page of a second wordline cell prior to programming an upper page of the first wordline cell. The method includes programming the upper page of the first wordline cell such that the first Vt is increased to a second Vt, wherein the second Vt is within a Vt range which is then a lowermost Vt range and is positive. | 2009-04-30 |
20090109752 | MEMORY CELL HEIGHTS - Embodiments of the present disclosure provide methods, arrays, devices, modules, and systems for memory cell heights. One array of memory cells includes a number of semiconductor pillars having a number of charge storage nodes, each of the charge storage nodes being associated with a respective number of pillars and separated from the respective pillars by a dielectric. The array also includes a number of conductively coupled gates, each of the number of gates being associated with a respective one of the number of storage nodes. At least two pillars in the array have different heights. | 2009-04-30 |
20090109753 | NONVOLATILE SEMICONDUCTOR MEMORY - A semiconductor memory device including: a package; a first semiconductor chip provided in the package; a first nonvolatile memory provided on the first semiconductor chip; a second semiconductor chip provided in the package; a second nonvolatile memory provided on the second semiconductor chip; a system bus provided in the package, the system bus connecting the first and second nonvolatile memories; a plurality of data terminals exposed to outside of the package, the data terminals being connected to the first and second nonvolatile memories through the system bus; and an enable terminal exposed to the outside of the package, the enable terminal being connected to the first and second nonvolatile memories. | 2009-04-30 |
20090109754 | NON-VOLATILE MEMORY ARRAY ARCHITECTURE WITH JOINED WORD LINES - In an embodiment, a non-volatile memory array wherein narrow word lines, as small as the minimum feature size width F, in separate strings, are extended outwardly from a non-volatile memory array and joined by wider connector segments. The joined word lines provide new opportunities. First, metal straps that can be formed to overlie the word lines can be joined by metal connector segments to the word lines. The connector segments can serve as an interface between the polysilicon word lines and the metal straps. Two adjacent word lines in the same string share a single metal strap using these segments thereby reducing the overall number of segments and contacts in the array. Increased width of the polysilicon joinder segments joining word lines in different strings, provides the opportunity for widening the connection beyond the minimum feature size so that contact may be readily made between the metal straps and the polysilicon word lines. Second, the joined word lines require fewer row decoder circuits. One row decoder is provided for each joined set of word lines. | 2009-04-30 |
20090109755 | Neighbor block refresh for non-volatile memory - Two or more erase sectors (blocks) in a given physical sector of the array. When (after) erasing a target block, determining whether a neighbor block needs to be refreshed by checking a sub-population of Vt distributions at a given program level. Various timings and strategies for performing the refresh operation are disclosed. The effects of word line disturb (gate disturb) may thereby be reduced. | 2009-04-30 |
20090109756 | MEMORY DEVICE WITH VARIABLE TRIM SETTING - A memory device includes a memory array including a plurality of cells. The cells are divided into a plurality of subsets. Each subset has at least one associated trim parameter. The trim parameter for each subset is stored in the memory array within the associated subset. Circuitry is operable to program at least a portion of a selected subset using the associated trim parameter. A method for operating a memory device includes storing at least one trim parameter for each of a plurality of subsets of a memory array in the memory device within each of the subsets. At least a portion of a selected subset is programmed based on the at least one trim parameter associated with the selected subset. | 2009-04-30 |
20090109757 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. The present invention also provides a method of controlling the semiconductor device. | 2009-04-30 |
20090109758 | NONVOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI LEVEL CELLS WITHIN SAID ARCHITECTURE - A system comprising a program component that programs one or more non-volatile memory (“NVM”) cells of an array of pairs of NVM cells using FN tunneling, an erase component that erases the one or more NVM cells of the array of pairs of NVM cells using FN tunneling, and a read component that reads the one or more NVM cells of the array of pairs of NVM cells. | 2009-04-30 |
20090109759 | OPERATING MEMORY CELLS - Embodiments of the present disclosure provide methods, devices, modules, and systems for reading non-volatile memory cells. One method includes programming a number of memory cells coupled in series between a first and second select gate transistor where edge cells are coupled adjacent to the select gate transistors and non-edge cells are coupled between the edge cells. The method includes programming a non-edge cell within a first threshold voltage (Vt) distribution. The method also includes programming an edge cell within a second Vt distribution, wherein the first and second Vt distributions correspond to a same one of a number of data states, and wherein the second Vt distribution is different than the first Vt distribution for at least one of the number of data states. | 2009-04-30 |
20090109760 | DETERMINISTIC PROGRAMMING ALGORITHM THAT PROVIDES TIGHTER CELL DISTRIBUTIONS WITH A REDUCED NUMBER OF PROGRAMMING PULSES - Systems and methods for improving the programming of memory devices. A pulse component applies different programming pulses to a memory cell. An analysis component measures values of one or more characteristics of the memory cell as a function of the applied different programming pulses. A computation component computes the applied different programming pulses as a function of the measured values of the one or more characteristics of the memory cell. The analysis component measures one or more values of the one or more characteristics of the memory cell, the computation component computes one or more programming pulses as a function of the one or more measured values of the one or more characteristics of the memory cell, and the pulse component applies the one or more programming pulses to the memory cell. | 2009-04-30 |
20090109761 | Method of operating nonvolatile memory device - Provided is a method of operating a three-dimensional nonvolatile memory device which may increase the reliability and efficiency of the three-dimensional nonvolatile memory device. The method of operating a nonvolatile memory device may include: resetting the nonvolatile memory device by injecting charges into charge storage layers of a plurality of memory cells of a block; and setting the nonvolatile memory device by removing at least some of the charges injected into the charge storage layers of one or more memory cells selected from among the plurality of memory cells. | 2009-04-30 |
20090109762 | METHOD FOR PROGRAMMING NON-VOLATILE MEMORY - A method for programming non-volatile memory utilizes substrate hot carrier effect to conduct programming operations. A forward bias voltage is applied between an N-type well region and a P-type well region so as to inject electrons in the N-type well region into the P-type well region. After that, the electrons are accelerated by a depletion region established by a voltage applied to a source region and a drain region, and a vertical electrical field established between a control gate and the P-type well region further forces the electrons to be injected into a charge storage layer. Since the present invention adopts the substrate hot carrier effect to inject carriers into the charge storage layer, the required program operation voltage is low, which benefits to save power consumption and enhance the reliability of the device. | 2009-04-30 |
20090109763 | Semiconductor memory device and method of defective cell test - A semiconductor memory device simultaneously selects an object cell and a counter cell which connect with a common bit line, simultaneously activates sub-word lines of the object cell and the counter cell after predetermined levels are written in the object cell and the counter cell, simultaneously read data of the object cell and the counter cell from the common bit line, and hence, determines whether the object cell is normal or defective, based on a voltage level of the common bit line. Thereby, the defective cell in the semiconductor memory device can be reliably detected. | 2009-04-30 |
20090109764 | INTEGRATED CIRCUIT HAVING SUPPLY VOLTAGE CONTROLLER - An integrated circuit includes a supply voltage controller operable to receive a plurality of control signals and at least one circuit supply voltage and to output at least one variable supply voltage to at least one supply terminal of the integrated circuit The controller is operable to switch the variable supply voltage to a first voltage level when the control signals define a first operation and to a second voltage level different from the first voltage level when the control signals define a second operation. The controller is also operable to float the variable supply voltage to a third voltage level different from the first voltage level when the control signals define a third operation. | 2009-04-30 |
20090109765 | Single via structured IC device - A configurable logic array may include a multiplicity of logic components, which may contain customizable look-up tables, and layers of fixed metal segments all of which may be customizable using a single custom via layer. The integrated circuit containing the configurable logic array may also include a multiplicity of customizable register files, customizable RAM blocks; a ROM block with customizable contents; or test logic With customizable test options and configurations to separately test logic and the PLLs. | 2009-04-30 |
20090109766 | EFFICIENT SENSE COMMAND GENERATION - In one embodiment, a memory includes: an array of memory cells arranged according to word lines and columns, each column corresponding to bit lines; a sense amplifier adapted to couple to the bit lines to sense a binary content of selected cells from the array of memory cells, the sense amplifier sensing the binary content responsive to a sense command; an x-decoder configured to assert a selected one of the word lines in response to decoding an address as triggered by a clock edge, wherein the assertion of the selected word line switches on corresponding access transistors to develop voltages on the bit lines; and a bit line replica circuit adapted to replicate the development of the bit lines, the bit line replica circuit including a replica access transistor coupled between a replica bit line and a replica memory cell wherein the replica access transistor is switched on responsive to the clock edge such that the replica memory cell pulls the replica bit line to ground, the bit line replica circuit also including a comparator that asserts an output in response to comparing a voltage of the replica bit line to a threshold, the sense command being a buffered version of the output from the comparator. | 2009-04-30 |
20090109768 | SRAM Device with Enhanced Read/Write Operations - An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device. | 2009-04-30 |
20090109769 | SIGNAL DESCRAMBLING DETECTOR - Systems and/or methods that facilitate descrambling of data communicated between a memory and a host processor are presented. A descrambler component determines the bit order of data signals from a memory device based on pattern information provided to the descrambler component by the memory device during initialization. The descrambler component can receive one or more distinct patterns and can evaluate the data values associated with such patterns for each data line of the memory. The descrambler component can determine the bit order of the data signals based on such patterns and can generate a transformation function that can facilitate rearranging data, which can be received from or sent to the memory device, into a predetermined bit order. | 2009-04-30 |
20090109770 | SEMICONDUCTOR DEVICE WITH DDR MEMORY CONTROLLER - In a DDR memory controller, a clock control circuit is configured to output a clock signal selected from among a plurality of clock signals with different frequencies based on a frequency selection signal, to a DDR memory as an operation clock signal. A master DLL circuit is configured to receive one of the plurality of clock signals which has a maximum frequency as a reference clock signal to determine a delay code. A slave delay circuit is configured to delay a strobe signal from the DDR memory based on the determined delay code to generate an internal strobe signal for a data signal from the DDR memory. | 2009-04-30 |
20090109771 | Optimizing mode register set commands - In one embodiment, the present invention includes a method for generating a mode register set (MRS) decoded signal to identify presence of a MRS command in the register device of a registered DIMM memory, delaying the MRS decoded signal for a predetermined delay and disabling address inversion using the delayed MRS decoded signal, switching from a first command timing frequency to a second command timing frequency for a predetermined number of clock cycles, performing a MRS command to a mode register of the DRAM device, and switching back to the first command timing frequency. Other embodiments are described and claimed. | 2009-04-30 |
20090109772 | RAM WITH INDEPENDENT LOCAL CLOCK - In one embodiment, a random access memory (RAM) is provided that includes: an array of memory cells arranged in rows corresponding to word lines, the memory cells also being arranged in columns corresponding to bit lines; a local clock source that asserts a local clock in response to an assertion of an external clock; a plurality of x-decoders, each x-decoder adapted to assert a corresponding one of the word lines in response to a decoding of an appropriate address, wherein the assertion of a word line couples a corresponding row of the memory cells to their bit lines such that the bit lines are developed with corresponding voltages; and a plurality of sense amplifiers adapted to sense the voltage developments of the bit lines so as to determine a binary content of the memory cells, wherein the local clock source is triggered to de-assert the local clock independently of whether the external clock has been de-asserted. | 2009-04-30 |
20090109773 | SEMICONDUCTOR DEVICE AND REFRESH METHOD - In order to successively perform refresh operations, a semiconductor device has a plurality of regions performing a repair independently from each other, even when the repair is carried out in the region by a replacement with a repair memory block included in a plate included in each region. Specifically, the successive refresh operations are performed by alternately activating word lines in the respective regions so as to ensure a sufficiently long precharge period. | 2009-04-30 |
20090109774 | TEST METHOD AND SEMICONDUCTOR DEVICE - A test method and a semiconductor device is disclosed. One embodiment provides sending out a test signal by a semiconductor device. A reflected signal generated in reaction is compared to the test signal with a first threshold value. The reflected signal is compared with a second threshold value differing from the first threshold value. | 2009-04-30 |
20090109775 | Precharge voltage supply circuit and semiconductor memory device using the same - A precharge voltage supply circuit and a semiconductor memory device using the same are described. The precharge voltage supply circuit includes a first voltage supplier configured to reduce a precharge voltage and supply the reduced precharge voltage in response to a power down mode signal that is activated in a power down mode, a second voltage supplier configured to supply a power voltage in a predetermined section from a point of time when exiting the power down mode, and a third voltage supplier configured to supply the precharge voltage after a lapse of the predetermined section. | 2009-04-30 |
20090109776 | Sense amplifier driving circult and semiconductor device having the same - The semiconductor memory device blocks a power supply voltage, which is supplied to the sense amplifier, in a write operation, or pull-down drives first and second local I/O lines LIO and LIOB lest they reach the level of ground voltage Vss. Driving time of a write driver of the semiconductor memory device is reduced, and current consumption is reduced. A sense amplifier driving circuit of a semiconductor memory device includes a transfer unit for transferring first and second control signals in response to an enable signal which is activated in a write operation, and a power supply unit for supplying first and second power supply voltages to a sense amplifier in response to the first and second control signals. | 2009-04-30 |