18th week of 2009 patent applcation highlights part 21 |
Patent application number | Title | Published |
20090108876 | DECODER CIRCUIT - The decoder circuit includes: a power supply control circuit for supplying a first voltage; first and second transistors connected in series between the power supply control circuit and a first reference node; and third and fourth transistors connected between a connection node between the first and second transistors and a second reference node. The first transistor receives a first signal at its gate, and the second transistor receives a second signal corresponding to the first signal at its gate. The third transistor receives a third signal at its gate, and the fourth transistor receives a fourth signal corresponding to the third signal at its gate. The potential difference between the first voltage and the first reference node is smaller than the potential difference between the first reference node and the second reference node. | 2009-04-30 |
20090108877 | Logic Gate and Semiconductor Integrated Circuit Device Using the Logic Gate - A disclosed logic gate including a CMOS circuit having a p-channel MOS transistor and an n-channel MOS transistor and also includes a resistance device connected in series with a source or a drain of at least one of the p-channel MOS transistor and the n-channel MOS transistor, a switching device connected in parallel with the resistance device and configured to switch on and off, and a switching control circuit configured to control the switching on and off of the switching device according to an output signal output from the CMOS circuit. | 2009-04-30 |
20090108878 | HIGH-FREQUENCY CLOCK DETECTION CIRCUIT - In order to provide a high frequency clock detection circuit capable to detect a high frequency clock using any period as a threshold, the high frequency clock detection circuit of the present invention includes a delay circuit having a delay time set to be longer than a clock period corresponding to the irregular high frequency state, a first flip-flop circuit for delay flip-flopping according to the clock signal and for being provided with the inverted and feedback inputted output from the first flip-flop circuit, a second flip-flop circuit for delay flip-flopping according to the clock signal and for being provided with the inverted and feedback inputted output from the second flip-flop circuit through the delay circuit, and a detection-result output circuit for detecting a difference between the output signal from the first flip-flop circuit and the output signal from the second flip-flop circuit and for providing the function circuit with the high frequency clock detection signal indicating the irregular high frequency state corresponding to an occurrence of the difference. | 2009-04-30 |
20090108879 | PROGRAMMABLE SENSITIVITY FREQUENCY COINCIDENCE DETECTION CIRCUIT AND METHOD - A frequency coincidence detection circuit for detecting frequency edges for each of a plurality of periodic digital signals. The circuit generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The circuit determines a signal coincidence of the coincidence windows. In another embodiment, a frequency coincidence detection method is provided. The method detects frequency edges for each of a plurality of periodic digital signals, generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The method determines a signal coincidence of the coincidence windows. | 2009-04-30 |
20090108880 | Systems, Circuits and Methods for Extended Range Input Comparison - Various embodiments of the present invention provide systems and circuits for processing information through comparison of input signals. For example, various embodiments of the present invention provide comparator circuits that include two input stages that each receive a first input and a second input. One of the input stages is sensitive to a difference between the first input and the second input for at least a low common mode, and provides a first output. The other of the input stages is sensitive to a difference between the positive input and the negative input for at least a high common mode, and provides a second output. The comparator circuits further include a regeneration stage that receives the first output and the second output, and provides a comparator output reflecting the difference between the first input and the second input. | 2009-04-30 |
20090108881 | Latch-Based Sense Amplifier - Various embodiments of the present invention provide systems and circuits for processing information through comparison of input signals. For example, various embodiments of the present invention provide differential latch circuits. Such differential latch circuits include an input stage and a latch stage. The input stage provides an interim output that is available during a defined period, and the latch stage is operable to latch the temporary interim output during the defined period using a common clock. | 2009-04-30 |
20090108882 | LOW POWER LOW VOLTAGE DIFFERENTIAL SIGNALING (LVDS) OUTPUT DRIVERS - A method and apparatus for providing a low power low voltage differential signaling driver are disclosed. In an example, a low voltage differential signaling driver circuit is described, comprising a first current source to provide current to a first differential pair of PNP transistors, a pair of transresistance amplifiers driven by a corresponding pair of transconductance stages, a second current source to provide current to a second differential pair of PNP transistors, and an output port having a common mode output voltage and a differential output voltage based on a state of the first differential pair of PNP transistors and the second differential pair of PNP transistors. | 2009-04-30 |
20090108883 | Digital sine wave generator - In accordance with described exemplary embodiments, correction is inserted into the feedback loop of a second order resonator used at the time of frequency transition. The correction is based upon parameters generated from a desired output signal frequency and a desired sampling frequency. The correction is generated to maintain i) constant amplitude, ii) continuous phase, and iii) the same sampling frequency during the frequency transition. | 2009-04-30 |
20090108884 | High Side Boosted Gate Drive Circuit - A high-side boosted gate drive circuit is disclosed. In a particular example, an output driver is described, comprising a switching device configured to selectively conduct current in response to a charge being present at a control terminal for a duty cycle, a charging device configured to deliver charge to the control terminal based on the first duty cycle, a charge control device configured to selectively couple the charging device to deliver charge to the control terminal and to selectively decouple the charging device from the control terminal to charge the charging device, and a discharge control device configured to remove charge from the control terminal. | 2009-04-30 |
20090108885 | Design structure for CMOS differential rail-to-rail latch circuits - A design structure including a CMOS rail-to-rail differential latch is provided in which a plurality of cross-coupled devices pull first and second nodes of the latch to opposite rail-to-rail voltages. Desirably, first and second output isolating elements have inputs coupled to the first and second nodes, the output isolating elements being operable to output versions of the opposite rail-to-rail voltages as a true and a complementary output of the latch. In this way, the true output has a rising edge occurring simultaneously with a falling edge of the complementary output. The complementary output has a rising edge occurring simultaneously with a falling edge of the true output. First and second input isolating elements of the latch have outputs coupled to the first and second nodes, the first and second input isolating elements being operable to apply versions of input signals to the first and second nodes. | 2009-04-30 |
20090108886 | Semiconductor Device - A semiconductor device includes a circuit having a first data holding node and a second data holding node; a first MOS field-effect transistor coupled to the first data holding node; a second MOS field-effect transistor coupled to the second data holding node; and a clock generation circuit coupled to a first gate electrode of the first MOS field-effect transistor for outputting a clock signal, wherein the first gate electrode is coupled to the second data holding node via the second MOS field-effect transistor, and a second gate electrode of the second MOS field-effect transistor is coupled to the first data holding node via the first MOS field-effect transistor. | 2009-04-30 |
20090108887 | FAST POWER-ON DETECT CIRCUIT WITH ACCURATE TRIP-POINTS - A power-on reset circuit includes a first PNP transistor having an emitter, a base, and a collector coupled to ground; a second PNP transistor having an emitter coupled to the base of the first transistor, and a base and collector coupled to ground; a third PNP transistor having an emitter, a base coupled to the base of the first transistor, and a collector coupled to ground; a first resistor coupled between VDD and an internal node; a second resistor coupled between VDD and the emitter of the first transistor; a third resistor coupled between the internal node and the emitter of the third transistor; and a comparator having a first input coupled to the internal node and a second input coupled to the emitter of the first transistor for generating a power-on reset signal. | 2009-04-30 |
20090108888 | Switched-Capacitor Charge Pumps - A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit advantageously utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors. | 2009-04-30 |
20090108889 | Precision Integrated Phase Lock Loop Circuit Loop Filter - A loop filter in a phase lock loop circuit comprising a reference precision resistor, a first FET and a second FET, wherein the gate of the first FET is tied to the gate of the second FET, and a filter capacitor connected to the first FET for producing a capacitor voltage. The capacitor voltage is applied to the source of the first FET, the source of the second FET, and to the bottom of the reference precision resistor acting as a virtual ground. The capacitor voltage generated by the filter capacitor sets the bias point of the second FET such that the second FET comprises characteristics of an integrated precision resistor. A predetermined voltage generated by the second FET is applied to the gate of the first FET to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor. | 2009-04-30 |
20090108890 | Internal Supply Voltage Controlled PLL and Methods for Using Such - Various embodiments of the present invention provide systems and circuits for clock signal generation. For example, various embodiments of the present invention provide semiconductor devices that include a power source and a phase lock loop circuit. The power source provides a supply voltage to the phase lock loop circuit. The phase lock loop circuit includes and on-chip control voltage source and a voltage controlled oscillator. The on-chip control voltage source is capable of producing a control voltage that varies between a minimum voltage and a maximum voltage. The voltage controlled oscillator receives the control voltage and provides a clock signal with a frequency corresponding to the control voltage. The maximum voltage is greater than the supply voltage. For example, in some embodiments of the present invention, the maximum voltage is more than double the supply voltage. As another example, in some embodiments of the present invention, the maximum voltage is more than six times the supply voltage. | 2009-04-30 |
20090108891 | BANDWIDTH CONTROL IN A MOSTLY-DIGITAL PLL/FLL - Methods and apparatus for controlling a controlled oscillator using a phase-locked loop (PLL) or frequency-locked loop (FLL) having a digital loop filter with programmable filter parameters. An exemplary PLL (or FLL) includes a digital loop filter having one or more of the programmable filter parameters, which are changed by increments during operation in order to minimize disturbances (e.g., settling transients) as the loop bandwidth of the PLL is varied from a narrow loop bandwidth to a wide loop bandwidth, or vice versa. By changing the loop filter parameters in increments the loop bandwidth can be varied with substantially no perturbation. The end result is a much faster frequency switching time, improved settling dynamics, and predictable and stable loop operating performance. According to another aspect of the invention, one or more of the programmable filter parameters are changed in order to oppose a change in tuning sensitivity of the controlled oscillator (e.g., in order to maintain a constant loop bandwidth). By holding the loop bandwidth constant, switching time is maintained substantially constant under all conditions. This allows design and production margins to be reduced in a frequency agile system, and also relaxes the tuning sensitivity linearity requirements of the controlled oscillator. | 2009-04-30 |
20090108892 | FREQUENCY SYNTHESIZER - A frequency synthesizer includes: a fractional-N synthesizer configured to provide, in a locked condition, an output signal with an output frequency based on an input signal with a reference frequency, the fractional-N synthesizer including a charge pump outputting a current to be calibrated; a lock detector coupled to the fractional-N synthesizer to detect the locked condition, the lock detector being configured to send a first signal indicating the detection; a calibration component coupled to the lock detector and the fractional-N synthesizer, the calibration component being configured to provide a second signal to calibrate the current after receiving the first signal, based on a voltage sampled from the fractional-N synthesizer; and a current source array coupled to the calibration component and the fractional N synthesizer, the current source array being configured to calibrate the current based on the second signal. | 2009-04-30 |
20090108893 | Electric circuit and method for designing electric circuit - A designing method is provided for designing an electric circuit including a clock output circuit for delivering a clock signal and a plurality of processing circuits for receiving the clock signal from the clock output circuit via wirings for clock transmission so as to perform a predetermined process based on the clock signal. The method includes, as a method for designing the wirings for clock transmission to have a predetermined length, a first step of connecting wirings between each of the processing circuits and an arbitrary point (as a “first point”) so that the wirings have substantially the same length (as a “first length”), and a second step of connecting the first point to the clock output circuit by a single wire having the length that is obtained by subtracting the first length from the predetermined length. Thus, lengths of the wirings for transmitting the clock signal to the plurality of circuits are adjustable while the entire length of the wirings is minimized. | 2009-04-30 |
20090108894 | PWM Signal Generator - After an output signal S | 2009-04-30 |
20090108895 | Latch Structure and Self-Adjusting Pulse Generator Using the Latch - The disclosure includes a latch structure and self-adjusting pulse generator using the latch. In an embodiment, the system includes a first latch and a pulse generator coupled to provide a timing signal to the first latch. The pulse generator includes a second latch that has characteristics matching the first latch. | 2009-04-30 |
20090108896 | Semiconductor Integrated Circuit Apparatus - It is made possible to provide a flip-flop circuit capable of implementing the error correction function with a small area increase as far as possible and a pipeline system using such a flip-flop circuit. A flip-flop circuit includes: a flip-flop configured to operate based on a rising edge or a falling edge of a first clock signal; a decision circuit configured to compare an input of the flip-flop with an output thereof and output a request signal when the input of the flip-flop is different from the output thereof; and a control circuit configured to receive a second clock signal from outside and generate the first clock signal and a confirmation signal. When the request signal is sent from the decision circuit after the flip-flop has been activated, the control circuit inverts the first clock signal, sends the confirmation to the decision circuit, and makes the decision circuit cancel the request signal. | 2009-04-30 |
20090108897 | SEMICONDUCTOR DEVICE AND TIMING CONTROL METHOD FOR THE SAME - A semiconductor device includes a power-supply control portion and a latch portion. The power-supply control portion supplies power to an internal circuit in response to an input signal synchronized with rising of clock. The latch portion latches the input signal in synchronization with falling of the clock and supplies the latched input signal to the internal circuit. | 2009-04-30 |
20090108898 | METHODS AND APPARATUS FOR IMPROVED PHASE SWITCHING AND LINEARITY IN AN ANALOG PHASE INTERPOLATOR - Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal. | 2009-04-30 |
20090108899 | DYNAMIC VOLTAGE SCALING FOR SELF-TIMED OR RACING PATHS - A timing-constrained circuit (e.g., a self-timed circuit) of optimal performance is achieved by allowing the delay of the circuit to be changed dynamically as a function of operating conditions (e.g., operating voltages or temperatures). The delay of timing signals in the timing-constrained circuit for a given operating condition may be selected to have the minimum margin for that operating condition among the available delays to maximize performance over the entire dynamic range of operating conditions. | 2009-04-30 |
20090108900 | APPARATUS AND METHOD FOR OPTIMIZING DELAY ELEMENT IN ASYNCHRONOUS DIGITAL CIRCUITS - A computer readable storage medium includes executable instructions to construct a delay element to replicate the timing of critical gates and paths within a segment of an asynchronous circuit. The rise and fall delay mismatch of the delay element is minimized without obeying timing constraints. The position of each output of the delay element is determined to include a globally shared node within the segment and a non-shared local node in the segment. | 2009-04-30 |
20090108901 | PULSE GENERATION CIRCUIT AND UWB COMMUNICATION DEVICE - A pulse generation circuit for outputting to an output terminal (OT) includes an inverter delay circuit (IDC) for processing a start signal with a predetermined delay; a first switching circuit (SC) adapted to connect the OT to a first voltage when a logical product of the IDC is true, and to connect the OT to a second voltage when a logical sum of the IDC is false; a second SC adapted to connect the OT to the first voltage when a logical product of the IDC is true, and to connect the OT to the second voltage when a logical sum of the IDC is false; and a start signal control circuit adapted to input the start signal to the IDC with a delay when the first SC is activated, and to input the start signal to the IDC without the delay when the second SC is activated. | 2009-04-30 |
20090108902 | Delay Circuit Having Reduced Duty Cycle Distortion - A delay circuit having reduced duty cycle distortion is provided. The delay circuit includes a plurality of delay elements connected together in a series configuration. Each of the delay elements has a prescribed delay associated therewith. The delay circuit further includes a controller connected to respective outputs of the delay elements. The controller is configured such that signal paths between the respective outputs of the delay elements and an output of the controller have delays that are substantially the same relative to one another. Each of the signal paths has a tri-statable switching element associated therewith. | 2009-04-30 |
20090108903 | LEVEL SHIFTER DEVICE - A first transistor of a level shifter provides conductivity between a reference voltage and a node of the level shifter to hold a state of the level shifter output. When an input signal of the level shifter switches, additional transistors assist in reducing the conductivity of the first transistor. This enhances the ability of the level shifter to change the state of the output in response to the change in the input signal, thereby improving the writeability of the level shifter. | 2009-04-30 |
20090108904 | Shifting of a voltage level between different voltage level domains - A voltage level shifter for receiving a digital signal from a first voltage domain and converting said signal to a digital signal in a second voltage domain is disclosed. The voltage level shifter comprises: an input for receiving said digital signal from said first voltage domain; a device connected to said input of said voltage level shifter for receiving said digital signal from said first voltage domain and for outputting a digital signal in said second voltage domain, said device being powered by said second voltage domain; a first switching device arranged to connect a high level voltage source of said second domain to an input of said device in response to said input digital signal having a high level and to isolate said high level voltage source of said second domain from said input of said device in response to said input digital signal having a low level; and a second switching device arranged between said voltage level shifter input and said input of said device for inhibiting current flow from said high level voltage source of said second domain to said voltage level shifter input in response to a high level signal at said voltage level shifter input and for allowing current flow in both directions between said voltage level shifter input and said input of said device in response to said voltage level shifter input having a low level signal. | 2009-04-30 |
20090108905 | Dynamic NP-swappable body bias circuit - A dynamic NP-swappable body bias circuit includes a core circuit, a power switch and a body bias controller. The core circuit includes a body bias terminal. The power switch includes a body bias terminal, and connects the core circuit to an external voltage supply. The body bias controller is connected to the body bias terminals of the core circuit and the power switch so that the power switch and the core circuit are under the control of the body bias controller. | 2009-04-30 |
20090108906 | CABLE DRIVER USING SIGNAL DETECT TO CONTROL INPUT STAGE OFFSET - A system, apparatus and method are arranged for monitoring an input signal for a line driver and determining if a valid data signal is present. When the input signal is determined to be an invalid data signal, an offset is introduced into the input stage of the line driver to prevent noise induced toggling of the output of the line driver. When the input signal is determined to be a valid data signal, the offset is removed from the input stage since inclusion of the offset can introduce undesirable duty cycle distortion in the output of the line driver. By dynamically adding or removing the offset from the input stage of the line driver, invalid signals are prevented from toggling the output of the line driver while preserving a clean data transmission for valid signals. | 2009-04-30 |
20090108907 | SIGNAL DETECTOR OUTPUT FOR CABLE DRIVER APPLICATIONS - The present disclosure relates to a system, apparatus and method for a line driver circuit to generate a signal detect (SD) signal when an invalid data signal is detected at its input. An invalid signal may be present either when no signal is available or when the line driver circuit or another component in the system (e.g., a crosspoint switch, a multiplexer, etc.) fails. The SD signal is coupled to an external controller that can either power down the line driver circuit to save power when no signal is available, or change over to a different line driver circuit or other component of the system when a failure is identified. When the input signal is determined to be a valid data signal via the SD signal, the line driver circuit can be enabled for operation. The described systems, apparatus and methods can save the user from having to directly control the line driver power state, especially in systems with large router configurations that may include hundreds of line drivers. | 2009-04-30 |
20090108908 | BOOTSTRAP CIRCUIT AND STEP-DOWN CONVERTER USING SAME - The invention provides a bootstrap circuit which enables adequate charging of a capacitor used in the bootstrap circuit even during light load or no load conditions, and which does not impede the performance of a step-down converter proper, as well as a step-down converter using the bootstrap circuit. A capacitor charge/discharge path formation mechanism is provided in the bootstrap circuit that enables a terminal of a capacitor used in the bootstrap circuit to be separated and made independent from a step-down converter circuit. | 2009-04-30 |
20090108909 | High Current Power Output Stage - A high current end power stage (PA) comprises at least four power transistors (T), two electrical supply lines and at least a safety fuse (S). The at least four power transistors (T) have each a diode (D) which is blocked during normal operation of the respective power transistor (T). The two electrical supply lines couple the at least four power transistors (T) with a supply potential (Up) and a reference potential (Un) in such a way that two of the at least four power transistors (T) are at a time connected in series to each other, to be precise connected electrically between the supply potential (Up) and the reference potential (Un). The at least one safety fuse (S) is connected in series to the at least four power transistors (T) in at least one of the two electrical supply lines. The at least one safety fuse (S) can be triggered by a current which flows through the diode (D) of the at least four power transistors (T), said diode being then arranged in the direction of conduction (D), when the supply potential (Up) and reference potential (Un) are exchanged. | 2009-04-30 |
20090108910 | Very low power consumption solid state relay - A normally closed solid state power relay with an optionally optically coupled input circuit at an input terminal with a driver circuit electrically coupled to input terminal to drive one or more a power transistors, preferably MOSFET transistors so that the power transistor is held in the on state by the driver when no voltage or a low level voltage is applied to the input terminal, and the power transistor is held in the off state by the driver when a high level voltage is applied to the input terminal. An energy storage device, a battery or capacitor, is coupled to the driver to powers the driver with the energy storage device being charged by energy from the input terminal when said input terminal when a high level voltage is applied to the input terminal. The energy storage device is charged by leakage current through a diode or through a resistor from the input circuit when the input circuit is in a high state. | 2009-04-30 |
20090108911 | ANALOG SWITCH - An analog signal is input to an input terminal. An analog signal is output via an output terminal. A first transistor is an N-channel MOSFET, and is provided between the input terminal and the output terminal. A first resistor is provided between the gate of the first transistor and a first fixed voltage terminal (power supply terminal), which sets the gate of the first transistor to a high-impedance state. | 2009-04-30 |
20090108912 | Circuit Architecture for Radiation Resilience - A system and method for extending the operating life of a device susceptible to defects caused by total ionizing dose radiation and/or bias dependent degradation are described. The device is replicated at least once and at least one switching mechanism is used to cycle between the devices such that only one device is operating normally. While the first device is operating normally, the other devices are biased. The bias condition may slow, eliminate, or even reverse device shifts that occur due to total ionizing dose radiation or bias effects. | 2009-04-30 |
20090108913 | MOS RESISTOR WITH SECOND OR HIGHER ORDER COMPENSATION - A circuit arrangement (e.g., an integrated circuit) generates a second or higher order compensation voltage to compensate for variations in operation parameters (e.g., temperature and process variations). In one aspect, the compensation voltage is applied to a MOS resistor to compensate for mobility variations of the MOS resistor by maintaining a stable equivalent resistance. The compensated MOS resistor can provide a relatively stable resistance for a variety of analog circuit applications, such as a current reference. | 2009-04-30 |
20090108914 | ADAPTIVE CAPACITIVE TOUCH SENSE CONTROL CIRCUIT - An adaptive capacitive touch sense control circuit includes a voltage buffer, a current setting resistor, a current mirror, a capacitor, a start comparator, an end comparator and a time-to-digital converter. The capacitor is connected with the current setting resistor. The circuit further includes a latch with a first control switch and a second control switch. The current setting resistor is switched between the ground and a voltage source through a switching element, so that when the current setting resistor is grounded, the first control switch is closed and the second control switch is opened, and when the current setting resistor is connected with the voltage source, the second control switch is closed and the first control switch is opened. An adaptive charging mode is adopted to sense a capacitance variation with a great ability of interference recognition, a simple structure, low power consumption and real time processing. | 2009-04-30 |
20090108915 | Charge Pump System and Method of Operating the Same - A charge pump system includes a charge pump circuit, a level shifter and a start circuit. The charge pump circuit has a voltage input terminal and a voltage output terminal. The charge pump circuit receives an input voltage at the voltage input terminal and generates an output voltage at the voltage output terminal. The level shifter is electrically coupled to the voltage output terminal of the charge pump circuit. The start circuit is electrically coupled between the voltage input terminal and the voltage output terminal of the charge pump circuit. A method of operating the charge pump system is also disclosed. | 2009-04-30 |
20090108916 | PUMP CIRCUIT - A pump circuit includes a plurality of transfer elements, capacitors, and controllers. The transfer elements are connected in series between a power supply terminal and an output terminal. The capacitors charge two terminals of each of the transfer elements according to first and second clock signals, respectively. Each of the controllers includes first and second switch elements, which are operated in opposite manners in response to the first or second clock signal to control each of the transfer elements. | 2009-04-30 |
20090108917 | METHODS AND APPARATUS TO PRODUCE FULLY ISOLATED NPN-BASED BANDGAP REFERENCE - Methods and apparatus to produce fully isolated NPN-based bandgap references are disclosed. A disclosed method to form a bandgap reference comprises generating a first current that is proportional-to-temperature, generating a second current that is complementary-to-temperature, and adding the currents to form a third current that is constant over a change in temperature. | 2009-04-30 |
20090108918 | METHODS AND APPARATUS TO SENSE A PTAT REFERENCE IN A FULLY ISOLATED NPN-BASED BANDGAP REFERENCE - Methods and apparatus for a PTAT reference in a fully isolated NPN-based bandgap references are disclosed. A disclosed method to form a bandgap reference comprises generating a first current that is constant over a change in temperature, generating a second current that is complementary-to-temperature, and generating a current that is proportional-to-temperature. | 2009-04-30 |
20090108919 | POWER SUPPLY CIRCUIT USING INSULATED-GATE FIELD-EFFECT TRANSISTORS - A power supply circuit is disclosed. The power supply circuit is provided with a reference voltage generation circuit to receive a voltage from a higher voltage supply so as to generate a reference voltage. The reference voltage from the reference voltage generation circuit is outputted to a power supply voltage generation circuit. The power supply voltage generation circuit boosts the reference voltage to generate a boosted power supply voltage. The boosted power supply voltage is inputted to a bandgap reference circuit. The bandgap reference circuit generates a reference voltage by using the boosted power supply voltage. | 2009-04-30 |
20090108920 | ENERGY-SAVING CIRCUIT AND METHOD USING CHARGE EQUALIZATION ACROSS COMPLEMENTARY NODES - An energy-saving circuit and method using charge equalization across complementary nodes reduces power consumption in memory circuits and other circuits such as wide multiplexers having complementary high-capacitance nodes. A change detection circuit detects a state change to be applied to the bitlines, and generates a pulse if a state change is to be applied. A pass gate connected between the nodes is activated in response to the pulse to equalize the charge on the bitlines. The driver circuit enable inputs are also delayed, so that the bitlines are not driven until after the charge has been equalized and the pass gate disabled. In one embodiment, the driver circuits are only enabled momentarily by a pulsed output of the change detector and keeper circuits are employed to retain the bitlines in their asserted states. | 2009-04-30 |
20090108921 | Timing Control circuit with power-saving function and method thereof - A timing control circuit with a power-saving function includes a receiving circuit, a processor, and a first switch. The receiving circuit receives a first set of differential signals for generating a set of command signals. The processor is coupled to the receiving circuit and generates a first control signal according to the set of command signals. The switch is coupled between the receiving circuit and the processor for selectively decoupling the receiving circuit from a first power supply according to the first control signal. | 2009-04-30 |
20090108922 | Method and System for Managing Voltage Swings Across Field Effect Transistors - A circuit for managing voltage swings across FETs comprising a reference precision resistor, a first FET and a second FET, wherein a gate of the first FET is tied to a gate of the second FET, wherein a drain to source resistance of the second FET is substantially equal to or is a multiple of a resistance of the reference precision resistor, and wherein a gate voltage of the second FET is applied to a gate of the first FET to set a bias point of the first FET, and a third FET cascoded to the first FET, wherein a source of the first FET is coupled to the drain of the third FET to extend a voltage range in which respective gate voltages of the first FET and the third FET maintain a linear relationship with respective drain to source voltages of the first FET and the third FET. | 2009-04-30 |
20090108923 | Structure for Precision Integrated Phase Lock Loop Circuit Loop Filter - A design structure for a loop filter in a phase lock loop circuit comprising a reference precision resistor, a first and second FET, wherein the gate of the first FET is tied to the gate of the second FET, and a filter capacitor connected to the first FET for producing a capacitor voltage. The capacitor voltage is applied to the source of the first FET, the source of the second FET, and the bottom of the reference precision resistor acting as a virtual ground. The capacitor voltage generated by the filter capacitor sets the bias point of the second FET such that the second FET comprises characteristics of an integrated precision resistor. A predetermined voltage generated by the second FET is applied to the gate of the first FET to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor. | 2009-04-30 |
20090108924 | Structure for Managing Voltage Swings Across Field Effect Transistors - A design structure of a circuit for managing voltage swings across FETs comprising a reference precision resistor, a first and second FET, wherein a gate of the first FET is tied to a gate of the second FET, wherein a drain to source resistance of the second FET is substantially equal to or is a multiple of a resistance of the reference precision resistor, and wherein a gate voltage of the second FET is applied to a gate of the first FET to set a bias point of the first FET, and a third FET cascoded to the first FET, wherein a source of the first FET is coupled to the drain of the third FET to extend a voltage range in which respective gate voltages of the first and third FETs maintain a linear relationship with respective drain to source voltages of the first and third FETs. | 2009-04-30 |
20090108925 | LOW POWER ON-CHIP GLOBAL INTERCONNECTS - An apparatus including a first circuit, a second circuit and a third circuit. The first circuit may be configured to (a) receive (i) a plurality of input signals and (ii) a clock signal and (b) present (i) a plurality of low-swing differential signals and (ii) a full-swing differential signal. The second circuit may be configured to (a) receive (i) the plurality of low-swing differential signals, (ii) the full-swing differential signal and (iii) the clock signal and (b) present a plurality of output signals. The third circuit may be configured to communicate the plurality of low-swing differential signals and the full-swing differential signal from the first circuit to the second circuit. The third circuit may be further configured to generate a local clock in response to the full-swing differential signal. | 2009-04-30 |
20090108926 | FILTER CIRCUIT - One aspect of the embodiments utilizes a filter circuit which can be connected to a signal source has a low-frequency cutoff of 1/(R×C). The filter includes a buffer circuit which can be connected to an output end of the signal source and has an output impedance of R, and a capacitor which is connected to an output end of the buffer circuit in a floating state and has a capacitance of C/2. The filter includes a resistor circuit which is connected to an output end of the capacitor and has a resistance value of R. | 2009-04-30 |
20090108927 | FILTER ADJUSTING CIRCUIT - A filter adjusting circuit, has: a filter circuit which has a circuit configuration operating as an n-th order filter including n (n≧1) integrators and can switch a connection of the circuit configuration to operate as a circuit equivalent to the n integrators; a signal generating circuit that outputs a first signal having a predetermined reference frequency to the filter circuit, and outputs a second signal having the reference frequency; a phase comparator that compares a phase of a third signal and a phase of the second signal and determines a phase shift between the signals, the third signal being obtained by processing the first signal in the filter circuit and outputted from the filter circuit; and a control circuit controls the filter circuit. | 2009-04-30 |
20090108928 | LARGE-SCALE INTEGRATED CIRCUIT - A large-scale integrated circuit according to the present invention includes a plurality of functional blocks for independently performing a signal processing operation, and a selection controlling circuit for generating a first control signal to select one of the plurality of functional blocks, in which the selection controlling circuit includes a control signal generating circuit for generating a second control signal for stopping the operation of its circuit, and the selection controlling circuit generates the first and the second control signals by a command from a different control circuit. | 2009-04-30 |
20090108929 | Apparatuses and methods for providing offset compensation for operational amplifier - Apparatuses and methods for providing offset compensation include a primary amplifier which includes a first output, a second output, a first load input, and a second load input, a first feedback loop connected to the primary amplifier and which includes a first switch located between the first output of the primary amplifier and the first load input, and a first sampling capacitor coupled to the first switch between the first switch and the first load input and a second feedback loop connected to the primary amplifier and which includes a second switch located between the second output of the primary amplifier and the second load input, and a second sampling capacitor coupled to the second switch between the second switch and the second load input. | 2009-04-30 |
20090108930 | High power commutating multiple output amplifier system - An amplifier system includes a power divider for dividing an input RF signal into M RF signals of equal power and phase. The system has M low power selectable phase shifters each for phase shifting one of the M RF signals. M high power amplifiers are coupled to respective ones of the phase shifters. The system includes an M×N power distribution network having M input ports and N output ports, such as a Butler matrix. The M high power amplifiers are connected to a respective one of the M input ports of the distribution network. The phase of the M phase shifters may be adjusted to obtain a maximum output at the desired output with all the other outputs nulled. | 2009-04-30 |
20090108931 | PROGRAMMABLE GAIN CIRCUIT - A programmable gain circuit suitable for a programmable gain amplifier is described. In one design, the programmable gain circuit includes multiple attenuation circuits coupled in series. Each attenuation circuit operates in a first mode or a second mode, attenuates an input signal in the first mode, and passes the input signal in the second mode. The multiple attenuation circuits may provide the same or different amounts of attenuation. The multiple attenuation circuits may include binary decoded attenuation circuits and/or thermometer decoded attenuation circuits. In one design, each attenuation circuit includes a divider circuit and at least one switch. The switch(es) select the first mode or the second mode. The divider circuit attenuates an input signal in the first mode and passes the input signal in the second mode. The programmable gain circuit may have a predetermined input impedance and a predetermined output impedance for all gain settings. | 2009-04-30 |
20090108932 | Signal generating apparatus and class-d amplifying apparatus - A signal generating apparatus includes: a data generator which generates a data series in which first, second, third and fourth data are arranged at a sampling period; a first signal generator which generates a first pulse-width modulation signal in which a pulse is arranged in a pulse period longer than the sampling period, time points of front and rear edges of the pulse being set in response to the first and second data; and a second signal generator which generates a second pulse-width modulation signal in which a pulse is arranged between the adjacent pulses of the first pulse-width modulation signal, time points of front and rear edges of the pulse of the second pulse-width modulation signal been set in response to the third and fourth data, respectively. | 2009-04-30 |
20090108933 | Compensation For Amplifiers Driving A Capacitive Load - This disclosure relates to load compensating multi-stage amplifier structures at an output of one of the amplifier stages. | 2009-04-30 |
20090108934 | DIFFERENTIAL AMPLIFIER SYSTEM - One embodiment of the invention includes a differential amplifier circuit. A first input stage generates first and second control voltages in response to a differential input signal. A second input stage generates third and fourth control voltages in response to the differential input signal. The first and second control voltages can be inversely proportional and the third and fourth control voltages can be inversely proportional. The circuit also includes a first output stage that is configured to set a magnitude of a first output voltage of a differential output signal at a first output node in response to the first and second control voltages. The circuit further includes a second output stage that is configured to set a magnitude of a second output voltage of the differential output signal at a second output node in response to the third and fourth control voltages. | 2009-04-30 |
20090108935 | Variable gain amplifier including series-coupled cascode amplifiers - A variable gain amplifier to convert an amplifier input voltage to an amplifier output voltage, the variable gain amplifier includes: a plurality of cascode amplifiers coupled in series; a plurality of switching transistor pair circuits coupled in series; and a bias circuit coupled to provide bias voltages to each of the plurality of cascode amplifiers; wherein each of the switching transistor pair circuits is further coupled between two consecutive ones of the cascode amplifiers; a first one of the cascode amplifiers is configured to receive the amplifier input voltage; and a last one of the cascode amplifiers is configured to provide the amplifier output voltage. | 2009-04-30 |
20090108936 | Combination trim and CMFB circuit and method for differential amplifiers - A differential amplifier ( | 2009-04-30 |
20090108937 | LOW NOISE AMPLIFIER AND DIFFERENTIAL AMPLIFIER - In a double-loop negative feedback low noise amplifier having double negative feedback paths by a feedback transformer and a feedback resistor added to a cascode amplifier comprising transistors and a resistor, a phase compensation circuit comprising a capacitor and a resistor is added between the output terminal of the double-loop negative feedback low noise amplifier and the input terminal of the cascode amplifier, i.e., the input terminal of the input transistor, and a phase compensation circuit comprising a capacitor and a resistor is added to the upper-stage transistor of the cascode amplifier, i.e., the input terminal of the upper-stage transistor. Those phase compensation circuits enable a low noise negative feedback amplifier which maintains a high feedback loop gain to a high frequency band, has a wider bandwidth than a conventional one, and has a high dynamic range. | 2009-04-30 |
20090108938 | CIRCUIT AND METHOD FOR DYNAMIC CURRENT COMPENSATION - An operational amplifier includes a first stage and a second stage, the first stage for receiving two input signals and the second stage being coupled to the first stage, wherein the second stage includes a first part with a first output of the operational amplifier, and a second part with a second output of the operational amplifier. A method includes providing a first current to the first part of the second stage, and providing a second current to the second part of the second stage. The method further includes adjusting the first current based on a current consumption of the first part of the second stage, and adjusting the second current based on a current consumption of the second part of the second stage, wherein the sum of the first current and the second current is substantially constant. | 2009-04-30 |
20090108939 | AMPLIFYING APPARATUS AND BIAS STABILIZATION CIRCUIT - An amplifying apparatus including an amplifier having a first FET, a second FET having a source connected to a drain of the first FET, a load resistance connected to a drain of the second FET, a first bias circuit configured to supply a first bias voltage to a gate of the first FET, and a second bias circuit configured to supply a second bias voltage to a gate of the second FET. The second bias circuit includes a second comparison circuit configured to send a control signal to the gate of the second FET so that a bias voltage of a connection node between the first and second FETs changes in conjunction with an output voltage of the first bias circuit. | 2009-04-30 |
20090108940 | Amplifier - An amplifier comprises an input terminal that inputs an AC voltage signal; an amplifying unit having a transistor for amplifying the input AC voltage signal; a current detecting unit connected internally of said amplifying unit; and a control-current source controlled by said current detecting unit that drives an input stage of the transistor. | 2009-04-30 |
20090108941 | TRANSCONDUCTANCE COMPENSATING BIAS CIRCUIT AND AMPLIFIER - A transconductance compensating bias circuit is disclosed that includes a first field-effect transistor (FET) having a first electrode, a second electrode, and a gate connected to the first electrode, wherein a reference current flows through the first and second electrodes; a second FET having a first electrode, a second electrode, and a gate connected to the gate of the first FET, wherein a bias current flows through the first and second electrodes; a resistor connected to the second electrode of the first or second FET; and a comparison part configured to output a signal corresponding to the result of comparison of the first potential of the first electrode of the first FET and the second potential of the first electrode of the second FET. The reference current and the bias current are controlled by the output signal of the comparison part so as to equalize the first and second potentials. | 2009-04-30 |
20090108942 | Low noise, low power and high bandwidth capacitive feedback trans-impedance amplifier with differential fet input and bipolar emitter follower feedback - A differential amplifier topology includes circuitry to create a higher bandwidth output using less current than an existing Capacitive Trans-Impedance Amplifier (CTIA) using an all Field Effect Transistor (FET) circuit design. A bipolar npn emitter follower in the circuit topology provides low output impedance and some degree of output inductive peaking, and the CTIA differential output is buffered by the bipolar npn emitter follower in the CTIA feedback loop such as the open-loop high voltage gain is maintained without being affected by output loads. | 2009-04-30 |
20090108943 | LOW NOISE AMPLIFIER - A low-noise amplifier circuit to convert a single-ended input into a dual-ended output includes an input transconductance stage circuit, including a first MOS transistor coupled in parallel with a second MOS transistor; a current buffer circuit, including a third MOS transistor coupled in parallel with a fourth MOS transistor; each of the first, second, third, and fourth transistors having a body, gate, source, and drain; the input transconductance stage circuit and the current buffer circuit being cascode coupled, forming a cascode amplifier configuration; the single-ended input being at the source of one of the first and second transistors in the input transconductance stage circuit; the dual-ended output being a differential output across the drain of the third transistor and the drain of the fourth transistor; the first and second transistors of the input transconductance stage circuit being cross-coupled, wherein the body of the first transistor is coupled to the source of the second transistor, and the body of the second transistor is coupled to the source of the first transistor; and the third and fourth transistors of the current buffer circuit being cross-coupled, wherein a first capacitance is coupled between the gate of the third transistor and the source of the fourth transistor, and a second capacitance is coupled between the gate of the fourth transistor and the source of the third transistor. | 2009-04-30 |
20090108944 | LOW-NOISE AMPLIFIER CIRCUIT INCLUDING BAND-STOP FILTER - A low-noise amplifier circuit includes a MOS transistor in a common gate amplifier configuration. A single-ended input is at a source of the MOS transistor. A resonant cavity filter circuit is coupled to a gate of the MOS transistor. | 2009-04-30 |
20090108945 | FREQUENCY SYNTHESIZER - A frequency synthesizer switches the frequency at a high rate, is of low power consumption, and has a high signal-to-noise ratio. CMOS quadrature VCOs | 2009-04-30 |
20090108946 | SWITCH, NEGATIVE RESISTANCE CELL, AND DIFFERENTIAL VOLTAGE CONTROLLED OSCILLATOR USING THE SAME - The present invention relates to a switch, a negative resistance cell, and a differential voltage controlled oscillator using the same. The present invention includes a first signal line provided in a first direction, a second signal line provided in parallel with the first signal line, and first to fourth gate electrodes, first to third source electrodes, and first to fourth drain electrodes formed between the first signal line and the second signal line, and provides a switch having electrodes in the order of the first gate electrode, the first drain electrode, the second gate electrode, the first source electrode, the third gate electrode, the second drain electrode, the fourth gate electrode, the second source electrode, the fifth gate electrode, the third drain electrode, the sixth gate electrode, the third source electrode, the seventh gate electrode, the fourth drain electrode, and the eighth gate electrode. According to the present invention, a differential voltage controlled oscillator for RF oscillation operation in the broadband area is realized by minimizing generation of parasitic components. | 2009-04-30 |
20090108947 | Voltage Controlled Oscillator - A voltage controlled oscillator includes an LC-tank circuit, a cross-coupled pair circuit, and a trans-conductance adjusting circuit. The LC-tank circuit provides an inductance and a capacitance. The cross-coupled pair circuit is coupled to the LC-tank circuit and has a first transistor and a second transistor in a cross-coupled manner. The trans-conductance adjusting circuit is utilized for adjusting a trans-conductance value of the voltage controlled oscillator according to a first control signal, which includes a third transistor coupled to the first transistor and a first switch unit, and a forth transistor coupled to the second transistor and the first switch unit. The first control signal is used for controlling whether to turn on the first switch unit so as to adjust the trans-conductance value of the voltage controlled oscillator. | 2009-04-30 |
20090108948 | Relaxation oscillator for compensating system delay - A relaxation oscillator compensates for system delay. The relaxation oscillator includes first and second input signal units that generates first and second capacitor voltages, a delay compensation unit that receives a reference voltage and the first and second capacitor voltages and that generates a compensation voltage. In certain embodiments, a voltage generating unit applies the reference voltage to the delay compensation unit, and a latch unit stores first and second comparison signals compared by the first and second input signal units and transmits a clock signal and a inverted clock signal to the first and second input signal units. The first and second input signal units compare the first and second capacitor voltages with a compensation voltage transmitted from the delay compensation unit. | 2009-04-30 |
20090108949 | TEMPERATURE COMPENSATION FOR CRYSTAL OSCILLATORS - Methods and apparatus for generating a temperature compensated frequency estimate for a crystal oscillator, wherein the temperatures of the crystal and oscillator are both accounted for. A crystal temperature measurement is used to generate a first frequency component. The difference between the oscillator temperature measurement and a second temperature is scaled, and used to generate a second frequency component. The first and second frequency components may be summed to produce a frequency estimate for the crystal oscillator. In an embodiment, the computations may be performed in the slope domain. | 2009-04-30 |
20090108950 | OSCILLATION CONTROL APPARATUS AND OSCILLATOR - An oscillation control apparatus is provided with: an oscillating unit for oscillating an oscillating element; an output amplifying circuit having two pieces of same types of transistors series-connected to each other, for outputting a signal from a junction point between the two transistors in response to an oscillation signal outputted from the oscillating unit; a bias unit for generating two DC bias voltages having different levels from each other, which are applied to either respective gates or respective bases of the two transistors; a constant voltage power supply unit for applying a constant voltage to the oscillating unit; and an inverter unit provided between the oscillating unit and any one of either the gates or the bases of the two transistors, for inverting a phase of the oscillation signal outputted from the oscillating unit. Both the oscillation signal outputted from the oscillating unit and one of the two bias voltages are applied to either the gate or the base of one of the two transistors; and both an oscillation signal outputted from the oscillating unit and whose phase has been inverted by the inverting unit and the other bias voltage of the two bias voltages are applied to either the gate or the base of the other transistor of the two transistors. | 2009-04-30 |
20090108951 | METHODS AND APPARATUS FOR REDUCING PEAK-TO-RMS AMPLITUDE RATIO IN COMMUNICATION SIGNALS - A pulse amplitude modulation (PAM) signal generator that injects a copy of a pulse into the PAM baseband signal prior to frequency upconversion and power amplification. The pulse comprises a function of, or an extra copy of, a pulse in the PAM baseband signal. The pulse injector analyzes the PAM baseband signal for times when a predetermined threshold is exceeded and forms a pulse that is constructed and arranged to reduce the amplitude of the PAM baseband signal to a desired peak amplitude when the pulse is added to the PAM baseband signal. | 2009-04-30 |
20090108952 | DISTORTION COMPENSATING CIRCUIT - A distortion compensating circuit is provided in which, in the polar modulation system, while suppressing increase of compensation data and increase of the circuit scale, a modulated signal can be correctly expressed, or low-distortion characteristics of a power amplifier can be realized. Based on a steady characteristic compensating circuit | 2009-04-30 |
20090108953 | MULTI-JUNCTION WAVEGUIDE CIRCULATOR WITH OVERLAPPING QUARTER-WAVE TRANSFORMERS - An improved multi-junction waveguide circulator overlaps two quarter-wave dielectric transformer sections so that the transitional sections occur concurrently in the same length of waveguide. Consequently, the two quarter-wavelength sections require a total length of between one-quarter wavelength and one-half wavelength, with no air gap between the two sections along the length of the internal cavity. The improved waveguide circulator can be implemented in variations from a minimum of two ferrite circulator elements held in close proximity to one another to any number of ferrite elements as required to achieve the desired isolation performance or to create a switch matrix with any combination of input and output ports. The improved waveguide circulator minimizes the length of the transitions between adjacent ferrite elements and thus reduces losses, component size, and mass. | 2009-04-30 |
20090108954 | Quasi active MIMIC circulator - A circulator capable of simultaneous transmit and receive operations, high frequency, and high isolation and broadband performance comprising: an antenna port; a transmission port; a receiving port; wherein each port is connected to a 90 degree combiner/divider for splitting an input signal into two output components, the said output components have a ninety degrees relative phase difference to each other; each of said 90 degree combiner/dividers in addition to the connection to the above mentioned ports has at least two output connections each of which are connected to a Y-junction and if a fourth connection, said fourth connection is attached to a matching load circuit; this arrangement of circuits allows the potion of the phase shifted signals from the transmit port to enter the antenna 90 degree combiner/divider and be enhanced at the antenna port, while the rest of the signal enters the receive 90 degree combiner/divider and are phased cancelled; said arrangement allows the signals from the antenna port 90 degree combiner/divider to combine in phase at the receive port. | 2009-04-30 |
20090108955 | Semiconductor Device and Method for Adjusting Characteristics Thereof - The object of the invention is to provide a semiconductor device including signal-transmission interconnections preferable for transmitting high frequency signal and capability to adjust characteristics of the above signal-transmission interconnections. A semiconductor device according to the present invention consists of a signal-transmission interconnection | 2009-04-30 |
20090108956 | CIRCUIT TOPOLOGY FOR MULTIPLE LOADS - A circuit topology for multiple loads includes a driving terminal, a first node coupled to the driving terminal and a second node via a first branch transmission line, a first receiving terminal which is a test point configured to detect errors of the circuit topology coupled to the first node via a second branch transmission line, a second and a third receiving terminal respectively coupled to the second node via a third branch transmission line and a fourth branch transmission line, wherein the difference between the length of the second branch transmitting line and that of the third branch transmitting line, and the difference between the length of the third branch transmitting line and that of the fourth branch transmitting line are greater than the product of a transmission speed and a rise time of the signal, and a first resistor is connected in the third branch transmission line. | 2009-04-30 |
20090108957 | PHASE SHIFTER - A phase shifter includes a metal plate, a support portion, a slot, a coupling portion, and a ground portion. The phase shifter effectively improves signal coupling efficiency, and inhibits noise generated with the change of phase shift due to signal transmission. The phase shifter is advantageous in smaller volume, easy to assemble, and low cost. | 2009-04-30 |
20090108958 | NOISE FILTER ARRAY - A noise filter array includes filter elements, each of which includes an LC parallel resonant circuit having a coil and a capacitor and an LC series resonant circuit having a coil and a capacitor, are arranged substantially parallel to one another in an array and integrally provided. Grounding capacitors that define the filter elements are arranged so that a common ground-side electrode faces signal-side electrodes and is connected to an inductance adjusting conductor that defines the LC series resonant circuits along with the capacitors through a via hole. The lengths of the inductance adjusting conductor from a connection location within the via hole to ground terminals are substantially equal in each of the filter elements. | 2009-04-30 |
20090108959 | Contour-Mode Piezoelectric Micromechanical Resonators - A contour mode micromechanical piezoelectric resonator. The resonator has a bottom electrode; a top electrode; and a piezoelectric layer disposed between the bottom electrode and the top electrode. The piezoelectric resonator has a planar surface with a cantilevered periphery, dimensioned to undergo in-plane lateral displacement at the periphery. The resonator also includes means for applying an alternating electric field across the thickness of the piezoelectric resonator. The electric field is configured to cause the resonator to have a contour mode in-plane lateral displacement that is substantially in the plane of the planar surface of the resonator, wherein the fundamental frequency for the displacement of the piezoelectric resonator is set in part lithographically by the planar dimension of the bottom electrode, the top electrode or the piezoelectric layer. | 2009-04-30 |
20090108960 | Surface Acoustic Wave Resonator, and Surface Acoustic Wave Filter - A surface acoustic wave resonator has piezoelectric substrate ( | 2009-04-30 |
20090108961 | Electroacoustic Component - An electroacoustic component operates with guided acoustic waves and includes a first substrate, a second substrate, a metallic layer and an intermediate layer. The first substrate (S | 2009-04-30 |
20090108962 | Dielectric Filter for Base Station Communication Equipment - In a dielectric filter ( | 2009-04-30 |
20090108963 | Integral variable termination for alarm system devices - Disclosed is a system for quickly and easily installing end-of-line termination devices at the end of alarm system signal circuits. The termination devices in this invention are both variable and integral to the housing of the alarm system devices. Each alarm system device is constructed with a receptacle at the point of protection, in which may be placed a cartridge, jumper, or similar device on-site to terminate the communication signal. The various embodiments of the invention include a set of devices at discrete values or a variable device to complete each protection loop. | 2009-04-30 |
20090108964 | Ethernet Coupling - Improved coupler for Ethernet over twisted pair. An improved coupler has a first common mode choke for connecting an Ethernet PHY to the primary winding of a transformer. The secondary winding of the transformer connects through a second common mode choke for connection to a twisted pair line. In one embodiment, the first common mode choke, transformer, and second common mode choke are placed in the same package. In a second environment, a plurality of choke-transformer-choke units are placed in the same package. In a third embodiment, the plurality of choke-transformer-choke units may be integrated into a connector. Pairs of the second common mode chokes may share cores. | 2009-04-30 |
20090108965 | RF STEP ATTENUATOR - A broadband, high-speed RF step attenuator implemented using long-lifetime PIN diode switches is presented which provides step attenuation across a significant portion of the entire RF frequency spectrum while maintaining minimal insertion loss, return loss, and harmonics. | 2009-04-30 |
20090108966 | LINE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A line structure is provided which includes a ferroelectric film which is formed on at least one surface of both sides of a substrate and a permittivity of which changes according to a magnitude of an applied voltage, an inductor which is formed on a first side of the substrate, and a capacitor which has a capacitance corresponding to the permittivity of the ferroelectric film and the substrate. | 2009-04-30 |
20090108967 | CIRCUIT INTERRUPTER AND METHOD OF PROCESSOR PHASE SYNCHRONIZATION - A circuit breaker includes a line terminal, a load terminal, separable contacts electrically connected in series between the terminals, a neutral conductor, and an operating mechanism structured to open and close the contacts and trip open the contacts in response to a trip signal. A first sensor senses an electrical characteristic operatively associated with the contacts. A second sensor detects zero crossings, a consecutive pair of the crossings defining a corresponding half-cycle and a first frequency. A processor cooperates with the sensors and includes a routine and a timer having a second frequency. The routine determines, for each of the half-cycles and responsive to the timer, plural samples of the sensed electrical characteristic in a phase synchronized relationship to a corresponding one of the crossings, and determines whether one of the frequencies exceeds a number of corresponding predetermined values for a number of times and responsively outputs the trip signal. | 2009-04-30 |
20090108968 | MAGNETIC DEVICE COMBINED WITH A VELCRO TAPE - A magnetic device combined with a Velcro tape comprises: a magnet body having a surface equipped a groove; a Velcro tape placing in the groove for functioned with magnetic and hooking force from both the magnet body and the Velcro tape. The Velcro tape can also directly connect on the surface of the magnet body. | 2009-04-30 |
20090108969 | APPARATUS AND METHOD FOR TRANSCRANIAL AND NERVE MAGNETIC STIMULATION - An electromagnet coil comprising Litz wire windings and power leads without break or interruption is cooled by a perfluorinated liquid by sensible and phase change heat transfer in a closed system. The electromagnet coil may be housed in a pentagonal or hexagonal pressure vessel to allow high packing densities in an array or helmet configuration. The helmet is then lowered over a human cranium for transcranial electromagnetic stimulation. The Litz wire windings reduce the power and voltages required for operation, yet allow production of over 2 T of accurately directed magnetic pulses for direct nerve or neuron stimulation. The perfluorinated liquid maintains the temperature of the helmet to less than 35-40° C., ensuring a comfortable temperature device for a human test subject. A utility cable connects the helmet to an external cooling unit and an external power supply. | 2009-04-30 |
20090108970 | PROCESS FOR PRODUCTION OF MAGNET, MAGNET OBTAINED THEREBY AND PRODUCTION APPARATUS FOR MOLDED ARTICLES FOR MAGNET - A process for production of a magnet which comprises step of supplying a slurry S containing magnetic powder and a dispersing medium into the cavity C of a molding apparatus | 2009-04-30 |
20090108971 | Core Securing Member And Its Structure - [PROBLEM] By simplifying a core securing structure of a reactor, miniaturization, lightweight, and low costs of the reactor are achieved. | 2009-04-30 |
20090108972 | IGNITION COIL AND METHOD FOR MANUFACTURING THE SAME - An ignition coil includes a coil body, a primary resin molded body, and a secondary resin molded body. The coil body has a primary coil and a secondary coil. The primary resin molded body has the coil body therein in a fixed relation, and the primary resin molded body has a plurality of exposed side portions that hold the coil body therebetween. The secondary resin molded body is molded to have the coil body and the primary resin molded body embedded therein. The secondary resin molded body is configured to allow the plurality of exposed side portions of the primary resin molded body to be exposed to an exterior of the secondary resin molded body. | 2009-04-30 |
20090108973 | HIGH VOLTAGE INSULATION SYSTEM AND A METHOD OF MANUFACTURING SAME - A high voltage insulation system for high-voltage direct current including a bushing, a conductor, a transformer conductor, and a connection between the conductor and the transformer conductor. A conductive shielding electrode shields the connection between the bushing and transformer. A surrounding insulation system is immersed in transformer oil. The surrounding insulation system includes transformer insulation material and bushing insulation material. A cylindrical solid insulation barrier encloses the connection between the bushing conductor and transformer conductor. At least one solid insulation barrier is fastened on the outer side of the shielding electrode. The at least one solid insulation barrier extends in an axial direction outside the axial direction of the shielding electrode and forms a distance to the insulation material of the bushing and the insulation material of the transformer, whereby a moderate voltage drop over the solid insulation barrier is obtained. | 2009-04-30 |
20090108974 | Integrated Circuit Device Including A Contactless Integrated Circuit Inlay - Embodiments provide an integrated circuit device including a contactless integrated circuit inlay. The device includes a substrate, an integrated circuit coupled to the substrate, and a coil electrically coupled to the integrated circuit and coupled to the substrate. The coil includes a first conductive line disposed in multiple turns on the substrate and a second conductive line disposed in multiple turns on the substrate. | 2009-04-30 |
20090108975 | HIGH-VOLTAGE TRANSFORMER - A high-voltage transformer includes a core, a secondary coil bobbin surrounding the core, and a secondary winding which is wound on the secondary coil bobbin. The secondary winding includes a first partial secondary winding and a second partial secondary winding which are wound on the secondary coil bobbin. Between the first and second partial secondary windings of the secondary winding, there are provided insulators and parallel-connected diodes. The diodes are arranged in a direction away from the core. These diodes are not required to be resistant to high current, thus achieving a compact high-voltage transformer. | 2009-04-30 |