| 17th week of 2011 patent applcation highlights part 54 |
| Patent application number | Title | Published |
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| 20110099296 | ACCELERATED ACCESS APPARATUS AND READING AND WRITING METHODS THEREOF - An accelerated access apparatus and reading and writing methods thereof are described. A processing unit is used to determine whether the continuation state of a plurality of first address parameters of first request signals. Each first request signal has a first address length. When the first address parameters are continuous thereamong, the processing unit converts one of the second request signals into a second reading command which has a second reading address and a second reading address length. The second reading address length is greater than one of the first address lengths. The processing unit executes the second reading command to read data content to be stored in a buffer unit based on the second reading address and the second reading address length for responding to the second request signals. | 2011-04-28 |
| 20110099297 | METHOD AND SYSTEM FOR REMOTELY CONFIGURING A DEVICE ASSOCIATED WITH A LOCAL MACHINE - A system and method of configuring a USB device connected to a client machine includes detecting, by a local low level device insertion detection system of a client machine, a USB device connected to the client machine by a USB port, the client machine in communication with a remote machine via a remoting protocol; establishing, by the low level device insertion detection system of the client machine, a low-level connection by a USB remoting with a low level device insertion detection system executing in the remote machine; executing, by the remote machine, an application to determine whether to use a driver on the client machine or a driver on the remote machine to configure the device. | 2011-04-28 |
| 20110099298 | METHOD OF DETECTING ACCESSORIES ON AN AUDIO JACK - An apparatus comprises an audio or video jack connector configured to receive an audio or video jack plug of a separate device, a detection circuit in electrical communication with the connector, and a processor communicatively coupled to the detection circuit. The connector includes an electrical contact for connection to a conducting terminal of the plug. The detection circuit is configured to determine a resistance at the conducting terminal. The resistance is a resistive load of the separate device at the conducting terminal of the plug. The processor is configured to identify a function of the separate device according to the determined resistance, and configure an operation of the apparatus according to the determined function. | 2011-04-28 |
| 20110099299 | Mode Switching - Mode switching may be provided. A selection of a non-native mode for a first input device may be received having a native mode. Then the use of the first input device may be enabled in the selected non-native mode. Next, a switch may be detected from the first input device to a second input device and then a switch back to the first input device may be detected. The use of the first input device may be enabled in the native mode in response to detecting the switch back to the first input device. | 2011-04-28 |
| 20110099300 | CAMERA SHUTTER CONTROL THROUGH A USB PORT OR AUDIO/VIDEO PORT - An apparatus comprises a digital image sensor, a communication port, a detection circuit and a processor. The detection circuit is configured to detect a change in electrical resistance at a connector of the communication port. The processor is configured to initiate an operation of the apparatus according to the detected change in resistance. | 2011-04-28 |
| 20110099301 | Using Central Direct Memory Access (CDMA) Controller to Test Integrated Circuit - In an embodiment, an integrated circuit includes a direct memory access (DMA) controller configured to perform DMA operations between peripheral components of the integrated circuit and/or a memory to which the integrated circuit is configured to be coupled. Combinations of memory-to-memory, memory-to-peripheral, and peripheral-to-memory operations may be used. The DMA controller may be programmed to perform a number of DMA operations concurrently. The DMA operations may be programmed and performed as part of testing the integrated circuit during design and/or manufacture of the integrated circuit. The DMA operations may cause many of the components in the integrated circuit to be busy performing various operations. In some embodiments, programmed input/output (PIO) operations may also be performed while the DMA operations are in progress. In some embodiments, various parameters of the DMA operations and/or PIO operations may be randomized. | 2011-04-28 |
| 20110099302 | CONTENT PROCESSING APPARATUS - A content processing apparatus includes a first transferor which transfers a predetermined content to an external device when accepting a transfer operation to any one of contents stored in a memory device. A predictor predicts a time period required for a transfer process of the content designated by the transfer operation, based on the time period taken for the transfer process of the first transferor and a size of the content designated by the transfer operation. A second transferor transfers the content designated by the transfer operation to the external device. A controller determines whether or not the time period predicted by the predictor falls below a reference based on a remaining amount of a battery, so as to permit a transfer process of the second transferor when the determined result is positive while restrict the transfer process of the second transferor when the determined result is negative. | 2011-04-28 |
| 20110099303 | MULTI-CORE DATA PROCESSOR - To provide a multi-core LSI capable of improving the stability of operation. A multi-core LSI comprises a plurality of CPUs coupled to a first shared bus, one or more modules coupled to a second shared bus, a shared bus controller coupled between the first shared bus and the second shared bus, for arbitrating an access to the module (s) by the CPUs, and a system controller that monitors whether or not a response signal to an access request signal of the CPUs is output from module to be accessed, wherein the system controller outputs a pseudo response signal to the first shared bus via the shared bus controller to terminate the access by the CPU while accessing if the response signal is not output from the module to be accessed after the access request signal is output to the second shared bus from the shared bus controller and before a predetermined time elapses. | 2011-04-28 |
| 20110099304 | Controller and a Method for Controlling the Communication Between a Processor and an External Peripheral Device - The present invention relates to a data processing system based on a multithreaded operating system. The data processing system comprises at least one processor (PROC) for processing data based on multiple threads, at least one controller unit (CU) for controlling the communication between said at least one processor (PROC) and an external peripheral device (PD) connected to said at least one controller unit (CU). Said at least one controller unit (CU) comprises at least one buffer memory (BM) for buffering data from said peripheral device (PD) connected to said at least one controller unit (CU), and at least one memory managing unit (MMU) for managing the access to said at least one buffer memory (BM) by mapping said at least one buffer memory (BM) into N banks (C | 2011-04-28 |
| 20110099305 | Universal Serial Bus Host Control Methods and Universal Serial Bus Host Controllers - A USB host control method is provided for a USB host controller. The USB host controller includes a USB device and a buffer, the USB device includes one or more endpoints. The USB host control method includes the steps of: storing first output data to be sent to a first endpoint into one or more buffer units used for the first endpoint; sending the first output data to the first endpoint; and when a first predetermined response from the first endpoint is received, configuring fake releasing labels and information tags corresponding to the first endpoint in the one or more buffer units, and not releasing the one or more buffer units. | 2011-04-28 |
| 20110099306 | ENABLING CONSECUTIVE COMMAND MESSAGE TRANSMISSION TO DIFFERENT DEVICES - In one embodiment, the present invention includes a method for transmitting a frame information structure (FIS) message from a host controller or receiving a FIS message at the host controller, transmitting a synchronization signal from the host controller to a port multiplier coupled to the host controller via a link and sustaining a transmit ready signal from the host controller to the port multiplier to thereby lock the link between the host controller and the port multiplier after sending the synchronization signal, and transmitting multiple command FIS messages from the host controller to the port multiplier in a back-to-back manner, where the back-to-back command FIS messages are directed to different devices. Other embodiments are described and claimed. | 2011-04-28 |
| 20110099307 | ELECTRONIC DEVICE AND METHOD FOR READING IMAGE FILES USING THE ELECTRONIC DEVICE - A method for reading image files using an electronic device sends a communication command from a field programmable gate array (FPGA) of the electronic device to a host computer, receives a read command for reading an image file sent from the host computer by the FPGA. The method further reads the image file from a storage device of the electronic device if the storage device includes the image file, parses the image file, places the parsed image file in a virtual drive of the FPGA, and reads the parsed image file from the virtual drive of the FPGA by the host computer. | 2011-04-28 |
| 20110099308 | SPLIT TRANSACTION PROTOCOL FOR A BUS SYSTEM - A method of and apparatus for communicating between a host and an agent. The method includes the step of performing a first transaction between a host controller and a hub. The hub is operable to perform a single transaction with an agent based on the first transaction. The method then includes the step of performing a second transaction between the host controller and the hub. The second transaction is based on the single transaction. | 2011-04-28 |
| 20110099309 | POWER SUPPLY CIRCUIT FOR CPU - A power supply circuit includes a PWM controller capable of providing pulse signals to a CPU, and an I/O controller electrically coupled to the PWM controller and the CPU respectively. The I/O controller is capable of receiving voltage selection signals from the CPU and outputting a control signal to the PWM controller. The PWM controller is capable of adjusting pulse signals provided to the CPU according to the control signal. | 2011-04-28 |
| 20110099310 | CONTROLLING PASSTHROUGH OF COMMUNICATION BETWEEN MULTIPLE BUSES - A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus. | 2011-04-28 |
| 20110099311 | COMMUNICATION SYSTEM, COMMUNICATION APPARATUS, CONTROL METHOD THEREFOR, AND COMPUTER PROGRAM - In a communication system, one of a plurality of communication apparatuses that acts as a host controls data transmission and the other communication apparatuses that act as devices perform data transmission under control of the host over a predetermined communication interface. The communication apparatuses have both host and device roles, and are configured to exchange the host and device roles by using a predetermined communication protocol are connected to the predetermined communication interface. A first apparatus acts as a host and a second apparatus as a device. The second apparatus transmits information concerning the second apparatus to the first apparatus. The first apparatus compares the transmitted information with information concerning the first apparatus to determine whether or not to switch the host and device roles according to a predetermined criterion. In response to an affirmative determination, the host and device roles are switched by using the predetermined communication protocol. | 2011-04-28 |
| 20110099312 | CIRCUIT AND METHOD FOR PIPE ARBITRATION - Provided is an arbitration circuit included in a host controller that can be connected to a plurality of external devices via a plurality of pipe control circuits. The arbitration circuit includes an available state information storage unit that stores available state information. The available state information indicates an available state of the plurality of pipe control circuits and is updated by the pipe control circuit by a unit of data transfer of a predetermined communication size. The arbitration circuit further includes an arbitration unit that refers to the available state information storage unit, selects the arbitrary pipe control circuit from the available pipe control circuit, and allocates the selected pipe control circuit to the external device, while updating the available state information storage unit. | 2011-04-28 |
| 20110099313 | SYSTEM AND METHOD FOR CONTROLLING INTERRUPTION OF A PROCESS IN ELECTRONIC EQUIPMENT BASED ON PRIORITY OF THE PROCESS, AND PROGRAM - System, method, and program to determine whether to interrupt a process, e.g., a write function, to carry out another process, e.g., a high priority read function, in a device that uses memory devices, e.g., eMMC devices, that use a single channel to carry out two different processes, e.g., write and read processes. | 2011-04-28 |
| 20110099314 | Method for Operating a Trip Recorder of a Motor Vehicle and a Trip Recorder for Performing the Method - A trip recorder, a memory card or a cleaning card being passed by a reading device by an electric motor drive. The trip recorder attempts to establish communication with the inserted card. If no communication can be established, the reader device or the memory card is dirty, or the cleaning card is inserted in the trip recorder. In case of a failed attempt at communication, the electric motor drive moves the inserted card past the reader device repeatedly removing potential contamination. | 2011-04-28 |
| 20110099315 | MULTIMEDIA SYSTEM - A multimedia system includes a portable device, a multimedia expansion apparatus and a second display. The portable device further includes a main body and a first display coupling with the main body, in which the main body has a first multimedia module and a switch module. The multimedia further includes an expansion port for coupling the portable device, a multimedia switch circuit, a plurality of signal output ports and a power control circuit for energizing the expansion port, the multimedia switch circuit and the signal output ports. The second display is coupled with one of the signal output ports. The switch module forwards a multimedia signal of the main body to one of the first multimedia module and the multimedia switch circuit, and the power control circuit is to terminate power output to while the portable device is separated from the expansion port of the multimedia expansion apparatus. | 2011-04-28 |
| 20110099316 | Dock-Specific Display Modes - In general, the subject matter described in this specification can be embodied in methods, systems, and program products. A mobile computing device is determined to have electrically coupled by physical contact with a docking system that is adapted to supply electrical power for charging the mobile computing device. The docking system is determined to be a first type of docking system from a plurality of types of docking systems. A first user interface profile that corresponds to the first type of docking system is selected from among a plurality of user interface profiles. Each of the plurality of user interface profiles corresponds to a respective type of docking system from the plurality of types of docking systems. The first user interface profile is presented by the mobile computing device in response to selection of the first user interface profile. | 2011-04-28 |
| 20110099317 | INPUT-OUTPUT MODULE FOR OPERATION IN MEMORY MODULE SOCKET AND METHOD FOR EXTENDING A MEMORY INTERFACE FOR INPUT-OUTPUT OPERATIONS - An I/O module configured to operate in a memory module socket and method for extending a memory interface are generally described herein. The I/O module may include a serial-presence detection (SPD) device to indicate that the I/O module is an I/O device and to indicate one or more functions associated with the I/O module. The I/O module may also include a serial data controller to communicate serial data in accordance with a predetermined communication technique with a configurable switch of a host system over preselected system management (SM) bus address lines and unused system clock signal lines of the memory module socket. The predetermined communication technique may include a peripheral component interconnect express (PCIe), a Serial Advanced Technology Attachment (SATA), a Serial Attached Small Computer System Interface (SAS), a universal-serial bus (USB) or a switched-fabric (InfiniBand) communication technique. | 2011-04-28 |
| 20110099318 | Leveraging Memory Similarity During Live Migrations - A page scanner may be configured to identify, during a live migration of a virtual machine including a transfer of a plurality of memory pages from source hardware resources to destination hardware resources, a candidate memory page of the plurality of memory pages to include in the transfer while at least one operation of the virtual machine continues to execute. A fingerprint comparator may be configured to compare a candidate page fingerprint of the candidate memory page to existing page fingerprints of existing memory pages stored using the second hardware resources, and further configured to determine, based on the comparing, that a duplicate of the candidate page is included within the existing memory pages. A duplicate page handler may be configured to facilitate continued execution of the virtual machine using the duplicate of the candidate page and the second hardware resources. | 2011-04-28 |
| 20110099319 | INPUT-OUTPUT MEMORY MANAGEMENT UNIT (IOMMU) AND METHOD FOR TRACKING MEMORY PAGES DURING VIRTUAL-MACHINE MIGRATION - An input-output memory management unit (IOMMU) and method for tracking memory pages during virtual-machine migration are generally described herein. The IOMMU includes an IOMMU manager to service address translation requests associated with memory pages received from a plurality of I/O devices, and a translation request filter to identify translations previously requested from a translation manager. The IOMMU also includes a device context table to identify whether virtual-machine migration is enabled for memory pages associated with virtual addresses identified in received address translation requests. Based on information in the device context table, the IOMMU manager may send a virtual page identifier to the translation manager identifying a virtual page when virtual-machine migration is enabled to indicate that the virtual page has been accessed. The IOMMU manager refrains from sending the virtual page identifier to the translation manager when the virtual page is listed in the translation request filter. | 2011-04-28 |
| 20110099320 | Solid State Drive with Adjustable Drive Life and Capacity - A method for adjusting a drive life and a capacity of a solid state drive (SSD), the SSD comprising a plurality of memory devices includes determining a desired drive life for the SSD; determining a utilization for the SSD; and allocating a portion of the plurality of memory devices as available memory and a portion of the plurality of memory devices as spare memory based on the desired drive life and the utilization. An SSD with an adjustable drive life and capacity includes a plurality of memory devices; and a memory allocation module configured to: determine a desired drive life for the SSD; determine a utilization for the SSD; and allocate a portion of the plurality of memory devices as available memory and a portion of the plurality of memory devices as spare memory based on the desired drive life and the utilization. | 2011-04-28 |
| 20110099321 | ENABLING SPANNING FOR A STORAGE DEVICE - A storage device, e.g., an SSD, is configured to enable spanning for a logical block between pages of the device. In one example, a device includes a data storage module to receive data to be stored, wherein the data comprises a plurality of logical blocks, and wherein a size of the plurality of logical blocks exceeds a size of a first page of the device, and a spanning determination module to determine whether to partition one of the plurality of logical blocks into a first partition and a second partition, wherein the data storage module is configured to partition the one of the plurality of logical blocks into the first partition and the second partition and to store the first partition in the first page and the second partition in a second, different page when the spanning determination module determines to partition the one of the plurality of logical blocks. | 2011-04-28 |
| 20110099322 | DATA STORAGE DEVICE WITH INTEGRATED DNA STORAGE MEDIA - An integral digital memory storage device having a standard form factor to be received by and communicating with a computing device and having memory capability for storage of digital data. An integral multiwell DNA sample tray is carried in a body of the memory storage device for protection and exposed by manipulation of the case for receiving DNA samples. | 2011-04-28 |
| 20110099323 | NON-VOLATILE SEMICONDUCTOR MEMORY SEGREGATING SEQUENTIAL, RANDOM, AND SYSTEM DATA TO REDUCE GARBAGE COLLECTION FOR PAGE BASED MAPPING - A non-volatile semiconductor memory is disclosed comprising a memory device having a memory array including a plurality of memory segments. A plurality of sequential access write commands and random access write commands are received from a host, wherein each write command identifies at least one logical block address (LBA). The LBAs for the sequential access write commands are mapped to a plurality of the memory segments to generate sequential mapping data, and the sequential mapping data is mapped to a first one of the zones. The LBAs for the random access write commands are mapped to a plurality of the memory segments to generate random mapping data, and the random mapping data is mapped to a second one of the zones. | 2011-04-28 |
| 20110099324 | FLASH MEMORY STORAGE SYSTEM AND FLASH MEMORY CONTROLLER AND DATA PROCESSING METHOD THEREOF - A flash memory storage system including a flash memory chip, a connector, and a flash memory controller is provided. The flash memory controller configures a plurality of logical addresses and maps the logical addresses to a part of the physical addresses in the flash memory chip, and a host system uses a file system to access the logical addresses. Besides, the flash memory controller identifies a deleted logical address among the logical addresses and marks data in the physical address mapped to the deleted logical address as invalid data. Thereby, the flash memory storage system can identify data deleted by the host system in the physical addresses, so that the time for sorting data can be effectively reduced. | 2011-04-28 |
| 20110099325 | USER DEVICE AND MAPPING DATA MANAGEMENT METHOD THEREOF - In the mapping data management method, data that is being used by a host is stored in response to a power-off command from a user. The host generates a power-off notification signal to a storage device. The storage device stores mapping data of a volatile memory in a nonvolatile memory in response to the power-off notification signal. | 2011-04-28 |
| 20110099326 | FLASH MEMORY SYSTEM AND DEFRAGMENTATION METHOD - Provided is a flash memory system supporting flash defragmentation. The flash memory system includes a host and a flash storage device. In response to a flash defragmentation command by the host, the flash storage device performs flash defragmentation by grouping fragments stored in fragmented blocks of a flash memory on a flash memory management unit basis. The flash memory management unit may be a memory block or page. The flash storage device performs the flash defragmentation regardless of the arrangement order of fragmented files stored in the flash memory. | 2011-04-28 |
| 20110099327 | SYSTEM AND METHOD FOR LAUNCHING AN APPLICATION PROGRAMMING UTILIZING A HYBRID VERSION OF DEMAND PAGING - A system and method for launching a computer application program stored in a nonvolatile medium, wherein by reusing a page load scheme from a standard demand page based launch. The system and method includes launching a computer application program one or more times using demand paging to load memory pages of the nonvolatile medium associated with the computer application into a volatile memory for execution of the computer application program. Memory address information corresponding to the pages of the nonvolatile medium corresponding to portions of the computer application program accessed during use of the computer application program are stored in a launch record. The computer application program is launched using the address information stored in the launch record to read nonvolatile medium addresses stored in the launch record in a single or consecutive read step. | 2011-04-28 |
| 20110099328 | EFFICIENTLY RESTORING DATA FROM A SEQUENTIAL-ACCESS BACKUP ARCHIVE - A method for efficiently restoring data from a sequential-access backup archive includes receiving a candidate list identifying data sets that are potentially contained within a sequential-access backup archive. The method further receives a filter list identifying data sets that are desired to be restored from the backup archive. Using the candidate list and filter list, the method generates a search list identifying data sets that are to be ignored when searching the backup archive. The method then sequentially performs multiple searches of the backup archive such that the multiple searches collectively perform a single pass through the backup archive. When performing these searches, each search begins from the last accessed portion of the backup archive and stops upon encountering a data set not explicitly ignored by the search list. A corresponding system, apparatus, and computer program product are also disclosed herein. | 2011-04-28 |
| 20110099329 | ANALYSIS AND TIMELINE VISUALIZATION OF STORAGE CHANNELS - The visualization of a storage access on a timeline that represents various disk access events, such as a storage read event, or a storage write event. The storage access timeline may be formulated using event data gathered regarding storage access events, such as storage read requests, or storage write requests. The timeline may be displayed in conjunction with non-storage events, such as thread events, process events, processor events, or such, in order to give a visual indication of what is causing the storage access events. There may even be a control for displaying an identification of the file being accessed for one or more of the storage access events. With a better understanding of correlation between storage access events and application operation, optimization of the application itself may be achieved to more efficiently interface with the storage medium. | 2011-04-28 |
| 20110099330 | MEMORY OPTIMIZATION FOR VIDEO PROCESSING - Memory storage requirements for digital signal processing operations, for example, motion-compensated video scan rate conversion, that produce intermediate output data, which is then used as an input to the operation, are reduced by reordering operations and organizing memory allocations in a special manner to allow intermediate output at a particular execution time, to substantially share the same memory space as the intermediate output of a previous execution time. Such a reduction in the amount of memory required for processing operations advantageously reduces cost and power consumption. | 2011-04-28 |
| 20110099331 | STORAGE SYSTEM - In a computer system including a plurality of data storage apparatuses and a management computer, a given data storage apparatus, upon receipt of a control request for a local data storage apparatus from a management computer, accesses the hierarchical relation information between the storage areas in the local data storage apparatus and the storage areas of the other data storage apparatuses, and in the case where a storage area in the local data storage apparatus is set to correspond to a level lower than the other data storage apparatuses, transmits an approval request to the other data storage apparatuses. The given data storage apparatus, upon receipt of the approval from the other data storage apparatuses, executes the control request of the management computer. | 2011-04-28 |
| 20110099332 | METHOD AND SYSTEM OF OPTIMAL CACHE ALLOCATION IN IPTV NETWORKS - In an IPTV network, one or more caches may be provided at the network nodes for storing video content in order to reduce bandwidth requirements. Cache functions such as cache effectiveness and cacheability may be defined and optimized to determine the optimal size and location of cache memory and to determine optimal partitioning of cache memory for the unicast services of the IPTV network. | 2011-04-28 |
| 20110099333 | MECHANISM FOR EFFECTIVELY CACHING STREAMING AND NON-STREAMING DATA PATTERNS - A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of instructions or an amount of time. As a result of performing an access to a cache line for a last use instruction/operation, the cache line is updated to a streaming data no longer needed (SDN) state. When control logic is to determine a cache line to be replaced, a modified Least Recently Used (LRU) algorithm is biased to select SDN state lines first to replace no longer needed streaming data. | 2011-04-28 |
| 20110099334 | CORE CLUSTER, ENERGY SCALABLE VECTOR PROCESSING APPARATUS AND METHOD OF VECTOR PROCESSING INCLUDING THE SAME - A core cluster includes a cache memory, a core, and a cluster cache controller. The cache memory stores and provides instructions and data. The core accesses the cache memory or a cache memory provided in an adjacent core cluster, and performs an operation. The cluster cache controller allows the core to access the cache memory when the core requests memory access. The cluster cache controller allows the core to access the cache memory provided in the adjacent core cluster when the core requests a clustering to the adjacent core cluster. The cluster cache controller allows a core provided in the adjacent core cluster to access the cache memory when the core receives a clustering request from the adjacent core cluster. | 2011-04-28 |
| 20110099335 | SYSTEM AND METHOD FOR HARDWARE ACCELERATION OF A SOFTWARE TRANSACTIONAL MEMORY - In a transactional memory technique, hardware serves simply to optimize the performance of transactions that are controlled fundamentally by software. The hardware support reduces the overhead of common TM tasks—conflict detection, validation, and data isolation—for common-case bounded transactions. Software control preserves policy flexibility and supports transactions unbounded in space and in time. The hardware includes 1) an alert-on-update mechanism for fast software-controlled conflict detection; and 2) programmable data isolation, allowing potentially conflicting readers and writers to proceed concurrently under software control. | 2011-04-28 |
| 20110099336 | CACHE MEMORY CONTROL CIRCUIT AND CACHE MEMORY CONTROL METHOD - A cache memory control circuit has a plurality of counters, each of which is provided per set and per memory space and configured to count how many pieces of data of a corresponding memory space is stored in a corresponding set. The cache memory control circuit controls activation of a tag memory and a data memory of each of a plurality of sets according to a count value of each of the plurality of counters. | 2011-04-28 |
| 20110099337 | PROCESSING CIRCUIT WITH CACHE CIRCUIT AND DETECTION OF RUNS OF UPDATED ADDRESSES IN CACHE LINES - A circuit that comprises a processor core ( | 2011-04-28 |
| 20110099338 | DATA MANAGEMENT SYSTEM AND METHOD - The present invention relates to a data management system and method for storing a plurality of data records ( | 2011-04-28 |
| 20110099339 | INFORMATION PROCESSING APPARATUS, METHOD FOR CONTROLLING INFORMATION PROCESSING APPARATUS AND STORAGE MEDIUM - The information processing apparatus of the present invention comprises a control unit configured to control such that part of a storage region of the second storage unit is used as a virtual storage region for the first storage unit when the information processing apparatus is operating in the first mode, and part of a storage region of the third storage unit is used as the virtual storage region for the first storage unit when the information processing apparatus is operating in the second mode. | 2011-04-28 |
| 20110099340 | MEMORY ACCESS CONTROL DEVICE AND METHOD THEREOF - A memory access control device and method is provided with a cache memory having a plurality of cache areas, each for storing image data of one macroblock, and a cache table having a plurality of table areas, corresponding to the plurality of cache areas, each for storing a scheduled access counter that counts the number of scheduled accesses to a corresponding cache area and an in-frame address of image data of one macroblock stored in the corresponding cache area. A data request processor receives a data request including specification of an in-frame occupation region of the requested image data from the image processor, determines target image data of at least one macroblock required to process requested image data based on the in-frame occupation region of the requested image data, acquires the target image data from the cache memory, processes the image data requested by the data request using the acquired image data, and outputs the processed image data to the image processor. | 2011-04-28 |
| 20110099341 | SYSTEM, APPARATUS, AND METHOD FOR MODIFYING THE ORDER OF MEMORY ACCESSES - Systems and methods for controlling memory access operations are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a request queue receives requests from a requestor, a bank decoder determines a destination bank, and the request is placed in an appropriate bank queue. An ordering unit determines if the current request can be reordered relative to the received order and generates a new memory cycle order based on the reordering determination. The reordering may be based on whether there are multiple requests to the same memory page, multiple reads, or multiple writes. A memory interface executes each memory request in the memory cycle order. A data buffer holds write data until it is written to the memory and read data until it is returned to the requestor. The data buffer also may hold memory words used in read-modify-write operations. | 2011-04-28 |
| 20110099342 | Efficient Logging for Asynchronously Replicating Volume Groups - A system and method for logging for asynchronously replicating volume groups. A write request to write data to a location in a volume may be received. Metadata associated with the write request may be stored. It may be determined if the write request possibly overlaps with one or more earlier write requests to the volume that have not yet been replicated to a secondary storage. The data may be stored in a replication log only if the write request possibly overlaps with one or more earlier write requests to the volume. The data may not be stored in the replication log if the write request does not overlap with one or more earlier write requests to the volume. The data may be written to the location in the volume. Changes to the volume may periodically be replicated to the secondary storage using the replication log. | 2011-04-28 |
| 20110099343 | Self-Adjusting Change Tracking for Fast Resynchronization - System and method for tracking changes to a volume. A write request to write data to a first location in the volume may be received. It may be determined if the first location is overlapping with or adjacent to one or more locations of earlier write requests to the volume. First location information may be stored in a data structure in response to determining that the first location is overlapping with or adjacent to one or more second locations of earlier write requests to the volume. The first location information may identify the first location and the one or more second locations. Second location information may be removed from the data structure, where the second location information identifies the one or more second locations of earlier write requests to the volume. The data may be written to the first location in the volume in response to the write request. | 2011-04-28 |
| 20110099344 | FACILITATING DATA COMPRESSION DURING REPLICATION USING A COMPRESSIBLE CONFIGURATION BIT - Computer program product, system and method are provided for facilitating data replication in a storage system. A logical volume of a first storage array of a replicated pair is preconfigured with one or more logical volume attributes, which include a compressible configuration bit that indicates whether data blocks to be stored to that logical volume are compressible during replication. Subsequently, with receipt of a data block at the first storage array to be stored to the logical volume, a check of the compressible configuration bit is made to determine whether the data block is compressible during replication, and if so, the data block is compressed for replication. The compressible configuration bit is placed into the payload region of the data packet being replicated to the second storage array. At the second storage array, the compressible configuration bit is used to determine whether to uncompress the replicated data block. | 2011-04-28 |
| 20110099345 | COMPUTER SYSTEM AND PROGRAM RECORDING MEDIUM - One or a plurality of copy pairs are disposed in a plurality of storage systems. A management server determines the propriety of execution of an operation request for each user for either a local copy pair or a remote copy pair. As operation requests, a pair create, a split, a resync, a restore, and a pair delete can be cited. | 2011-04-28 |
| 20110099346 | APPARATUS AND METHOD FOR CONTROLLING STORAGE SYSTEM - In a storage control apparatus, a first duplication control unit causes a logical volume in a disk array device to be copied to a secondary storage medium. A second duplication control unit causes the logical volume to be copied also to an export storage medium in a library device, in connection with the copying to the primary storage medium by the first duplication control unit, when export attributes indicate that the logical volume copied by the first duplication control unit is supposed to be exported. A medium ejection control unit causes the library device to eject the export storage medium, in response to an ejection request therefor. | 2011-04-28 |
| 20110099347 | MANAGING ALLOCATION AND DEALLOCATION OF STORAGE FOR DATA OBJECTS - Various approaches for managing storage for data objects. In one approach, data describing a plurality of allocation control areas are stored. Each allocation control area references a respective set of free pages that are available for allocation for storing data objects. In response to a request to delete a data object, a non-blocking exclusive lock is sought on an initial one of the allocation control areas. If the lock is granted, each page having data of the data object is returned to the respective set of free pages of the initial one of the allocation control areas. If the lock is denied, another one of the allocation control areas to which a non-blocking exclusive lock can be granted is determined, and each page is returned to the respective set of free pages of the other one of the allocation control areas. | 2011-04-28 |
| 20110099348 | CONTROLLING MEMORY VISIBILITY - Embodiments are disclosed herein that are related to controlling the visibility of a portion of memory in a hardware device. For example, one disclosed embodiment provides a hardware device comprising a communications interface configured to connect to a complementary communications interface on a computing device. The hardware device further comprises a portion of memory having a first ID configured to cause the portion of memory to be visible to a user of the computing device to which the hardware device is connected. Further still, the hardware device comprises instructions stored in the portion of memory which are executable by and transferable to the computing device to cause the installation of a computer program related to the hardware device, and to cause the portion of memory to be hidden from the user of the computing device upon transferring of the instructions to the computing device. | 2011-04-28 |
| 20110099349 | MEMORY SYSTEM - A controller executes first processing for writing a plurality of data in a sector unit in the first storing area; second processing for flushing the data stored in the first storing area to the first input buffer in a first management unit twice or larger natural number times as large as the sector unit; third processing for flushing the data stored in the first storing area to the second input buffer in a second management unit twice or larger natural number times as large as the first management unit; fourth processing for relocating a logical block in which all pages are written in the first input buffer to the second storing area; fifth processing for relocating a logical block in which all pages are written in the second input buffer to the third storing area; and sixth processing for flushing a plurality of data stored in the second storing area to the second input buffer in the second management unit. | 2011-04-28 |
| 20110099350 | BLOCK BOUNDARY RESOLUTION FOR MISMATCHED LOGICAL AND PHYSICAL BLOCK SIZES - The present disclosure describes various techniques resolving block boundary issues and reconstructing logical blocks in a block access storage device when there are resulting mismatches between logical and physical block sizes or alignments, such that logical blocks span multiple physical block boundaries in irregular ways. In one example, a method comprises the following features: receiving logical block addresses that are associated with a sequence of logical blocks; and locating a first portion of a logical block within a first physical block that is stored in a block access storage device based upon a logical block address of the logical block, wherein the logical block is part of the sequence of logical blocks, and wherein at least two logical blocks within the sequence of logical blocks have different sizes. | 2011-04-28 |
| 20110099351 | Use of Similarity Hash to Route Data for Improved Deduplication in a Storage Server Cluster - A technique for routing data for improved deduplication in a storage server cluster includes computing, for each node in the cluster, a value collectively representative of the data stored on the node, such as a “geometric center” of the node. New or modified data is routed to the node which has stored data identical or most similar to the new or modified data, as determined based on those values. Each node stores a plurality of chunks of data, where each chunk includes multiple deduplication segments. A content hash is computed for each deduplication segment in each node, and a similarity hash is computed for each chunk from the content hashes of all segments in the chunk. A geometric center of a node is computed from the similarity hashes of the chunks stored in the node. | 2011-04-28 |
| 20110099352 | Automatic control of multiple arithmetic/logic SIMD units - There is provided a method of performing single instruction multiple data (SIMD) operations. The method comprises storing a plurality of arrays in memory for performing SIMD operations thereon; determining a total number of SIMD operations to be performed on the plurality of arrays; loading a counter with the total number of SIMD operations to be performed on the plurality of arrays; enabling a plurality of arithmetic logic units (ALUs) to perform a first number of operations on first elements of the plurality of arrays; performing the first number of operations on first elements of the plurality of arrays using the plurality of ALUs; decrementing the counter by the first number of operations to provide a remaining number of operations; and enabling a number of the plurality of ALUs to perform the remaining number of operations on second elements of the plurality of arrays. | 2011-04-28 |
| 20110099353 | System and Method for Extracting Fields from Packets Having Fields Spread Over More Than One Register - Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register designated as a first source register, and executes a second instruction extracting any part of the field from a second general register designated as a second source register. The second instruction inserts any extracted field parts in a result register. | 2011-04-28 |
| 20110099354 | Information processing apparatus and instruction decoder for the information processing apparatus - An information processing apparatus includes an instruction supplying section that supplies a plurality of instructions as a single instruction group, an executing section that repetitively executes a plurality of execution processes corresponding to the plurality of instructions in parallel, an issue timing control section that controls an issue timing of each of the instructions to the executing section so that the plurality of execution processes are executed with a timing delayed in accordance with a predetermined latency, and an operand transforming section that transforms an operand register address of each of the instructions in accordance with a predetermined increment value upon every repetition of execution in the executing section. | 2011-04-28 |
| 20110099355 | MULTI-THREADING PROCESSORS, INTEGRATED CIRCUIT DEVICES, SYSTEMS, AND PROCESSES OF OPERATION AND MANUFACTURE - A multi-threaded microprocessor ( | 2011-04-28 |
| 20110099356 | DEVICE FOR CORRECTING SET-POINT SIGNALS AND SYSTEM FOR THE GENERATION OF GRADIENTS COMPRISING SUCH A DEVICE - A device for real-time correction of set-point signals intended to receive at the input set-point signals and to deliver at its output set-point signals that are modified to compensate for defects, negative effects or the like subsequently encountered during the processing and/or the application of the set-point signals. This device ( | 2011-04-28 |
| 20110099357 | Utilizing a Bidding Model in a Microparallel Processor Architecture to Allocate Additional Registers and Execution Units for Short to Intermediate Stretches of Code Identified as Opportunities for Microparallelization - An enhanced mechanism for parallel execution of computer programs utilizes a bidding model to allocate additional registers and execution units for stretches of code identified as opportunities for microparallelization. A microparallel processor architecture apparatus permits software (e.g. compiler) to implement short-term parallel execution of stretches of code identified as such before execution. In one embodiment, an additional paired unit, if available, is allocated for execution of an identified stretch of code. Each additional paired unit includes an execution unit and a half set of registers. This apparatus is available for compilers or assembler language coders to use and allows software to unlock parallel execution capabilities that are present in existing computer programs but heretofore were executed sequentially for lack of a suitable apparatus. The enhanced mechanism enables a variable amount of parallelism to be implemented and yet provides correct program execution even if less parallelism is available than ideal for a given computer program. | 2011-04-28 |
| 20110099358 | NETWORK SYSTEM, METHOD OF CONTROLLING ACCESS TO STORAGE DEVICE, ADMINISTRATION SERVER, STORAGE DEVICE, LOG-IN CONTROL METHOD, NETWORK BOOT SYSTEM, AND METHOD OF ACCESSING INDIVIDUAL STORAGE UNIT - A network boot system including one or more client terminals, a DHCP (Dynamic Host Configuration Protocol) server, a PXE (Preboot Execution Environment) server, a TFTP (Trivial File Transfer Protocol) server, a database administration server, one or more storage devices, and an authentification server (such as a Radius server) connected to each other via a TCP/IP (Transmission Control Protocol)/Internet Protocol) network. A plurality of LU provided in the storage devices as separated into a system area LU and a user area LU prepared per user. | 2011-04-28 |
| 20110099359 | Controlling A Device's Boot Path With Disk Locking - The computing system whose boot path is controlled by data locking comprised of: a processing device capable of executing instructions, including BIOS instructions for determining the booting priority of at least an application memory storage device and a services memory storage device, wherein the applications memory storage device and the services memory storage device are electrically coupled to the processing device, wherein the BIOS instructions set the booting priority of the services memory storage device higher than the priority of the application memory storage device and wherein the services memory storage device is capable of being locked and unlocked. | 2011-04-28 |
| 20110099360 | Addressing Node Failure During A Hyperswap Operation - A method, system, and article are provided to enable a Hyperswap operation in a clustered computer system. Each node in the system is configured with flash memory, with a hierarchical list of boot volumes therein. Following a Hyperswap operation, the current boot volume is communicated to each node in the cluster and each node joining the cluster. All previously inactive nodes that were booted from the improper boot volume are re-booted from the correct and the flash memory is amended to reflect the correct boot volume. | 2011-04-28 |
| 20110099361 | Validation And/Or Authentication Of A Device For Communication With Network - A device may include a trusted component. The trusted component may be verified by a trusted third party and may have a certificate of verification stored therein based on the verification by the trusted third party. The trusted component may include a root of trust that may provide secure code and data storage and secure application execution. The root of trust may also be configured to verify an integrity of the trusted component via a secure boot and to prevent access to the certain information in the device if the integrity of the trusted component may not be verified. | 2011-04-28 |
| 20110099362 | INFORMATION PROCESSING DEVICE, ENCRYPTION KEY MANAGEMENT METHOD, COMPUTER PROGRAM AND INTEGRATED CIRCUIT - For the keys in a key tree group composed of root keys for each of multiple stakeholders, a shared key is generated between the multiple stakeholders, and access restrictions with respect to the generated shared key are flexibly set. A shared key control unit and a tamper-resistant module are provided for each of the multiple stakeholders. The shared key is set based on stakeholder dependency relationships. After the shared key is set, access to the shared key is controlled so that access is not possible by malicious stakeholders, so as to maintain the security level. | 2011-04-28 |
| 20110099363 | SECURE END-TO-END TRANSPORT THROUGH INTERMEDIARY NODES - A communication network encrypts a first portion of a transaction associated with point-to-point communications using a point-to-point encryption key. A second portion of the transaction associated with end-to-end communications is encrypted using an end-to-end encryption key. | 2011-04-28 |
| 20110099364 | Method for accessing services by a user unit - The invention concerns a method for accessing services by a user unit, said services being a subset of all services broadcast by a management center and comprising at least two services, said subset of services defining a package, each service being simultaneously broadcast and containing audio/video data, the data of a service being encrypted by at least one control word, the method comprising the steps of:
| 2011-04-28 |
| 20110099365 | METHODS AND APPARATUS FOR MULTI-LEVEL DYNAMIC SECURITY SYSTEM - Methods and apparatus for converting original data into a plurality of sub-bands using wavelet decomposition; encrypting at least one of the sub-bands using a key to produce encrypted sub-band data; and transmitting the encrypted sub-band data to a recipient separately from the other sub-bands. | 2011-04-28 |
| 20110099366 | Secure Transfer of Information - Disclosed is a method for secure transfer of information through a centralized system. The method comprising: maintaining user account information, a user account of a certain user comprising at least a user id and associated public and private keys, the private key being retrievable by means of a password of said certain user; receiving ( | 2011-04-28 |
| 20110099367 | KEY CERTIFICATION IN ONE ROUND TRIP - Certification of a key, which a Trusted Platform Module (TPM) has attested as being non-migratable, can be performed in a single round trip between the certificate authority (CA) and the client that requests the certificate. The client creates a certificate request, and then has the TPM create an attestation identity key (AIK) that is bound to the certificate request. The client then asks the TPM to sign the new key as an attestation of non-migratability. The client then sends the certificate request, along with the attestation of non-migratability to the CA. The CA examines the certificate request and attestation of non-migratability. However, since the CA does not know whether the attestation has been made by a trusted TPM, it certifies the key but includes, in the certificate, an encrypted signature that can only be decrypted using the endorsement key of the trusted TPM. | 2011-04-28 |
| 20110099368 | CABLE MODEM AND CERTIFICATE TESTING METHOD THEREOF - A cable modem stores certificates including a root certificate authority (CA) certificate, a root CA public key, a manufacturer CA certificate, and a cable modem certificate. The cable modem reads the root CA public key, determines whether the root CA public key complies with a key industry standard, determines whether the manufacturer CA certificate is generated according to the root CA certificate, and determines whether the cable modem certificate is generated according to the manufacturer CA certificate. | 2011-04-28 |
| 20110099369 | FILE ENCRYPTION SYSTEM AND METHOD - An electronic document comparison system and method converts a test file into a compressed file having a specific format. A public key of the CA certificate of a user is obtained and a random key is generated using a random function. Furthermore, the compressed file is symmetrically encrypted using the random key, and the random key is asymmetrically encrypted using the public key to generate an asymmetric encryption key. A header of the compressed file is attached with the asymmetric encryption key and data length of the asymmetric encryption key. | 2011-04-28 |
| 20110099370 | METHOD, APPARATUS, AND SYSTEM FOR PROCESSING DYNAMIC HOST CONFIGURATION PROTOCOL MESSAGE - A method, apparatus, and system for processing a Dynamic Host Configuration Protocol (DHCP) message are disclosed. The method includes: receiving a DHCP message, where the source address of the DHCP message is a Cryptographically Generated Address (CGA) and a signature of a DHCP message sender is carried in the DHCP message; verifying the CGA and the signature; and processing a payload of the DHCP message after the verification of the CGA and the signature succeeds. The CGA and the signature are verified in the embodiment of the present invention, thus improving the security of DHCPv6, and bringing convenience for key management due to publicity of the public key. In addition, because the life of the public key is long, configuration on the DHCP server and/or the network client is convenient. | 2011-04-28 |
| 20110099371 | AERONAUTICAL SECURITY MANAGEMENT OVER BROADBAND AIR/GROUND NETWORK - A method to facilitate securing of air-to-ground communications for an aircraft is provided. The method includes receiving security management information at the aircraft via at least one broadband data link prior to takeoff of the aircraft. The security management information is received for ground entities that can be communicatively coupled with the aircraft traveling on a flight path. The method of securing avionics also includes validating the security management information for the ground entities, and storing the validated security management information for the ground entities in the aircraft. The validating and storing of security management information occur prior to takeoff of the aircraft. | 2011-04-28 |
| 20110099372 | METHOD AND SYSTEM FOR PROVIDING PEER-TO-PEER VIDEO ON DEMAND - A method in which user generated video content is distributed over a peer to peer network as video on demand. Video is rendered during download and a user may request a specific point in the video content and that point and all subsequent video content will be downloaded and rendered first via the peer to peer network. | 2011-04-28 |
| 20110099373 | Digital Broadcasting System and Method of Processing Data in Digital Broadcasting System - A digital broadcasting system and a method for processing data in the same are disclosed. A method for controlling a digital television (DTV) located in one independent space among a plurality of independent spaces physically separated from one another is disclosed. The DTV includes an access point (AP) card. The method includes receiving independent space identification information recorded in a storage area of a compact wireless device and a wired equivalent privacy (WEP) key value of the AP card, receiving the WEP key value corresponding to the AP card of the DTV from a management server, comparing the WEP key value received from the compact wireless device with the WEP key value received from the management server, receiving first checklist information associated with the use of the independent space from the management server, if the WEP key values are identical to each other, displaying the received first checklist information, and transmitting second checklist information, in which one or more elements of the displayed first checklist information is marked, to the management server. | 2011-04-28 |
| 20110099374 | AUTHENTICATION OF A SECURE VIRTUAL NETWORK COMPUTING (VNC) CONNECTION - A secure Virtual Network Computing (VNC) connection between a server and a client is authenticated using a series of message exchanges. A server receives a request from a client to establish a VNC connection. If the request indicates that the client supports an encryption scheme, the server provides a first set of mechanisms for a subsequent authentication process. If the request indicates that the client does not support the encryption scheme, the server provides the client a second set of mechanisms for the subsequent authentication process. The second set contains fewer mechanisms than the first set. The client chooses an authentication mechanism from the first set or the second set provided by the server. The server and the client then perform the subsequent authentication process, using the authentication mechanism chosen by the client, with a series of message exchanges. | 2011-04-28 |
| 20110099375 | System and Method for Managing Security Testing - The subject matter relates generally to a system and method for managing security testing. Particularly, this invention relates to maintaining a security database by correlating multiple sources of vulnerability data and also to managing security testing from plural vendors. This invention also relates to providing secure session tracking by performing plural authentications of a user. | 2011-04-28 |
| 20110099376 | SYSTEMS AND METHODS FOR AUTHENTICATING AN ELECTRONIC TRANSACTION - Systems and methods for authenticating a request between a client computer and a transaction server are provided. An application request, comprising an identity of a user originating the request, is received at an application server from the client. The application server constructs a signing key based on (i) the identity of the user making the request, (ii) a time based salt value, (iii) a secret shared between the application and transaction servers and, optionally, (iv) an identifier of the distributor or developer of the application. The signing key is embedded in an unbranded version of the application thereby branding the application. The branded application can sign a request with the signing key and submit the signed request to the transaction server with the identity of the user and the identifier of the distributor or developer of the application. | 2011-04-28 |
| 20110099377 | COMPACT SECURITY DEVICE WITH TRANSACTION RISK LEVEL APPROVAL CAPABILITY - The present invention relates to the field of securing electronic transactions and more specifically to methods to indicate and verify the approval of the risk level of a transaction and to apparatuses for generating transaction risk level approval codes. | 2011-04-28 |
| 20110099378 | DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA IN DIGITAL BROADCASTING SYSTEM - A method for controlling a DTV located in one independent space among physically-separated independent spaces includes receiving an AP-card WEP key value recorded in a storage of a compact wireless device, receiving the WEP key value corresponding to an AP card of the DTV from a management server, comparing the WEP key value from the compact wireless device with the WEP key value from the management server, transmitting first general wireless device ID from the general wireless device to the compact wireless device if the WEP key values are identical, receiving an Internet service accept packet from the compact wireless device if at least one second general wireless device ID recorded in the storage area of the compact wireless device is identical to the first general wireless device ID, and controlling the general wireless device to use an Internet service through the AP card of the DTV. | 2011-04-28 |
| 20110099379 | AUGMENTED SINGLE FACTOR SPLIT KEY ASYMMETRIC CRYPTOGRAPHY-KEY GENERATION AND DISTRIBUTOR - A system for authenticating a user of a communication network is disclosed. The system includes a user station associated with the user and an authenticating station communicatively coupled to the user station via the communication network. The authenticating station is configured to authenticate the user. The authenticating station is further configured to perform an operation, which includes receiving a first value, from a user station associated with the user, via the communication network. The first value represents a first user credential. A first key portion is generated based on the first value and a second value that is unknown to the user. The first key portion, along with a second key portion, is used for authenticating credentials of the user for a predefined period of time or for authenticating user credentials for a predefined number of times. The second key portion is generated based on the first key portion. A cookie that includes the second value or a value derived from the second value is generated and transmitted to the user station and then the second value is destroyed. | 2011-04-28 |
| 20110099380 | System and Method of Controlling Access to Information Content Transmitted Over Communication Network - An electronic communication system provides sender controlled access to electronic communications transmitted through an electronic communication network. A sender profile and recipient profile are registered with an electronic content service provider. An electronic communication with information content is transmitted from a sender computer to the electronic content service provider. A signature is generated unique to the electronic communication. The signature without the information content is transmitted to a recipient computer. The information content of the electronic communication is accessed by transmitting an authorization based on the recipient profile from the recipient computer to the electronic content service provider. The information content of the electronic communication is transmitted from the electronic content service provider through the electronic communication network to the recipient computer with restricted access as determined by the sender computer upon confirmation of the authorization. If the authorization is not confirmed, access to the electronic communication is blocked. | 2011-04-28 |
| 20110099381 | SYSTEM AND METHOD FOR RETRIEVING CERTIFICATES ASSOCIATED WITH SENDERS OF DIGITALLY SIGNED MESSAGES - A system and method for retrieving certificates and/or verifying the revocation status of certificates. In one embodiment, when a user opens a digitally signed message, a certificate that is required to verify the digital signature on the message may be automatically retrieved if it is not stored on the user's computing device (e.g. a mobile device), eliminating the need for users to initiate the task manually. Verification of the digital signature may also be automatically performed by the application after the certificate is retrieved. Verification of the revocation status of a certificate may also be automatically performed if it is determined that the time that has elapsed since the status was last updated exceeds a pre-specified limit. | 2011-04-28 |
| 20110099382 | PERSONALIZED DIGITAL MEDIA ACCESS SYSTEM (PDMAS) - The invention is an apparatus that facilitates access to encrypted digital media to accept verification and authentication from an excelsior enabler using at least one token and at least one electronic identification. The at least one electronic identification could be a device serial number, a networking MAC address, or a membership ID reference from a web service. Access to the product is also managed with a plurality of secondary enablers using the at least one electronic identification reference. | 2011-04-28 |
| 20110099383 | METHOD FOR TRANSMITTING DATA AND PREVENTING UNAUTHORIZED DATA DUPLICATION FOR HUMAN-MACHINE INTERFACE DEVICE USING MASS STORAGE CLASS OPERATING ON UNIVERSAL SERIAL BUS - A method for transmitting data and preventing unauthorized data duplication for human-machine interface device (HID) using Mass Storage Class (MSC) operating on Universal Serial Bus (USB) simulating the HID as an external USB storage device to make data connection to an external computer thus driver installation is not required when the operating system used by the external computer is not compatible with the operating used by the HID. The method encrypted the transmitted data via a dynamic password and does not write the data to the File Allocation Table (FAT) therefore the transmitted data is not under threat of unauthorized data duplication by a third party. | 2011-04-28 |
| 20110099384 | STRONG AUTHENTICATION TOKEN USABLE WITH A PLURALITY OF INDEPENDENT APPLICATION PROVIDERS - The present invention defines a strong authentication token for generating different dynamic credentials for different application providers comprising an input interface providing an output representing an application provider indicator; a secret key storage for storing one or more secret keys; a variability source for providing a dynamic variable value; a key providing agent for providing an application provider specific key as a function of said application provider indicator using one or more keys stored in said secret key storage; a cryptographic agent for cryptographically combining said application provider specific key with said dynamic variable value using symmetric cryptography; a transformation agent coupled to said cryptographic agent for transforming an output of said cryptographic agent to produce a dynamic credential; and an output interface to output said dynamic credential. | 2011-04-28 |
| 20110099385 | BIOMETRIC AUTHENTICATION METHOD AND COMPUTER SYSTEM - A biometric authentication method for a computer system, the computer system comprising: a computer; and an authentication server, the biometric authentication method including steps of: extracting a first feature from the captured biometric information; generating a template polynomial for enrollment; extracting a second feature from the captured biometric information; generating a template polynomial for authentication; generating a correlation function for calculating a correlation between the template polynomial for authentication and the enrolled template polynomial; calculating a correlation value between the template polynomial for authentication and the enrolled template polynomial by using the generated correlation function, and determining based on the calculated correlation value whether or not the biometric information at the time of authentication coincides with the biometric information enrolled. | 2011-04-28 |
| 20110099386 | DEVICE AND METHOD FOR DETECTING A MANIPULATION OF AN INFORMATION SIGNAL - The present invention relates to a device for detecting a manipulation of an information signal, having an extractor for extracting an information signal component characteristic for the information signal from the information signal, an encryptor for encrypting the information signal component to obtain an encrypted signal, and a comparator for comparing the encrypted signal to a reference signal, wherein the reference signal is an encrypted representation of a non-manipulated reference signal component of a reference information signal to detect the manipulation. | 2011-04-28 |
| 20110099387 | METHOD AND APPARATUS FOR ENFORCING A PREDETERMINED MEMORY MAPPING - A system and a method are disclosed for enforcing a predetermined mapping of addresses in a physical address space to addresses in a virtual address space in a data processing system including a processor in the virtual address space and a memory in a physical address space. During the compilation and linking of an application to be run on the data processing system, in at least one embodiment, the mapping table is generated linking the virtual addresses to physical addresses. This mapping table is kept secret. A second mapping table is generated using a cryptographic function of the physical address with the virtual address as a key to link virtual addresses to intermediate addresses. The second mapping table is loaded into the memory management unit. The data processing system further includes cryptographic hardware to convert the intermediate address to the physical address using the inverse of the cryptographic function which was used to calculate the intermediate address. | 2011-04-28 |
| 20110099388 | METHOD AND COMPUTER SYSTEM FOR LONG-TERM ARCHIVING OF QUALIFIED SIGNED DATA - The current invention describes a method for long term archiving of qualifiedly signed data in accordance with the current invention, which comprises the steps of hashing the data, encrypting the data through a cryptography algorithm, hashing the encrypted data, signing the hashed data with an advanced time stamp, generating a hash tree over the whole data file or the subgroups thereof and signing the hash tree(s) with a qualified time stamp. Furthermore, a computer system for conducting the method is disclosed. | 2011-04-28 |
| 20110099389 | STAND-BY POWER SYSTEM FOR INFORMATION HANDLING SYSTEMS - A power supply system includes a power supply coupled to a load via a main power rail, and a switch coupled between the power supply and the load on an auxiliary power rail. A controller controls the switch to couple the auxiliary power rail to the load in response to a startup command, and the controller controls the switch to uncouple the load from the auxiliary power rail in response to a shut down command and a low power mode being enabled. | 2011-04-28 |
| 20110099390 | COMPUTER SET PROVIDED WITH A DISK TYPE BATTERY UNIT - A computer set for coupling to a disk drive and a battery unit, includes a disk-drive connecting port, a power diverter circuit and a power source. The connecting port includes a set of disk terminals, a set of battery terminals, and a set of power terminals. The diverter circuit is coupled electrically to the connecting port. The power source is electrically coupled to the diverter circuit such that when the computer set is coupled to the disk drive, the sets of disk and power terminals are electrically coupled to the disk drive and the power source supplies a first electrical power for the disk drive via the diverter circuit. When the computer set is coupled to the battery unit, the sets of battery and power terminals are coupled electrically to the battery unit so as to permit the battery unit to supply a second electrical power for the computer set via the diverter circuit. | 2011-04-28 |
| 20110099391 | STORAGE SYSTEM - A storage system includes: a basic apparatus for transmitting an access request through a data input line for transmitting data; and an extension apparatus for receiving an access request from the basic apparatus through the data input line, the extension apparatus including a storage for storing data and a controller for controlling the access request from the basic apparatus, wherein the basic apparatus superimposes a voltage to the data input line in accordance with the access request, and wherein the extension apparatus includes an upper input voltage detector for detecting the voltage superimposed on the upper data input line and includes a power controller for controlling the power supply to the controller on the basis of the detected voltage. | 2011-04-28 |
| 20110099392 | Delayed Execution of Operations - In general, the subject matter described in this specification can be embodied in methods, systems, and program products for performing power management. A computer process that requires, to be performed, substantial portions of battery storage on the mobile computing device is identified. Execution of the identified process can be deferred while the mobile computing device is not connected to a power source that is for charging the battery storage and that is external to the mobile computing device. Connection of the mobile computing device to the power source is sensed. Performance of the process is triggered in response to sensing that the mobile computing device has been connected to the power source. | 2011-04-28 |
| 20110099393 | MULTI-THREADING PROCESSORS, INTEGRATED CIRCUIT DEVICES, SYSTEMS, AND PROCESSES OF OPERATION AND MANUFACTURE - A multi-threaded microprocessor ( | 2011-04-28 |
| 20110099394 | POWER MANAGEMENT IN A DATA PROCESSING APPARATUS - In a data processing apparatus, a power mode is selected based on data regarding an operating status of a power utility powering the apparatus. The data is transmitted via power supply lines and includes information on timing/duration of present or anticipated brown-out and/or black-out conditions of the power utility. Power management functions can be performed, for example, using a BIOS of the apparatus or a power management application program. | 2011-04-28 |
| 20110099395 | Integrated System Power Controller - Systems and methods for controlling power delivery to system components are disclosed. A Centralized Integrated Power Management Controller is disclosed which includes a controller and a power stage communicatively coupled to the controller through a control bus and a power telemetry bus. The Centralized Integrated Power Management Controller includes an intelligence control unit in the controller corresponding to the power stage. The intelligence control unit drives the power stage through the control bus. | 2011-04-28 |
