17th week of 2012 patent applcation highlights part 41 |
Patent application number | Title | Published |
20120100615 | CELL FATE CONVERSION OF DIFFERENTIATED SOMATIC CELLS INTO GLIAL CELLS - The present invention relates to the reprogramming of differentiated somatic cells, such as those differentiated cells that arise from embryonic mesoderm, into glial cells. Glial cells produced from this reprogramming are functionally equivalent to glial cells that arise from ectodermal origins. | 2012-04-26 |
20120100616 | METHOD OF DOUBLE CROSSOVER HOMOLOGOUS RECOMBINATION IN CLOSTRIDIA - The invention relates to a method of double crossover homologous recombination in a host Clostridia cell comprising: a first homologous recombination event between a donor DNA molecule and DNA of the host cell to form a product of the first recombination event in the host cell, wherein the donor DNA molecule comprises a codA gene and at least two homology arms; and a second recombination event within the product of the first homologous recombination event, thereby to form a product of the second homologous recombination event in the host cell which is selectable by the loss of the codA gene; and a related vector and altered host cell. | 2012-04-26 |
20120100617 | PICHIA PASTORIS LOCI ENCODING ENZYMES IN THE ADENINE BIOSYNTHETIC PATHWAY - Disclosed are the ADE3, ADE4, ADE5, 7, ADE6, ADE8, ADE12, and ADE13 genes encoding various enzymes in the adenine biosynthesis pathway of | 2012-04-26 |
20120100618 | PICHIA PASTORIS LOCI ENCODING ENZYMES IN THE HISTIDINE BIOSYNTHETIC PATHWAY - Disclosed is the HIS7 gene encoding the His7p enzyme in the histidine biosynthesis pathway of | 2012-04-26 |
20120100619 | PICHIA PASTORIS LOCI ENCODING ENZYMES IN THE METHIONINE BIOSYNTHETIC PATHWAY - Disclosed are the MET1, MET3, MET4, MET6, MET7, MET8, MET10, MET14, MET16, MET17, MET19, MET22, MET2, and MET28 genes encoding various enzymes in the methionine biosynthesis pathway of | 2012-04-26 |
20120100620 | PICHIA PASTORIS LOCI ENCODING ENZYMES IN THE LYSINE BIOSYNTHETIC PATHWAY - Disclosed are the LYS1, LYS2, LYS4, LYS5, and LYS9 genes encoding various enzymes in the lysine biosynthesis pathway of | 2012-04-26 |
20120100621 | PICHIA PASTORIS LOCI ENCODING ENZYMES IN THE ARGININE BIOSYNTHETIC PATHWAY - Disclosed are the ARG5, 6, ARG8, ARG9, ARG80, ARG81, and ARG82 genes encoding various enzymes in the arginine biosynthesis pathway of | 2012-04-26 |
20120100622 | PICHIA PASTORIS LOCI ENCODING ENZYMES IN THE URACIL BIOSYNTHETIC PATHWAY - Disclosed are the URA1, URA2, URA4, and URA6 genes encoding various enzymes in the uracil biosynthesis pathway of | 2012-04-26 |
20120100623 | METHOD OF OLIGONUCLEOTIDE SEQUENCING BY MASS SPECTROMETRY - A computer-implemented method for confirming the nucleotide sequence of an oligonucleotide is provided. In certain embodiments, the method comprises: a) inputting the nucleotide sequence of an oligonucleotide; b) executing an algorithm that provides the predicted molecular formulas of fragments of the oligonucleotide; c) comparing the predicted m/z values of the predicted molecular formulas to experimentally-obtained m/z values obtained by analysis of the oligonucleotide by tandem mass spectrometry to determine if the predicted masses correspond with the experimentally-obtained masses. The method may be used, for example, to confirm the identity of a. oligonucleotide after it is synthesized, i.e., to confirm that it has the expected sequence. | 2012-04-26 |
20120100624 | OPTICAL REACTION MEASUREMENT DEVICE AND OPTICAL REACTION MEASUREMENT METHOD - Provided is an optical reaction measurement device that measures whether a reaction is occurring between a sample and a reagent, or how a reaction is progressing, on the basis of changes over time of optical properties of a liquid mixture of the sample and the reagent. The preparation time required for tasks such as mixing the sample and the reagent is predetermined, and when a start switch on the measurement device is turned to “on,” a timer starts running, and the time remaining until the preparation time begins is shown to an operator as a countdown. When the count reaches zero, the operator is informed that the preparation time has begun. The amount of time that has passed since the preparation time began is used as time data to accompany measurement data, and optical property data from after the end of the preparation time is used in analysis. | 2012-04-26 |
20120100625 | Method and Assembly for Determining the Temperature of a Test Sensor - An assembly determines an analyte concentration in a sample of body fluid. The assembly includes a test sensor having a fluid-receiving area for receiving a sample of body fluid, where the fluid-receiving area contains a reagent that produces a measurable reaction with an analyte in the sample. The assembly also includes a meter having a port or opening configured to receive the test sensor; a measurement system configured to determine a measurement of the reaction between the reagent and the analyte; and a temperature-measuring system configured to determine a measurement of the test-sensor temperature when the test sensor is received into the opening. The meter determines a concentration of the analyte in the sample according to the measurement of the reaction and the measurement of the test-sensor temperature. | 2012-04-26 |
20120100626 | Apparatus and Associated Methods - An apparatus comprising a processor and memory including computer program code. The memory and computer program code can be configured to, with the processor, cause the apparatus to illuminate one or more sensor elements with electromagnetic radiation emitted from corresponding regions of an electronic display. The one or more sensor elements can be configured to exhibit a specific electrical response to the illumination when a specific set of analytes are bound to the one or more sensor elements, determine the electrical response of the one or more sensor elements, and compare the determined electrical response with one or more predetermined electrical responses to determine a match. Each predetermined electrical response can be associated with the binding of a different set of analytes, wherein determination of a match allows the specific set of analytes bound to the one or more sensor elements to be identified. | 2012-04-26 |
20120100627 | MEASUREMENT DEVICE USED FOR SPECIFICALLY DETECTING SUBSTANCE TO BE EXAMINED USING PHOTOCURRENT, SENSOR UNIT USED FOR SAME, AND METHOD FOR SPECIFICALLY DETECTING SUBSTANCE TO BE EXAMINED USING PHOTOCURRENT - In utilizing photocurrent generated in the photoexcitation of a dye in specific detection of an analyte, highly accurate detection can be realized by discharging charged current generated in the formation of a sensor unit and, in the detection of photocurrent of a plurality of detection spots provided on a working electrode, discharging photocurrent which is derived from a detection spot subjected to the latest photocurrent measurement and becomes noise current. The present invention provides a measuring apparatus comprising a sensor unit comprising a working electrode, a counter electrode, and an electrolyte-containing substance, a single or plurality of light sources that apply light to the working electrode, an XY moving device provided when the light source is moved relatively in an XY direction relative to the working electrode, an ammeter that measures current which flows across the working electrode and the counter electrode, and a discharge device that discharges charged current and photocurrent derived from a detection spot subjected to the latest photocurrent measurement. The specific detection method using the measuring apparatus is carried out by controlling the timing of light irradiation and the timing of connection to the ammeter and the discharge device. | 2012-04-26 |
20120100628 | EMISSIVE AND BROADBAND NONLINEAR ABSORBING METAL COMPLEXES AND LIGANDS AS OLED, OPTICAL SWITCHING OR OPTICAL SENSING MATERIALS - Platinum (II) terdentate or bidentate complexes with non-linear optical properties are provided. The complexes have a broadband spectral and temporal response, and strong reverse saturable absorption and two-photon absorption in the visible and the near-IR region. As such, the complexes are useful for organic light-emitting diodes and optical-switching or sensing devices. | 2012-04-26 |
20120100629 | Device For Investigating Chemical Interactions And Process Utilizing Such Device - The invention relates to a device for investigating reactions between interactive species, said device comprising: one or more plasma deposited layers, which layers comprise one or more first pre-selected functional group species, which functional group species are interactible with a pre-selectable second species. | 2012-04-26 |
20120100630 | MIXER WITH ZERO DEAD VOLUME AND METHOD FOR MIXING - The invention relates to a micro fluidics system ( | 2012-04-26 |
20120100631 | BIOSENSOR DEVICE FOR SENSING AMPHIPATHIC ANALYTES - The current invention relates to sensing elements and devices comprising at least one amphipathic lipid-binding protein or fatty acid binding protein, wherein the binding proteins are associated with a luminescent reporter group. The binding proteins and luminescent reporter groups are encapsulated within a hydrogel matrix that comprises at least one co-monomer, wherein the co-monomer is present at a concentration that decreases or inhibits micelle formation of the amphipathic lipid. Binding of the amphipathic lipid or fatty acid to the appropriate binding protein can produce at least one detectable change in the property of the luminescent reporter group. | 2012-04-26 |
20120100632 | MONOCLONAL ANTIBODIES TO HUMAN IMMUNODEFICIENCY VIRUS AND USES THEREOF - The present invention relates to novel monoclonal antibodies which may be used in the detection of Human Immunodeficiency Virus (HIV). These antibodies exhibit an unusually high degree of sensitivity, a remarkably broad range of specificity, and bind to novel shared, non-cross-reactive epitopes. In particular, the monoclonal antibodies of the present invention may be utilized to detect HIV-1 antigen and HIV-2 core antigen in a patient sample. | 2012-04-26 |
20120100633 | CLICK CHEMISTRY ON HETEROGENEOUS CATALYSTS - The present invention relates to new methods and reagents for coupling molecules by a Click reaction using a heterogeneous catalyst system. Further, the present invention refers to novel devices for carrying out Click reactions | 2012-04-26 |
20120100634 | ASSAY SYSTEM FOR DETERMINING BINDING OF HYDROPHOBIC DRUGS - The invention comprises a method for the determination of the binding coefficient of a hydrophobic chemical compound comprising: g. Providing an assay plate with a plurality of rows and columns of test vessels; h. Providing the majority of the test vessels in said assay plate with a polymer, wherein in each row the amount of polymer coating per test vessel is increased; i. Filling each test vessel with a solution of binding partner to which the binding coefficient should be assayed, wherein in each column the amount of binding partner is increased; j. Adding the hydrophobic compound and incubate the plate; k. Determining the concentration of said compound in said polymer or in the solution; l. Calculating the protein binding coefficient of the compound. | 2012-04-26 |
20120100635 | RISK ASSESSMENT FOR ANTIBOTICS TREATMENT IN PATIENTS SUFFERING FROM PRIMARY NON-INFECTIOUS DISEASE BY DETERMINING THE LEVEL OF PROCALCITONIN - The present invention relates to a diagnostic method for the identification of a subject suffering from a primary non-infectious disease having an increased risk of an adverse outcome potentially being induced by the administration of an antibiotic to said subject comprising the determination of the level of Procalcitonin (PCT) or a fragment thereof or a precursor or fragment thereof having a length of at least 12 amino acid residues in a sample of a bodily fluid from said subject and the correlation of the determined level to a potential risk induced by the administration of an antibiotic. | 2012-04-26 |
20120100636 | APPARATUS AND METHOD FOR MEASURING BINDING KINETICS WITH A RESONATING SENSOR - A subject material in a fluid sample is detected using a resonating sensor immersible in the fluid sample. Binding kinetics of an interaction of an analyte material present in the fluid sample are measured with the resonating sensor, which has binding sites for the analyte material. Prior to exposing the resonating sensor to the fluid sample, operation of the resonating sensor is initiated, producing a sensor output signal representing a resonance characteristic of the resonating sensor. Optionally, a reference resonator that lacks binding sites for the analyte is used to produce a reference output signal. Introduction of a fluid sample to the resonating sensor is automatically detected based on a characteristic change in the sensor output signal or a reference output signal. In response to the detecting of the introduction of the fluid sample, automated measurement of the binding kinetics are measured. | 2012-04-26 |
20120100637 | GENETIC MARKERS OF SCHIZOPHRENIA ENDOPHENOTYPES - This document provides methods and materials related to genetic markers of schizophrenia (SZ), schizotypal personality disorder (SPD), and/or schizoaffective disorder (SD), (collectively referred to herein as “schizophrenia spectrum disorders” or SSDs). For example, methods for using such genetic markers to identify an SSD (e.g., SZ) endophenotype are provided. | 2012-04-26 |
20120100638 | Method and Test Strip for Detection of Residues - A method, test strip and method of manufacturing a test strip useful for detecting one or more analytes, such as an antibiotic, in a test sample such as a milk sample. The test strip and method include a labeled specific binder and test capture agent for the specific binder that increases test sensitivity to the analyte for which the specific binder has affinity while decreasing test sensitivity to an analyte for which a multianalyte binder has affinity. | 2012-04-26 |
20120100639 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND MANUFACTURING APPARATUS - A semiconductor device manufacturing method and manufacturing apparatus with which it is possible, when a wafer has a warp, to effectively peel off an ultraviolet peelable tape with ultraviolet irradiation of a short duration. Even when a wafer has a warp, by correcting the warp of the wafer with an ultraviolet transmitting plate, and uniformly irradiating an ultraviolet peelable tape attached to the wafer with ultraviolet light, it is possible to reduce a distance between an ultraviolet light source and the ultraviolet peelable tape. Also, by blocking heat from the ultraviolet light source with the ultraviolet transmitting plate, it is possible to suppress a rise in temperature of the wafer. As a result of this, it is possible to effectively peel the ultraviolet peelable tape from the wafer with ultraviolet irradiation of a short duration without any adhesive residue remaining. | 2012-04-26 |
20120100640 | Systems and methods for forming a time-averaged line image - Systems and methods for forming a time-average line image are disclosed. The method includes forming a line image with a first amount of intensity non-uniformity. The method also includes forming and scanning a secondary image over at least a portion of the line image to form a time-averaged modified line image having a second amount of intensity non-uniformity that is less than the first amount. Wafer emissivity is measured in real time to control the intensity of the secondary image. Temperature is also measured in real time based on the wafer emissivity and reflectivity of the secondary image, and can be used to control the intensity of the secondary image. | 2012-04-26 |
20120100641 | ETCHING APPARATUS AND ETCHING METHOD - According to an embodiment, an etching apparatus includes a reaction chamber, a vacuum pump connected to the reaction chamber through the gate valve, a holding unit which holds a processing subject, an etching gas supply unit, a heating unit, and a sublimation amount determining unit. The etching gas supply unit supplies an etching gas which forms a reaction product by reacting with the processing subject to the reaction chamber. The heating unit heats the processing subject to an equal or higher temperature than temperature at which the reaction product will be sublimated. The sublimation amount determining unit monitors a predetermined physical amount which changes depending on the degree of sublimation of the reaction product during the sublimation process using the heating unit, in which the physical amount is used as a sublimation-amount-dependent change value which changes over time. | 2012-04-26 |
20120100642 | Spectra Based Endpointing for Chemical Mechanical Polishing - A computer implemented method of monitoring a polishing process includes, for each sweep of a plurality of sweeps of an optical sensor across a substrate undergoing polishing, obtaining a plurality of current spectra, each current spectrum of the plurality of current spectra being a spectrum resulting from reflection of white light from the substrate, for each sweep of the plurality of sweeps, determining a difference between each current spectrum and each reference spectrum of a plurality of reference spectra to generate a plurality of differences, for each sweep of the plurality of sweeps, determining a smallest difference of the plurality of differences, thus generating a sequence of smallest difference, and determining a polishing endpoint based on the sequence of smallest differences. | 2012-04-26 |
20120100643 | DAMAGE EVALUATION METHOD OF COMPOUND SEMICONDUCTOR MEMBER, PRODUCTION METHOD OF COMPOUND SEMICONDUCTOR MEMBER, GALLIUM NITRIDE COMPOUND SEMICONDUCTOR MEMBER, AND GALLIUM NITRIDE COMPOUND SEMICONDUCTOR MEMBRANE - A method of evaluating damage of a compound semiconductor member, comprising: a step of performing spectroscopic ellipsometry measurement on a surface of the compound semiconductor member; and a step of evaluating damage on the surface of the compound semiconductor member, using a spectrum in a wavelength band containing a wavelength corresponding to a bandgap of the compound semiconductor member, in a spectrum of an optical constant obtained by the spectroscopic ellipsometry measurement. | 2012-04-26 |
20120100644 | ORGANIC LAYER DEPOSITION APPARATUS, AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY APPARATUS USING THE SAME - An organic layer deposition apparatus including an electrostatic chuck combined with a substrate so as to fixedly support the substrate. The organic layer deposition apparatus including a receiving surface that has a set curvature for receiving the substrate; a deposition source for discharging a deposition material toward the substrate; a deposition source nozzle unit disposed at a side of the deposition source and including a plurality of deposition source nozzles arranged in a first direction; and a patterning slit sheet disposed to face the deposition source nozzle unit, and having a plurality of patterning slits arranged in a second direction perpendicular to the first direction, wherein a cross section of the patterning slit sheet on a plane formed by lines extending in the second direction and a third direction is bent by a set degree, wherein the third direction is perpendicular to the first and second directions. | 2012-04-26 |
20120100645 | METHOD FOR FABRICATING LIGHT EMITTING DEVICE - A method for fabricating a light emitting device is provided. The method comprises forming a light emitting structure comprising a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer and forming a mixed-period photonic crystal structure on the light emitting structure. And the forming of the mixed-period photonic crystal structure includes defining a first photonic crystal structure through a lithography process and a dry etching process, and forming a second photonic crystal structure through a wet etching process. | 2012-04-26 |
20120100646 | METHOD FOR DISTRIBUTING PHOSPHOR PARTICULATES ON LED CHIP - A method for distributing phosphor particulates on an LED chip, includes steps of: providing a substrate having an LED chip mounted thereon; dispensing an adhesive on the chip, wherein the adhesive have positively charged phosphor particulates doped therein; providing an upper mold and a lower mold for producing an electric field through the adhesive and moving the upper mold to press the adhesive, wherein the phosphor particulates are driven by the electric field to move to a top face of the chip; and curing the adhesive and removing the upper mold and the lower mold. | 2012-04-26 |
20120100647 | Method of manufacturing flexible display device - A method of manufacturing a flexible display device is provided. The method includes: preparing a first flexible substrate on which a display unit is formed; forming an encapsulation unit including a base substrate, a second flexible substrate formed on the base substrate, and a barrier layer formed on the second flexible substrate; combining the encapsulation unit with the display unit; and separating the base substrate from the second flexible substrate by using a difference between a coefficient of thermal expansion of the base substrate and a coefficient of thermal expansion of the second flexible substrate, by applying a heated solution between the base substrate and the second flexible substrate. The flexible display device is easily manufactured since the base substrate and the second flexible substrate, which have different coefficients of thermal expansion and are coupled to each other, are separable from each other by applying the heated solution. | 2012-04-26 |
20120100648 | METHOD FOR MANUFACTURING LIGHT EMITTING CHIP - A method for manufacturing light emitting chips includes steps of: providing a substrate having a plurality of separate epitaxy islands thereon, wherein the epitaxy islands are spaced from each other by channels; filling the channels with an insulation material; sequentially forming a reflective layer, a transition layer and a base on the insulation material and the epitaxy islands; removing the substrate and the insulation material to expose the channels; and cutting the reflective layer, the transition layer and the base to form a plurality of individual chips along the channels. | 2012-04-26 |
20120100649 | METHOD FOR MANUFACTURING A FILM STRUCTURE - Provided is a method for manufacturing a film structure. | 2012-04-26 |
20120100650 | VICINAL SEMIPOLAR III-NITRIDE SUBSTRATES TO COMPENSATE TILT OF RELAXED HETERO-EPITAXIAL LAYERS - A method for fabricating a semi-polar III-nitride substrate for semi-polar III-nitride device layers, comprising providing a vicinal surface of the III-nitride substrate, so that growth of relaxed heteroepitaxial III-nitride device layers on the vicinal surface compensates for epilayer tilt of the III-nitride device layers caused by one or more misfit dislocations at one or more heterointerfaces between the device layers. | 2012-04-26 |
20120100651 | METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY APPARATUS USING THE SAME - A method of manufacturing an organic light emitting device that readily increases the characteristics of an intermediate layer having an organic light emitting layer, and a method of manufacturing an organic light emitting display apparatus. The method of manufacturing an organic light emitting device includes preparing a substrate having a first electrode; disposing the substrate on a base member; disposing a donor film that covers the substrate and contacts the base member exposed around the substrate; combining the base member and the donor film; forming an intermediate layer having an organic light emitting layer on the first electrode by performing a transfer process in a laser thermal transfer apparatus after placing the base member and the donor film combined with each other with the substrate interposed therebetween in the laser thermal transfer apparatus; and forming a second electrode on the intermediate layer. | 2012-04-26 |
20120100652 | FABRICATION METHOD OF ACTIVE DEVICE ARRAY SUBSTRATE - A fabrication method of an active device array substrate is disclosed. A first metal material layer, a gate insulation material layer, a channel material layer, a second metal material layer, and a first photoresist layer are formed over a substrate sequentially. The first photoresist layer is patterned with a multi-tone mask to form a first patterned photoresist layer with two thicknesses. A first and second removing processes are performed sequentially using the first patterned photoresist layer as a mask to form a gate, a gate insulation layer, a channel layer, and a source/drain. The first patterned photoresist layer is removed. A passivation layer and a second patterned photoresist layer are formed over the substrate. A third removing process is performed to form a plurality of contact holes. A pixel electrode material layer is formed over the substrate. The second patterned photoresist layer is lifted off to form a pixel electrode. | 2012-04-26 |
20120100653 | METHODS OF MANUFACTURING MASTER, PIXEL ARRAY SUBSTRATE AND ELECTRO-OPTICAL DEVICE - A master having a substrate including displaying units and an ESD protection structure including an adjacent first region and a second region is provided. The displaying units have a predetermined-cutting region therebetween. Each displaying unit includes a peripheral circuit region and a display region having pixels. The ESD protection structure disposed on the predetermined-cutting region, located in the peripheral circuit region, and connecting the display region includes a first patterned conductive layer disposed on the first region and having an end away from the predetermined-cutting region, a first patterned dielectric layer disposed on the first patterned conductive layer and the substrate and having a first opening exposing a portion of the first patterned conductive layer, a patterned transparent conductive layer disposed corresponding to the predetermined-cutting region and connecting the first patterned conductive layer, and a second patterned dielectric layer covering the patterned transparent conductive layer and the substrate. | 2012-04-26 |
20120100654 | GROUP-III NITRIDE SEMICONDUCTOR LASER DEVICE, AND METHOD OF FABRICATING GROUP-III NITRIDE SEMICONDUCTOR LASER DEVICE - A method of fabricating a III-nitride semiconductor laser device includes: preparing a substrate having a hexagonal III-nitride semiconductor and having a semipolar primary surface; forming a substrate product having a laser structure, an anode electrode and a cathode electrode, the laser structure including a substrate and a semiconductor region formed on the semipolar primary surface; scribing a first surface of the substrate product in part in a direction of the a-axis of the hexagonal III-nitride semiconductor; and carrying out breakup of the substrate product by press against a second surface of the substrate product, to form another substrate product and a laser bar. | 2012-04-26 |
20120100655 | ORGANIC EL DEVICE - According to one embodiment, a method of manufacturing an organic EL device includes providing a structure including a substrate and an electrode positioned above the substrate, and forming an organic layer including a mixture of first and second organic materials above the electrode. The first organic material has a first sublimation point. The second organic material has a second sublimation point higher than the first sublimation point. The formation of the organic layer includes heating an evaporation material including a mixture of the first and second organic materials to an evaporation temperature so as to sublimate the first and second organic materials, and delivering the sublimed first and second organic materials toward the electrode to deposit a mixture including the first and second organic materials above the electrode. The evaporation temperature is, for example, a temperature higher than the second sublimation temperature by 50° C. or more. | 2012-04-26 |
20120100656 | METHOD FOR MAKING A SOLID STATE SEMICONDUCTOR DEVICE - A method for making a solid state semiconductor device includes: providing a substrate; forming a buffer layer on the substrate; forming a first epitaxial layer on the buffer layer; forming a surface-textured second epitaxial layer on the first epitaxial layer by chemical vapor deposition; and forming a solid state stacked layer structure having a PN-junction type light-emitting part on a textured surface of the second epitaxial layer. | 2012-04-26 |
20120100657 | SIMPLIFIED COPPER-COPPER BONDING - A method for bonding a first copper element onto a second copper element including forming a crystalline copper layer enriched in oxygen on each of surfaces of each of the first and second elements through which the elements will be in contact, the total thickness of both layers being less than 6 nm, which includes: a) polishing the surfaces so as to obtain a roughness of less than 1 nm RMS, and hydrophilic surfaces, b) cleaning the surfaces to suppress presence of particles due to the polishing and the major portion of corrosion inhibitors, and c) putting both crystalline copper layer enriched in oxygen in contact with each other. | 2012-04-26 |
20120100658 | METHOD OF FORMING SEMICONDUCTOR DEVICE - Provided is a method of forming a semiconductor device. The method includes forming an insulating film on a semiconductor substrate, a conductive film on the insulating film, and a first structure and a second structure on the conductive film. The semiconductor substrate has first and second regions. The first and second structures are formed on the first and second regions, respectively. An impurity diffused region is formed in the semiconductor substrate using the first structure as a mask. The impurity diffused region overlaps the first structure. A portion of the first structure, and the conductive film are etched to respectively form a gate structure and a capacitor structure on the first and second regions. | 2012-04-26 |
20120100659 | METHOD FOR MANUFACTURING SOLID-STATE IMAGE SENSOR - A method for manufacturing a solid-state image sensor includes forming a gate electrode structure including a gate electrode on a gate insulating film formed on a semiconductor substrate, and implanting ions into a first region and simultaneously implanting the ions into a second region of the semiconductor substrate via the gate electrode structure and the gate insulating film, wherein the first region is a region where a charge accumulation region is to be formed, and the second region is a region where an extended region that extends from the charge accumulation region to a portion below the gate electrode is to be formed, and a mean projected range of the ions in the step of simultaneous implanting of the ions into the first region and the second region is larger than a sum total of thicknesses of the gate electrode and the gate insulating film. | 2012-04-26 |
20120100660 | METHOD FOR PREPARATION OF METAL CHALCOGENIDE SOLAR CELLS ON COMPLEXLY SHAPED SURFACES - Methods for fabricating a photovoltaic device on complexly shaped fabricated objects, such as car bodies are disclosed. Preferably the photovoltaic device includes absorber layers comprising Copper, Indium, Gallium, Selenide (CIGS) or Copper, Zinc, Tin, Sulfide (CZTS). The method includes the following steps: a colloidal suspension of metal surface-charged nanoparticles is formed; electrophoretic deposition is used to deposit the nanopartieles in a metal thin film onto a complexly shaped surface of the substrate; the metal thin film is heated in the presence of a chalcogen source to convert the metal thin film into a metal chalcogenide thin film layer; a buffer layer is formed on the metal chalcogenide thin film layer using a chemical bath deposition; an intrinsic zinc oxide insulating layer is formed adjacent to a side of the buffer layer, opposite the metal chalcogenide thin film layer, by chemical vapor deposition; and finally, a transparent conducting oxide is formed adjacent to a side of the intrinsic zinc oxide, opposite the buffer layer, by chemical vapor deposition. | 2012-04-26 |
20120100661 | INK FOR FORMING THIN FILM OF SOLAR CELLS AND METHOD FOR PREPARING THE SAME, CIGS THIN FILM SOLAR CELL USING THE SAME AND MANUFACTURING METHOD THEREOF - Discussed are an ink containing nanoparticles for formation of thin film of a solar cell and its preparation method, CIGS thin film solar cell having at least one light absorption layer formed by coating or printing the above ink containing nanoparticles on a rear electrode, and a process for manufacturing the same. More particularly, the above absorption layer includes Cu, In, Ga and Se elements as constitutional ingredients thereof and such elements exist in the light absorption layer by coating or printing an ink that contains Cu | 2012-04-26 |
20120100662 | METHOD OF MANUFACTURING SOLID-STATE IMAGE SENSOR - A method of manufacturing a solid-state image sensor, includes forming a color-filter layer including a plurality of color filters on a wiring structure arranged on a semiconductor substrate on which a plurality of photoelectric converters are formed, forming a photosensitive microlens material layer on the color-filter layer, and forming microlenses by forming a latent image on the microlens material layer by exposing the microlens material layer using a photomask having a transmitted light distribution corresponding to a density of light-shielding portions each having a size smaller than a resolution limit of an exposure apparatus, and developing the microlens material layer, wherein the color-filter layer has a surface step, and the microlens material layer has a surface step corresponding to the surface step of the color-filter layer. | 2012-04-26 |
20120100663 | Fabrication of CuZnSn(S,Se) Thin Film Solar Cell with Valve Controlled S and Se - Techniques for fabricating thin film solar cells are provided. In one aspect, a method of fabricating a solar cell includes the following steps. A molybdenum (Mo)-coated substrate is provided. Absorber layer constituent components, two of which are sulfur (S) and selenium (Se), are deposited on the Mo-coated substrate. The S and Se are deposited on the Mo-coated substrate using thermal evaporation in a vapor chamber. Controlled amounts of the S and Se are introduced into the vapor chamber to regulate a ratio of the S and Se provided for deposition. The constituent components are annealed to form an absorber layer on the Mo-coated substrate. A buffer layer is formed on the absorber layer. A transparent conductive electrode is formed on the buffer layer. | 2012-04-26 |
20120100664 | FABRICATING KESTERITE SOLAR CELLS AND PARTS THEREOF - A Kesterite film is vacuum deposited and annealed on a substrate. Deposition is conducted at low temperature to provide good composition control and efficient use of metals. Annealing is conducted at a high temperature for a short period of time. Thermal evaporation, E-beam evaporation or sputtering in a high vacuum environment may be employed as part of a deposition process. | 2012-04-26 |
20120100665 | METHOD FOR MANUFACTURING SILICON THIN-FILM SOLAR CELLS - The present invention relates to a method for manufacturing silicon thin-film solar cells, including: providing a substrate; forming a first electrode on the substrate; forming a first doped semiconductor layer on the first electrode by chemical vapor deposition; forming an intrinsic layer on the first doped semiconductor layer by chemical vapor deposition, where the intrinsic layer includes a plurality of amorphous/nanocrystalline silicon layers, and the intrinsic layer has various energy bandgaps formed by varying average grain sizes of the amorphous/nanocrystalline silicon layers; forming a second doped semiconductor layer on the intrinsic layer by chemical vapor deposition, where one of the first doped semiconductor layer and the second doped semiconductor layer is a p-type amorphous silicon layer and the other is an n-type amorphous/nano-microcrystalline silicon layer; and forming a second electrode on the second doped semiconductor layer. Accordingly, the present invention can achieve broadband absorption in a single junction structure. | 2012-04-26 |
20120100666 | PHOTOLUMINESCENCE IMAGE FOR ALIGNMENT OF SELECTIVE-EMITTER DIFFUSIONS - Embodiments of the invention generally provide a solar cell formation process that includes the formation of metal contacts over heavily doped regions that are formed in a desired pattern on a surface of a substrate. Embodiments of the invention also provide an inspection system and supporting hardware that is used to reliably position a similarly shaped, or patterned, metal contact structure on the patterned heavily doped regions to allow an Ohmic contact to be made. The metal contact structure, such as fingers and busbars, are formed on the heavily doped regions so that a high quality electrical connection can be formed between these two regions. | 2012-04-26 |
20120100667 | ORGANIC SEMICONDUCTOR INK COMPOSITION AND METHOD FOR FORMING ORGANIC SEMICONDUCTOR PATTERN USING THE SAME - Provided is an ink that is the most suitable for a method for forming an organic transistor by transferring a pattern using a liquid-repellent transfer substrate, for example, a microcontact printing method or a reverse printing method. Specifically, provided is an organic semiconductor ink composition which can provide a uniform ink coating film on a surface of a liquid-repellent transfer substrate and which can provide a dry ink film or a semi-dry ink film capable of being easily transferred from the transfer substrate to a transfer-receiving base material. Also provided is a method for forming an organic semiconductor pattern of an organic transistor, the method using the organic semiconductor ink composition. The organic semiconductor ink composition used for obtaining a desired pattern by transferring an ink layer formed on a liquid-repellent transfer substrate to a printing base material contains an organic semiconductor, an organic solvent, and a fluorine-based surfactant. | 2012-04-26 |
20120100668 | METHOD OF MANUFACTURING A FLIP CHIP PACKAGE AND APPARATUS TO ATTACH A SEMICONDUCTOR CHIP USED IN THE METHOD - A method and apparatus to manufacture a flip chip package includes dotting a flux on a first preliminary bump of a package substrate, attaching a preliminary bump of a first semiconductor chip to the first preliminary bump of the package substrate via the flux, dotting a flux on a second preliminary bump of the package substrate, and attaching a preliminary bump of a second semiconductor chip to the second preliminary bump of the package substrate via the flux. Accordingly, an evaporation of the flux on the preliminary bump of the package substrate may be suppressed. | 2012-04-26 |
20120100669 | METHOD OF MANUFACTURING TMV PACKAGE-ON-PACKAGE DEVICE - A method of manufacturing a Through Mold Via (TMV) package-on-package device while preventing a bad solder joint from occurring in the TMV package-on-package device is provided. The method includes coating exposed portions of a lower semiconductor package with an organic soldering preservative, and stacking a top semiconductor package on the lower semiconductor package and connecting lower solder balls of the top semiconductor package with the top solder balls of the lower semiconductor package. According to the method, a bad solder joint may be prevented from occurring when a top semiconductor package is bonded to a lower semiconductor package. | 2012-04-26 |
20120100670 | WAFER LEVEL BUCK CONVERTER - A buck converter module includes a high side (HS) die having source, drain, and gate bonding pads on a front side of the HS die, a low side (LS) die having a first section thereof with a plurality of through silicon vias (TSVs) extending from a back side to a front side of the LS die, the LS die having source, drain, and gate bonding pads located on a front side of a second section separate from the first section, the drain bonding pad electrically connected to the back side of the LS die in the second section. The HS die and the LS die are bonded together such that the source bonding pad of the HS die is electrically connected to the back side of the LS die, and each of the drain and gate bonding pads are electrically connected to separate TSVs in the LS die. | 2012-04-26 |
20120100671 | Semiconductor Package And Method Of Manufacturing The Same - A semiconductor package includes a circuit substrate, a semiconductor chip on the circuit substrate, an inner solder ball between the circuit substrate and the semiconductor chip, and dummy solder filling a dummy opening in at least one of an substrate insulation layer of the circuit substrate and a chip insulation layer. The dummy solder does not electrically connect the semiconductor chip with the substrate. The circuit substrate may include a base substrate, a substrate connection terminal on the base substrate, and the substrate insulation layer covering the base substrate. The semiconductor chip may include a chip connection terminal and the chip insulation layer exposing the chip connection terminal. The inner solder ball may be interposed between the substrate connection terminal and the chip connection terminal to electrically connect the circuit substrate to the semiconductor chip. | 2012-04-26 |
20120100672 | METHODS AND APPARATUS FOR A STACKED-DIE INTERPOSER - An improved stacked-die package includes an interposer which improves the manufacturability of the package. A semiconductor package includes a package substrate having a plurality of bond pads; a first semiconductor device mounted on the package substrate, the first semiconductor device having a plurality of bond pads provided thereon; an interposer mounted on the first semiconductor device, the interposer having a first interposer bond pad and a second interposer bond pad, wherein the first and second interposer bond pads are electrically coupled; a second semiconductor device mounted on the interposer, the second semiconductor device having a plurality of bond pads provided thereon; a first bond wire connected to one of the plurality of bond pads on said first semiconductor and to the first interposer bond pad; and a second bond wire connected to the second interposer bond pad and to one of the plurality of bond pads on the semiconductor device. | 2012-04-26 |
20120100673 | Cross OD FinFET Patterning - A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening. | 2012-04-26 |
20120100674 | SEMICONDUCTOR STRUCTURE AND METHODS OF MANUFACTURE - FinFET end-implanted-semiconductor structures and methods of manufacture are disclosed herein. The method includes forming at least one mandrel on a silicon layer of a substrate comprising an underlying insulator layer. The method further includes etching the silicon layer to form at least one silicon island under the at least one mandrel. The method further includes ion-implanting sidewalls of the at least one silicon island to form doped regions on the sidewalls. The method further includes forming a dielectric layer on the substrate, a top surface of which is planarized to be coplanar with a top surface of the at least one mandrel. The method further includes removing the at least one mandrel to form an opening in the dielectric layer. The method further includes etching the at least one silicon island to form at least one fin island having doped source and drain regions. | 2012-04-26 |
20120100675 | MANUFACTURING METHOD OF MICROCRYSTALLINE SILICON FILM AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a manufacturing method of a microcrystalline silicon film having both high crystallinity and high film density. In the manufacturing method of a microcrystalline silicon film according to the present invention, a first microcrystalline silicon film that includes mixed phase grains is formed over an insulating film under a first condition, and a second microcrystalline silicon film is formed thereover under a second condition. The first condition and the second condition are a condition in which a deposition gas containing silicon and a gas containing hydrogen are used as a first source gas and a second source gas. The first source gas is supplied under the first condition in such a manner that supply of a first gas and supply of a second gas are alternately performed. | 2012-04-26 |
20120100676 | Thin Film Transistor Substrate of Horizontal Electric Field Type Liquid Crystal Display Device and Fabricating Method Thereof - A thin film transistor substrate of horizontal electric field type liquid crystal display device includes: a gate line and a common line arranged in parallel on a substrate; a data line crossing the gate line and the common line to define a pixel area; a thin film transistor having a gate connected to the gate line and a source electrode connected to the data line; a common electrode extending from the common line into the pixel area; a protective film for covering a plurality of signal lines and electrodes and the thin film transistor; a pixel hole in the protective film having an elongated shape that parallels the common electrode; and a pixel electrode connected to a side surface of a drain electrode of the thin film transistor within the pixel hole. | 2012-04-26 |
20120100677 | METHOD FOR MANUFACTURING MICROCRYSTALLINE SEMICONDUCTOR AND THIN FILM TRANSISTOR - A technique for manufacturing a microcrystalline semiconductor layer with high mass productivity is provided. In a reaction chamber of a plasma CVD apparatus, an upper electrode and a lower electrode are provided in almost parallel to each other. A hollow portion is formed in the upper electrode, and the upper electrode includes a shower plate having a plurality of holes formed on a surface of the upper electrode which faces the lower electrode. A substrate is provided over the lower electrode. A gas containing a deposition gas and hydrogen is supplied to the reaction chamber from the shower plate through the hollow portion of the upper electrode, and a rare gas is supplied to the reaction chamber from a portion different from the upper electrode. Accordingly, high-frequency power is supplied to the upper electrode to generate plasma, so that a microcrystalline semiconductor layer is formed over the substrate. | 2012-04-26 |
20120100678 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes the following processes. A first interlayer insulating film is formed over a cell transistor and a peripheral transistor. A cell contact hole is formed in the first interlayer insulating film, the cell contact hole reaching the cell transistor. A lower contact plug is formed at a bottom of the cell contact hole. A peripheral contact hole is formed in the first interlayer insulating film, the peripheral contact hole reaching the peripheral transistor. A first peripheral contact plug is simultaneously formed in the peripheral contact hole and an upper contact plug in the cell contact hole, the upper contact plug being disposed on the lower contact plug. | 2012-04-26 |
20120100679 | THICK GATE OXIDE FOR LDMOS AND DEMOS - A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage transistors, replacing the dummy oxide in the low voltage transistor area with a thinner gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor. A process of forming an integrated circuit, including forming a dummy oxide layer for ion implanting low voltage and intermediate voltage transistors, replacing the dummy oxide in the low voltage transistors with a thinner gate dielectric layer, replacing the dummy oxide in the intermediate voltage transistor with another gate dielectric layer, and retaining the dummy oxide for a gate dielectric for a DEMOS or LDMOS transistor. | 2012-04-26 |
20120100680 | Low Temperature Implant Scheme to Improve BJT Current Gain - A process of forming an integrated circuit containing an npn BJT and an NMOS transistor by cooling the integrated circuit substrate to 5° C. or colder and concurrently implanting n-type dopants, at a specified minimum dose according to species, into the emitter region of the BJT and the source and drain regions of the NMOS transistor. A process of forming an integrated circuit containing a pnp BJT and a PMOS transistor by cooling the integrated circuit substrate to 5° C. or colder and concurrently implanting p-type dopants, at a specified minimum dose according to species, into the emitter region of the BJT and the source and drain regions of the PMOS transistor. A process of forming an integrated circuit containing an implant region by cooling the integrated circuit substrate to 5° C. or colder and implanting atoms, at a specified minimum dose according to species, into the implant region. | 2012-04-26 |
20120100681 | METHOD OF MANUFACTURING SOURCE/DRAIN STRUCTURES - An integrated circuit device and method for manufacturing the integrated circuit device provide improved control over a shape of a trench for forming the source and drain features of integrated circuit device, by forming a second doped region in a first doped region and removing the first and the second doped regions by a first and a second wet etching processes. | 2012-04-26 |
20120100682 | Manufactruing method of semiconductor device having vertical type transistor - A manufacturing method of a semiconductor device includes the steps of: forming an insulating pillar on the main surface of a silicon substrate; forming a protective film on the side surface of the insulating pillar; forming a silicon pillar on the main surface of the silicon substrate; forming a gate insulating film on the side surface of the silicon pillar; and forming first and second gate electrodes so as to contact each other and so as to cover the side surfaces of the silicon pillar and insulating pillar, respectively. According to the present manufacturing method, the protective film is formed on the side surface of the insulating pillar as a dummy pillar, thus preventing the dummy pillar from being eroded when the silicon pillar for channel is processed into a transistor. Therefore, it is possible to reduce a probability of occurrence of gate electrode disconnection. | 2012-04-26 |
20120100683 | TRENCH-TYPED POWER MOS TRANSISTOR AND METHOD FOR MAKING THE SAME - A trench-typed power MOS transistor comprises a trench-typed gate area, which includes a gate conductor and an isolation layer. A thin sidewall region of the isolation layer is formed between the gate conductor and a well region. A thick sidewall region of the isolation layer is formed between the gate conductor and a double diffusion region. A thick bottom region of the isolation layer is formed between the gate conductor and a deep well region. | 2012-04-26 |
20120100684 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes sequentially forming a first gate insulating layer and a second gate insulating layer on a substrate, implanting impurity ions into the substrate and performing a first thermal process for activating the impurity ions to form a source and drain region, and forming a third gate insulating layer on the substrate after the first thermal process has been completed. | 2012-04-26 |
20120100685 | LOCALIZED IMPLANT INTO ACTIVE REGION FOR ENHANCED STRESS - Methods for enhancing strain in an integrated circuit are provided. Embodiments of the invention include using a localized implant into an active region prior to a gate etch. In another embodiment, source/drain regions adjacent to the gates are recessed to allow the strain to expand to full potential. New source/drain regions are allowed to grow back to maximize stress in the active region. | 2012-04-26 |
20120100686 | METHOD OF FORMING ULTRA-SHALLOW JUNCTIONS IN SEMICONDUCTOR DEVICES - A method of forming ultra-shallow lightly doped source/drain (LDD) regions of a CMOS transistor in a surface of a substrate includes the steps of providing a semiconductor substrate, providing a gate stack on the semiconductor substrate, performing a low temperature pocket implantation process on the substrate, performing a low temperature co-implanted ion implantation process on the substrate, and/or performing a low temperature lightly doped source/drain implantation process on the substrate. | 2012-04-26 |
20120100687 | METHODS FOR FABRICATING CAPACITOR AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICE INCLUDING THE CAPACITOR - Example embodiments relate to methods for fabricating a capacitor and methods for fabricating a semiconductor device including the capacitor. The methods for fabricating a capacitor may include forming a preliminary lower electrode with a first area on a substrate; implanting ions in the preliminary lower electrode to form a lower electrode with a second area that is larger or substantially larger than the first area; and forming a dielectric layer and an upper electrode on the lower electrode. | 2012-04-26 |
20120100688 | Self-Aligned Electrode Phase Change Memory - A phase change memory may be formed with an upper electrode self-aligned to a phase change memory element. In some embodiments, patterning techniques may be used to form the elements of the memory. The memory element may be formed as a sidewall spacer formed on both opposed sides of an elongate strip of material. The resulting elongate strip of phase change memory element material may then be singulated in the same etching step that forms the upper electrodes extending in the column direction. Thus, the memory elements may be singulated in the row direction, while, at the same time, the top electrodes are defined to extend continuously in the column direction. | 2012-04-26 |
20120100689 | MIM CAPACITOR AND ASSOCIATED PRODUCTION METHOD - An MIM capacitor includes a first capacitor electrode, which is formed in the surface of a first intermediate dielectric, a second intermediate dielectric, which is formed on the first intermediate dielectric and has an opening that exposes the first capacitor electrode, and a first electrically conducting diffusion barrier layer, which is formed on the surface of the exposed first capacitor electrode. On the diffusion barrier layer and on the side walls of the opening there is also formed a capacitor dielectric and a second capacitor electrode on top. | 2012-04-26 |
20120100690 | METHOD FOR MANUFACTURING A HETEROSTRUCTURE AIMING AT REDUCING THE TENSILE STRESS CONDITION OF THE DONOR SUBSTRATE - A method for manufacturing a heterostructure for applications in the fields of electronics, photovoltaics, optics or optoelectronics, by implanting atomic species in a donor substrate so as to form an embrittlement area therein, assembling a receiver substrate on the donor substrate, wherein the receiver substrate has a larger thermal expansion coefficient than that of the donor substrate, detaching a rear portion of the donor substrate along the embrittlement area so as to transfer a thin layer of interest of the donor substrate onto the receiver substrate, and applying a detachment annealing after assembling and but before detaching, in order to facilitate the detaching. The detachment annealing includes the simultaneous application of a first temperature to the donor substrate and a second temperature different from the first to the receiver substrate; with the first and second temperatures being selected to reduce the tensile stress condition of the donor substrate. | 2012-04-26 |
20120100691 | PROCESSES FOR FABRICATING HETEROSTRUCTURES - The invention relates to a process for fabricating a heterostructure. This process comprises heating an intermediate heterostructure. The intermediate heterostructure comprises a crystalline strain relaxation layer interposed directly between a first substrate and a strained layer of crystalline semiconductor material. The process further comprises causing plastic deformation of the crystalline strain relaxation layer and elastic deformation of the strained layer of crystalline semiconductor material to at least partially relax the strained layer of crystalline semiconductor material. | 2012-04-26 |
20120100692 | METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES AND DEVICES WITH STRAINED SEMICONDUCTOR MATERIAL - Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material. | 2012-04-26 |
20120100693 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device formed by fractionization and division after a plurality of semiconductor elements are formed over a semiconductor substrate, includes forming a first resist portion over the semiconductor substrate prior to its fractionization. Trenches are formed in areas for dicing the semiconductor substrate. A second resin portion different in composition from the first resin portion is formed in each of the trenches. The semiconductor substrate is diced with respect to the second resin portion with widths each narrower than the trench thereby to bring the semiconductor device into fractionization and division. | 2012-04-26 |
20120100694 | DIVIDING METHOD FOR WAFER HAVING DIE BONDING FILM ATTACHED TO THE BACK SIDE THEREOF - A wafer is divided into individual devices along division lines formed on the front side of the wafer. The devices are respectively formed in a plurality of regions partitioned by the division lines. A protective member is provided on the front of the wafer, and the back of the wafer is ground to a predetermined thickness. A laser beam is applied to the wafer from the back side of the wafer along the division lines with the focal point of the laser beam set inside the wafer at a position corresponding to each division line, thereby forming a plurality of modified layers inside the wafer along the division lines. The wafer is divided along the modified layers into the individual devices, and the back side of the wafer is ground to remove the modified layers and reduce the thickness of each device to the finished thickness. | 2012-04-26 |
20120100695 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device according to one embodiment includes attaching a front-side protecting member to a first main surface of a semiconductor wafer having an element region formed therein; laser-dicing the semiconductor wafer by applying a laser beam from a second main surface opposite to the first main surface of the semiconductor wafer; forming a backside metal film on the second main surface of the semiconductor wafer; and pressing a spherical surface against the front-side protecting member to expand the front-side protecting member and form individually divided semiconductor chips having the backside metal film attached thereto. | 2012-04-26 |
20120100696 | WORKPIECE DIVIDING METHOD - A workpiece has a substrate and a film formed on the front side of the substrate. A first laser beam applied to the film from the front side of the workpiece along streets formed on the film, thereby forming a plurality of laser processed grooves along the streets. An adhesive tape is attached to the front side of the workpiece. Thereafter, a second laser beam is applied to the substrate from the back side of the workpiece along the streets, with the focal point of the second laser beam set inside the substrate, forming a plurality of modified layers along the streets. Thereafter, the adhesive tape is expanded to divide the substrate along the streets, thereby obtaining a plurality of individual devices. The back side of the substrate of each device is then ground to remove the modified layers and reduce the thickness of each device to a predetermined thickness. | 2012-04-26 |
20120100697 | FILM FOR SEMICONDUCTOR AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A film for semiconductor includes a support film, a second adhesive layer, a first adhesive layer and a bonding layer which are laminated together in this order. This film for semiconductor is configured so that it supports a semiconductor wafer laminated on the bonding layer thereof when the semiconductor wafer is diced and the bonding layer is selectively peeled off from the first adhesive layer when the diced semiconductor wafer (semiconductor element) is picked up. This film for semiconductor is characterized in that when the semiconductor wafer is laminated thereon and diced, and then adhesive strength of the obtained semiconductor element is measured, a ratio of “a (N/cm)” which is adhesive strength of an edge portion of the semiconductor element to “b (N/cm)” which is adhesive strength of a portion of the semiconductor element other than the edge portion thereof (that is, a/b) is in the range of 1 to 4. By optimizing the a/b, it is possible to reliably suppress defects such as breakage and crack which would be generated in the semiconductor element due to local impartation of a large load thereto when being picked up. | 2012-04-26 |
20120100698 | METHOD FOR FORMING AN ALUMINUM NITRIDE THIN FILM - The method is adapted for forming an aluminum nitride thin film having a high density and a high resistance to thermal shock by a chemical vapor deposition process and includes steps of mixing a gas containing aluminum atoms (Al) and a gas containing nitrogen atoms (N) with a gas containing oxygen atoms (O) and feeding the mixture to a member to be covered by an aluminum nitride thin film. | 2012-04-26 |
20120100699 | METHODS OF MAKING QUANTUM DOT FILMS - In an example embodiment, an optical device includes an integrated circuit, an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region. In another example embodiment, a method of forming a nanocrystalline film includes fabricating nanocrystals having a plurality of first ligands attached to their outer surfaces, exchanging the first ligands for second ligands of a different chemical composition, forming a film of the ligand-exchanged nanocrystals, removing the second ligands, and fusing the cores of adjacent nanocrystals in the film to form an electrical network of fused nanocrystals. In another example embodiment, a film includes a network of fused nanocrystals with at least portions of the fused nanocrystals being in direct physical contact with adjacent nanocrystals, the film having substantially no defect states in regions where cores of the nanocrystals are fused. | 2012-04-26 |
20120100700 | METHOD FOR FABRICATING NON-VOLATILE MEMORY DEVICE - A method for fabricating a non-volatile memory device includes repeatedly stacking interlayer dielectric layers and gate conductive layers on a substrate; etching the interlayer dielectric layers and the gate conductive layers to form cell channel holes that expose the substrate, forming a protective layer along a resultant structure, forming a capping layer on the protective layer to fill the cell channel holes, planarizing the protective layer and the capping layer until an uppermost one of the interlayer dielectric layers is exposed, forming a gate conductive layer for select transistors and an interlayer dielectric layer for select transistors on a resultant structure, etching the interlayer dielectric layer and the gate conductive layer, to form select transistor channel holes that expose the capping layer while removing the capping layer buried in the cell channel holes, and removing the protective layer. | 2012-04-26 |
20120100701 | METHOD FOR CLEANING SILICON WAFER, AND METHOD FOR PRODUCING EPITAXIAL WAFER USING THE CLEANING METHOD - A silicon wafer after being subjected to mirror polishing but before being subjected to form an epitaxial layer thereon is subjected to an ozone gas treatment that oxidizes a surface of the silicon wafer by use of ozone gas, a hydrofluoric acid gas treatment that dissolves and removes the oxidized surface of the silicon wafer by use of hydrofluoric acid gas, and a washing treatment that removes foreign substances remaining on the surface of the silicon wafer, whereby PIDs (Polishing Induced Defects) generated by the mirror polishing are forcedly oxidized, dissolved and removed. By performing epitaxial treatment thereafter, PID-induced convex defects can be prevented from generating on the surface of the epitaxial wafer. | 2012-04-26 |
20120100702 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method for forming a semiconductor device includes the following processes. A first well including a memory cell region of a semiconductor substrate is formed. A second well including a first peripheral circuit region of the semiconductor substrate is formed after forming the first well. | 2012-04-26 |
20120100703 | ION IMPLANTATION SYSTEM AND ION IMPLANTATION METHOD USING THE SAME - According to the present invention, an ion implantation system capable of implanting ions into a large substrate and reducing a manufacturing cost, and an ion implantation method using the same may be provided. The ion implantation system includes a plurality of ion implantation assemblies arranged in a line, each ion implantation assembly to implant ions into a partial region of the substrate. This allows for a compact ion implantation system to implant ions into a very large substrate. The substrate moves through the ion implantation system in a first direction, turns around, and then moves back through the ion implantation system in a second and opposite direction, where ions are implanted into the substrate while the substrate is moving to in both directions. The path in the first direction can be spaced-apart from the path in the second direction to allow for two substrates to be processed simultaneously. | 2012-04-26 |
20120100704 | SEMICONDUCTOR DEVICE WITH VERTICAL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device with a vertical transistor includes a plurality of active pillars; a plurality of vertical gates surrounding sidewalls of the active pillars; a plurality of word lines having exposed sidewalls whose surfaces are higher than the active pillars and connecting the adjacent vertical gates together; and a plurality of spacers surrounding the exposed sidewalls of the word lines over the vertical gates. | 2012-04-26 |
20120100705 | METHOD FOR FORMING MEMORY CELL TRANSISTOR - A method for forming a memory cell transistor is disclosed which includes providing a substrate, forming a trench structure in the substrate, depositing a conductive substance on the surface of the substrate to form a conductive member inside the trench structure, forming one or more dielectric layers on the surface of the substrate, forming one or more first conductive layers on top of the dielectric layers, and etching the first conductive layers and the dielectric layers to form a hole structure extending through the first conductive and the dielectric layers, reaching to the substrate surface. One or more second conductive layers may be formed on top of the first conductive layers, with the second conductive layer material filling the hole structure. | 2012-04-26 |
20120100706 | Microelectronic Fabrication Methods Using Composite Layers for Double Patterning - Some embodiments provide microelectronic fabrication methods in which a sacrificial pattern is formed on a substrate. A spacer formation layer is formed on the substrate, the spacer formation layer covering the sacrificial pattern. The spacer formation layer is etched to expose an upper surface of the sacrificial pattern and to leave at least one spacer on at least one sidewall of the sacrificial pattern. A first portion of the sacrificial pattern having a first width is removed while leaving intact a second portion of the sacrificial pattern having a second width greater than the first width to thereby form a composite mask pattern including the at least one spacer and a portion of the sacrificial layer. An underlying portion of the substrate is etched using the composite mask pattern as an etching mask. | 2012-04-26 |
20120100707 | METHOD FOR FABRICATING NON-VOLATILE MEMORY DEVICE WITH THREE-DIMENSIONAL STRUCTURE - A method for fabricating a non-volatile memory device with a three-dimensional structure includes forming a pipe gate conductive layer on a substrate, forming a pipe channel hole in the pipe gate conductive layer, burying a first sacrificial layer in the pipe channel hole, stacking interlayer dielectric layers and gate conductive layers on the pipe gate conductive layer including the first sacrificial layer, forming a pair of cell channel holes in the interlayer dielectric layers and the gate conductive layers, forming a second sacrificial layer on a resultant structure including the pair of cell channel holes, and forming a third sacrificial layer with etching selectivity relative to the second sacrificial layer on the second sacrificial layer and filling the cell channel holes with the third sacrificial layer. | 2012-04-26 |
20120100708 | Methods of Forming Integrated Circuit Devices Having Anisotropically-Oxidized Nitride Layers - Methods of forming integrated circuit devices include forming a gate electrode on a substrate and forming a nitride layer on a sidewall and upper surface of the gate electrode. The nitride layer is then anisotropically oxidized under conditions that cause a first portion of the nitride layer extending on the upper surface of the gate electrode to be more heavily oxidized relative to a second portion of the nitride layer extending on the sidewall of the gate electrode. A ratio of a thickness of an oxidized first portion of the nitride layer relative to a thickness of an oxidized second portion of the nitride layer may be in a range from about 3:1 to about 7:1. | 2012-04-26 |
20120100709 | PLATING APPARATUS AND PLATING METHOD - A plating apparatus allows a substrate holder to be serviced easily while ensuring easy access to the substrate holder and while a substrate is being processed in the plating apparatus. The plating apparatus includes a plating section for plating a substrate, a substrate holder for holding the substrate, a substrate holder transporter for holding and transporting the substrate holder, a stocker for storing the substrate holder, and a stocker setting section for storing the stocker therein. The stocker includes a moving mechanism for moving the stocker into and out of the stocker setting section. | 2012-04-26 |
20120100710 | METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method and apparatus for manufacturing a semiconductor device is disclosed, which is capable of realizing an extension of a cleaning cycle for a processing chamber, the method comprising preheating a substrate; placing the preheated substrate onto a substrate-supporting unit provided in a susceptor while the preheated substrate is maintained at a predetermined height from an upper surface of the susceptor provided in a processing chamber; and forming a thin film on the preheated substrate, wherein a temperature of the preheated substrate is higher than a processing temperature for forming the thin film in the processing chamber. | 2012-04-26 |
20120100711 | SINGLE CHIP SEMICONDUCTOR COATING STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a single chip semiconductor coating structure includes following steps. Step | 2012-04-26 |
20120100712 | STRUCTURE OF POWER GRID FOR SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME - An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided. | 2012-04-26 |
20120100713 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device and a method for forming the same are disclosed. In the method for manufacturing the semiconductor device, a lower electrode material is deposited over a semiconductor substrate including a lower electrode contact plug so as to form a sacrificial insulation film. After the sacrificial insulation film and a lower electrode material are etched using a dry etching process, additional lower electrode material is deposited and etched back so as to form a lower electrode. As a result, a margin or region between a lower electrode contact plug and the lower electrode can be guaranteed. | 2012-04-26 |
20120100714 | Method of Fabricating a Landing Plug in a Semiconductor Device - A method of fabricating a landing plug in a semiconductor memory device, which in one embodiment includes forming a landing plug contact hole on a semiconductor substrate having an impurity region to expose the impurity region; forming a landing plug by filling the landing plug contact hole with a polysilicon layer, wherein the landing plug is divided into a first region, a second region, a third region, and a fourth region from a lower portion of the landing plug, and the first region is doped with a first doping concentration that is relatively lowest, the second region is doped with a second doping concentration that is higher than the first doping concentration, the third region is doped with a third doping concentration that is higher than the second doping concentration and the fourth region is not doped; and annealing the resulting product formed with the landing plug. | 2012-04-26 |