| 17th week of 2013 patent applcation highlights part 44 |
| Patent application number | Title | Published |
|---|
| 20130102059 | METHODS AND APPARATUS FOR ORGAN SUPPORT - An organ support apparatus includes: (a) a fluid circuit defining upstream and downstream legs adapted to be connected to an organ to be supported; (b) a circulation pump connected to the fluid circuit for circulating a process fluid through the fluid circuit and the organ; and (c) a first waveform generator connected to the fluid circuit for impressing a preselected pressure waveform on the process fluid. | 2013-04-25 |
| 20130102060 | LANCE DEVICE AND ASSOCIATED METHODS FOR DELIVERING A BIOLOGICAL MATERIAL INTO A BIOLOGICAL STRUCTURE - Systems, devices, and methods for delivering a biological material into a biological structure are provided. In one aspect, for example, a lance device for introducing biological material into a biological structure and configured for use in a nanoinjection system including a microscope is provided. Such a device can include a substrate including a handle region located between a manipulator coupling region and a lance shaft region, a lance tip operable to introduce biological material into a biological structure, the lance tip being coupled to the lance shaft region, and an electrically conductive layer extending from the manipulator coupling region to the lance tip, the conductive layer being configured to electrically couple to a power source. Thus, the conductive layer provides an electrical connection from the power source to the lance tip when in use. | 2013-04-25 |
| 20130102061 | SYSTEMS AND METHODS FOR AUTO-CALIBRATION OF RESISTIVE TEMPERATURE SENSORS - The invention relates to systems and methods for calibrating and using resistance temperature detectors. In one embodiment, the system includes a calibration circuit comprising a resistance temperature detector in a bridge circuit with at least one potentiometer, and a programmable gain amplifier coupled to the bridge circuit. Embodiments of the invention further comprise methods for calibrating the bridge circuit and the programmable gain amplifier for use with the resistance temperature detector and methods for determining the self heating voltage of the bridge circuit. | 2013-04-25 |
| 20130102062 | MICROCHIP FOR NUCLEIC ACID AMPLIFICATION REACTION AND METHOD OF PRODUCING THE SAME - Provided is a microchip for a nucleic acid amplification reaction, including a well configured to function as a reaction site of the nucleic acid amplification reaction, and the well has a center portion and a marginal portion, a substance anchored in a form that the substance is eccentrically-located less at the center portion and much at the marginal portion of the well, in which the substance is at least a part of a substance for the nucleic and amplification reaction. | 2013-04-25 |
| 20130102063 | SMALL MOLECULES AND PROTEIN ANALYSIS DEVICES BASED ON MOLECULAR IMPRINTED POLYMERS - Devices, methods and kits for rapid and simple determination of target molecules, including small molecules, polypeptides, proteins, cells and infectious disease agents in liquid samples that are capable of real-time measurement of these entities in fluid samples that are highly selective, highly sensitive, simple to operate, low cost, and portable. The devices, methods and kits also provide, in at least some embodiments, the use of MIPs in a flow through or lateral flow device. | 2013-04-25 |
| 20130102064 | RT-PCR CHIP WITH OPTICAL DETECTION - An apparatus ( | 2013-04-25 |
| 20130102065 | Small Volume and Fast Acting Optical Analyte Sensor - A fast acting sensor designed to accommodate an aqueous analyte-containing sample having a volume of less than one microliter and that can be used to quantify the amount and concentration of such analyte in the sample through light reflectance or fiber-optic light reflectance. The sensor includes a storage chamber, a capillary passage, and a reaction membrane. The storage chamber acts to collect the sample and to secure such sample while it undergoes detection. The capillary passage acts to direct the sample over the reaction membrane and controls the diffusion of the sample in the storage chamber. The reaction membrane contains all of the chemicals and enzymes needed to cause a color-change reaction when contacted with the sample. The amount of analyte can be determined by light reflectance intensity with an optical measurement instrument. | 2013-04-25 |
| 20130102066 | CHALCOGENIDE-FIBRE, INFRARED EVANESCENT WAVE SENSOR AND PROCESS FOR PRODUCING SAME - The invention relates to a fibre sensor that enables the propagation of infrared light at at least one wavelength of 0.8 to 25 micrometres, the fibre successively comprising along its length a first infrared waveguide section ( | 2013-04-25 |
| 20130102067 | CELL MONITORING BY MEANS OF SCATTERED LIGHT MEASUREMENT - A device for monitoring test cells has at least one receiving unit for the test cells and a first measuring unit for cell measurement. With a second measuring unit, which has a light source and a scattered light detector, cell monitoring can be carried out during the cell measurement. For this purpose the receiving unit has an at least partially light-permeable substrate and is arranged between the light source and scattered light detector such that at least a part of the light generated by the light source shines on the receiving unit, is scattered on the test cells and, after leaving the receiving unit through the substrate, impinges on the scattered light detector. | 2013-04-25 |
| 20130102068 | CULTURE APPARATUS AND METHOD OF REPLACING CULTURE MEDIUM - There is provided a culture apparatus including: a first pipe having a discharge channel formed at one end thereof; a second pipe having a suction channel formed at one end thereof; and a connection channel connecting the first and second pipes. | 2013-04-25 |
| 20130102069 | ALGAE REACTOR - The invention relates to a method for transferring light generated by a light emitting diode towards an aqueous liquid containing algae. The method includes emitting light by the light emitting diode having a first refractive index, transferring the light through a liquid medium having a second refractive index, and a solid medium having a third refractive index, into the aqueous liquid having a fourth refractive index. The value of the first refractive index is equal to or greater than the value of the second refractive index. The value of the second refractive index is equal to or greater than the value of the third refractive index. The value of the third refractive index is equal to or greater than the value of the fourth refractive index. The invention further relates to a reactor designed to perform such method. | 2013-04-25 |
| 20130102070 | Cell Expansion System and Methods of Use - Cell expansion systems and methods of use are provided. The cell expansion systems generally include a hollow fiber cell growth chamber, and first and second circulation loops (intracapillary loops and extracapillary loops) associated with the interior of the hollow fibers and exterior of the hollow fibers, respectively. Detachable flow circuits and methods of expanding cells are also provided. | 2013-04-25 |
| 20130102071 | SYSTEM AND METHOD FOR PREPARING CELL CULTURE DISH MEDIA - Systems for preparing cell culture dish media are provided which are well adapted for preparing cell culture media, supplements, additives and/or other ingredients in an efficient and versatile manner to form sterilized cell culture dish media having a variety of ingredients well adapted with respect to uniformity and nutritional content to culture microorganisms in a particularly effective manner. The systems include an array of filtration and steam sterilization devices to sterilize various types of media for selective combination of one or more of the types of media in a mixing chamber to form cell culture dishes (e.g., agar plates). Methods of preparing cell culture dish media and cell culture dishes are also provided. | 2013-04-25 |
| 20130102072 | SUPPRESSION OF B-CELL APOPTOSIS IN TRANSGENIC ANIMALS EXPRESSING HUMANIZED IMMUNOGLOBULIN - The invention provides a novel approach to increase immunoglobulin expression in non-human transgenic animals. For instance, the invention provides a method to increase humanized immunoglobulin production in animals genetically engineered to express one or several human or humanized immunoglobulin transloci. This can be done by overexpressing the apoptosis inhibitor, i.e. a rabbit bcl-2, whose expression is driven by a B-cell specific promoter specifically in the B-cell of the animal, thereby enhancing the survival of B-cells. This invention further relates to a method for selectively enhancing the survival of exogenous B-cells, that is B-cells expressing any immunoglobulin transgene locus, over the survival of endogenous B-cells that do not express the transgene locus. Selectivity is achieved by expressing the apoptosis-inhibitor only within exogenous B-cells, that is, by coupling exogenous immunoglobulin expression with apoptosis inhibitor expression. This latter method allows for increased expression and production of the transgene encoded product(s) over the endogenously produced immunoglobulin of the transgenic animal. The invention also provides a novel apoptosis-inhibitor, rabbit bcl-2. | 2013-04-25 |
| 20130102073 | METHODS FOR MAKING AND USING REPROGRAMMED HUMAN SOMATIC CELL NUCLEI AND AUTOLOGOUS AND ISOGENIC HUMAN STEM CELLS - Activated human embryos produced by therapeutic cloning can give rise to human totipotent and pluripotent stem cells from which autologous cells for transplantation therapy are derived. The present invention provides methods for producing activated human embryos that can be used to generate totipotent and pluripotent stem cells from which autologous cells and tissues suitable for transplantation can be derived. The ability to create autologous human embryos represents a critical step towards generating immune-compatible stem cells that can be used to overcome the problem of immune rejection in regenerative medicine. The activated human embryos produced by the present invention also provide model systems for identifying and analyzing the molecular mechanisms of epigenetic imprinting and the genetic regulation of embryogenesis and development. | 2013-04-25 |
| 20130102074 | METHODS FOR REPROGRAMMING SOMATIC CELLS - The invention provides methods for reprogramming somatic cells to generate multipotent or pluripotent cells. Such methods are useful for a variety of purposes, including treating or preventing a medical condition in an individual. The invention further provides methods for identifying an agent that reprograms somatic cells to a less differentiated state. | 2013-04-25 |
| 20130102075 | METHODS OF CELL CULTURE FOR ADOPTIVE CELL THERAPY - An improved method of culturing cells for cell therapy applications that includes growing desired cells in the presence of antigen-presenting cells and/or feeder cells and with medium volume to surface area ratio of up to 1 ml/cm | 2013-04-25 |
| 20130102076 | Systems and methods for growing photosynthetic organisms - Methods and apparatus for promoting the growth of an aquatic photosynthetic organism within a growth medium in a photobioreactor may use a luminescent material targeting the aquatic photosynthetic organism in the photobioreactor. The luminescent material may be a substrate with a matrix of conductors coupled to the substrate, and light emitting diodes (“LEDs”) electrically coupled to the matrix of conductors. The aquatic photosynthetic organism in the photobioreactor is exposed to the light emitted by the LEDs. | 2013-04-25 |
| 20130102077 | ALTERATIONS UTILIZING NANOPARTICLES - Alterations utilizing nanoparticles. Certain embodiments of the invention are methods of delivering a substance to a target using a delivery-aid which includes nanoparticles. Those nanoparticles may be nanocarbon particles. Other embodiments are methods of delivering nanoparticles to a target involving placing a mask between a source of ballistic delivery of nanoparticles and the target. Other embodiments include irradiating a target to cause localized heating of the region of the target in which the nanodiamonds or OLC particles are present. Other embodiments utilize nanoparticles to make cells competent for genetic transformation. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract. | 2013-04-25 |
| 20130102078 | NANOINJECTION SYSTEM DNA PLACEMENT PIPETTE COUPLER - Systems, devices, and methods for injecting biological material into a micro-object such as a cell are provided. In one aspect, for example, a cellular injection device can include a housing, an injection lance coupled to the housing and having a working tip extending outward from the housing, and a biological material delivery device coupled to the housing and having an effluent tip extending outward from the housing. The effluent tip can be positioned sufficiently proximal to the working tip such that biological material expelled from the effluent tip substantially contacts the working tip. In one aspect, the injection lance is removably coupled to the housing. In another aspect, the biological material delivery device is removably coupled to the housing. | 2013-04-25 |
| 20130102079 | POLYAMINE-CONTAINING POLYMERS AND METHODS OF SYNTHESIS AND USE - The present invention relates to polyamine-containing polymers and methods of their synthesis and use. The polymer may be hydroxyethylcellulose, dextran, poly(vinyl alcohol) or poly(methyl acrylate). | 2013-04-25 |
| 20130102080 | METHODS FOR REPROGRAMMING SOMATIC CELLS - The invention provides methods for reprogramming somatic cells to generate multipotent or pluripotent cells. Such methods are useful for a variety of purposes, including treating or preventing a medical condition in an individual. The invention further provides methods for identifying an agent that reprograms somatic cells to a less differentiated state. | 2013-04-25 |
| 20130102081 | Detection and Characterization of Protein Degradation, Protein Degradation Modulation and Protein Degradation Modulators - Protein degradation, protein degradation modulation and protein degradation modulators can be detected and characterized through assessment of differential angular mobility exhibited by protein degradation reactants and products. | 2013-04-25 |
| 20130102082 | PROTEIN CONCENTRATION ASSAY METHOD ANALYSIS TOOL AND ANALYZER - Provided is a protein concentration assay method that uses a protein indicating reagent and that enables highly accurate assay. The protein concentration assay method includes: optically analyzing a color exhibited after a sample to be assayed and a protein indicating reagent are brought into contact with each other; measuring pH of the sample to be assayed; and assaying a concentration of protein in the sample based on the result of the optical analysis, the measured value of pH, and data for protein concentration assay, wherein the protein indicating reagent is a protein indicating reagent whose color varies with pH and a concentration of protein, and the data for protein concentration assay include information indicating a way to assay the result of the optical analysis corresponding to the measured value of pH. | 2013-04-25 |
| 20130102083 | METHOD FOR DETERMINING ONE OR MORE CHARACTERIZING FEATURES OF A MACROMOLECULE AND AN APPARATUS FOR CARRYING OUT SAID METHOD - The invention concerns a method and apparatus for determining one or more characterizing features of a macromolecule, in particular torque and/or twist of nucleic acids like DNA, using magnetic fields. | 2013-04-25 |
| 20130102084 | Methods of forming graphene by graphite exfoliation - Methods of forming graphene by graphite exfoliation, wherein the methods include: providing a graphite sample having atomic layers of carbon; introducing a salt and a solvent into the space between the atomic layers; expanding the space between the atomic layers using organic molecules and ions from the solvent and the salt; and separating the atomic layers using a driving force to form one or more sheets of graphene; the graphene produced by the methods can be used to form solar cells, to perform DNA analysis, and for other electrical, optical and biological applications. | 2013-04-25 |
| 20130102085 | METHOD OF SENSING A MOLECULE, AN APPARATUS AND A SEMICONDUCTOR CHIP THEREFOR - A semiconductor chip, apparatus, and associated method wherein the semiconductor chip, having at least one electrode and configured as a sensor such as a biosensor, is removably attachable to a tip of a dipstick. The dipstick tip, with the attached semiconductor chip, is arranged to be dipped into a well containing an analyte. The well may be part of a micro-titre plate. The chip electrically senses the presence of a target molecule in the analyte. The sensing may be by detecting a change in capacitance associated with the electrode which occurs in the presence of the target molecule. The apparatus may include plural dipsticks and associated semiconductor chips which are sensitive for different target molecules. Alternatively or in addition, a single semiconductor chip may have a plurality of electrodes, which may be sensitive to different target molecules. | 2013-04-25 |
| 20130102086 | METHODS AND APPARATUSES FOR DETECTING A CORROSION INHIBITOR - Methods, apparatuses, compositions and kits are disclosed for detecting the presence or absence of an inhibitor in a fluid. In one embodiment, methods, apparatuses, compositions and kits are disclosed for determining if the level of a corrosion inhibitor in a coolant fluid is sufficient to provide protection against corrosion. | 2013-04-25 |
| 20130102087 | DEVICE, SYSTEM AND METHOD FOR RAPID DETERMINATION OF A MEDICAL CONDITION - Provided is a system and method for determination of a medical condition, the system including a disposable cartridge adapted to receive a volume of a body fluid, the cartridge comprising a plurality of sections, at least one of the sections adapted to react at least one reactant with the bodily fluid to form a pretreated sample; and an optics unit comprising at least one excitation illumination adapted to convey radiation to the pre-treated sample, at least one multi-spectral emission detector and at least one of a photon counter and an integrator, wherein the at least one excitation illumination and the at least one multi-spectral emission detector are disposed on the same side of the cartridge; and wherein the optics unit is adapted to detect a plurality of spectrally distinct signals generated by interaction of the radiation and the pre-treated sample in the cartridge, thereby determining said medical condition. | 2013-04-25 |
| 20130102088 | Fluorescent Sensor and Methods - Binding an analyte can cause a change in fluorescence emission of a sensor. The change in fluorescence can be related to the amount of analyte present. The sensor can include a semiconductor nanocrystal linked to a fluorescent moiety. Upon excitation, the fluorescent moiety can transfer energy to the semiconductor nanocrystal, or vice versa. | 2013-04-25 |
| 20130102089 | Method For Processing A Sensor Chip - The method for processing a sensor chip in accordance with the present invention has: 1) providing an acoustic wave operation system and a biochemical sensor chip, wherein the acoustic wave operation system has a piezoelectric transducer generating at least one cycle of longitudinal acoustic waves by a driving voltage and wherein a probe is immobilized on a surface of the biochemical sensor chip; 2) arranging the piezoelectric transducer at a distance from the biochemical sensor chip and filling therebetween with a medium for transmitting longitudinal acoustic waves; and 3) applying longitudinal acoustic waves to the biochemical sensor chip to remove an adsorbate bound to the probe. | 2013-04-25 |
| 20130102090 | OPTICAL ANALYTE SENSOR - A waveguide sensor capable of direct, real-time detection and monitoring of analytes in the vicinity of the waveguide surface without requiring the tagging or labeling of the analyte, is described. Analytic and numerical calculations have predicted that by locally detecting either changes in the evanescent field or changes in the light coupled out of the waveguide as a result of the presence of the analyte, high detection sensitivity will be able to be achieved. | 2013-04-25 |
| 20130102091 | TEST SYSTEM SUPPORTING SIMPLIFIED CONFIGURATION FOR CONTROLLING TEST BLOCK CONCURRENCY - Techniques for configuring a test system that enable simple specification of a degree of concurrency in testing separate functional portions of a semiconductor device. For a test flow with multiple sub-flows; the pins accessed in connection with each sub-flow may define a flow domain. Site regions, each associated with a flow domain, may be defined. Tester sites may be associated with each of these flow domain specific site regions and independently operating resources may be assigned to these tester sites. A second portion of the defined site regions may be associated with tester sites, but resources assigned to these site regions may be accessed from multiple flow domains. Test blocks, even if not developed for concurrent execution, may be executed concurrently using resources in the flow domain specific site regions. Flexibility is provided to share resources through the use of the second portion of the site regions. | 2013-04-25 |
| 20130102092 | POLYCRYSTALLINE SILICON ROD AND METHOD FOR MANUFACTURING POLYCRYSTALLINE SILICON ROD - The length of the polycrystalline silicon rod ( | 2013-04-25 |
| 20130102093 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device which solves a problem with a burn-in process where current and voltage are applied to finished semiconductor devices at high-temperature. The method uses an organic multilayer wiring substrate for a burn-in board in which power supply/grounding wiring is formed with microscopic openings formed at least almost all over the areas around sockets over the front or back surface of the substrate. For increasing the supply voltage and reference voltage for the burn-in board and other purposes, whenever possible, signal wires are disposed in inner wiring layers of the board. The related-art burn-in board which has a solid or blanket-type conductor pattern in an outermost layer as wiring for supply or reference voltage may cause an insulating protective film over the metal wiring to peel due to weak adhesion between the wiring and film when thermal cycles are repeated. The method solves the problem. | 2013-04-25 |
| 20130102094 | METHOD FOR FABRICATING ORGANIC EL DEVICE AND METHOD FOR EVALUATING ORGANIC EL DEVICE - An organic EL device (OELD) having a defective portion is irradiated with a laser beam; first luminance of light emitted from the OELD is measured after the OELD is irradiated with the laser beam, while supplying, to the OELD, a first amount of current with which the OELD in a normal state would emit light having luminance corresponding to a first grayscale level smaller than a reference level; the OELD is re-irradiated with the laser beam when the first luminance is smaller than a threshold; and second luminance of light emitted from the OELD is measured when the first luminance is greater than or equal to the threshold, while supplying, to the OELD, a second amount of current with which the OELD in the normal state would emit light having luminance corresponding to a second grayscale level greater than or equal to the reference level. | 2013-04-25 |
| 20130102095 | Light Emitting Diodes with Smooth Surface for Reflective Electrode - A light emitting diode comprising an epitaxial layer structure, a first electrode, and a second electrode. The first and second electrodes are separately disposed on the epitaxial layer structure, and the epitaxial layer structure has a root-means-square (RMS) roughness less than about 3 at a surface whereon the first electrode is formed. | 2013-04-25 |
| 20130102096 | SIMULTANEOUS SILICONE DISPENSION ON COUPLER - A semiconductor device and methods of manufacturing the same are disclosed. Specifically, methods and devices for manufacturing optocouplers are disclosed. Even more specifically, methods and devices that deposit one or more encapsulant materials on optocouplers are disclosed. The encapsulant material may include silicone and the devices used to deposit the silicone may be configured to simultaneously deposit the silicone on different sides of the optocoupler, thereby reducing manufacturing steps and time. | 2013-04-25 |
| 20130102097 | MULTICOLOR LIGHT EMITTING DIODES - A device such as a multicolor light emitting diode that emits different colors of light and that may combine the different colors emitted by individual light emitting diodes. The multicolor LED may include a common anode terminal that may be connected to each anode of the individual light emitting diodes. The multicolor LED may be a five terminal multicolor LED. Additionally, the multicolor LED may include two anode terminals, in which the first anode terminal may be a common anode terminal connected to three of the individual color LEDs and the second anode terminal may be connected to an anode of a white LED. In this embodiment, the multicolor LED may be a six terminal multicolor LED. | 2013-04-25 |
| 20130102098 | ARRAY SUBSTRATE FOR LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An array substrate for an in-plane switching mode liquid crystal display device includes a substrate, a gate line disposed along a first direction on the substrate, a data line disposed along a second direction and crossing the gate line to define a pixel region, a thin film transistor connected to the gate line and the data line, pixel electrodes disposed in the pixel region and connected to the thin film transistor, common electrodes disposed in the pixel region and alternating with the pixel electrodes, a semiconductor layer underlying the data line and including a portion having a width greater than a width of the data line, and a first blocking pattern comprising an opaque material and disposed under the semiconductor layer. | 2013-04-25 |
| 20130102099 | METHOD OF MANUFACTURING CELLULAR ELECTROPHYSIOLOGY SENSOR CHIP - A cellular electrophysiology sensor is adapted to measure an electrical change of a test cell. A chip for the sensor includes a diaphragm, and a thermally-oxidized film mainly containing silicon dioxide on the diaphragm. The diaphragm includes a silicon layer and a silicon dioxide layer on an upper surface of the silicon layer. A through-hole passing through the silicon layer and the silicon dioxide layer is formed. The through-hole has an opening which opens at the silicon dioxide layer and is adapted to capture the test cell. The thermally-oxidized film is provided on an inner wall surface of the through-hole, and unified with the silicon dioxide layer at the opening of the through-hole. This cellular electrophysiology sensor chip can stably capture the test cell and provides a gigaseal stably even if test cells have different properties. | 2013-04-25 |
| 20130102100 | Method for Making Micro-Electro-Mechanical System Device - The present invention discloses a method for making a MEMS device, comprising: providing a zero-layer substrate; forming a MEMS device region on the substrate, wherein the MEMS device region is provided with a first sacrificial region to separate a suspension structure of the MEMS device from another part of the MEMS device; removing the first sacrificial region by etching; and micromachining the zero-layer substrate. | 2013-04-25 |
| 20130102101 | Wafer Level Packaging - A method of wafer level packaging includes providing a substrate including a buried oxide layer and a top oxide layer, and etching the substrate to form openings above the buried oxide layer and a micro-electro-mechanical systems (MEMS) resonator element between the openings, the MEMS resonator element enclosed within the buried oxide layer, the top oxide layer, and sidewall oxide layers. The method further includes filling the openings with polysilicon to form polysilicon electrodes adjacent the MEMS resonator element, removing the top oxide layer and the sidewall oxide layers adjacent the MEMS resonator element, bonding the polysilicon electrodes to one of a complementary metal-oxide semiconductor (CMOS) wafer or a carrier wafer, removing the buried oxide layer adjacent the MEMS resonator element, and bonding the substrate to a capping wafer to seal the MEMS resonator element between the capping wafer and one of the CMOS wafer or the carrier wafer. | 2013-04-25 |
| 20130102102 | VACUUM RECYCLING APPARATUS AND METHOD FOR REFINING SOLAR GRADE POLYSILICON - A vacuum recycling apparatus for refining solar grade polysilicon is provided which contains a vacuum degassing (VD) device and a vacuum recycling (RH) device. By storing liquid silicon in a bucket in the VD device, controlling the pressure inside the VD and RH devices, and introducing inert gas into the apparatus, the liquid silicon is stirred for the removal of impurities. With the present invention, solar grade polysilicon can be directly produced with a specified purity, significantly reducing the production time and cost. | 2013-04-25 |
| 20130102103 | METHODS AND APPARATUS FOR THE CLOSED-LOOP FEEDBACK CONTROL OF THE PRINTING OF A MULTILAYER PATTERN - Embodiments of the present invention provide apparatus and methods for closed-loop control utilized in printing a multilayer pattern on a substrate. In one embodiment, a solar cell formation process is provided. The process comprises positioning a substrate on a substrate receiving surface of a printing station, printing a first patterned layer on a region of the substrate, acquiring a first optical image of the first patterned layer and storing the first optical image in a buffer, printing a second patterned layer over the region of the substrate, wherein the second patterned layer is aligned over the region of the substrate using information received from the acquired first optical image. | 2013-04-25 |
| 20130102104 | SOLAR CELL MODULE AND MANUFACTURING METHOD OF SOLAR CELL MODULE - A solar cell module includes a structure in which a back surface material, a back-surface-side sealing resin, a solar cell, a light-receiving-surface-side sealing resin, and a front surface material are laminated in sequential order, in which a melting point of a portion, which is in contact with the solar cell, of at least one of the light-receiving-surface-side sealing resin and the back-surface-side sealing resin is lower than a melting point of a portion, which is in contact with the back surface material, of the back-surface-side sealing resin. | 2013-04-25 |
| 20130102105 | PRODUCTION METHOD OF SOLAR CELL MODULE - The present invention provides a production method of a solar cell module, comprising: a first process of mounting a module layered body, which comprises at least a glass member, an encapsulant, a solar cell element and a translucent member in this order, and in which an outer periphery of the encapsulant is positioned at an inner side of outer peripheries of the glass member and the translucent member, on a mounting platen of a double vacuum chamber system laminator comprising a first chamber and a second chamber that are partitioned by a flexible member, and the mounting platen, which is provided in the second chamber facing the flexible member and comprises a heating means, the module layered body being mounted on the mounting platen so that the glass member is at the flexible member side; a second process of depressurizing the inside of the first chamber and the inside of the second chamber; and a third process of heat-pressure bonding and integrating the module layered body by raising a pressure in the first chamber to from 0.005 MPa to 0.090 MPa (gauge pressure of from −0.096 MPa to −0.011 MPa) and pressing the module layered body to the heated mounting platen by the flexible member which has undergone flexural deformation. | 2013-04-25 |
| 20130102106 | IMAGE SENSOR MODULE AND METHOD OF MANUFACTURING THE SAME - An image sensor module includes a transparent substrate having recesses defined in a lower face thereof. A light concentration member includes transparent light concentration parts each of which are disposed in a corresponding one of the recesses. Color filters are disposed over each of the light concentration parts and photo diode units having photo diodes are disposed over each of the color filters. An insulation member covers the photo diode units and input/output terminals disposed over the insulation member are each electrically connected to a corresponding photo diode unit. | 2013-04-25 |
| 20130102107 | METHOD FOR PROCESSING SILICON SUBSTRATE - It is an object to provide a method for processing a silicon substrate that can reduce surface reflectance as much as possible. The method includes a first step of forming a thin film including a metal having higher electronegativity than silicon and having a plurality of openings on a silicon substrate, a second step of soaking the silicon substrate subjected to the first step in a hydrofluoric acid solution containing oxidizer, and a third step of soaking the silicon substrate subjected to the second step in an ammonia aqueous solution containing oxidizer. By performing the steps in the above order, a minute uneven structure is formed on a surface of the silicon substrate to reduce the reflectance. | 2013-04-25 |
| 20130102108 | PREPARATION OF SEMICONDUCTOR FILMS - The invention relates to a preparation process for thin semiconducting inorganic films comprising various metals (Cu/In/Zn/Ga/Sn), selenium and/or sulfur. The process uses molecular precursors comprising metal complexes with oximato ligands. Copper-based chalcopyrites of the I-III-IV | 2013-04-25 |
| 20130102109 | METHOD AND APPARATUS OF REMOVING A PASSIVATION FILM AND IMPROVING CONTACT RESISTANCE IN REAR POINT CONTACT SOLAR CELLS - Embodiments of the present invention generally provide improved processes and apparatus for removing passivation layers from a surface of photovoltaic cells and improving contact resistance in rear point contact photovoltaic cells. In one embodiment, a method of processing a solar cell substrate includes providing a substrate having a passivation layer deposited on a first surface of the substrate. The passivation layer is a layer stack comprising an aluminum oxide and a silicon nitride. The method also includes exposing the first surface of the substrate to an etchant, and heating the etchant to dissolve the aluminum oxide of the passivation layer on the first surface. The method may further include forming a metal containing layer on a second surface of the substrate that is opposite to the first surface. | 2013-04-25 |
| 20130102110 | METHOD AND APPARATUS OF FORMING A CONDUCTIVE LAYER - The present invention generally includes an apparatus and process of forming a conductive layer on a surface of a host substrate, which can be directly used to form a portion of an electronic device. More specifically, one or more of the embodiments disclosed herein include a process of forming a conductive layer on a surface of a substrate using an electrospinning type deposition process. Embodiments of the conductive layer forming process described herein can be used to reduce the number of processing steps required to form the conductive layer, improve the electrical properties of the formed conductive layer and reduce the conductive layer formation process complexity over current state-of-the-art conductive layer formation techniques. Typical electronic device formation processes that can benefit from one or more of the embodiments described herein include, but are not limited to processes used to form solar cells, electronic visual display devices and touchscreen type technologies. | 2013-04-25 |
| 20130102111 | STACKED SEMICONDUCTOR DEVICES INCLUDING A MASTER DEVICE - A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s). | 2013-04-25 |
| 20130102112 | Process for Forming Packages - A method includes loading a first package component on a concave boat, and placing a second package component over the first package component. A load clamp is placed over the second package component, wherein the load clamp is supported by a temperature-variable spacer of the concave boat. A reflow step is performed to bond the second package component to the first package component. During a temperature-elevation step of the reflow step, the temperature-variable spacer is softened in response to an increase in temperature, and a height of the softened temperature-variable spacer is reduced, until the load clamp is stopped by a rigid spacer of the concave boat. | 2013-04-25 |
| 20130102113 | METHOD FOR ENCAPSULATING SEMICONDUCTOR AND STRUCTURE THEREOF - Embodiments of the present invention disclose a method for encapsulating a component with plastic and its encapsulation structure, which belong to the plastic encapsulation technology field. The method includes: processing, by using the surface mounting technology, a first surface of a part to be encapsulated with plastic and/or performing die bonding on the first surface; encapsulating, with plastic, the first surface of the part to be encapsulated with plastic a second surface of the part to be encapsulated with plastic the first surface and/or performing die bonding in the second face; and encapsulating, with plastic, the second surface of the part to be encapsulated with plastic. This encapsulation structure includes a substrate, where components are fixed on an upper surface and a lower surface of the substrate, and the components on the upper surface and lower surface are all encapsulated with plastic in seal. | 2013-04-25 |
| 20130102114 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A technology is capable of simplifying a process of manufacturing an asymmetric device in forming a Tunneling Field Effect Transistor (TFET) structure. A method for manufacturing a semiconductor device comprises forming a conductive pattern over a semiconductor substrate, implanting impurity ions with the conductive pattern as a mask to form a first junction region in the semiconductor substrate, forming a first insulating film planarized with the conductive pattern over the first junction region, etching the top of the conductive pattern to expose a sidewall of the first insulating film, forming a spacer at the sidewall of the first insulating film disposed over the conductive pattern, etching the conductive pattern with the spacer as an etching mask to form a gate pattern, and forming a second junction region in the semiconductor substrate with the gate pattern as a mask. | 2013-04-25 |
| 20130102115 | METHOD FOR MANUFACTURING ACTIVE MATRIX SUBSTRATE - The disclosed method for manufacturing an active matrix substrate includes a step in which a first mask is used to pattern a first conductive layer G, CS, and S, a step in which a second mask is used to pattern a first insulating layer, a step in which a third mask is used to pattern a semiconductor layer, a step in which a fourth mask is used to pattern a second conductive later, a step in which a fifth mask is used to pattern a second insulating layer, and a step in which a sixth mask is used to pattern a third conductive layer. | 2013-04-25 |
| 20130102116 | HYBRID INTEGRATED SEMICONDUCTOR TRI-GATE AND SPLIT DUAL-GATE FINFET DEVICES AND METHOD FOR MANUFACTURING - A method for making a tri-gate FinFET and a dual-gate FinFET includes providing a semiconductor on insulator (SOI) wafer having a semiconductor layer over an insulator layer. The method further includes forming a hard mask on the semiconductor layer and patterning the hard mask to form first and second cap portions. The method also includes etching the semiconductor layer to form first and second fins using the first and second cap portions as an etch mask. The method also includes removing the second cap portion to expose the top surface of the second fin and forming a gate dielectric layer on the first and second fins. The method further includes forming a conductive layer over the gate dielectric layer, selectively etching the conductive layer to form first and second gate structures, forming an interlayer dielectric layer over the gate structures, and planarizing the interlayer dielectric layer using the first cap portion as a polish stop. | 2013-04-25 |
| 20130102117 | Manufacturing Processes for Field Effect Transistors Having Strain-Induced Chanels - One embodiment relates to a method of semiconductor manufacture. In this method, a strain inducing layer is formed over a p-type field effect transistor structure and an n-type field effect transistor structure. The strain inducing layer is removed from over the p-type field effect transistor while the strain inducing layer over the n-type field effect transistor is left in place. A treatment of the strain inducing layer over the n-type field effect transistor is performed after the strain-inducing layer has been removed from over the p-type field effect transistor. | 2013-04-25 |
| 20130102118 | SEMICONDUCTOR DEVICE WITH ONE-SIDE-CONTACT AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench. | 2013-04-25 |
| 20130102119 | BULK FIN-FIELD EFFECT TRANSISTORS WITH WELL DEFINED ISOLATION - A fin field-effect-transistor fabricated by forming a dummy fin structure on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. The dielectric layer surrounds the dummy fin structure. The dummy fin structure is removed to form a cavity within the dielectric layer. The cavity exposes a portion of the semiconductor substrate thereby forming an exposed portion of the semiconductor substrate within the cavity. A dopant is implanted into the exposed portion of the semiconductor substrate within the cavity thereby creating a dopant implanted exposed portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate. | 2013-04-25 |
| 20130102120 | METHODS OF MANUFACTURING PHASE-CHANGE MEMORY DEVICE AND SEMICONDUCTOR DEVICE - Methods of manufacturing a phase-change memory device and a semiconductor device are provided. The method of manufacturing the phase-change memory device includes forming a switching device layer, an ohmic contact layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer to form a hard mask pattern, etching the ohmic layer and the switching layer using the hard mask pattern to form a pattern structure including an ohmic contact pattern, a switching device pattern, and the hard mask pattern, selectively oxidizing a surface of the pattern structure, forming an insulating layer to bury the pattern structure, and selectively removing the hard mask pattern other than the oxidized surface thereof to form a contact hole. | 2013-04-25 |
| 20130102121 | Oxygen Diffusion Barrier Comprising Ru - A method for forming a MIM capacitor structure includes the steps of obtaining a base structure provided with a recess, the recess exposing a conductive bottom electrode plug; selectively growing Ru on the bottom electrode plug, based on a difference in incubation time of Ru growth on the bottom electrode plug compared to the base structure material; oxidizing the selectively grown Ru; depositing a Ru-comprising bottom electrode over the oxidized Ru; forming a dielectric layer on the Ru-comprising bottom electrode; and—forming a conductive top electrode over the dielectric layer. | 2013-04-25 |
| 20130102122 | SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME - The present invention relates to a semiconductor package and a method for making the same. The method includes the steps of: (a) providing a base material; (b) forming a first metal layer on the base material, wherein the first metal layer comprises a first inductor and a first lower electrode; (c) forming a first dielectric layer and a first upper electrode on the first lower electrode, wherein the first dielectric layer is disposed between the first upper electrode and the first lower electrode, and the first upper electrode, the first dielectric layer and the first lower electrode form a first capacitor; and (d) forming a first protective layer, so as to encapsulate the first inductor and the first capacitor. | 2013-04-25 |
| 20130102123 | METHOD FOR FABRICATING SINGLE-SIDED BURIED STRAP IN A SEMICONDUCTOR DEVICE - A method for manufacturing a buried-strap includes: forming a trench capacitor structure in a semiconductor substrate, wherein the trench capacitor structure has a doped polysilicon layer and an isolation collar covered by the doped polysilicon layer, and a top surface of the doped polysilicon layer is lower than a top surface of the semiconductor substrate such that a first recess is formed; sequentially forming a first resist layer, a second resist layer and a third resist layer over the semiconductor substrate; sequentially patterning the third resist layer, the second resist layer and the first resist layer, forming a patterned tri-layer resist layer over the semiconductor substrate; partially removing a portion of the doped polysilicon layer exposed by the patterned tri-layer resist layer to form a second recess; removing the patterned tri-layer resist layer; and forming an insulating layer in the second recess and a portion of the first recess. | 2013-04-25 |
| 20130102124 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a method of manufacturing a semiconductor device includes forming an isolation trench in a substrate, and forming an amorphous layer on a sidewall surface of the isolation trench. The method further includes forming a sacrificial layer in the isolation trench via the amorphous layer, and forming an air gap layer on the sacrificial layer. The method further includes forming an air gap in the isolation trench under the air gap layer by removing the sacrificial layer after forming the air gap layer. | 2013-04-25 |
| 20130102125 | METHOD FOR CONTROLLING STRUCTURE HEIGHT - Methods for controlling the height of semiconductor structures are disclosed. Amorphous carbon is used as a stopping layer for controlling height variability. In one embodiment, the height of replacement metal gates for transistors is controlled. In another embodiment, the step height of a shallow trench isolation region is controlled. | 2013-04-25 |
| 20130102126 | METHOD FOR MANUFACTURING BONDED WAFER - A method for manufacturing a bonded wafer including: forming an ion-implanted layer in a bond wafer, bonding the bond wafer to a base wafer, delaminating the bond wafer at the ion-implanted layer, and performing a flattening heat treatment on a surface after delamination, in which a silicon single crystal wafer is used as the bond wafer where the region to form the ion-implanted layer has a resistivity of 0.2 Ωcm or less, the ion-implanted layer is formed where the ion dose for forming the layer is 4×10 | 2013-04-25 |
| 20130102127 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device having an ohmic electrode is disclosed. The manufacturing method includes: forming a metal thin film on a rear surface of a semiconductor substrate; forming an ohmic electrode by laser annealing by irradiating the metal thin film with laser beam; and dicing the semiconductor substrate into chips by cutting at a dicing region of the semiconductor substrate. In forming the ohmic electrode, laser irradiation of the metal thin film is performed on a chip-by-chip basis while the dicing region is not being irradiated with the laser beam. | 2013-04-25 |
| 20130102128 | METHOD FOR TREATING THE DISLOCATION IN A GAN-CONTAINING SEMICONDUCTOR LAYER - A method for treating the threading dislocation within a GaN-containing semiconductor layer is provided. The method includes a substrate is provided. A GaN-containing semiconductor layer with the threading dislocation is formed on the substrate. An etching process with an etching gas is performed to remove the threading dislocation in the GaN-containing semiconductor layer so as to increase the efficiency for the light emitting device. | 2013-04-25 |
| 20130102129 | PROCESSES FOR SUPPRESSING MINORITY CARRIER LIFETIME DEGRADATION IN SILICON WAFERS - Processes for suppressing minority carrier lifetime degradation in silicon wafers are disclosed. The processes involve quench cooling the wafers to increase the density of nano-precipitates in the silicon wafers and the rate at which interstitial atoms are consumed by the nano-precipitates. | 2013-04-25 |
| 20130102130 | BULK FIN-FIELD EFFECT TRANSISTORS WITH WELL DEFINED ISOLATION - A fin field-effect-transistor fabricated by forming a dummy fin structure on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. The dielectric layer surrounds the dummy fin structure. The dummy fin structure is removed to form a cavity within the dielectric layer. The cavity exposes a portion of the semiconductor substrate thereby forming an exposed portion of the semiconductor substrate within the cavity. A dopant is implanted into the exposed portion of the semiconductor substrate within the cavity thereby creating a dopant implanted exposed portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate. | 2013-04-25 |
| 20130102131 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device wherein a film containing Si and Ge is formed on a conducting film over a substrate by using a raw material gas containing Si and a raw material gas containing Ge, includes: forming Si nuclei on the conducting film at a first ratio of a flow rate of the raw material gas containing Ge to a flow rate of the raw material gas containing Si; and forming, on the Si nuclei, a film having Si and Ge at a second ratio of the flow rate of the raw material gas containing Ge to the flow rate of the raw material gas containing Si, the second ratio being greater than the first ratio. | 2013-04-25 |
| 20130102132 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING APPARATUS AND RECORDING MEDIUM - A method of manufacturing a semiconductor device includes: accommodating a substrate in a processing chamber; and supplying an organosilicon-based gas into the processing chamber that is heated to form a film including silicon and carbon on the substrate. In the forming of the film including silicon and carbon, a cycle is performed a predetermined number of times. The cycle includes supplying the organosilicon-based gas into the processing chamber and confining the organosilicon-based gas in the processing chamber, maintaining a state in which the organosilicon-based gas is confined in the processing chamber, and exhausting an inside of the processing chamber. | 2013-04-25 |
| 20130102133 | METHOD AND APPARATUS FOR FABRICATING SILICON HETEROJUNCTION SOLAR CELLS - A method for fabricating a semiconductor layer within a plasma enhanced chemical vapor deposition (PECVD) apparatus. The PECVD apparatus includes a plurality of walls defining a processing region, a substrate support, a shadow frame, a gas distribution showerhead, a gas source in fluid communication with the gas distribution showerhead and the processing region, a radio frequency power source coupled to the gas distribution showerhead, and one or more VHF grounding straps electrically coupled to at least one of the plurality of walls. The VHF grounding straps provide a low-impedance current path between at least one of the plurality of walls and at least one of a shadow frame or the substrate support. The method further includes delivering a semiconductor precursor gas and a dopant precursor gas and delivering a very high frequency (VHF) power to generate a plasma to form a first layer on the one or more substrates. | 2013-04-25 |
| 20130102134 | METHOD FOR PRODUCING SILICON NANOWIRE DEVICES - The invention provides a method for producing silicon nanowire devices, including the following steps: growing SiNW on a substrate; depositing an amorphous carbon layer and dielectric anti-reflectivity coating orderly; removing part of dielectric anti-reflectivity coating and amorphous carbon layer above the SiNW through dry etching to expose the SiNW device area; depositing an oxide film on the surface of the above structure; forming a metal pad connected with the SiNW in the SiNW device area; depositing a passivation layer on the surface of the above structure; applying photolithography and etching technology to form contact holes on the metal pad and to remove the passivation layer, the oxide film and the dielectric anti-reflectivity coating above the SiNW outside the device area, stopping on the amorphous carbon layer; removing the amorphous carbon layer above the SiNW outside the device area through ashing process to expose the SiNW. | 2013-04-25 |
| 20130102135 | 2DEG SCHOTTKY DIODE FORMED IN NITRIDE MATERIAL WITH A COMPOSITE SCHOTTKY/OHMIC ELECTRODE STRUCTURE AND METHOD OF MAKING THE SAME - A method for manufacturing a semiconductor device includes preparing a base substrate; forming a semiconductor layer on the base substrate; forming an ohmic electrode part having ohmic electrode lines, on the semiconductor layer; and forming a Schottky electrode part, which is disposed on the semiconductor layer to be spaced apart from the ohmic electrode lines and has Schottky electrode lines parallel to the ohmic electrode lines, wherein forming the ohmic electrode part further comprises forming an ohmic electrode plate connected to one end of the ohmic electrode lines, forming the Schottky electrode part further comprises forming a Schottky electrode plate connected one end of the Schottky electrode lines, and one line of the Schottky electrode lines is disposed between two of the ohmic electrode lines to thereby achieve an interdigited configuration in which the ohmic electrode part and the Schottky electrode part are formed. | 2013-04-25 |
| 20130102136 | METHOD OF FORMING AN INTEGRATED CIRCUIT - A method of forming an integrated circuit is disclosed. A second material layer is formed on a first material layer. A patterned mask layer having a plurality of first features with a first pitch P | 2013-04-25 |
| 20130102137 | DOPING METHOD IN 3D SEMICONDUCTOR DEVICE - The present disclosure provides a method to dope fins of a semiconductor device. The method includes forming a first doping film on a first fin and forming a second doping film on the second fin. The first and second doping films include a different dopant type (e.g., n-type and p-type). An anneal process is performed which drives a first dopant from the first doping film into the first fin and drives a second dopant from the second doping film into the second fin. In an embodiment, the first and second dopants are driven into the sidewall of the respective fin. | 2013-04-25 |
| 20130102138 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A method for fabricating a semiconductor device is disclosed. A dummy gate feature is formed between two active gate features in an inter-layer dielectric (ILD) over a substrate. An isolation structure is in the substrate and the dummy gate feature is over the isolation structure. Source/drain (S/D) features are formed at edges of the active gate features in the substrate for forming transistor devices. The disclosed method provides an improved method for reducing parasitic capacitance among the transistor devices. In an embodiment, the improved formation method is achieved by introducing species into the dummy gate feature to increase the resistance of the dummy gate feature. | 2013-04-25 |
| 20130102139 | METHOD FOR MANUFACTURING DOUBLE-GATE STRUCTURES - A method is provided for manufacturing a double-gate structure. The method includes providing a substrate and forming a first gate region on a surface of the substrate using a first gate layer. The method also includes forming a second gate layer on the surface of the substrate, wherein the second gate layer covers the first gate region, forming an etch-stop layer on the second gate layer, and forming a silicide layer on the etch-stop layer. The method also includes forming a second gate region, different from the first gate region, containing the second gate layer and the silicide layer without the etch-stop layer. Further, the etch-stop layer is arranged between the second gate layer and the silicide layer to facilitate even etching of the second gate layer around the first gate region. | 2013-04-25 |
| 20130102140 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. In one aspect, the device has a first and second active layer on a substrate, the second active layer having a higher bandgap than the first active layer, being substantially Ga-free and including at least Al. The device has a gate insulating layer on a part of the second active layer formed by thermal oxidation of a part of the second active layer. The device has a gate electrode on at least a part of the gate insulating layer and a source electrode and drain electrode on the second active layer. The device has, when in operation and when the gate and source electrode are at the same voltage, a two-dimensional electron gas layer between the first and second active layer only outside the location of the gate electrode and not at the location of the gate electrode. | 2013-04-25 |
| 20130102141 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a MOSFET includes the steps of preparing a substrate ( | 2013-04-25 |
| 20130102142 | STRESS MODULATION FOR METAL GATE SEMICONDUCTOR DEVICE - The present disclosure provides a method of semiconductor device fabrication including removing a sacrificial gate structure formed on a substrate to provide an opening. A metal gate structure is then formed in the opening. The forming of the metal gate structure includes forming a first layer (including metal) on a gate dielectric layer, wherein the first layer includes a metal and performing a stress modulation process on the first layer. The stress modulation process may include ion implantation of a neutral species such as silicon, argon, germanium, and xenon. | 2013-04-25 |
| 20130102143 | METHOD OF MAKING A NON-VOLATILE MEMORY CELL HAVING A FLOATING GATE - Forming an NVM structure includes forming a floating gate layer; forming a first dielectric layer over the floating gate layer; forming a plurality of nanocrystals over the first dielectric layer; etching the first dielectric layer using the plurality of nanocrystals as a mask to form dielectric structures, wherein the floating gate layer is exposed between adjacent dielectric structures; etching a first depth into the floating gate layer using the plurality of dielectric structures as a mask to form a plurality of patterned structures, wherein the first depth is less than a thickness of the floating gate layer; patterning the floating gate layer to form a floating gate; forming a second dielectric layer over the floating gate, wherein the second dielectric layer is formed over the patterned structures and on the floating gate layer between adjacent patterned structures; and forming a control gate layer over the second dielectric layer. | 2013-04-25 |
| 20130102144 | METHODS FOR FORMING A METAL GATE STRUCTURE ON A SUBSTRATE - Methods for forming a metal gate structure on a substrate are provided herein. In some embodiments, a method for forming a metal gate structure on a substrate having a dielectric layer formed on the substrate may include depositing a metal layer while providing a process gas comprising oxygen to form an oxygen doped work function layer atop the dielectric layer; and depositing a metal gate layer atop dielectric layer. | 2013-04-25 |
| 20130102145 | METAL GATE PROCESS - A metal gate process includes the following steps. An isolating layer on a substrate is provided, where the isolating layer has a first recess and a second recess. A first metal layer covering the first recess and the second recess is formed. A material is filled in the first recess but exposing a top part of the first recess. The first metal layer in the top part of the first recess and in the second recess is simultaneously removed. The material is removed. A second metal layer and a metal gate layer in the first recess and the second recess are sequentially filled. | 2013-04-25 |
| 20130102146 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR FABRICATING THE SAME - A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via. | 2013-04-25 |
| 20130102147 | Methods of Forming Conductive Structures in Dielectric Layers on an Integrated Circuit Device - One method disclosed herein includes the steps of forming a ULK material layer, forming a hard mask layer above the ULK material layer, forming a patterned photoresist layer above the hard mask layer, performing at least one etching process to define an opening in at least the ULK material layer for a conductive structure to be positioned in at least the ULK material layer, forming a fill material such that it overfills the opening, performing a process operation to remove the patterned photoresist layer and to remove the fill material positioned outside of the opening, removing the fill material from within the opening and, after removing the fill material from within the opening, forming a conductive structure in the opening. | 2013-04-25 |
| 20130102148 | Interconnect Structure for Semiconductor Devices - A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium. | 2013-04-25 |
| 20130102149 | LINER PROPERTY IMPROVEMENT - Methods of forming a dielectric liner layer on a semiconductor substrate are described. The method may include flowing a phosphorus-containing precursor with a silicon-containing precursor and an oxygen-containing precursor over the substrate to deposit a dielectric material. The dielectric material may be deposited along a field region and within at least one via on the substrate having a depth of at least 1 μm. The method may also include forming a liner layer within the via with the dielectric material. The liner may include a silicon oxide doped with phosphorus, and the thickness of the liner layer at an upper portion of the via sidewall may be less than about 5 times the thickness of the liner layer at a lower portion of the via sidewall. | 2013-04-25 |
| 20130102150 | METHOD OF FABRICATING NON-VOLATILE MEMORY DEVICE HAVING SMALL CONTACT AND RELATED DEVICES - A sacrificial pattern is formed to partially cover the pipe-shaped electrode. A sacrificial spacer is formed on a lateral surface of the sacrificial pattern. The sacrificial spacer extends across the pipe-shaped electrode. The sacrificial spacer has a first side and a second side opposite the first side. The sacrificial pattern is removed to expose the pipe-shaped electrode proximal to the first and second sides of the sacrificial spacer. The pipe-shaped electrode exposed on both sides of the sacrificial spacer may be primarily trimmed. The pipe-shaped electrode is retained under the sacrificial spacer to form a first portion, and a second portion facing the first portion. The second portion of the pipe-shaped electrode is secondarily trimmed. The sacrificial spacer is removed to expose the first portion of the pipe-shaped electrode. A data storage plug is formed on the first portion of the pipe-shaped electrode. | 2013-04-25 |
| 20130102151 | METHODS OF MANUFACTURING NAND FLASH MEMORY DEVICES - A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction | 2013-04-25 |
| 20130102152 | SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor manufacturing apparatus includes at least one inner retaining ring, and an outer retaining ring. The at least one inner retaining ring applies a first pressure to the polishing pad, and retains a substrate on the polishing pad. The outer retaining ring applies a second pressure to the polishing pad, and retains the at least one inner retaining ring on the polishing pad. Control of the first pressure is independent with respect to control of the second pressure. | 2013-04-25 |
| 20130102153 | METHOD AND COMPOSITION FOR CHEMICAL MECHANICAL PLANARIZATION OF A METAL OR A METAL ALLOY - A composition and associated method for chemical mechanical planarization of a metal-containing substrate (e.g., a copper substrate) are described herein which afford high and tunable rates of metal removal as well as low dishing and erosion levels during CMP processing. | 2013-04-25 |
| 20130102154 | METHODS AND SYSTEMS FOR REMOVING MATERIALS FROM MICROFEATURE WORKPIECES WITH ORGANIC AND/OR NON-AQUEOUS ELECTROLYTIC MEDIA - Methods and systems for removing materials from microfeature workpieces are disclosed. A method in accordance with one embodiment of the invention includes providing a microfeature workpiece having a substrate material and a conductive material that includes a refractory metal (e.g., tantalum, tantalum nitride, titanium, and/or titanium nitride). First and second electrodes are positioned in electrical communication with the conductive material via a generally organic and/or non-aqueous electrolytic medium. At least one of the electrodes is spaced apart from the workpiece. At least a portion of the conductive material is removed by passing an electrical current along an electrical path that includes the first electrode, the electrolytic medium, and the second electrode. Electrolytically removing the conductive material can reduce the downforce applied to the workpiece. | 2013-04-25 |
| 20130102155 | ICP SOURCE DESIGN FOR PLASMA UNIFORMITY AND EFFICIENCY ENHANCEMENT - An ICP A plasma reactor having an enclosure wherein at least part of the ceiling forms a dielectric window. A substrate support is positioned within the enclosure below the dielectric window. An RF power applicator is positioned above the dielectric window to radiate RF power through the dielectric window and into the enclosure. A plurality of gas injectors are distributed uniformly above the substrate support to supply processing gas into the enclosure. A circular baffle is situated inside the enclosure and positioned above the substrate support but below the plurality of gas injectors so as to redirect flow of the processing gas. | 2013-04-25 |
| 20130102156 | COMPONENTS OF PLASMA PROCESSING CHAMBERS HAVING TEXTURED PLASMA RESISTANT COATINGS - A component of a plasma processing chamber includes a three dimensional body having a highly dense plasma resistant coating thereon wherein a plasma exposed surface of the coating has a texture which inhibits particle generation from film buildup on the plasma exposed surface. The component can be a window of an inductively coupled plasma reactor wherein the window includes a textured yttria coating. The texture can be provided by contacting the plasma exposed surface with a polishing pad having a grit size effective to provide intersecting scratches with a depth of 1 to 2 microns. | 2013-04-25 |
| 20130102157 | ETCHING METHOD AND DEVICE - An etching method can prevent adverse effects of oxygen plasma from arising under an insulating film when etching the insulating film formed on a substrate. The etching method includes: a first etching step for exposing the insulating film to processing gas that has been turned into a plasma to etch the insulating film to a portion in the thickness direction; a deposition material removing step for exposing the insulating film remaining after completion of the first etching to oxygen plasma to remove deposition material deposited on the surface of the remaining insulating film; and a second etching of exposing the remaining insulating film to processing gas that has been turned into a plasma to etch the remaining insulating film. | 2013-04-25 |
| 20130102158 | METHOD, APPARATUS AND COMPOSITION FOR WET ETCHING - A liquid composition for wet etching has improved selectivity for polysilicon over silicon dioxide, even when the polysilicon is heavily doped and/or the silicon dioxide is a low temperature oxide. The composition comprises 0.05-0.4 percent by weight hydrofluoric acid, 15-40 percent by weight nitric acid, 55-85 percent by weight sulfuric acid and 2-20 percent by weight water. A method and apparatus for wet etching using the composition are also disclosed. | 2013-04-25 |
