| 17th week of 2009 patent applcation highlights part 60 |
| Patent application number | Title | Published |
|---|
| 20090106457 | Sequencing control of functions on interacting devices - A method for controlling the sequence of a plurality of functions which are executable on at least two interacting devices is provided, first of the functions being implemented on a first device and the second of the functions being implemented on a second device. A system for implementing the method is provided, including an administrative unit which controls a sequence of the functions in such a manner that it prevents a first function and a second function which interfere with one another from simultaneously running. | 2009-04-23 |
| 20090106458 | IMAGING SYSTEM AND METHOD CAPABLE OF MANAGING FILE TRANSMISSION WITH EXTERNAL DEVICE - An imaging system includes an internal storage unit, a connection unit, a user interface, and a management unit. The internal storage unit is configured for storing a file. The connection unit is configured for connecting the imaging system to an external storage device, and thereby establishing a communication for file transmission therebetween. The user interface is configured for receiving file transmission parameters. The management unit is configured for managing the file transmission, based on the received file transmission parameters. | 2009-04-23 |
| 20090106459 | CONFIGURATION IDENTIFICATION TOOL AND METHODS - A tool for communicating configuration information includes an analysis tool to determine changes to the configuration of an information handling device. The analysis tool develops a set of configuration tags to identify the configuration changes by identifying a subset of tables or other information, such as XML pairs, associated with a configuration management database (CMDB) and by identifying values for each table to reflect the configuration of the information handling device. The analysis tool encodes the configuration tags into an information string. Because the information string is encoded and does not represent the complete configuration of the information handling system configuration, it can be easily and accurately communicated to a technical support center by a user, thereby reducing potential communication problems and improving technical support. | 2009-04-23 |
| 20090106460 | REMOVABLE MEMORY DEVICE, PHASE SYNCHRONIZING METHOD, PHASE SYNCHRONIZING PROGRAM, MEDIUM RECORDING THE SAME, AND HOST TERMINAL - An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time. A removable memory device that transmits/receives data to and from a host terminal, which includes: a clock reception section | 2009-04-23 |
| 20090106461 | Information Processing Apparatus and Information Processing Method - An information processing apparatus comprises a first device and a second device of which each executes the same processing independently, a status acquiring part which acquires a status of the first device, and an event generating part which generates a common event according to the acquired status in the first device and the second device. | 2009-04-23 |
| 20090106462 | METHOD AND CIRCUIT FOR CAPTURING KEYPAD DATA SERIALIZING/DESERIALIZING AND REGENERATING THE KEYPAD INTERFACE - A serializer/deserializer interfacing a keypad or keyboard to a processing system is illustrated. In one application, the processor is arranged to generate keypad scan and input keypad sense lines directly. However, to minimize wires on intervening cables, a serializer and deserializer is inserted between the processor system, the serializer/deserializer forming a virtual keypad. In this case, the processor scans the deserializer as if it were the keypad and the keypad is scanned by the serializer as if it were the processor. However, the serializer converts the scanning of the keypad into a serial bit stream that is sent to the deserializer using only a data line and a clock line. The deserializer accepts the serial bit stream and reconfigures the data into a response that mimics the response of the physical keypad as the computer system scans the virtual keypad, the deserializer. In one embodiment an actual second keypad is formed in the deserializer and activated as the first keypad is activated, wherein the computer scans the second keypad in the usual fashion. | 2009-04-23 |
| 20090106463 | INFORMATION PROCESSING APPARATUS METHOD FOR PROCESSING DATA - An information processing apparatus including: an input unit that allows a user to input operation; an input controller that receives the operation input through the input unit; a data conversion unit that converts console data, which is output from another apparatus used as a serial console, into code data that is recognizable by an operating system; a console data output unit that outputs the console data to the data conversion unit; and a code data output unit that outputs the code data provided by the data conversion unit to the input controller. | 2009-04-23 |
| 20090106464 | Interface Device for Printing From a Host to an Imaging Apparatus Having a Pictbridge Port - An interface device is configured for printing from a host having a communications port to an imaging apparatus having a PictBridge port for receiving print data from a camera. The host includes an operating system having a spool subsystem. The interface device includes an input port configured to communicatively connect to the communications port; an output port configured to communicatively connect to the PictBridge port; and a controller interconnecting the input port and the output port. The controller is configured to execute program instructions to print from the host via the communications port to the imaging apparatus via the PictBridge port in real time using an output of the spool subsystem. | 2009-04-23 |
| 20090106465 | Method of Piggybacking Multiple Data Tenures on a Single Data Bus Grant to Achieve Higher Bus Utilization - An improved method, device and data processing system are presented. In one embodiment, the method includes a source device sending a request for a bus grant to deliver data to a data bus connecting a source device and a destination device. The device receives the bus grant and logic within the device determines whether the bandwidth of the data bus allocated to the bus grant will be filled by the data. If the bandwidth of the data bus allocated to the bus grant will not be filled by the data, the device appends additional data to the first data and delivers the combined data to the data bus during the bus grant for the first data. When the bandwidth of the data bus allocated to the bus grant will be filled by the first data, the device delivers only the first data to the data bus during the bus grant. | 2009-04-23 |
| 20090106466 | DESIGN STRUCTURE FOR PIGGYBACKING MULTIPLE DATA TENURES ON A SINGLE DATA BUS GRANT TO ACHIEVE HIGHER BUS UTILIZATION - A design structure for piggybacking multiple data tenures on a single data bus grant to achieve higher bus utilization is disclosed. In one embodiment of the design structure, a method in a computer-aided design system includes a source device sending a request for a bus grant to deliver data to a data bus connecting a source device and a destination device. The device receives the bus grant and logic within the device determines whether the bandwidth of the data bus allocated to the bus grant will be filled by the data. If the bandwidth of the data bus allocated to the bus grant will not be filled by the data, the device appends additional data to the first data and delivers the combined data to the data bus during the bus grant for the first data. When the bandwidth of the data bus allocated to the bus grant will be filled by the first data, the device delivers only the first data to the data bus during the bus grant. | 2009-04-23 |
| 20090106467 | MULTIPROCESSOR APPARATUS - Disclosed is a multiprocessor apparatus including a co-processor provided in common to a plurality of processors and including a plurality of resources and an arbitration circuit that arbitrates contention among the processors with respect to use of a resource in the co-processor by the processors through a co-processor bus, which is a tightly coupled bus, for each resource or each resource hierarchy according to instructions issued from the processors to the co-processor. Under control by the arbitration circuit, simultaneous use of a plurality of resources on a same hierarchy or different hierarchies in the co-processor by the processors through the tightly coupled bus is allowed. | 2009-04-23 |
| 20090106468 | Hierarchical Bus Structure and Memory Access Protocol for Multiprocessor Systems - A hierarchical bus structure is disclosed in which clusters of processors are arranged and interconnected within a hierarchy to facilitate processor communications via shared memories. The bus structure is well suited for voice processing applications in which clusters of embedded processors process voice streams in parallel, although the architecture is not so limited. Also disclosed is a memory access protocol in which the address and data portions of shared-memory access operations are performed as separate bus transactions that are separated in time, such that multiple concurrent memory access operations from different processors may be interleaved over a shared bus. | 2009-04-23 |
| 20090106469 | SIGNALING AN INTERRUPT REQUEST THROUGH DAISY CHAINED DEVICES - A system and a method for asynchronously signaling interrupts from a plurality of devices in a computing system, while optimizing the latencies in handling the interrupts. In a particular embodiment, an interrupt is signaled via a plurality of daisy chained devices by handing over the interrupt request from one device to another while retaining information regarding any interrupts handed over (also referred to as passed). In this way, the interrupt source can be readily identified (using a binary search, for example) thereby reducing interrupt latency and memory resources required to retain interrupt history. | 2009-04-23 |
| 20090106470 | HOST BUS ADAPTER WITH MULTIPLE HOSTS - A multi-host host bus adapter (HBA) can be connected to multiple host devices to allow the multiple host devices to communicate on a SAN fabric. More specifically, the multi-host HBA provides an interface for multiple SAN hosts without necessitating an HBA on each host, eliminating the need for an on-board HBA on each SAN host. The multi-host HBA interfaces to memory in each SAN host to which it is connected using PCI-Express (or a similar protocol), and communicates with other devices on the SAN fabric using Fibre Channel ports. The multi-host HBA communicates by receiving a command from a connected host, forwarding the command to a processor in the multi-host HBA, and sending the command to a device on a SAN. When the multi-host HBA receives a response from the device on the SAN, the multi-host HBA associates the response with the process and sends the response to the host. | 2009-04-23 |
| 20090106471 | APPARATUS AND METHOD FOR ENUMERATION OF PROCESSORS DURING HOT-PLUG OF A COMPUTE NODE - An apparatus and method for enumeration of processors during hot-plug of a compute node are described. The method includes the enumeration, in response to a hot-plug reset, of one or more processors. The enumeration is provided to a system architecture operating system in which a compute node is hot-plugged. Once enumeration is complete, the compute node is started in response to an operating system activation request. Accordingly, once device enumeration, as well as resource enumeration are complete, the one or more processors of the processor memory node are activated, such that the operating system may begin utilizing the processors of the hot-plugged compute node. | 2009-04-23 |
| 20090106472 | Virtual SATA port multiplier, virtual SATA device, SATA system and data transfer method in a SATA system - A virtual SATA port multiplier and a virtual SATA device are provided for a SATA system. The virtual SATA port multiplier uses a SATA physical layer for data transfer between it and a SATA host, and a non-physical layer for direct data transfer between it and the virtual SATA device. Since the data transfer between the virtual SATA port multiplier and the virtual SATA device is not carried out by way of SATA physical layers, no physical layer circuits are required accordingly, thereby reducing the manufacturing cost, power consumption and hardware size of the SATA system. | 2009-04-23 |
| 20090106473 | CROSSOVER OPERATION IN A 1+1 PROTECTION SWITCHING ENVIRONMENT - A communication unit comprises a first port; a second port, each of the first and second ports configured to transmit signals to and receive signals from another communication unit; a programmable logic unit configured to process signals transmitted and received by the first and second ports; and a processor configured to program the programmable logic unit for crossover operation based on detection of a crossover connection. | 2009-04-23 |
| 20090106474 | Multi-Host USB Device - A USB device may be simultaneously configured and accessed by two or more USB hosts. The USB device may include separate upstream ports and buffers for each host, and a multi-host capable device controller configured to respond to simultaneous USB requests received from more than one host. The USB device may maintain a dedicated address, configuration, and response information for each host. The USB device may include a shared USB function block, and a multi-host controller configured to establish concurrent respective USB connections between the shared USB function block and two or more USB hosts, to allow the two or more USB hosts to simultaneously configure the USB device for the shared USB function. The multi-host controller may be configured to receive and respond to simultaneous respective USB access requests for the shared USB function sent by the two or more USB hosts. | 2009-04-23 |
| 20090106475 | System and Method for Managing Metrics Table Per Virtual Port in a Logically Partitioned Data Processing System - A method, computer program product, and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to track performance and reliability statistics per virtual upstream and downstream port, thereby allowing a system and network management to be performed at finer granularity than what is possible using conventional physical port statistics, is provided. Particularly, a mechanism of managing per-virtual port performance metrics in a logically partitioned data processing system including allocating a subset of resources of a physical adapter to a virtual adapter of a plurality of virtual adapters is provided. The subset of resources includes a virtual port having an identifier assigned thereto. The identifier of the virtual port is associated with an address of a physical port. A metric table is associated with the virtual port, wherein the metric table includes metrics of operations that target the virtual port. | 2009-04-23 |
| 20090106476 | ASSOCIATION OF MULTIPLE PCI EXPRESS LINKS WITH A SINGLE PCI EXPRESS PORT - A method and apparatus for association of multiple PCI Express links with a single PCI Express port. The method includes: connecting a first bus interface component to a second bus interface component with a set of K lanes and set of N lanes, each lane of the set of K lanes and each lane of the set of N lanes consisting of a unidirectional and differentially driven transmitter signal pair and a unidirectional and differentially driven receiver signal pair, wherein K and N are independently whole positive integers equal to or greater than 1. | 2009-04-23 |
| 20090106477 | ASYNCHRONOUS/SYNCHRONOUS KVMP SWITCH FOR CONSOLE DEVICES AND PERIPHERAL DEVICES - A signal switch for sharing a video monitor, a plurality of console devices compliant with an industry standard and one or more than one peripheral device in any of a plurality of computer systems, is provided comprising a CPU with a first memory for storing a management program for managing the signal switch; a hub switch module connected to the CPU and configured to communicate with any of the plurality of computer systems, and the one or more than one peripheral device; a device control module for emulating according to the industry standard the plurality of console devices, connected to the CPU and the hub switch module; a host control module connected to the CPU and configured to communicate with the plurality of console devices; and a video control module connected to the CPU and configured to communicate with a video monitor device. | 2009-04-23 |
| 20090106478 | Managing Memory Systems Containing Components with Asymmetric Characteristics - A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components. | 2009-04-23 |
| 20090106479 | MANAGING MEMORY SYSTEMS CONTAINING COMPONENTS WITH ASYMMETRIC CHARACTERISTICS - A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components. | 2009-04-23 |
| 20090106480 | COMPUTER STORAGE DEVICE HAVING SEPARATE READ-ONLY SPACE AND READ-WRITE SPACE, REMOVABLE MEDIA COMPONENT, SYSTEM MANAGEMENT INTERFACE, AND NETWORK INTERFACE - A storage device for use with a computer is disclosed. The storage device includes a processor communicably connected to a computer through a computer interface and a system interface. The computer interface enables communications exclusively between the processor and the computer, while the system interface enables to processor to manage one or more hardware components of the computer. A network interface is also included to enable the processor to communicate over a network with select file servers to the exclusion of other file servers. A storage means is communicably connected to the processor and includes first and second designated storage sections. The processor has read-write access to both storage sections, while the computer has read-only access to the first storage section and read-write access to the second storage section. A removable media storage component is also communicably connected to the processor. | 2009-04-23 |
| 20090106481 | HYBRID FLASH MEMORY DEVICE - A hybrid memory system is provided that combines the advantages of NAND flash memory devices with the advantages of NOR flashes memory devices. The system includes a NAND flash memory portion to provide mass storage and fast programming/erasure capabilities of conventional NAND flash memory devices. The system further comprises a NOR flash memory portion to provide code storage and fast random reading capabilities of conventional NOR flash memory devices. Accordingly, the hybrid memory system provides both mass storage and code storage. along with fast programming/erasure speeds and fast random access speeds. | 2009-04-23 |
| 20090106482 | MEMORY DEVICE PROGRAM WINDOW ADJUSTMENT - In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes. | 2009-04-23 |
| 20090106483 | SECURE PERSONALIZATION OF MEMORY-BASED ELECTRONIC DEVICES - Systems and/or methods that facilitate programming content to a plurality of nonvolatile memory devices are presented. A wafer program component facilitates programming content to a plurality of memory devices contained on a wafer. The wafer program component can interface with the wafer and can employ parallel processes to program the memory devices on the wafer at substantially the same time. The content programmed to the memory devices can be the same content or different content. A portion of the content can be access-restricted where authentication information is to be provided in order to be granted access to such content, where access-restricted content can include content associated with subscriptions or personal information of a user(s). | 2009-04-23 |
| 20090106484 | DATA WRITING METHOD FOR NON-VOLATILE MEMORY AND CONTROLLER USING THE SAME - A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area. | 2009-04-23 |
| 20090106485 | READING ANALOG MEMORY CELLS USING BUILT-IN MULTI-THRESHOLD COMMANDS - A method for data storage includes storing data in a memory that includes multi-bit analog memory cells, each of which stores at least first and second data bits by assuming one of a predefined plurality of programming levels associated with respective storage values. The memory has at least a first built-in command for reading the first data bits of the memory cells by comparing the storage values of the memory cells to a first number of first thresholds, and a second built-in command for reading the second data bits of the memory cells by comparing the storage values of the memory cells to a second number of second thresholds, such that the first number is less than the second number. After storing the data, the first data bits are read from the memory cells by executing at least the second built-in command. | 2009-04-23 |
| 20090106486 | EFFICIENT PREFETCHING AND ASYNCHRONOUS WRITING FOR FLASH MEMORY - Disclosed herein are a flash file system and an address translation method. The flash file system includes a file system, a Flash Translation Layer (FTL), and flash memory. The FTL receives Local Block Addresses (LBAs) from the file system, and translates the LBAs into Physical Block Address (PBAs. The flash memory receives the resulting PBAs. The FTL includes a memory block in which a multi-stage clustered hash table for mapping the LBAs to the PBAs is stored, and performs the address translation using the clustered hash table. | 2009-04-23 |
| 20090106487 | Electronic Device Having a Memory Element and Method of Operation Therefor - An electronic device comprises a processing unit operably coupled to a buffer random access memory, in turn operably coupled to a non-volatile memory configured to emulate an electrically erasable programmable read only memory. The processing unit is arranged to transfer data between the buffer RAM and the non-volatile memory at a first clock frequency. A second RAM is operably coupled between the processing unit and the non-volatile memory and the processing unit sets a Tag bit in the second RAM to identify an address in the buffer RAM that is being written to or read from by the processing unit. | 2009-04-23 |
| 20090106488 | STATIC RANDOM ACCESS MEMORY (SRAM) COMPATIBLE, HIGH AVAILABILITY MEMORY ARRAY AND METHOD EMPLOYING SYNCHRONOUS DYNAMIC RANDOM ACCESS MEMORY (DRAM) IN CONJUNCTION WITH A DATA CACHE AND SEPARATE READ AND WRITE REGISTERS AND TAG BLOCKS - A high-speed, static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate data read and write registers and tag blocks. The inclusion of separate data read and write registers allows the device to effectively operate at a cycle time limited only by the DRAM subarray cycle time. Further, the inclusion of two tag blocks allows one to be accessed with an externally supplied address and the other to be accessed with a write-back address, thus eliminating the requirement for a single tag to execute two read-modify write cycles in one DRAM cycle time. | 2009-04-23 |
| 20090106489 | Data processing apparatus with shadow register and method thereof - A data processing apparatus comprising a register bank, a shadow register and an arithmetic operation unit is provided. The register bank comprises a number of registers for respectively storing a number of operands, respectively, wherein the registers are n-bit registers, and n is a nature number. The shadow register is for storing first backup operand for making a backup of a first operand, which is stored in a first register among the registers in response to first control signal. The arithmetic operation unit is for performing at least an arithmetic operation on the operands to obtain an operational data, and storing the operational data in the first register in response to an arithmetic operation command. | 2009-04-23 |
| 20090106490 | DATA PROCESSING APPARATUS AND PROGRAM FOR SAME - The present invention provides a data processing apparatus capable of maintaining consistency of specific data without switching between a write-back method and a write-through method. A first microcomputer of an engine ECU performs data updating in the write-back method. In the case of performing data writing process on specific data, the data writing process is performed on dummy data having the same index and a different tag (i.e., a forced write-back). Consequently, the specific data written in a cache memory is evicted from the cache memory immediately by writing of the dummy data and is written in a main-storage RAM. Therefore, without switching the write-back method to the write-through method, the same specific data can be stored in both of the cache memory and the main-storage RAM. | 2009-04-23 |
| 20090106491 | Method for reducing latency in a raid memory system while maintaining data integrity - A latency reduction method for read operations of an array of N disk storage devices ( | 2009-04-23 |
| 20090106492 | Storage apparatus and data storage method using the same - A storage apparatus comprises a disk device and a disk controller for controlling the disk device. The disk controller provides a data volume including an actual volume and virtual volume with a volume capacity virtualization function. The virtual volume is associated with a pool volume for storing the actual data and the actual data is stored in the pool volume. In response to a write command from a host computer, the disk controller compresses write data under RAID 5 control and stores the compressed data in a storage area in the actual volume. If the entire compressed data cannot be stored in that storage area, the disk controller stores the remaining portion of the compressed data in the virtual volume. | 2009-04-23 |
| 20090106493 | INFORMATION PROCESSOR, VIRTUAL DISK MANAGING METHOD, AND COMPUTER-READABLE RECORDING MEDIUM THAT RECORDS DEVICE DRIVER - The present invention claims and discloses an information processor comprising: an auxiliary storing unit that has at least one and preferably two auxiliary storage devices in which at least three distributable virtual disks are formed so as to be distributed; a disk array control unit that controls the at least three distributable virtual disks that designate one of disk control modes; a CB storing unit that stores a control block in each virtual disk that includes but is not limited to first designation information for designating the disk control mode and second designation information for designating an auxiliary storage; and a device driver unit that generates control information of the disk array control unit including but not limited to the first designation information and the second designation information and that transmits the control information to the disk array control unit based on a request for accessing any of the at least three distributable virtual disks and a control block corresponding to the requested virtual disk. | 2009-04-23 |
| 20090106494 | ALLOCATING SPACE IN DEDICATED CACHE WAYS - A system comprises a processor core and a cache coupled to the core and comprising at least one cache way dedicated to the core, where the cache way comprises multiple cache lines. The system also comprises a cache controller coupled to the cache. Upon receiving a data request from the core, the cache controller determines whether the cache has a predetermined amount of invalid cache lines. If the cache does not have the predetermined amount of invalid cache lines, the cache controller is adapted to allocate space in the cache for new data, where the space is allocable in the at least one cache way dedicated to the core. | 2009-04-23 |
| 20090106495 | FAST INTER-STRAND DATA COMMUNICATION FOR PROCESSORS WITH WRITE-THROUGH L1 CACHES - A method is disclosed that uses a non-coherent store instruction to reduce inter-thread communication latency between threads sharing a level one write-through cache. When a thread executes the non-coherent store instruction, the level one cache is immediately updated with the data value. The data value is immediately available to another thread sharing the level-one write-through cache. A computer system having reduced inter-thread communication latency is disclosed. The computer system includes a first plurality of processor cores, each processor core including a second plurality of processing engines sharing a level one write-through cache. The level one caches are connected to a level two cache via a crossbar switch. The computer system further implements a non-coherent store instruction that updates a data value in the level one cache prior to updating the corresponding data value in the level two cache. | 2009-04-23 |
| 20090106496 | UPDATING CACHE BITS USING HINT TRANSACTION SIGNALS - A system comprises processing logic that issues a request associated with an address. The system comprises a first cache that comprises a plurality of line frames. Each line frame has a status bit indicative of how recently that line frame has been accessed. The system comprises a second cache comprising another line frame having another status bit that is indicative of how recently the another line frame has been accessed. The another line frame comprises data other than the another status bit. If one of the plurality of line frames comprises the data associated with the address and the status bit associated with the one of the plurality of line frames is in a predetermined state, the first cache generates a hint transaction signal which is used to update the another status bit. The hint transaction signal does not cause the data to be updated. | 2009-04-23 |
| 20090106497 | Apparatus, processor and method of controlling cache memory - An apparatus includes a processor which issues a plurality of commands including an identifier for classifying each of the commands, a cache memory which includes a plurality of ways to store a data corresponding to a command, wherein the cache memory includes a register to store the identifier, the register corresponding to at least one of the ways being fixed, the fixed way exclusively storing the data corresponding to the identifier during which the register stores the identifier, a replacement controller which selects a replacement way based on a predetermined replacement algorithm in case of a cache miss, and excludes the fixed way from a candidate of the replacement way when the register corresponding to the fixed way stores the identifier. | 2009-04-23 |
| 20090106498 | COHERENT DRAM PREFETCHER - A system and method for obtaining coherence permission for speculative prefetched data. A memory controller stores an address of a prefetch memory line in a prefetch buffer. Upon allocation of an entry in the prefetch buffer a snoop of all the caches in the system occurs. Coherency permission information is stored in the prefetch buffer. The corresponding prefetch data may be stored elsewhere. During a subsequent memory access request for a memory address stored in the prefetch buffer, both the coherency information and prefetched data may be already available and the memory access latency is reduced. | 2009-04-23 |
| 20090106499 | Processor with prefetch function - Non-speculatively prefetched data is prevented from being discarded from a cache memory before being accessed. In a cache memory including a cache control unit for reading data from a main memory into the cache memory and registering the data in the cache memory upon reception of a fill request from a processor and for accessing the data in the cache memory upon reception of a memory instruction from the processor, a cache line of the cache memory includes a registration information storage unit for storing information indicating whether the registered data is written into the cache line in response to the fill request and whether the registered data is accessed by the memory instruction. The cache control unit sets information in the registration information storage unit for performing a prefetch based on the fill request and resets the information for accessing the cache line based on the memory instruction. | 2009-04-23 |
| 20090106500 | Method and Apparatus for Managing Buffers in a Data Processing System - A buffer management for a data processing system is provided. According to one embodiment, a method for managing buffers in a telephony device is provided. The method comprising providing a plurality of buffers stored in a memory, providing a cache having a pointer pointing to the buffer, scanning the cache to determine if the cache is full, and when the scan determines the cache is not full determining a free buffer from the plurality of buffers, generating a pointer for the free buffer, and placing the generated pointer into the cache. | 2009-04-23 |
| 20090106501 | Data cache management mechanism for packet forwarding - There is provided a method of managing a cache memory. The method comprising resetting a flag indicative of lack of incoming data for generating a packet for forwarding; receiving the incoming data; storing the incoming data in the main memory; transferring the incoming data from the main memory into a cache buffer within the cache memory, the cache buffer having a buffer size; setting the flag indicative of the incoming data received for generating the packet for forwarding; processing the incoming data to generate the packet in the cache buffer for forwarding, the packet having a packet size; writing back the packet from the cache buffer into the main memory; first invalidating a portion of the cache buffer; transmitting the packet after the first invalidating; and second invalidating, after the transmitting, the cache buffer for the buffer size if the flag is not set by the setting. | 2009-04-23 |
| 20090106502 | Translation lookaside buffer snooping within memory coherent system - A node of a multiple-node system includes a translation lookaside buffer (TLB), a cache, and a TLB snoop mechanism. The node shares memory with other nodes of the multiple-node systems, and is connected with the other nodes via a bus. The TLB snooping mechanism snoops inbound memory access requests and/or outbound memory access requests. Inbound requests are received from over the bus and are intended for the cache. However, the cache receives only the inbound requests that relate to memory addresses having associated entries within the TLB. Outbound requests are received from within the node and are intended for transmission over the bus. However, the bus coherently transmits only the outbound requests that relate to memory addresses that are part of memory pages having set shared-memory page memory flags. All other outbound memory access requests are sent over the bus non-coherently. | 2009-04-23 |
| 20090106503 | Method, device, and system for preventing refresh starvation in shared memory bank - A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register. | 2009-04-23 |
| 20090106504 | Memory system and method for operating a memory system - A memory system, in particular a buffered memory system, e.g., a fully buffered memory system, a method for operating a memory system, and a device for use with a memory system is disclosed. The memory system may include a first buffered memory module, and a second buffered memory module, wherein the first and the second buffered memory modules are adapted to be accessed in parallel. According to a further embodiment of the invention, a device is provided which is adapted to map consecutive accesses to the first or the second memory module to a parallel access of both the first and the second memory module. | 2009-04-23 |
| 20090106505 | DIGITAL MEMORY WITH FINE GRAIN WRITE OPERATION - Methods, systems, and apparatus for operating digital memory including determining, by a controller, a bit to be written to the digital memory and writing, by the controller, the bit. The bit may be part of a data word comprising a plurality of bits and both the determining and the writing may be performed at a granularity level finer than a data word. In embodiments, the bit to be written may be determined by error correction. | 2009-04-23 |
| 20090106506 | Method and Apparatus for Memory Access Optimization - Access to a memory is optimized by monitoring physical memory addresses and by detecting a memory access conflict based on the monitored physical memory addresses. The data stored at a physical address for which a conflict was detected is transferred to a new physical address. | 2009-04-23 |
| 20090106507 | Memory System and Method for Using a Memory System with Virtual Address Translation Capabilities - A memory system comprises a first memory having associated therewith a first local memory access controller configured to access the first local memory using physical memory addresses and a second memory having associated therewith a second local memory access controller configured to access the second local memory using physical memory addresses. A global controller coupled to the first and second local controllers is configured to communicate virtual memory addresses to the first and second local memory controllers. | 2009-04-23 |
| 20090106508 | DIGITAL MEMORY WITH CONTROLLABLE INPUT/OUTPUT TERMINALS - Methods and apparatus for controlling an input/output (I/O) driver of an I/O terminal based at least in part on the values being provided to the I/O terminal is disclosed. In various embodiments, a detector is employed. The detector shuts off power to the I/O driver if the digital value being presented is the same as a previously presented digital value. | 2009-04-23 |
| 20090106509 | MEMORY SYSTEM AND METHOD OF DRIVING THE SAME - Provided are a memory system and a method of driving the same. The method includes setting microcodes in a top control sequencer and multiple channel control sequencers, and executing the microcode set in the top control sequencer. The method may further include checking execution results of the microcode. | 2009-04-23 |
| 20090106510 | Controlling Replication of Data Among Storage Devices - A control apparatus connected to different types of storage devices include a performance-information storing section that stores performance information on the storage devices; a list storing section that stores a list of data on the storage devices; a monitoring section that monitors the load statuses of the storage devices and the control apparatus; a detecting section; an estimating section; and a determining section. | 2009-04-23 |
| 20090106511 | Methods and systems for fragments retrieval from a type based push to storage system - Methods and systems for fragments retrieval from a type based push to storage system. One method includes the steps of receiving fragment-to-type association information and type-to-physical-address association information of a content comprising a plurality of content fragments distributed among a plurality of storage-and-computing elements; and providing at least one storage-and-computing element physical address for each of the content fragments to be retrieved. | 2009-04-23 |
| 20090106512 | HISTOGRAM GENERATION WITH MIXED BINNING MEMORY - Memory is divided up during the gathering of histogram data so that a portion of the memory is configured for storing the high counts expected at the minimum and maximum codes/addresses, and at least one other portion is configured for storing the lower counts expected at other codes/addresses. By configuring memory portions in this manner, memory can be more efficiently allocated. | 2009-04-23 |
| 20090106513 | Method for copying data in non-volatile memory system - A method for copying data in a non-volatile memory system is disclosed. The method includes calculating a number of errors of a first set of data from a source block of the non-volatile memory saved in the buffer of the controller, transmitting the first set of data saved in the buffer of the controller to a buffer of the non-volatile memory when the number of errors is lower than a threshold, and programming a destination block of the non-volatile memory with the first set of data saved in the buffer of the non-volatile memory when the number of errors is lower than the threshold. | 2009-04-23 |
| 20090106514 | METHOD FOR PROTECTING DATA AND METHOD FOR MANAGING ACCESS AUTHORITY - A method for protecting data, adapted for a computer system, is provided. The computer system includes a storage device. The method includes: when the computer system executes a power-off procedure, inspecting whether a preset external storage device is connected to the computer system; if it is determined that the preset external storage device is connected to the computer system, when the computer system executes the power-off procedure, backing up data of a predetermined segment of the storage device to the preset external storage device, and generating a back-up data, and then writing a specific data template to the predetermined segment for covering original data of the predetermined segment. | 2009-04-23 |
| 20090106515 | System and Method for Replicating Data - According to the present invention, techniques for controlling copying of logical volumes within a computer storage system are provided. A representative embodiment includes a plurality of storage devices controlled by a control unit, one or more processors, and a buffer memory for temporarily storing data read from the storage devices within the control unit. The storage devices can be addressed as logical volumes. | 2009-04-23 |
| 20090106516 | METHOD AND APPARATUS FOR PREVENTING ERRONEOUS WRITING OF DATA - A method for preventing erroneous writing of data includes the steps of: providing a memory positioned in a writing protection state, connecting the memory to a host computer installed with a control program, using the control program to control the memory to remove the writing protection state and writing external data into the memory. Whereby, the erroneous writing of the external data is prevented and the safety of internal data of the memory is protected accurately. | 2009-04-23 |
| 20090106517 | DATA PROTECTION METHOD - A data protection method for an electronic device having a storage medium is provided, wherein the storage medium includes a plurality of partitions and a partition table. In the data protection method, a partition entry point and a partition data corresponding to the specific partition are captured and sent to an external storage device when the electronic device enters a shutdown process. Then, the partition entry point is deleted from the partition table and the partition data is removed from the storage medium. When the electronic device is turned on, a user has to provide the corresponding external storage device to restore the partition entry point and the partition data back to the storage medium. Thereby, personal data stored in the storage medium is protected and accordingly data security is ensured. | 2009-04-23 |
| 20090106518 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR FILE RELOCATION ON A DATA STORAGE DEVICE - A method, system, and computer program product for file relocation on a data storage device are provided. The method includes initiating file relocation in response to invoking a cleaner function for a data storage device. The method also includes examining metadata associated with a file on the data storage device to determine an access frequency of the file, and classifying the file as a function of the access frequency. The method further includes relocating the file to a fast region of the data storage device when the file is classified as frequently accessed, and relocating the file to a slow region of the data storage device when the file is classified as infrequently accessed. | 2009-04-23 |
| 20090106519 | Storage Device and Method of Accessing a Status Thereof - A storage device and a method of accessing a status thereof are provided. The storage device is disposed in a host. The device data structure field of the storage device is adapted to record the status of the non-volatile memory. The control module is adapted to access the status according to a control signal from the host. Therefore, the operating system or the application of the host is capable of getting the status of the non-volatile memory to ensure the safety of the stored data. | 2009-04-23 |
| 20090106520 | DATA PROCESSING CIRCUIT WITH MULTIPLEXED MEMORY - A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted. The time point at which the particular request is accepted is always within the validity duration interval in which the particular access request is made. The timing circuit varies the position of the acceptance time points within the validity duration intervals, so that the position is delayed to make room for previously accepting an access request from another processor. The position is subsequently moved back toward a start of the validity duration interval in successive steps during application of successive access requests from the first data processing circuit. | 2009-04-23 |
| 20090106521 | MULTIVALUE STATISTICAL COMPRESSION OF TELEMETRIC TIME SERIES DATA IN A BOUNDED STORAGE FOOTPRINT - Some embodiments of the present invention provide a system that stores telemetry data from a computer system. The system includes a first buffer, a second buffer, and a third buffer. During operation, the system periodically obtains the telemetry data from the computer system and stores the telemetry data in the first buffer, second buffer, and third buffer. The system also compresses the telemetry data in the first and second buffers. To compress the data, the system creates a first set of summary statistics from the telemetry data in the first buffer and the second buffer and stores the first set of summary statistics in the first buffer, which becomes a historical data buffer. | 2009-04-23 |
| 20090106522 | ELECTRONIC SYSTEM WITH DYNAMIC SELECTION OF MULTIPLE COMPUTING DEVICE - An electronic system is provided including powering a computing integrated circuit device having a first processor device and a second processor device; generating an address transform for the first processor device and the second processor device; operating a software code having a first processor address for the first processor device and a second processor address for the second processor device with the software code provides a display or actuates a mechanic device; mapping the first processor address with the address transform to the second processor address; and reconfiguring the address transform. | 2009-04-23 |
| 20090106523 | TRANSLATION LOOK-ASIDE BUFFER WITH VARIABLE PAGE SIZES - Multiple pipelined Translation Look-aside Buffer (TLB) units are configured to compare a translation address with associated TLB entries. The TLB units operated in serial order comparing the translation address with associated TLB entries until an identified one of the TLB units produces a hit. The TLB units following the TLB unit producing the hit might be disabled. | 2009-04-23 |
| 20090106524 | METHODS FOR ACCESSING MULTIPLE PAGE TABLES IN A COMPUTER SYSTEM - A virtual memory system implementing the invention provides concurrent access to translations for virtual addresses from multiple address spaces. One embodiment of the invention is implemented in a virtual computer system, in which a virtual machine monitor supports a virtual machine. In this embodiment, the invention provides concurrent access to translations for virtual addresses from the respective address spaces of both the virtual machine monitor and the virtual machine. Multiple page tables contain the translations for the multiple address spaces. Information about an operating state of the computer system, as well as an address space identifier, are used to determine whether, and under what circumstances, an attempted memory access is permissible. If the attempted memory access is permissible, the address space identifier is also used to determine which of the multiple page tables contains the translation for the attempted memory access. | 2009-04-23 |
| 20090106525 | DESIGN STRUCTURE FOR SCALAR PRECISION FLOAT IMPLEMENTATION ON THE "W" LANE OF VECTOR UNIT - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for image processing, and more specifically to vector units for supporting image processing is provided. A combined vector/scalar unit is provided wherein one or more processing lanes of the vector unit are used for performing scalar operations. An integrated register file is also provided for storing vector and scalar data. Therefore, the transfer of data to memory to exchange data between independent vector and scalar units is obviated and a significant amount of chip area is saved. | 2009-04-23 |
| 20090106526 | Scalar Float Register Overlay on Vector Register File for Efficient Register Allocation and Scalar Float and Vector Register Sharing - Embodiments of the invention are generally related to image processing, and more specifically to register files for supporting image processing. An integrated register file is also provided for storing vector and scalar data. Therefore, the transfer of data to memory to exchange data between independent vector and scalar units is obviated. | 2009-04-23 |
| 20090106527 | Scalar Precision Float Implementation on the "W" Lane of Vector Unit - Embodiments of the invention are generally related to image processing, and more specifically to vector units for supporting image processing. A combined vector/scalar unit is provided wherein one or more processing lanes of the vector unit are used for performing scalar operations. An integrated register file is also provided for storing vector and scalar data. Therefore, the transfer of data to memory to exchange data between independent vector and scalar units is obviated and a significant amount of chip area is saved. | 2009-04-23 |
| 20090106528 | Parallel Image Processing System Control Method And Apparatus - To reduce the required amount of program codes when processing the whole image in a one-dimensional SIMD parallel image processing system having a smaller number of PEs than the number of pixels in the width direction of the image to be processed. A controller for controlling a PE array includes a command repetitive-execution part, which includes an operand converting part, a memory address converting part, and an operation code converting part. When a command fetching/decoding part reads and executes program codes stored in a program memory, the repetitive-execution part determines the program codes to cause the operand converting part, memory address converting part and operation code converting part to perform conversions in accordance with the command, thereby performing a repetitive execution of the one-command program description adaptive to a plurality of related pixels assigned to the PEs, whereby the program code amount can be reduced. | 2009-04-23 |
| 20090106529 | FLATTENED BUTTERFLY PROCESSOR INTERCONNECT NETWORK - A multiprocessor computer system comprises a folded butterfly processor interconnect network, the folded butterfly interconnect network comprising a traditional butterfly interconnect network derived from a butterfly network by flattening routers in each row into a single router for each row, and eliminating channels entirely local to the single row. | 2009-04-23 |
| 20090106530 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR GENERATING A RAY TRACING DATA STRUCTURE UTILIZING A PARALLEL PROCESSOR ARCHITECTURE - A system, method, and computer program product are provided for generating a ray tracing data structure utilizing a parallel processor architecture. In operation, a global set of data is received. Additionally, a data structure is generated utilizing a parallel processor architecture including a plurality of processors. Such data structure is adapted for use in performing ray tracing utilizing the parallel processor architecture, and is generated by allocating the global set of data among the processors such that results of processing of at least one of the processors is processed by another one of the processors. | 2009-04-23 |
| 20090106531 | FIELD PROGRAMMABLE GATE ARRAY AND MICROCONTROLLER SYSTEM-ON-A-CHIP - A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core. | 2009-04-23 |
| 20090106532 | RAPID CREATION AND CONFIGURATION OF MICROCONTROLLER PRODUCTS WITH CONFIGURABLE LOGIC DEVICES - Methods and apparatus suitable for rapid creation and configuration of microcontroller products, which include a microcontroller or similar computational resource, and configurable logic devices are described. Various embodiments of the present invention allow development of new microcontroller-based products and product families in a rapid and cost-effective manner, thereby enabling early entry of such products into the marketplace. An existing microcontroller block and existing configurable logic devices are combined to form a unique product, wherein the microcontroller block is operable to configure the configurable logic devices to form the desired unique hardware characteristics of the microcontroller-based product. The microcontroller block configures the configurable logic devices when the product is reset, and/or when a power-up condition is recognized. | 2009-04-23 |
| 20090106533 | DATA PROCESSING APPARATUS - The data processing apparatus includes two or more execution resources, each enabling a predetermined process for executing an instruction. The execution resources enable a pipeline process. Each execution resource treats instructions according to an in-order system following the instructions' flow order in case that the execution resource is in charge of the instructions. Also, each execution resource treats instructions according to an out-of-order system regardless of the instructions' flow order in case that the instructions are treated by different execution resources. Thus, local processes in the execution resources can be simplified and materialized in a small-scale of hardware. Consequently, the need for the whole synchronization in processing across execution resources is eliminated, and the locality of processes and the efficiency of electric power are increased. | 2009-04-23 |
| 20090106534 | System and Method for Implementing a Software-Supported Thread Assist Mechanism for a Microprocessor - A system and computer-implementable method for implementing software-supported thread assist within a data processing system, wherein the data processing system supports processing instructions within at least a first thread and a second thread. An instruction dispatch unit (IDU) places the first thread into a sleep mode. The IDU separates an instruction stream for the second thread into at least a first independent instruction stream and a second independent instruction stream. The first independent instruction stream is processed utilizing facilities allocated to the first thread and the second independent instruction stream is processed utilizing facilities allocated to the second thread. In response to determining a result of the processing in the first independent instruction stream requires write back to registers allocated to the second thread, the IDU sets at least one selection bit to enable selective copying of content within registers allocated to the first thread to registers allocated to the second thread. | 2009-04-23 |
| 20090106535 | SHARED PROCESSOR ARCHITECTURE APPLIED TO FUNCTIONAL STAGES CONFIGURED IN A RECEIVER SYSTEM FOR PROCESSING SIGNALS FROM DIFFERENT TRANSMITTER SYSTEMS AND METHOD THEREOF - According to an embodiment of the present invention, a shared processor architecture in a receiver system is disclosed. The receiver system is configured to have a first functional stage and a second functional stage for processing information carried by signals from a first transmitter system and a second transmitter system respectively. The first functional stage and the second functional stage correspond to an identical signal processing function. The shared processor architecture includes a first processor, allocated to the first functional stage and the second functional stage, for processing an output generated from the first functional stage or an output from the second functional stage. | 2009-04-23 |
| 20090106536 | Processor for executing group extract instructions requiring wide operands - A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers. | 2009-04-23 |
| 20090106537 | PROCESSOR SUPPORTING VECTOR MODE EXECUTION - An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to execute multiple instances of a bundle, representing multiple iterations of the bundle in a vector run. Scheduling logic determines whether, for each bundle, multiple instances can be executed in parallel. If multiple instances can be executed in parallel, coupling circuitry couples an instance of the bundle from one lane into one or more other lanes. In each lane, register addresses are renamed to ensure proper execution of the bundles in the vector run. Additionally, the processor may include a register bank separate from the architectural register file. Renaming logic can generate addresses to this separate register bank that are longer than used to address architectural registers, allowing longer vectors and more efficient processor operation. | 2009-04-23 |
| 20090106538 | System and Method for Implementing a Hardware-Supported Thread Assist Under Load Lookahead Mechanism for a Microprocessor - The present invention includes a system and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor. According to an embodiment of the present invention, hardware thread-assist mode can be activated when one thread of the microprocessor is in a sleep mode. When load lookahead mode is activated, the fixed point unit copies the content of one or more architected facilities from an active thread to corresponding architected facilities in the first inactive thread. The load-store unit performs at least one speculative load in load lookahead mode and writes the results of the at least one speculative load to a duplicated architected facility in the first inactive thread. | 2009-04-23 |
| 20090106539 | METHOD AND SYSTEM FOR ANALYZING A COMPLETION DELAY IN A PROCESSOR USING AN ADDITIVE STALL COUNTER - In a data processing system having a set of components for performing a set of operations, in which one or more of the set of operations has processing dependencies with respect to other of the set of operations, a method for using an additive stall counter to analyze a completion delay is disclosed. The method includes initiating execution of a group of instructions and a performance monitor unit resetting a value stored within the additive stall counter. The method further includes the performance monitor unit incrementing the value within the additive stall counter until all instructions within the group of instructions complete. In response to all instructions within the group of instructions completing a cause of the completion delay is determined. In response to determining that the delay was caused by the first stall cause, the value stored within the additive stall counter is added to a first performance monitor counter designated for the first stall cause, and, in response to determining that the delay was caused by a second stall cause, the value stored within the additive stall counter is added to a second performance monitor counter designated for the second stall cause. | 2009-04-23 |
| 20090106540 | APPARATUS AND METHOD FOR REMANIPULATING INSTRUCTIONS - An apparatus for modifying instructions of a machine readable program according to remanipulation rules includes a remanipulation unit, which is configured to identify a manipulated instruction and to remanipulate the manipulated instruction according the remanipulation rules. The apparatus further includes a processor unit configured to process a predetermined instruction set, wherein the predetermined instruction set includes manipulated instructions and remanipulated instructions. | 2009-04-23 |
| 20090106541 | PROCESSORS WITH BRANCH INSTRUCTION, CIRCUITS, SYSTEMS AND PROCESSES OF MANUFACTURE AND OPERATION - An electronic processor is provided for use with a memory ( | 2009-04-23 |
| 20090106542 | AUTONOMIC COMPUTER CONFIGURATION BASED ON LOCATION - A system and apparatus for noticing and creating relational settings, actions, profiles, and tasks by tying resources to a location based on user behavior. | 2009-04-23 |
| 20090106543 | BOOT BLOCK FEATURES IN SYNCHRONOUS SERIAL INTERFACE NAND - Embodiments are provided for protecting boot block space in a NAND memory device connected to a host device via an SPI interface. One such method includes programming a boot block password into the NAND memory device such that the host device is required to provide the boot block password in order to access the boot block space. A counter may be provided to track the number of times the host device provides an incorrect password, permanently locking the boot block space if the counter reaches a predetermined value. A further method includes associating each of various areas of the boot block space with at least one write lock bit, setting the write lock bit to a lock enable or lock disable value, and locking or unlocking an area of the boot block space depending on the value of its associated write lock bit. Areas of the boot block space may include a single boot block page, a single boot block, or a plurality of boot blocks. | 2009-04-23 |
| 20090106544 | FUNCTION MANAGEMENT SYSTEM AND METHOD - A function management system includes a power source, an electronic switch, a plurality of function modules, and a function management module. The power source is for supplying power. The electronic switch is for controlling the power to the function management system. The function modules are for executing various functions. The function management module is for storing a plurality of sub boot-up programs corresponding to the function modules. Each sub boot-up program is used for booting up a corresponding function module. A function management method is also provided. | 2009-04-23 |
| 20090106545 | BOOTING METHOD FOR COMPUTER SYSTEM - A booting method for a computer system with a keyboard and a central processing unit (CPU). In the present method, the keyboard is initialized first. After that, the CPU is initialized in turn. Finally, other hardware devices of the computer system are initialized. The method modifies the order of the hardware initializations so as to determine whether to use system default values or BIOS setup values set by a user to do the initializations based on an input signal received by the keyboard before initializing the CPU. As a result, the situation of using the incorrect BIOS setup values for initializations, which leads to failure in booting the computer system, can be avoided. | 2009-04-23 |
| 20090106546 | Method and Software System for Configuring a Modular System - In order particularly easily and flexibly to configure a system including at least one module, a method has the following steps: creation of at least one implementation-independent configuration data file and/or modification of information stored in the at least one implementation-independent configuration data file; automatic setup and/or automatic update of configuration data, stored in a configuration data container, as a function of the information stored in the at least one implementation-independent configuration data file; automatic configuration of at least one module as a function of the stored in the configuration data container. | 2009-04-23 |
| 20090106547 | AUTHENTICATION SYSTEM, AUTHENTICATION DEVICE, TERMINAL, AND VERIFYING DEVICE - An authentication system, including a service use device | 2009-04-23 |
| 20090106548 | METHOD FOR CONTROLLING SECURED TRANSACTIONS USING A SINGLE PHYSICAL DEVICE, CORRESPONDING PHYSICAL DEVICE, SYSTEM AND COMPUTER PROGRAM - A method is provided for controlling secure transactions using a physical device held by a user and bearing at least one pair of asymmetric keys, including a device public key and a corresponding device private key. The method includes, prior to implementing the physical device, certifying the device public key with a first certification key of a particular certifying authority, delivering a device certificate after verifying that the device private key is housed in a tamper-proof zone of the physical device; verifying the device certificate by a second certification key corresponding to the first certification key; and in case of a positive verification, registering the user with a provider delivering a provider certificate corresponding to the signature by the provider of the device public key and an identifier of the user. | 2009-04-23 |
| 20090106549 | METHOD AND SYSTEM FOR EXTENDING ENCRYPTING FILE SYSTEM - Users can share encrypted files without having access to other users' public key certificates, by specifying only the other users' identity information. A client agent interacts with a trusted service account to transparently add user encryption certificates to encrypted files after it was created. A header of each encrypted file includes signed encrypted data blocks, file system metadata, and a digital signature. When a user attempting to open an encrypted file is denied access, the client agent transmits the header data and the encryption certificate of the user to the trusted service account, with a request that the user encryption certificate be added to modify the encrypting file system metadata. After the trusted service account determines tampering has not occurred enroute and the user is authorized to access the file, the modified header data are returned to the client agent to enable the user to open the file. | 2009-04-23 |
| 20090106550 | EXTENDING ENCRYPTING WEB SERVICE - A data encryption service is provided over the Internet. Users specifying only authorized users' identity information can share encrypted information without sharing passwords or accessing public key certificates. A user sends data to be encrypted to a trusted EWS, along with authorization information. An encrypted data envelope including signed encrypted data blocks, authorization information, and a digital signature is returned to the user. When a second user attempts to access the data inside the encrypted data envelope, it is transmitted to the EWS. If the EWS authenticates the second user, determines that tampering has not occurred, and verifies the second user's identity against the authorization information in the data envelope, then the data are returned. The encrypted data envelope can be expressed as a raw byte stream or encoded within an HTML file to enable browser-based data envelope submission and retrieval. | 2009-04-23 |
| 20090106551 | DYNAMIC DISTRIBUTED KEY SYSTEM AND METHOD FOR IDENTITY MANAGEMENT, AUTHENTICATION SERVERS, DATA SECURITY AND PREVENTING MAN-IN-THE-MIDDLE ATTACKS - A distributed key encryption system and method is provided in which a key storage server provides a session key to the source and destination computers by encrypting the session key with unique distributed private keys that are associated with the respective source and destination computers by unique private key identifiers The destination computer then decrypts the encrypted session key using it's distributed private key and then decrypts the communication using the decrypted session key. | 2009-04-23 |
| 20090106552 | RIGHTS MANAGEMENT SERVICES-BASED FILE ENCRYPTION SYSTEM AND METHOD - A method to leverage Windows Rights Management Services (RMS) to provide protection and sharing of encryption keys to file systems. Windows Rights Management Services (RMS) that enables users to share protected content without having to exchange encryption certificates or passwords. Using the method any EFS can be extended to protect its FEKs and assign it user access rights using RMS. This enables EFSs to delegate key sharing, management and recovery to the RMS system. User rights to FEKs are derived from files security descriptor information or as explicitly specified by users. Whenever an encrypted file is created its FEK is protected using RMS and the resulting byte stream is stored in the file encryption metadata information. When a user tries to access an encrypted file and doesn't have a private key to decrypt the FEK, the EFS transparently extracts the RMS protected byte stream from the file encryption metadata information. It then uses RMS to try and obtain access to the FEK stored in the bytes stream using the user security context. If the user is authorized access and the FEK is successfully obtained then EFS is able to decrypt the file data and the user is granted access. The FEK is protected with the user master key, encryption certificate or password and cached in the system protected non-page memory or local stable storage. This enables the system to reuse the FEK for the user on the next file access. If the user doesn't hold rights to extract the FEK then the user is denied access. | 2009-04-23 |
| 20090106553 | METHOD AND SYSTEM UTILIZING QUANTUM AUTHENTICATION - A system and a method with quantum cryptography authentication. The system includes an optical link connecting a sender and a receiver. The sender transmitting a first optical pulse and a second optical pulse having a defined time delay therebetween. The first pulse is modulated with a first authentication phase shift; and the second pulse is modulated with phases selected from one basis of two non-orthogonal bases, and encoded with one of two orthogonal states within the one basis based on an information of the sender, and with a second authentication phase shift. The receiver includes a splitter receiving and splitting the first and the second pulse into pulses of interest. The split pulses of interest are modulated with the first authentication phase shift; and the second authentication phase shift, respectively. The receiver includes a second coupler whereby the split pulses of interest arrive at the second coupler simultaneously. The receiver includes a first set of detectors receiving the combined pulses, which determine the one basis of the two non-orthogonal bases; and a second set of detectors receiving the combined pulses, and determine the one of the two orthogonal states within the basis and thereby decoding the information of the sender. | 2009-04-23 |
| 20090106554 | E-MAIL RELAY APPARATUS AND E-MAIL RELAY METHOD - An e-mail relay apparatus notifies a user of which e-mail could not be transmitted if a transmission error has occurred, without consuming a memory capacity. When an e-mail transmission instruction is received and after header information of the received e-mail is stored, a digital signature is added to the e-mail, and the e-mail text is encrypted. Then, after the digital signature is added, the encrypted e-mail is stored, and after the original e-mail is deleted, the transmission of the e-mail is started. If an error has occurred during the e-mail transmission and the transmission has failed, an error-notifying mail addressed to a transmission source is generated. After a header file of the e-mail is attached to the error-notifying mail, the error-notifying mail to which the header file is attached is stored in a mail box for the user of the transmission source. | 2009-04-23 |
| 20090106555 | System and Method For Control Of Security Configurations - Systems and methods are disclosed for using cryptographic techniques to configure data processing systems. A configuration manager cryptographically controls the configuration of a system by ensuring that only authorized users or applications can change the configuration. For example, requests to change configuration information may include authenticated and/or encrypted data. These cryptographic techniques are employed to enable and/or disable functions, features and capabilities of a system. For example, a system may be reconfigured to provide strong or weak encryption based on parameters in the configuration information. | 2009-04-23 |
| 20090106556 | Method of providing assured transactions using secure transaction appliance and watermark verification - Disclosed is a method of improving electronic security by establishing a path between a user and a secure transaction appliance. The secure transaction appliance receiving information destined for the user which includes a tagged portion, said tagged portion triggering the secure transaction appliance to forward the information to the computer from which the request was issued, and to seeking an electronic signature to verify the content or transaction by transmitting a watermark, tagged portion of the content, or similar electronic content. The secure trusted path providing the user with the tagged portion incorporating additional elements such as a watermark, or in some embodiments only the additional elements, upon a personalized security device associated with the user making interception or manipulation more complex and difficult. | 2009-04-23 |
