| 16th week of 2010 patent applcation highlights part 37 |
| Patent application number | Title | Published |
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| 20100096581 | METHOD AND ARRANGEMENT FOR SEPARATING MAGNETIC PARTICLES, MAGNETIC PARTICLES AND USE MAGNETIC PARTICLES - A method and an arrangement for separating magnetic particles, magnetic particles and the use of magnetic particles are disclosed wherein the method comprises the steps of: —subjecting the magnetic particles to a first magnetic field such that the particle direction of easy magnetization is oriented parallel to the magnetic field vector of the first magnetic field, —subjecting the magnetic particles to a second magnetic field having an orientation rotated about an angle relative to the magnetic field vector of the first magnetic field, —applying a separating force on the magnetic particles. | 2010-04-22 |
| 20100096582 | Magnetic rubber composition for encoder - A magnetic rubber composition for encoder having a magnetic characteristic in sufficient application range, used as encoder after magnetization as well as heat resistance, water resistance and oil resistance required for use as encoder, and excellent processing property, and capable of being bonded by vulcanization with a metal, is provided. Furthermore, a magnetic rubber composition for encoder capable of obtaining sufficient magnetic force required for encoder on a circumference of the molded encoder as well as capable of effectively restraining variation of the level of magnetic force, is provided. It is provided by comprising 300 to 1,800 parts of strontium-ferrite, or 300 to 1,800 parts of barium-ferrite, or 300 to 1,800 parts of a mixture of strontium-ferrite and barium-ferrite, 0.5 to 2 parts of silane coupling agent, and 1 to 10 parts of lubricating agent, per 100 parts of a hydrogenated nitrile butadiene rubber with 15 to 50% of acrylonitrile amount and 80 to 99% of hydrogenation ratio. | 2010-04-22 |
| 20100096583 | ANTIFOAMING AGENT FOR AQUEOUS MEDIA - The invention relates to the use of a polyamide prepared from at least one diamine and at least one dicarboxylic acid in a formulation for defoaming aqueous media. The invention also relates to defoamers for aqueous media that comprise such a polyamide. | 2010-04-22 |
| 20100096584 | Polishing Composition and Polishing Method Using the Same - A polishing composition used for chemical mechanical planarization of a substrate containing a noble metal layer is provided. The polishing composition contains positively-charged abrasive particles such as alpha-Al | 2010-04-22 |
| 20100096585 | Process for Preparing 2,6-Dichloro-4-(Trifluoromethyl)Phenylhydrazine Using Mixtures of Dichloro-Fluoro-Trifluoromethylbenzenes - This invention relates to a process for preparing 2,6-dichloro-4-(trifluoromethyl)phenylhydrazine of the formula (I) wherein a mixture comprising 1,3-dichloro-2-fluoro-5-trifluoromethylbenzene and 1,2-dichloro-3-fluoro-5-trifluoromethylbenzene is reacted with a hydrazine source selected from hydrazine, hydrazine hydrate or acid addition salts of hydrazine, optionally in the presence of at least one organic solvent. | 2010-04-22 |
| 20100096586 | NATURAL STUFFING FOR DUVETS/PILLOWS - A natural duvet/pillow stuffing, which consists of down and feathers with silver particles. The size of said silver particles is ≦5 nm. | 2010-04-22 |
| 20100096587 | POLYCRYSTALLINE ARTICLES FOR REAGENT DELIVERY - A reagent delivering article comprising porous sintered polycrystalline diamond where the delivering article is capable of retaining at least one chemical reagent and releasing the chemical reagent in a fluid or has reactive sites on diamond surfaces of the article. | 2010-04-22 |
| 20100096588 | Continuous Process for Converting Natural Gas to Liquid Hydrocarbons - A method comprising: providing a halogen stream; providing an alkane stream; providing a decoking agent; and reacting at least a portion of the halogen stream with at least a portion of the alkane stream in the presence of a halogenation catalyst and the decoking agent to form a halogenated stream. | 2010-04-22 |
| 20100096589 | Polyester compositions containing low amounts of cyclobutanediol and articles made therefrom - Described as one aspect of the invention are polyesters containing (a) a dicarboxylic acid component having from 70 to 100 mole % of terephthalic acid residues and up to 30 mole % of aromatic dicarboxylic acid residues or aliphatic dicarboxylic acid residues; and (b) a glycol component having from 11 to 25 mole % of 2,2,4,4-tetramethyl-1,3-cyclobutanediol residues, and 75 to 89 mole % of cyclohexanedimethanol residues; wherein the total mole % of the dicarboxylic acid component is 100 mole %, and the total mole % of the glycol component is 100 mole %. The polyesters may be manufactured into articles. | 2010-04-22 |
| 20100096590 | NOVEL LIQUID CRYSTAL COMPOUND CONTAINING SULFONE GROUP, LIQUID CRYSTAL COMPOSITION COMPRISING THE SAME, AND OPTICAL FILM USING THE SAME LIQUID CRYSTAL COMPOSITION - Disclosed are a novel liquid crystal compound containing a sulfone group, a liquid crystal composition comprising the same, and an optical film using the same liquid crystal composition. More particularly, there are provided a liquid crystal material for a viewing angle compensation film with high quality characteristics, which can improve a contrast ratio measured at a tilt angle to the front and minimize variations in color with viewing angles in a black state, a liquid crystal composition comprising the same liquid crystal material, and a compensation film obtained from the same liquid crystal composition. | 2010-04-22 |
| 20100096591 | POLYMERIZABLE LIQUID CRYSTAL COMPOUND, LIQUID CRYSTAL COMPOSITION AND POLYMER - The purpose the invention is to provide a polymerizable liquid crystal compound which has an excellent solubility with other compounds, a high homeotropic property, and a spirobiindan-backbone, and a liquid crystal composition comprising this compound. | 2010-04-22 |
| 20100096592 | Red-Emitting Luminophore and Light Source Comprising such a Luminophore - A red-emitting phosphor composed of an M—Al—Si—N system, comprising a cation M, wherein M is represented by at least one of the elements Ca or Ba or Sr and, if appropriate, can additionally be combined with at least one further element from the group Mg, Zn, Cd, wherein the phosphor is activated with Eu, which partly replaces M, and wherein the phosphor additionally contains LiF | 2010-04-22 |
| 20100096593 | Encapsulated luminescent particulates and aggregates made therefrom - An encapsulated luminescent particle for use in an aqueous environment includes a luminescent pigment capable of being illuminated by an external light source and an encapsulating material, wherein the encapsulated luminescent particles are between about 1.5 mm and about 5 mm in size. The encapsulating material permits luminescence from the luminescent pigment upon excitation by an external light source, such as, a blacklight, while allowing the luminescent pigment to be safely used in an aqueous environment, such as a pool, spa, or the like. | 2010-04-22 |
| 20100096594 | PROCESS FOR DECONTAMINATING SYNGAS - Disclosed herein is an apparatus and methods for decontaminating syngas generated in a fluidized-bed gasifier wherein metal contaminants, inter alia, alkali metals, halogens, particulates, and transition metals and sulfur containing contaminants are removed prior to the catalytic thermal cracking of tar and ammonia. Further disclosed is an apparatus and methods for removing ammonia from syngas. | 2010-04-22 |
| 20100096595 | Functional graphene-polymer nanocomposites for gas barrier applications - A gas diffusion barrier contains a polymer matrix and a functional graphene which displays no signature of graphite and/or graphite oxide, as determined by X-ray diffraction. | 2010-04-22 |
| 20100096596 | BIPHASIC INKS - A biphasic ink comprises a plurality of attractive particles, a plurality of repulsive particles, and a carrier liquid. | 2010-04-22 |
| 20100096597 | FUNCTIONAL GRAPHENE-RUBBER NANOCOMPOSITES - A polymer composition, containing a polymer matrix which contains an elastomer; and a functional graphene which displays no signature of graphite and/or graphite oxide, as determined by X-ray diffraction, exhibits excellent strength, toughness, modulus, thermal stability and electrical conductivity. | 2010-04-22 |
| 20100096598 | METHOD OF MAKING SOLAR CELL CONTACTS - Formulations and methods of making solar cells are disclosed. In general, the invention presents a solar cell contact made from a mixture wherein the mixture comprises a solids portion and an organics portion, wherein the solids portion comprises from about 85 to about 99 wt % of silver, and from about 1 to about 15 wt % of a glass component wherein the glass component comprises from about 15 to about 75 mol % PbO, and from about 5 to about 50 mol % SiO | 2010-04-22 |
| 20100096599 | CORE/SHELL TYPE SEMICONDUCTOR NANOPARTICLE AND METHOD FOR PRODUCTION THEREOF - Disclosed are core/shell type semiconductor nanoparticles exhibiting a sufficient emission intensity without causing a blink phenomenon (blinking). The core/shell-type semiconductor nanoparticles have an average particle size of from 2 to 50 nm and comprise an intermediate layer between a core portion and a shell portion, wherein band gap widths of bulk crystals which have the same compositions as those of the core portion, the intermediate portion and the shell portion, respectively, are in the order of:
| 2010-04-22 |
| 20100096600 | Square Planar Transition Metal Complexes and Organic Semiconductive Materials Using Them as Well as Electronic or Optoelectric Components - The present invention relates to square planar transition metal complexes and their use in organic semiconductive materials as well as in electronic or optoelectronic components. | 2010-04-22 |
| 20100096601 | Molecules with complexing groups for aqueous nanoparticle dispersions and uses thereof - Stable dispersions of nanoparticles and microparticles in liquids and method for their preparation are disclosed. The dispersions can comprise about 0.1 wt % to about 25 wt % of at least one disodium salt monohydrate of 4-5-dihydroxy-1,3 benzenedisulfonic acid; about 1 wt % to about 90 wt % of particles; and about 10 wt % to about 90 wt % of at least one liquid. The particles can comprise nanoparticulate metals, metal oxides, silica and coated particles. The liquid can comprise at least one polar liquid. | 2010-04-22 |
| 20100096602 | SYSTEM AND METHOD FOR IMPROVING ADHESION AND ABRASION RESISTANCE USING A FRONT SIDE TRANSFER PROCESS TO MANUFACTURE MULTI-COATED PHOTOCHROMIC OPTICAL LENSES - A novel photochromic latex formulation is provided, in one embodiment involving the addition of a polyurethane latex to a polyphasic latex, the formulation having improved adhesion qualities, in particular, adhesion onto a hard coat layer. In a preferred embodiment, the polyurethane latex is 20% by weight of the formulation. In addition, an optical article is provided having a coating including a novel photochromic latex formulation in accordance with the present invention, applied via a Front Side Transfer process. | 2010-04-22 |
| 20100096603 | OPTICAL DEVICES RESPONSIVE TO NEAR INFRARED LASER AND METHODS OF MODULATING LIGHT - A photorefractive composition that is photorefractive upon irradiation by a near infrared (NIR) laser. The photorefractive composition comprises a sensitizer and a polymer comprising a repeating unit including at least a moiety selected from the group consisting of the formulae (Ia), (Ib) and (Ic), as defined herein. The photorefractive composition can be used in optical devices. | 2010-04-22 |
| 20100096604 | SOLAR CONTROL LAMINATES - Provided is a solar control composition comprising an infrared absorbing phthalocyanine compound or naphthalocyanine compound and a resin having a modulus from 20,000 psi (138 MPa) to 1000 psi (7 MPa) and solar control laminates comprising the solar control composition of the invention. | 2010-04-22 |
| 20100096605 | Riding Mower Ramp - A ramp is provided for lifting and supporting a wheel of a vehicle thereon when the wheel is driven onto the ramp. The ramp includes a body that is shiftable between a ready position and a discrete support position and presents a ground-engaging surface including a first portion that engages the ground in the ready position and a second portion that engages the ground in the support position. The first and second surface portions are substantially planar and define an angle therebetween through which the body rocks about a fixed pivot as a wheel moving along a wheel-engaging surface causes the body to move from the ready position to the support position. A pair of ramps is provided for lifting and supporting a pair of wheels, with the ramps being nestable for compact storage. | 2010-04-22 |
| 20100096606 | Hydraulic jack for pallet truck - The main objective of the present invention is to provide a hydraulic jack for a pallet truck that has multiple pumping units. The hydraulic jack has a platform and a base plate being mounted on a mounting bracket. A holding frame protruding from the mounting bracket and has a gap. A main pumping unit, a secondary pumping unit and a lifting unit are mounted on a top surface of the base plate. The lifting unit is connected to the platform. The secondary pumping unit has an extension rod being selectively pushed into the gap to selectively lock the secondary pumping unit. Therefore, the user may choose to use one or two pumping units as desired. | 2010-04-22 |
| 20100096607 | DEVICE FOR TRANSPORTING PLANAR SOFC STACK - A device, adapted for transporting a planar solid oxide fuel cell stack while the SOFC stack is sandwiched between a top plate and a bottom plate, which comprises: a plurality of load units, a lifting unit and a mobile seat. Each of the plural load devices is adapted for exerting a pressure on the SOFC stack. The lifting unit is composed of a joint portion and a plurality of cantilevers. In an exemplary, there is a fixing part arranged at the end of each cantilever while being enabled to connect to the SOFC stack by the bottom thereof. With the aforesaid device, the SOFC stack can be moved out of a high temperature furnace and then into a fuel cell control system smoothly while keeping one's balance without worrying the SOFC stack being damaged or tipping over by collision or losing balance. | 2010-04-22 |
| 20100096608 | FENCE SYSTEM - A fence system includes a first extruded lineal extending lengthwise along a first longitudinal axis. The first lineal has a sidewall with at least a first slot in the sidewall and the first slot extends generally perpendicular to the longitudinal axis. The fence system also includes a second extruded lineal extending lengthwise along a second longitudinal axis. The second extruded lineal includes at least a corresponding first attachment leg extending outward from the second extruded lineal and parallel to the second longitudinal axis. The first attachment leg is integrally extruded with the second extruded lineal and is received in the first slot to secure together the first and second extruded lineals. | 2010-04-22 |
| 20100096609 | PHASE CHANGE MEMORY DEVICE HAVING A LAYERED PHASE CHANGE LAYER COMPOSED OF MULTIPLE PHASE CHANGE MATERIALS AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device that has a layered phase change layer composed of multiple phase change materials is presented. The device includes a semiconductor substrate, an interlayer dielectric layer, a high-temperature crystallization phase change, a low-temperature crystallization phase change layer, and an upper electrode. The interlayer dielectric layer formed on the semiconductor substrate and the high-temperature crystallization phase change layer is formed on the interlayer dielectric layer. The low-temperature crystallization phase change layer is formed over the high-temperature crystallization phase change layer. The upper electrode is formed over the low-temperature crystallization phase change layer. An optional diffusion barrier may be interposed between the two phase change layers. | 2010-04-22 |
| 20100096610 | PHASE-CHANGE MATERIAL MEMORY CELL - A memory cell includes a current-steering device, a phase-change material disposed thereover, and a heating element and/or a cooling element. | 2010-04-22 |
| 20100096611 | VERTICALLY INTEGRATED MEMORY STRUCTURES - A device including a transistor that includes a source region; a drain region; and a channel region, wherein the channel region electrically connects the source region and the drain region along a channel axis; and a memory cell, wherein the memory cell is disposed adjacent the drain region so that the channel axis runs through the memory cell. | 2010-04-22 |
| 20100096612 | PHASE CHANGE MEMORY DEVICE HAVING AN INVERSELY TAPERED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device having an inversely tapered bottom electrode and a method for forming the same is presented. The phase change memory device includes a semiconductor substrate, an insulation layer, a bottom electrode contact and a phase change pattern. The insulation layer includes a bottom electrode contact hole having an insulation sidewall spacer such that the bottom electrode contact hole has an upper portion diameter that is smaller than a lower portion diameter. The bottom electrode contact is formed within the bottom electrode contact hole. The phase change pattern is formed on the bottom electrode contact. | 2010-04-22 |
| 20100096613 | SEMICONDUCTOR DEVICE - A phase change memory is formed of a plug buried within a through-hole in an insulating film formed on a semiconductor substrate, an interface layer formed on the insulating film in which the plug is buried, a recording layer formed of a chalcogenide layer formed on the interface layer, and an upper contact electrode formed on the recording layer. The recording layer storing information according to resistance value change is made of chalcogenide material containing indium in an amount range from 20 atomic % to 38 atomic %, germanium in a range from 9 atomic % to 28 atomic %, antimony in a range from 3 atomic % to 18 atomic %, and tellurium in a range from 42 atomic % to 63 atomic %, where the content of germanium larger than or equal to the content of antimony. | 2010-04-22 |
| 20100096614 | Light-emitting diode and method of manufacturing the same - A light-emitting diode and a method of manufacturing the light-emitting diode are provide, the light-emitting diode including a lower electrode on a substrate, a template layer on the lower electrode. The template layer may have a plurality of open regions. A plurality of nano-dashes may be formed in the plurality of open regions of the template layer. A transparent insulating layer may be formed between the nano-dashes. A transparent upper electrode may be formed on the nano-dashes and the transparent insulating layer. | 2010-04-22 |
| 20100096615 | LIGHT-EMITTING DEVICE - A light-emitting device includes a group III nitride semiconductor layer of a multilayer structure consisting of a group III nitride semiconductor having a major surface defined by a nonpolar plane or a semipolar plane and having at least an n-type layer and a p-type layer. A surface of the group III nitride semiconductor layer on a light extraction side is a mirror surface. The light-emitting device may further include a transparent electrode in contact with the surface of the group III nitride semiconductor layer on the light extraction side. In this case, a surface of the transparent electrode on the light extraction side is preferably a mirror surface. | 2010-04-22 |
| 20100096616 | LIGHT-EMITTING AND LIGHT-DETECTING OPTOELECTRONIC DEVICE - An exemplary optoelectronic device includes a substrate and an epitaxial structure formed on the optoelectronic device. The epitaxial structure includes an N-type semiconductor layer, a P-type semiconductor layer, a multi-quantum-well layer and an undoped semiconductor layer. The multi-quantum-well layer is arranged between the N-type semiconductor layer and the P-type semiconductor layer. The undoped semiconductor layer is sandwiched between the N-type semiconductor layer and the multi-quantum-well layer. The undoped semiconductor layer is represented by a general formula Al | 2010-04-22 |
| 20100096617 | TRANSPARENT POLARIZED LIGHT-EMITTING DEVICE - A transparent directional polarized light-emitting device includes a transparent anode and a transparent cathode, a radiation-emitting layer between the anode and the cathode, an optically active reflective layer with a reflection band that matches a chirality and at least partially encompasses a wavelength band of radiation emitted from the radiation-emitting layer, the optically active light blocking layer located on a side of the radiation-emitting layer, and a transparent substrate adjacent to the optically active reflective layer. | 2010-04-22 |
| 20100096618 | DOPING OF NANOSTRUCTURES - A catalyst particle for use in growth of elongated nanostructures, such as e.g. nanowires, is provided. The catalyst particle comprises a catalyst compound for catalyzing growth of an elongated nanostructure comprising a nanostructure material without substantially dissolving in the nanostructure material and at least one dopant element for doping the elongated nanostructure during growth by substantially completely dissolving in the nanostructure material. A method for forming an elongated nanostructure, e.g. nanowire, on a substrate using the catalyst particle is also provided. The method allows controlling dopant concentration in the elongated nanostructures, e.g. nanowires, and allows elongated nanostructures with a low dopant concentration of lower than 10 | 2010-04-22 |
| 20100096619 | ELECTRONIC DEVICES USING CARBON NANOTUBES HAVING VERTICAL STRUCTURE AND THE MANUFACTURING METHOD THEREOF - Provided are an electronic device to which vertical carbon nanotubes (CNTs) are applied and a method of manufacturing the same. The method of manufacturing an electronic device having a vertical CNT includes the steps of: (a) preparing a substrate on which a silicon source is formed; (b) forming a first insulating layer on the substrate, and etching the first insulating layer such that a top surface of the silicon source is exposed; (c) forming a second insulating layer on the silicon source, and forming a gate by patterning the second insulating layer; (d) forming a third insulating layer on the gate, and forming a through hole in which a carbon nanotube channel is to be formed by etching the third insulating layer and the second insulating layer; (e) forming a fourth insulating layer surrounding the gate on the through hole and the third insulating layer, and forming a spacer by etching the fourth insulating layer; (f) forming a metal catalyst on the silicon source; (g) vertically growing the carbon nanotube channel on the silicon source using the metal catalyst; (h) forming a fifth insulating layer on the through hole in which the carbon nanotube is formed and the third insulating layer; and (i) patterning the fifth insulating layer such that the carbon nanotube channel is exposed, and forming a silicon drain. An arrangement problem of horizontal CNTs can be solved by applying vertical CNTs and a selective silicon growth technique. | 2010-04-22 |
| 20100096620 | ORGANIC THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME - A method of fabricating an organic thin film transistor is provided. The method includes forming a source, a drain and a gate on a substrate and forming a dielectric layer to isolate the gate from the source and isolate the gate from the drain. An organic active material layer is formed on the substrate to fill a channel region between the source and the drain and cover the source and the drain. A barrier material layer is formed on the organic active material layer. Thereafter, the barrier material layer and the organic active material layer are patterned to form a barrier layer and an organic active layer and expose the source and the drain. | 2010-04-22 |
| 20100096621 | ORGANIC TRANSISTOR AND MANUFACTURE METHOD THEREOF - [PROBLEMS] To provide an organic transistor in which high-resolution patterning can be performed, favorable contact can be achieved, and a leakage current can be prevented. | 2010-04-22 |
| 20100096622 | ORGANIC ELECTROLUMINESCENCE ELEMENT - An organic EL element which has no layer that prevents penetration of holes and electrons to the counter electrode. The organic EL element includes: an anode, a hole injecting and transporting layer formed on the anode, a light emitting layer formed on the hole injecting and transporting layer, an electron injecting and transporting layer formed on the light emitting layer, and a cathode formed on the electron injecting and transporting layer. Ip | 2010-04-22 |
| 20100096623 | Forming electrodes to small electronic devices having self-assembled organic layers - In one embodiment of the invention, a method of fabricating a SAM device comprises the steps of: (a) providing a substrate having a top surface and a first metal electrode disposed on the top surface, (b) annealing the first metal electrode, (c) forming a SAM layer on a major surface of the first electrode, the SAM layer having a free surface such that the SAM is disposed between the free surface and the major surface of the first electrode, and (d) forming a second metal electrode on the free surface of the molecular layer. Forming step (d) includes the step of (d | 2010-04-22 |
| 20100096624 | Organic electroluminescent device and display using same - An organic electroluminescent device ( | 2010-04-22 |
| 20100096625 | ORGANIC FIELD-EFFECT TRANSISTOR AND METHOD OF FABRICATING THIS TRANSISTOR - This organic field effect transistor comprises a semiconductor layer made of an organic semiconductor material. The mobility μl | 2010-04-22 |
| 20100096626 | ORGANIC LIGHT EMITTING DEVICE - An organic light emitting device includes a transistor having gate, source, and drain electrodes, and first electrode connected to one of the source or drain electrodes. The device also includes an emitting layer positioned on the first electrode and a second electrode positioned on the emitting layer. Each of the source and drain electrodes includes first, second, and third layers having different tapered angles. The first electrode may include a metallic layer and a conductive layer, with a tapered angle of the metallic layer being different from a tapered angle of the conductive layer. | 2010-04-22 |
| 20100096627 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting element is disclosed that can drive at a low driving voltage and that has a longer lifetime than the conventional light-emitting element, and a method is disclosed for manufacturing the light-emitting element. The disclosed light-emitting element includes a plurality of layers between a pair of electrodes; and at least one layer among the plurality of layers contains one compound selected from the group consisting of oxide semiconductor and a metal oxide, and a compound having high hole transportation properties. Such the light-emitting element can suppress the crystallization of a layer containing one compound selected from the group consisting of oxide semiconductor and a metal oxide, and a compound having high hole transportation properties. As a result, a lifetime of the light-emitting element can be extended. | 2010-04-22 |
| 20100096628 | Multi-layered memory apparatus including oxide thin film transistor - Provided is a multi-layered memory apparatus including an oxide thin film transistor. The multi-layered memory apparatus includes an active circuit unit and a memory unit formed on the active circuit unit. A row line and a column line are formed on memory layers. A selection transistor is formed at a side end of the row line and the column line. | 2010-04-22 |
| 20100096629 | MULTI-CHIP MODULE FOR AUTOMATIC FAILURE ANALYSIS - The invention provides a multi-chip module. In one embodiment, the multi-chip module comprises a serial flash die and a primary die, and the primary die comprises a built-in self-test controller and a serial flash controller. The built-in self-test controller generates a write command to write first data to a memory location of the serial flash die, generates a read command to read second data from the memory location of the serial flash die, and compares the second data with the first data to determine whether the memory location is defective for generating failed address information about the serial flash die. The serial flash controller accesses the serial flash die according to the write command and the read command. | 2010-04-22 |
| 20100096630 | Bottom-Gate Thin Film Transistor and Method of Fabricating the Same - A bottom-gate thin film transistor includes a gate electrode, a gate insulating layer and a microcrystalline silicon layer. The gate electrode is disposed on a substrate. The gate insulating layer is made up of silicon nitride and disposed on the gate electrode and the substrate. The microcrystalline silicon layer is disposed on the gate insulating layer and corresponds to the gate electrode, in which a contact interface between the gate insulating layer and the microcrystalline silicon layer has a plurality of oxygen atoms, and concentration of the oxygen atoms ranges between 10 | 2010-04-22 |
| 20100096631 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor includes, over a substrate having an insulating surface, a gate insulating layer covering a gate electrode; a semiconductor layer which includes a plurality of crystalline regions in an amorphous structure and which forms a channel formation region, in contact with the gate insulating layer; a semiconductor layer including an impurity element imparting one conductivity type, which forms source and drain regions; and a buffer layer including an amorphous semiconductor between the semiconductor layer and the semiconductor layer including an impurity element imparting one conductivity type. The crystalline regions have an inverted conical or inverted pyramidal crystal particle which grows approximately radially in a direction in which the semiconductor layer is deposited, from a position away from an interface between the gate insulating layer and the semiconductor layer. | 2010-04-22 |
| 20100096632 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A second insulation layer which is formed by stacking a plurality of layers made of different materials in a mutually contact manner is formed such that the second insulation layer covers a source region and a drain region and also covers a gate electrode from above. A first contact hole which reaches one of the source region and the drain region and a recessed portion which is arranged above the gate electrode but is not communicated with the gate electrode are simultaneously formed on the second insulation layer by dry etching. A first line layer is formed so as to cover the first contact hole. After forming the first line layer, a bottom surface of the recessed portion is etched by dry etching thus forming a second contact hole which reaches the gate electrode in the first and second insulation layers. A second line layer is formed on the second contact hole. | 2010-04-22 |
| 20100096633 | FLEXIBLE LIGHT-EMITTING DEVICE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING FLEXIBLE-LIGHT EMITTING DEVICE - It is an object to provide a flexible light-emitting device with long lifetime in a simple way and to provide an inexpensive electronic device with long lifetime using the flexible light-emitting device. A flexible light-emitting device is provided, which includes a substrate having flexibility and a light-transmitting property with respect to visible light; a first adhesive layer over the substrate; an insulating film containing nitrogen and silicon over the first adhesive layer; a light-emitting element including a first electrode, a second electrode facing the first electrode, and an EL layer between the first electrode and the second electrode; a second adhesive layer over the second electrode; and a metal substrate over the second adhesive layer, wherein the thickness of the metal substrate is 10 μm to 200 μm inclusive. Further, an electronic device using the flexible light-emitting device is provided. | 2010-04-22 |
| 20100096634 | Panel structure, display device including same, and methods of manufacturing panel structure and display device - Provided may be a panel structure, a display device including the panel structure, and methods of manufacturing the panel structure and the display device. Via holes for connecting elements of the panel structure may be formed by performing one process. For example, via holes for connecting a transistor and a conductive layer spaced apart from the transistor may be formed by performing only one process. | 2010-04-22 |
| 20100096635 | THIN FILM TRANSISTOR ARRAY PANEL INCLUDING ASSISTANT LINES - Improved thin film transistor array panels are provided. In one embodiment, a panel includes a plurality of gate lines, data lines, and a plurality of switching elements connected to the gate lines and the data lines. An interlayer insulating layer is formed between the gate lines and the data lines. A passivation layer covering the gate lines, the data lines, and the switching elements is also provided having a plurality of first contact holes exposing portions of the data lines, wherein the switching elements and the pixel electrodes are connected through the first contact holes. A plurality of contact assistants are formed on the passivation layer and are connected to the data lines through a plurality of second contact holes in the passivation layer. A plurality of auxiliary lines are connected to the data lines through a plurality of third contact holes in the interlayer insulating layer. | 2010-04-22 |
| 20100096636 | THIN FILM TRANSISTOR ARRAY HAVING STORAGE CAPACITOR - A thin film transistor array comprising a substrate, a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors, a plurality of common lines, a plurality of top electrodes, a plurality of connection lines and a plurality of pixel electrodes is provided. Wherein, each thin film transistor is disposed in one of the pixel areas and driven through the corresponding scan line and data line. Each thin film transistor includes a gate, a source and a drain. The drain of the thin film transistor is electrically connected to the corresponding top electrode by the corresponding connection line. Besides, the drain of the thin film transistor is electrically connected to the pixel electrode, and a portion of the connection line is not covered by the pixel electrode. | 2010-04-22 |
| 20100096637 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - Off current of a thin film transistor is reduced, and on current of the thin film transistor is increased, and variation in electric characteristics is reduced. As a structure of semiconductor layers which form a channel formation region of a thin film transistor, a first semiconductor layer including a plurality of crystalline regions is provided on a gate insulating layer side; a second semiconductor layer having an amorphous structure is provided on a source region and drain region side; an insulating layer with a thickness small enough to allow carrier travel is provided between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer is in contact with the gate insulating layer. The second semiconductor layer is provided on an opposite side to a face of the first semiconductor layer which is in contact with the gate insulating layer. | 2010-04-22 |
| 20100096638 | THIN FILM TRANSISTOR SUBSTRATE, METHOD OF MANUFACTURING THE SAME, AND DISPLAY APPARATUS HAVING THE SAME - A thin film transistor substrate that includes a substrate, first and second gate electrodes that are formed on the substrate, a gate insulating layer that is formed on the first and second gate electrodes, a first semiconductor and a second semiconductor that are formed on the gate insulating layer, and that overlap the first gate electrode and the second gate electrode, respectively, a first source electrode and a first drain electrode that are formed on the first semiconductor, and positioned opposed to and spaced from each other, a source electrode connected to the first drain electrode and a second drain electrode positioned opposed to and spaced from the second source electrode, wherein the second source and second drain electrodes are formed on the second semiconductor, and a pixel electrode that is electrically connected to the second drain electrode, a method of manufacturing the same, and a display apparatus having the same. | 2010-04-22 |
| 20100096639 | ACTIVE MATRIX SUBSTRATE - The active-matrix substrate ( | 2010-04-22 |
| 20100096640 | SELF-ASSEMBLED HETEROGENEOUS INTEGRATED OPTICAL ANALYSIS SYSTEM - Optical analysis system fluidically self-assembled using shape-coded freestanding optoelectronic components and a template having shape-coded recessed binding sites connected by an embedded interconnect network. Also includes methods of manufacture and use for optical analyses. | 2010-04-22 |
| 20100096641 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A light emitting device according to an embodiment is provided. The light emitting device comprises a second electrode layer, a third conductive semiconductor layer comprising a schottky contact region and an ohmic contact region on the second electrode layer, a second conductive semiconductor layer on the third conductive semiconductor layer, an active layer on the second conductive semiconductor layer, a first conductive semiconductor layer on the active layer, and a first electrode layer on the first conductive semiconductor layer. | 2010-04-22 |
| 20100096642 | PACKAGING STRUTURE FOR HIGH POWER LIGHT EMITTING DIODE(LED) CHIP - The present invention relates to a packaging structure for high-power light emitting diode (LED) chip, comprising a metal plate, insulators and a cover plate. The metal plate comprises a containing slot and isolating slots formed on the surface by working, and the insulators can be embedded in the isolating slot. After forming a hollow slot and notches on the surface of the cover plate by working, the cover plate is combined with the metal plate and insulators and at the same time, the hollow slot and the notches are corresponding to the containing slot and the isolating slots on the metal plate to form a hollowness state, followed by application of surface treatment to form soldering portions and an anti-soldering layer at the bottom of the metal plate. Then the metal plate is cut on both sides along free ends of the insulators so as to generate electrode contacts with positive and negative electrodes, and the surface mount technology (SMT) can be adopted for assembly of the packaging structure of high-power LED chip so as to simplify manufacturing processes, facilitate mass production and achieve separation of electricity from heat, etc. | 2010-04-22 |
| 20100096643 | SEMICONDUCTOR LIGHT SOURCE FOR ILLUMINATING A PHYSICAL SPACE INCLUDING A 3-DIMENSIONAL LEAD FRAME - The present invention is a semiconductor light source | 2010-04-22 |
| 20100096644 | Light Emitting Device Package and Light Emitting Apparatus - Disclosed are a light emitting device package and a light emitting apparatus. The light emitting device package comprises a package body comprising a light emitting surface inclined at an oblique angle with respect to a bottom surface, a plurality of lead electrodes in the package body, and at least one light emitting device electrically connected to the lead electrodes. | 2010-04-22 |
| 20100096645 | DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a display device and a display device which can reduce the number of times that an insulation substrate is put into a CVD device and is taken out from the CVD device are provided. The manufacturing method of a display device includes the steps of forming a conductive layer including first electrode films and second electrode films, a first insulation layer, semiconductor films, a second insulation layer and a protective layer on an insulation substrate; forming first resist films having a predetermined thickness which are arranged in first regions above the semiconductor films, opening portions which are arranged in second regions above the second electrode films and second resist films having a large thickness which are arranged in regions other than the first regions and the second regions on the protective layer; etching portions below the second regions, removing the first resist films by ashing; forming first holes which reach the semiconductor films below the first regions and second holes which reach the second electrode films below the second regions; removing the second resist films, and forming lines which are connected to the semiconductor films and lines which are connected to the second electrode films. | 2010-04-22 |
| 20100096646 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND LIGHT EMITTING APPARATUS HAVING THEREOF - Embodiments relate to a semiconductor light emitting device and a light emitting apparatus comprising the same. The semiconductor light emitting device according to embodiments comprises a plurality of light emitting cells comprising a plurality of compound semiconductor layers; a plurality of ohmic contact layers on the light emitting cells; a first insulating layer on the ohmic contact layer; a second electrode layer electrically connected to a first light emitting cell of the light emitting cells; and a plurality of interconnection layers connecting the light emitting cells in series. | 2010-04-22 |
| 20100096647 | LIGHT OUTPUT DEVICE - A light output device comprises a substrate arrangement comprising first and second light transmissive substrates ( | 2010-04-22 |
| 20100096648 | AC LIGHT EMITTING DIODE AND METHOD FOR FABRICATING THE SAME - The present invention relates to an AC light emitting diode. An object of the present invention is to provide an AC light emitting diode wherein various designs for enhancement of the intensity of light, prevention of flickering of light or the like become possible, while coming out of a unified method of always using only one metal wire with respect to one electrode when electrodes of adjacent light emitting cells are connected through metal wires. To this end, the present invention provides an AC light emitting diode comprising a substrate; bonding pads positioned on the substrate; a plurality of light emitting cells arranged in a matrix form on the substrate; and a wiring means electrically connecting the bonding pads and the plurality of light emitting cells, wherein the wiring means includes a plurality of metal wires connecting an electrode of one of the light emitting cells with electrodes of other electrodes adjacent to the one of the light emitting cells. | 2010-04-22 |
| 20100096649 | Semiconductor Light Emitting Device and Manufacturing Method Therefor - A semiconductor light emitting device of double hetero junction includes an active layer and clad layers. The clad layers include an n-type layer and p-type layer. The clad layers sandwich the active layer. A band gap energy of the clad layers is larger than that of the active layer. The band gap energy of the n-type clad layer is smaller than of the p-type clad layer. | 2010-04-22 |
| 20100096650 | NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT - Provided is a nitride semiconductor light emitting element capable of producing an emission spectrum having two peaks with stable ratio of emission peak intensity. The nitride semiconductor light emitting | 2010-04-22 |
| 20100096651 | III-Nitride Semiconductor Light Emitting Device - The present disclosure relates to a III-nitride semiconductor light-emitting device including a substrate with a first groove and a second groove formed therein, the substrate including a first surface and a second surface opposite to the first surface, a plurality of III-nitride semiconductor layers including a first semiconductor layer formed over the first surface of the substrate, a second semiconductor layer formed over the first III-nitride semiconductor layer, and an active layer disposed between the first and second III-nitride semiconductor layers and generating light by recombination of electrons and holes, a first opening formed on the first groove, a second opening formed on the second groove, a first electrode electrically connected from the second surface to the first III-nitride semiconductor layer through the first groove, and a second electrode electrically connected from the second surface to the second III-nitride semiconductor layer through the second groove and the second opening. | 2010-04-22 |
| 20100096652 | SEMICONDUCTOR LIGHT EMITTING DEVICE - The present invention provides a semiconductor light emitting device including a conductive substrate, a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer which are sequentially stacked, wherein an area where the first electrode layer and the first semiconductor layer are in contact with each other is 3 to 13% of an area of the semiconductor light emitting device. | 2010-04-22 |
| 20100096653 | LIGHT EMITTING DIODE PACKAGE - A side-view type light emitting diode package for emitting light, emitted from a light emitting diode chip, toward a side surface is disclosed. The side-view type light emitting diode package comprises a package body having an opening portion for exposing the light emitting diode chip in a light emitting direction; and a light-transmittable resin covering the light emitting diode chip, wherein at least a portion of an inner wall of the opening portion is formed with a step projection for partitioning the opening portion into upper and lower sections, and the lower section of the opening portion below the step projection is filled with the light-transmittable resin. Accordingly, the light-transmittable resin with the convex lens shape may be easily formed, so that the light emission efficiency thereof can be improved. | 2010-04-22 |
| 20100096654 | LIGHT-EMITTING DISPLAY DEVICE - The light-emitting display device comprises first and second thin film transistors. The first thin film transistor includes a first gate electrode; a first oxide semiconductor film; and a first electrode and a second electrode which are electrically connected to the first oxide semiconductor film. The second thin film transistor includes a second gate electrode electrically connected to the second electrode; a second oxide semiconductor film; a third electrode; a light-emitting layer and a fourth electrode over the second oxide semiconductor film. A work function of the second oxide semiconductor film is higher than a work function of the fourth electrode. | 2010-04-22 |
| 20100096655 | TOP EMISSION TYPE ORGANIC ELECTROLUMINESCENT DEVICE AND METHOD OF FABRICATING THE SAME - An organic electroluminescent device includes a first substrate including a plurality of pixel regions; a thin film transistor on the first substrate and in each pixel region; a second substrate facing the first substrate; an organic electroluminescent diode on the second substrate and connected to the thin film transistor; a seal pattern at edges of the first and second substrates; and an adhesive layer including a plurality of conductive balls, an inner space defined by the first substrate, the second substrate and the seal pattern filled with the adhesive layer. | 2010-04-22 |
| 20100096656 | CATIONIC CONJUGATED POLYELECTROLYTE ELECTRON INJECTION LAYERS ALTERED WITH COUNTER ANIONS HAVING OXIDATIVE PROPERTIES - Counter anions having oxidative properties alter the performance of solution processed multilayer polymer light emitting diodes (PLEDs) that use cationic conjugated polyelectrolytes (CPEs) as electron injection layers (EILs). In some versions, PLEDs with poly(2-methoxy-5-(2′-ethylhexyloxy)-1,4-phenylene vinylene) (MEH-PPV) emissive layers and cationic CPE EILs are altered with halide counter anions to exhibit a systematic increase in device performance. Exemplary oxidative counter anions are halide counter anions with F | 2010-04-22 |
| 20100096657 | LIGHT-EMITTING DEVICE HAVING A PATTERNED SURFACE - The disclosure provides a light-emitting device comprising a substrate, an intermediate layer formed on the substrate, a first doped semiconductor layer with first conductivity-type formed on the intermediate layer, a second doped semiconductor layer with second conductivity-type formed on the first doped semiconductor layer, an active layer formed between the first doped semiconductor layer and the second doped semiconductor layer, and a patterned surface having a plurality of ordered pattern units; wherein the patterned surface is substantially not parallel to the corresponding region of the surface of the active layer. | 2010-04-22 |
| 20100096658 | Structure of Light Emitting Diode - An improved structure of light emitting diode comprises that a copper clad laminate is made with a rectangular type slot thereon and a ring type slot on the outside boundary to enclose the rectangular type slot, while side wall of the slot form a natural guide angle with the surface of the copper clad laminate to further form an island type platform; a conductor being made between rectangular type slot and ring type slot is penetrated through the copper clad laminate and externally enclosed by the insulator thereby allowing conductor to be insulated; a light emitting diode chip is installed thereon; a fluorescent glue is optionally installed on the light emitting diode with a covering range smaller than the natural guiding angle of the rectangular type slot, wherein the copper clad laminate is installed on the printed circuit board. | 2010-04-22 |
| 20100096659 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention is directed to providing a smaller semiconductor device having a light emitting element with a low manufacturing cost and a method of manufacturing the same. An adhesive layer | 2010-04-22 |
| 20100096660 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed are a semiconductor light emitting device. The semiconductor light emitting device comprises a light emitting structure comprising a plurality of compound semiconductor layers, a passivation layer at the outside of the light emitting structure, a first electrode layer on the light emitting structure, and a second electrode layer under the light emitting structure. | 2010-04-22 |
| 20100096661 | LIGHT EMITTING DIODE MODULE - Provided an LED module comprising a metallic thin film having a flexibility; a circuit pattern printed on the metallic thin film so as to be insulated from the metallic thin film; one or more LEDs mounted on the metallic thin film on which the circuit pattern is not formed; wire for electrically connecting the LED and the circuit pattern; and a fluorescent body formed on the LED. | 2010-04-22 |
| 20100096662 | SEMICONDUCTOR CHIP ASSEMBLY WITH POST/BASE HEAT SPREADER AND SIGNAL POST - A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The heat spreader includes a thermal post and a base. The thermal post extends upwardly from the base into a first opening in the adhesive, and the base extends laterally from the thermal post. The conductive trace includes a pad, a terminal and a signal post. The signal post extends upwardly from the terminal into a second opening in the adhesive. | 2010-04-22 |
| 20100096663 | PHOTOSENSITIVE RESIN AND PROCESS FOR PRODUCING MICROLENS - A material for a microlens having heat resistance, high resolution and high light-extraction efficiency is provided. A positive resist composition comprises an alkali-soluble polymer (A) containing a unit structure having an aromatic fused ring or a derivative thereof, and a compound (B) having an organic group which undergoes photodecomposition to yield an alkali-soluble group. The positive resist composition has coating film properties of a refractive index at a wavelength of 633 nm of 1.6 or more and a transmittance at wavelengths of 400 to 730 nm of 80% or more. A pattern forming method comprises applying the positive resist composition, drying the composition, exposing the composition to light, and developing the composition. | 2010-04-22 |
| 20100096664 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first semiconductor layer; a first electrode provided on a first surface side of the first semiconductor layer; a first insulating layer; and a second semiconductor layer. The first insulating layer is provided between the first semiconductor layer and the first electrode and configured to constrict current flowing between the first semiconductor layer and the first electrode. The second semiconductor layer has a first conductivity type and is provided at least on a path of the current constricted by the first insulating layer. The second semiconductor layer is in contact with the first electrode. The second semiconductor layer contains first impurities at a concentration higher than a concentration of impurities contained in the first semiconductor layer. | 2010-04-22 |
| 20100096665 | InGaAsSbN PHOTODIODE ARRAYS - Embodiments of detectors made using lattice matched photoabsorbing layers are disclosed. A photodiode apparatus in accordance with one or more embodiments of the present invention comprises an indium phosphide substrate, and a photoabsorbing region comprising at least an indium gallium arsenide antimonide nitride (InGaAsSbN) layer, wherein the InGaAsSbN layer has a thickness of at least 100 nanometers and is nominally lattice-matched to the indium phosphide substrate. | 2010-04-22 |
| 20100096666 | LAMINAR STRUCTURE ON A SEMICONDUCTOR SUBSTRATE - An object of the present invention is to provide a ferroelectric element having excellent properties, which includes a monocrystalline film of γ-Al | 2010-04-22 |
| 20100096667 | SEMICONDUCTOR DEVICE - There is provided a technique for reducing the occurrence of higher harmonics which occur from a field effect transistor, particularly a field effect transistor configuring a switching element of an antenna switch. In a transistor having a meander structure, the gate width of a partial transistor closest to a gate input side is increased. More specifically, a comb-like electrode is made longer than the other comb-like electrodes. In other words, a finger length is made greater than any other finger length. In particular, the comb-like electrode has the greatest length in all the comb-like electrodes. | 2010-04-22 |
| 20100096668 | High voltage durability III-Nitride semiconductor device - A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer. The high voltage durability HEMT also comprises a III-nitride semiconductor body formed over the P type conductivity <111> silicon layer, the III-nitride semiconductor body forming a heterojunction of the HEMT. | 2010-04-22 |
| 20100096669 | MEMORY CELL ARRAY COMPRISING WIGGLED BIT LINES - An integrated circuit including a memory cell array comprises transistors being arranged along parallel active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines. | 2010-04-22 |
| 20100096670 | SEMICONDUCTOR DEVICE WITH INTERFACE CIRCUIT AND METHOD OF CONFIGURING SEMICONDUCTOR DEVICES - Methods and devices yielding an improved semiconductor device with interface circuit are disclosed. Configuring a semiconductor with parallel device features reduces process variation (e.g., lithographically-induced process variation or other defects). Embodiments of the present invention provide semiconductor devices with I/O cell device features (e.g., I/O gates or core gates) laid out in parallel. Additionally, embodiments of the present invention can allow patterning devices to be made to more exacting tolerances because some patterning devices may have a higher capability along one axis than another. Embodiments of the present invention also include a semiconductor device having like-functioned I/O cells arranged such that their layouts and rotational orientations with respect to their corresponding core remain constant. Furthermore, disclosed semiconductor devices may include at least one circuit cell having non-parallel features, where the circuit cell is arranged either within the core or within a corresponding interface circuit cell. | 2010-04-22 |
| 20100096671 | Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors - A cell of a semiconductor device includes a substrate portion formed to include a plurality of diffusion regions, including at least one p-type diffusion region and at least one n-type diffusion region separated from each other by one or more non-active regions. The cell includes a gate electrode level including a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features form respective PMOS and/or NMOS transistor devices. A total number of the PMOS and NMOS transistor devices in the cell is greater than or equal to eight. The cell also includes a number of interconnect levels formed above the gate electrode level. | 2010-04-22 |
| 20100096672 | SELF-ALIGNED, INTEGRATED CIRCUIT CONTACT - Embodiments concern contacts for use in integrated circuits, which have a reduced likelihood of shorting to unrelated portions of an overlying conductive layer due to contact misalignment. Embodiments for forming the integrated circuit include performing a first etching process to pattern the conductive layer, where the etching compound used in the first etching process is relatively selective to the conductive layer's materials. Embodiments also include performing a second, contact related etching process that removes a portion of any misaligned contacts that were exposed by the first etching process, where the etching compound used in the second etching process is selective to the contacts' materials. The embodiments can be used to form vias and other interconnect structures as well. The modified contacts and vias are adapted for use in conjunction with memory cells and apparatus incorporating such memory cells, as well as other integrated circuits. | 2010-04-22 |
| 20100096673 | SEMICONDUCTOR DEVICE STRUCTURE HAVING ENHANCED PERFORMANCE FET DEVICE - A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate: a first layer below and second layers on a gate with spacers, source and drain regions adjacent to the gate, silicides on the gate and source and drain regions; disposing a stress layer over the structure resulting from the forming step; disposing an insulating layer over the stress layer; removing portions of the insulating layer to expose a top surface of the stress layer; removing the top surface and other portions of the stress layer and portions of the spacers to form a trench, and then disposing a suitable stress material into the trench. | 2010-04-22 |
| 20100096674 | METHODS AND SYSTEMS OF THICK SEMICONDUCTOR DRIFT DETECTOR FABRICATION - Gray-tone lithography technology is used in combination with a reactive plasma etching operation in the fabrication method and system of a thick semiconductor drift detector. The thick semiconductor drift detector is based on a trench array, where the trenches in the trench array penetrate the bulk with different depths. These trenches form an electrode. By applying different electric potentials to the trenches in the trench array, the silicon between neighboring trenches fully depletes. Furthermore, the applied potentials cause a drifting field for generated charge carriers, which are directed towards a collecting electrode. | 2010-04-22 |
| 20100096675 | BACKSIDE ILLUMINATED CMOS IMAGE SENSOR WITH PHOTO GATE PIXEL - A pixel for a CMOS photo sensor with increased full well capacity is disclosed. The pixel having a photosensitive element, a photo gate, potential well and a readout circuit. The photosensitive element having a front side and a back side, for releasing charge when light strikes the back side of the photosensitive element. The potential well receives the released charge from the photosensitive element. The photo gate located on the front side of the photosensitive element, for transferring the released charge from the potential well to a sense node. The readout circuit coupled to the sense node, for measuring a voltage corresponding to the released charge transferred to the sense node. | 2010-04-22 |
| 20100096676 | PHOTOELECTRIC CONVERSION DEVICE, METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE, AND IMAGE PICKUP SYSTEM - A photoelectric conversion device comprising a semiconductor substrate of a first conduction type, and a photoelectric conversion element having an impurity region of the first conduction type and a plurality of impurity regions of a second conduction type opposite to the first conduction type. The plurality of second-conduction-type impurity regions include at least a first impurity region, a second impurity region provided between the first impurity region and a surface of the substrate, and a third impurity region provided between the second impurity region and the surface of the substrate. A concentration C | 2010-04-22 |
| 20100096677 | BACKSIDE-ILLUMINATED SOLID-STATE IMAGE PICKUP DEVICE - Provided is a backside-illuminated solid-state image pickup device capable of allowing peripheral circuits to produce stable waveforms and thereby achieving image characteristics with less noise, the device including: a first-conductivity-type semiconductor layer having a first principal surface and a second principal surface opposed to the first principal surface and also having a pixel area and an analog circuit area; a first P type area formed to lie between the second principal surface and the first principal surface in the analog circuit area; a metal layer formed at least partially on the second principal surface of the first P type area; a VSS electrode electrically connected to the metal layer; a photo-conversion area formed in the pixel area and used to accumulate electric charges generated by photoelectric conversion; and a microlens provided on the second principal surface in the pixel area so as to correspond to the photo-conversion area. | 2010-04-22 |
| 20100096678 | NANOSTRUCTURED BARIUM STRONTIUM TITANATE (BST) THIN-FILM VARACTORS ON SAPPHIRE - Varactor shunt switches based on a nonlinear dielectric tunability of Ba | 2010-04-22 |
| 20100096679 | FET, FERROELECTRIC MEMORY DEVICE, AND METHODS OF MANUFACTURING THE SAME - Disclosed herein are a field-effect transistor (FET), a ferroelectric memory device, and methods of manufacturing the same. The FET and the ferroelectric memory device in accordance with the present invention include: a substrate | 2010-04-22 |
| 20100096680 | OC DRAM CELL WITH INCREASED SENSE MARGIN - A memory device and method of making the memory device. The memory device comprises a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line is connected to the gate structure. | 2010-04-22 |
