16th week of 2010 patent applcation highlights part 22 |
Patent application number | Title | Published |
20100100659 | COMPUTER SYSTEM - A computer system includes hard disc, and a control circuit electrically connected to the hard disc. The control circuit includes a connecting port electrically connected to an external connecting port for transmitting data signals with another computer, a switch, a voltage converter, and a signal transforming controller. The switch includes a first terminal electrically connected to the connecting port, and a second terminal. The voltage converter includes an input terminal electrically connected to the connecting port for receiving an external voltage, and an output terminal for outputting a converted voltage. The signal transforming controller includes a first signal terminal electrically connected to the second terminal of the switch, a voltage input terminal electrically connected to the output terminal of the voltage converter, and a second signal terminal electrically connected to the hard disc. | 2010-04-22 |
20100100660 | Network storage system, disk array device, host device, access control method, and data access method - A network storage includes at least one host device, a plurality of disk array devices, an address map that is stored in one of the plurality of disk array devices and indicates a correspondence relation between a logical address to view the plurality of disk array devices as one storage device and a physical address of each of the plurality of disk array devices, a management master that is included in the host device or one of the plurality of disk array devices, an address map storing location information that is stored in the management master and indicates the disk array device that stores the address map and an address on which the address map is stored in the disk array device, and a command management unit that is included in the management master and transmits the address map storing location information to the host device. | 2010-04-22 |
20100100661 | PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES - An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols. | 2010-04-22 |
20100100662 | ACCESSING APPARATUS AND METHOD USING THE SAME - An accessing apparatus and a method using the same are provided for accessing a non-volatile memory storage device by an external electronic device. The accessing apparatus includes a fixing unit, a transmission interface device, and a transmission media. The transmission interface device has a resilience power interface unit and a data interface unit. One end portion of the transmission media is electrically connected to the transmission interface device. When the external electronic device accesses the non-volatile memory storage device, the transmission media transmits power to the non-volatile memory storage device through the resilience power interface unit for driving the non-volatile memory storage device so that the transmission media is capable of transmitting either an accessing command or an accessing data to the data interface unit. | 2010-04-22 |
20100100663 | Method of Performing Wear Leveling with Variable Threshold - A wear leveling limit and/or an overall erase count threshold used for activating wear leveling in a non-volatile memory may be adjusted by determining a stage according to a highest erase count, and determining the wear leveling limit and/or the overall erase count threshold corresponding to the stage. Wear leveling may then be performed according to the wear leveling limit and/or the overall erase count threshold. | 2010-04-22 |
20100100664 | STORAGE SYSTEM - Increase in read-access response time is avoided in a RAID storage system loaded with SSD. A process or is configured such that the processor sets SSD to a write-enable state, and sets different SSD, from which the same data can be acquired, to a write-disable state; allows predetermined data in CM to be written into the SSD in the write-enable state; receives a read request of data from a host computer; acquires object data of the read request from the different SSD in the case that a storage location of the data is the SSD being set to the write-enable state and transmits the acquired data to the host computer. | 2010-04-22 |
20100100665 | DATA UPDATE METHOD AND FLASH MEMORY APPARATUS UTILIZING THE SAME - The invention discloses a flash memory apparatus, including a plurality of blocks and a memory controller. The blocks include a first block, wherein the first block includes a first page. The memory controller receives a first data to be written into the first page of the first block. When the first page has already been written to, the memory controller further selects one of the blocks as a first cache block, writes the first data into a first cache page of the first cache block and records the number of the first block and the number of the first page into the first cache page. The memory controller further updates the first block according to the number of the first block and the number of the first page recorded in the first cache page when receiving an update command. | 2010-04-22 |
20100100666 | SYSTEM AND METHOD FOR CONTROLLING FLASH MEMORY USING DESCRIPTOR ARRAY - Disclosed are a system and method for controlling a flash memory using a descriptor array, which may maximize a performance of a flash memory based-storage system. The system includes a descriptor array receipt unit for receiving, from a processor, a descriptor array including, at least one descriptor corresponding to at least one operation; and a flash memory control unit for verifying the descriptor included in the descriptor array and executing a flash memory control command included in the verified descriptor, wherein the flash memory control unit executes the flash memory control command independent from the operation of the processor. | 2010-04-22 |
20100100667 | Flash memory system and designing method of flash translation layer thereof - The method of designing a flash translation layer includes receiving a logical address according to an external request and mapping a physical address that corresponds to the logical address. The mapping manages continuous logical addresses and physical addresses corresponding to the logical addresses as one mapping unit. | 2010-04-22 |
20100100668 | CONTROL METHOD FOR LOGICAL STRIPS BASED ON MULTI-CHANNEL SOLID-STATE NON-VOLATILE STORAGE DEVICE - A control method for logical strips based on a multi-channel solid-state non-volatile storage device is provided. The method includes the following processing steps. In Step 1, a storage space of every channel is partitioned into a plurality of storage units of equal size. In Step 2, at least one logical strip is set by which the storage units with discrete physical addresses across a plurality of channels are organized into a continuous logical space. In Step 3, during data reading/writing operation, the data is divided according to a size of each local strip, the divided data is mapped to the storage units of every channel, and a parallel reading/writing operation is performed across the channels. This method may increase the efficiency of reading and writing operations of the storage device and prolong the operating life span of the device. | 2010-04-22 |
20100100669 | SELF-ADAPTIVE CONTROL METHOD FOR LOGICAL STRIPS BASED ON MULTI-CHANNEL SOLID-STATE NON-VOLATILE STORAGE DEVICE - A self-adaptive control method for logical strips based on a multi-channel solid-state non-volatile storage device is provided. The method includes the following steps. Storage space of every channel is divided into a plurality of storage units of equal size. At least one logical strip is set by which the storage units with discrete physical addresses across the channels are organized into a continuous logical space, and a logical strip variable is set for determining the storage units organized by the logical strip. Historical operation information of the storage device is obtained statistically, and the logical strip variable is dynamically adjusted according to the obtained operation information. During data interaction, the data is divided according to the logical strip variable, the divided data is mapped to the storage units of every channel, and parallel reading and writing operations are performed among the channels. | 2010-04-22 |
20100100670 | Out of Order Dram Sequencer - Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the memory access requests were to be executed in the received order are detected, and the received order of the memory access requests is rearranged to avoid or minimize the conflicts or delays and to optimize the flow of data to and from the memory data bus. The memory access requests are executed in the reordered sequence, while the originally received order of the requests is tracked. After execution, data read from the memory device by the execution of the read-type memory access requests are transferred to the respective requestors in the order in which the read requests were originally received. | 2010-04-22 |
20100100671 | DOUBLE DENSITY CONTENT ADDRESSABLE MEMORY (CAM) LOOKUP SCHEME - The number of content addressable memory (CAM) lookups is reduced from two to one. Each side (left and right sides) of a CAM is programmed with network addresses, such as IP addresses, based on certain bits of the network addresses. These bits of the network addresses (which represent packet routes) are examined and used to determine whether the particular network address is to be placed on the left or right sides of the CAM. The grouping of certain network addresses either on the left or right sides of the CAM can be performed by examining an individual bit of each network address, by performing an exclusive OR (XOR) operation on a plurality of bits of each network address, and/or by searching for bit patterns of the network address in a decision table. Network addresses that cannot be readily assigned to a particular side of the CAM using these grouping techniques are programmed into both sides of the CAM. During packet routing, techniques similar to the grouping techniques that populated the CAM are used to determine which of the two sides of the CAM is to be searched. | 2010-04-22 |
20100100672 | RELAY APPARATUS AND DATA CONTROL METHOD - When a data word is designated through a network search engine, a FIFO unit, and the like, a relay apparatus according to the invention searches for an associative memory address corresponding to the data word. Even when the associative memory address is internally converted to a contents memory address, the relay apparatus stores the contents memory address by causing it to correspond to a search result corresponding to the contents memory address as well as outputs the associative memory address together with the search result. | 2010-04-22 |
20100100673 | Hierarchical immutable content-addressable memory processor - Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write. | 2010-04-22 |
20100100674 | MANAGING A REGION CACHE - A method, system, and computer program product are provided for managing a cache. A region to be stored within the cache is received. The cache includes multiple regions and each of the regions is defined by memory ranges having a starting index and an ending index. The region that has been received is stored in the cache in accordance with a cache invariant. The cache invariant guarantees that at any given point in time the regions in the cache are stored in a given order and none of the regions are completely contained within any other of the regions. | 2010-04-22 |
20100100675 | SYSTEM AND METHOD FOR MANAGING STORAGE DEVICE CACHING - A data storage device comprising at least one non-volatile storage medium, at least one data cache, and a controller configured to perform cache writing operations between the at least one non-volatile storage medium and the at least one data cache based on user-selected caching modes. | 2010-04-22 |
20100100676 | Systems And Methods Of Presenting Virtual Tape Products To A Client - Systems and methods for presenting virtual tape products to a client are disclosed. An exemplary method may include allocating a plurality of disks connected to a host bus adapter (HBA) as both virtual tape storage and virtual disk storage. The method may also include translating at the HBA an input/output (I/O) communication between the client and the plurality of disks to access at least a portion of the plurality of disks allocated as virtual tape storage. The method may also include handling all other I/O communication between the client and the plurality of disks for access to the plurality of disks allocated as virtual disk storage. | 2010-04-22 |
20100100677 | Power and performance management using MAIDx and adaptive data placement - The present invention is a method for storing data. The method includes the step of dividing data into a plurality of uniformly-sized segments. The method further includes storing said uniformly-sized segments on a plurality of storage mechanisms. The method includes the steps of monitoring access to the uniformly-sized segments stored on the plurality of storage mechanisms to determine an access pattern; monitoring access patterns between the plurality of disks and monitoring performance characteristics of the plurality of storage mechanisms to determine a performance requirement for the plurality of storage mechanisms. Finally, the method includes the step of migrating at least one segment of the plurality of uniformly-sized segments from a first storage mechanism of the plurality of storage mechanisms to a second storage mechanism of the plurality of storage mechanisms in response to at least one of the access patterns or the performance requirements. | 2010-04-22 |
20100100678 | Volume management system - The work load imposed on an administrator increases because the administrator has heretofore performed the work of allocating volumes to applications of PC server devices and the work of taking over volumes for applications in accordance with change in PC server devices. To solve this problem, there is provided a volume management system in a computer system having storage devices each of which has a unit which manages volume configuration information in accordance with each application, a unit which manages volume usage information in accordance with each of volumes for the applications, and a unit which manages allocatable areas of the storage devices while partitioning the allocatable areas of the storage devices in accordance with performance and reliability, wherein the volume management system has: a unit which selects suitable allocation regions in accordance with the volume usages of the applications; a unit which selects a suitable allocation region in accordance with change of host performance and migrates a volume to the suitable allocation region when host configuration of an application is changed; and a unit which changes configuration information to perform change of setting on each host. | 2010-04-22 |
20100100679 | Embedded scale-out aggregator for storage array controllers - Methods and systems for dynamic storage tiering may comprise: discovering one or more remote virtual drives associated with one or more remote storage arrays; advertising one or more local virtual drives associated with a local storage array; receiving one or more IO requests from a client addressed to one or more remote virtual drives associated with one or more remote storage arrays; transmitting one or more command descriptor block (CDB) requests to one or more remote storage arrays associated with the one or more virtual drives to allocate local cache space and transmitting the one or more IO requests to the one or more remote storage arrays via Remote Direct Memory Access (RDMA). | 2010-04-22 |
20100100680 | STORAGE APPARATUS AND CACHE CONTROL METHOD - The object of the present invention is to provide a storage apparatus capable of optimizing the cache-resident area in a case where cache residence control in units of LUs is employed to a storage apparatus that virtualizes the capacity by acquiring only a cache area of a size that is the same as the physical capacity assigned to the LU. In the storage apparatus, in a case where an LU that is a logical space resident in the cache memory is configured by a set of pages acquired by dividing a pool volume as a physical space created by using a plurality of storage devices in a predetermined size, when the LU to be resident in the cache memory is created, a capacity corresponding to the size of the LU is not initially acquired in the cache memory, a cache capacity that is the same as the physical capacity allocated to a new page is acquired in the cache memory each time when the page is newly allocated, and the new page is resident in the cache memory. | 2010-04-22 |
20100100681 | System on a chip for networking - A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries. | 2010-04-22 |
20100100682 | Victim Cache Replacement - A data processing system includes a processor core having an associated upper level cache and a lower level victim cache. In response to a memory access request of the processor core that specifies a non-modifying access to a target coherency granule, a determination is made whether the memory access request hits or misses in a directory of the lower level victim cache. In response to determining that the memory access request hits in the lower level victim cache in a data-valid coherence state, the lower level victim cache provides the target coherency granule of the memory access request to the upper level cache. The lower level victim cache preserves the target coherency granule in the lower level victim cache in a shared coherence state if the memory access request is of a first type and invalidates the target coherency granule if the memory access request is of a second type. | 2010-04-22 |
20100100683 | Victim Cache Prefetching - A processing unit for a multiprocessor data processing system includes a processor core and a cache hierarchy coupled to the processor core to provide low latency data access. The cache hierarchy includes an upper level cache coupled to the processor core and a lower level victim cache coupled to the upper level cache. In response to a prefetch request of the processor core that misses in the upper level cache, the lower level victim cache determines whether the prefetch request misses in the directory of the lower level victim cache and, if so, allocates a state machine in the lower level victim cache that services the prefetch request by issuing the prefetch request to at least one other processing unit of the multiprocessor data processing system. | 2010-04-22 |
20100100684 | SET ASSOCIATIVE CACHE APPARATUS, SET ASSOCIATIVE CACHE METHOD AND PROCESSOR SYSTEM - A set associative cache memory includes a tag memory configured to store tags which are predetermined high-order bits of an address, a tag comparator configured to compare a tag in a request address (RA) with the tag stored in the tag memory and a data memory configured to incorporate way information obtained through a comparison by the tag comparator in part of a column address. | 2010-04-22 |
20100100685 | EFFECTIVE ADDRESS CACHE MEMORY, PROCESSOR AND EFFECTIVE ADDRESS CACHING METHOD - An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index. | 2010-04-22 |
20100100686 | Cache controller and control method - In such a configuration that a port unit is provided which takes a form being shared among threads and has a plurality of entries for holding access requests, and the access requests for a cache shared by a plurality of threads being executed at the same time are controlled using the port unit, the access request issued from each tread is registered on a port section of the port unit which is assigned to the tread, thereby controlling the port unit to be divided for use in accordance with the thread configuration. In selecting the access request, the access requests are selected for each thread based on the specified priority control from among the access requests issued from the threads held in the port unit, thereafter a final access request is selected in accordance with a thread selection signal from among those selected access requests. In accordance with such a configuration, the cache access processing can be carried out while reducing the amount of resources of the port unit and assuring effective use of such resources. | 2010-04-22 |
20100100687 | Method and Apparatus For Increasing Performance of HTTP Over Long-Latency Links - The invention increases performance of HTTP over long-latency links by pre-fetching objects concurrently via aggregated and flow-controlled channels. An agent and gateway together assist a Web browser in fetching HTTP contents faster from Internet Web sites over long-latency data links. The gateway and the agent coordinate the fetching of selective embedded objects in such a way that an object is ready and available on a host platform before the resident browser requires it. The seemingly instantaneous availability of objects to a browser enables it to complete processing the object to request the next object without much wait. Without this instantaneous availability of an embedded object, a browser waits for its request and the corresponding response to traverse a long delay link. | 2010-04-22 |
20100100688 | LOW-LEVEL CONDITIONAL SYNCHRONIZATION SUPPORT - A low-overhead conditional synchronization instruction operates on a synchronization variable which includes a lock bit, a state specification, and bits for user-defined data. The instruction specifies the memory address of the synchronization variable and a condition. During the synchronization instruction the condition is compared to the state specification within an atomic region. The match succeeds if the condition matches the state specification and the lock bit is clear. The synchronization instruction may operate with a cache under a cache coherency protocol, or without a cache, and may include a timeout operand. | 2010-04-22 |
20100100689 | TRANSACTION PROCESSING IN TRANSACTIONAL MEMORY - A transactional memory processing system provides for the integration of transactional memory concepts at the compiler-level into a higher-level traditional transaction processing system. Atomic blocks at the compiler-level can be specified as atomic block transactions and include the features of atomicity and isolation. Actions within this atomic block transaction include the enlistment of resource managers from a repository. The repository can now include a pre-programmed memory resource manager to manage the transactional memory. As in traditional transactions, a commit protocol can be used to determine if the actions are valid and can be exposed outside of the transaction. Unlike traditional transactions, however, the transaction is not necessarily doomed if all of the actions are not validated. Rather, memory conflicts can cause a rollback and re-execution of the atomic block transaction, which can be repeated as long as necessary, until the memory resource manger votes to commit. | 2010-04-22 |
20100100690 | SYSTEM TO REDUCE INTERFERENCE IN CONCURRENT PROGRAMS - Locks are used to protect variables. All variables protected by a lock are allocated on a page associated with a lock. When a thread (called the owner) acquires the lock, a local copy of the memory page containing the variable is created, the original memory page is protected, and all access of the variable in the owner thread is directed to the local copy. Upon releasing the lock, the changes from the local copy are carried over to the memory page and the memory page is unprotected. Any concurrent access of the variable by non-owner threads triggers an exception handler (due to the protection mechanism) and delays such an access until after the owner thread has finished accessing the variable. | 2010-04-22 |
20100100691 | Indirect Register Access Method and System - Systems and methods are provided for managing access to registers. In one embodiment, a system may include a processor and a plurality of registers. The processor and the plurality of registers may be integrated into a single device, or may be in separate devices. The plurality of registers may include a first set of registers that are directly accessible by the processor, and a second set of registers that are not directly accessible by the processor. The second set of registers may, however, be accessed indirectly by the processor via the first set of registers. In one embodiment, the first set of registers may include a register for selecting a register bank from the second set of registers, and a register for selecting a particular address within the register bank, to allow indirect access by the processor to the registers of the second set. | 2010-04-22 |
20100100692 | Exploiting Register High-Words - A method of utilizing registers in a processor device is provided. The method includes: determining a first operand based on an operand notation indicating a subset of high-order bits of a first register, the first register having a total of sixty-four bits; determining a second operand based on an operand notation indicating at least one of a subset of high-order bits of a second register and a subset of low-order bits of the second register, the second register having a total of sixty-four bits; performing an operation based on the first operand and the second operand; and updating at least one of the first register and the second register based on a result of the operation, and wherein the high-order bits include bits that are greater than thirty-two, and wherein the low-order bits include bits that are less than or equal to thirty-two. | 2010-04-22 |
20100100693 | DETECTION OF ACTIVITY PATTERNS - A monitoring system ( | 2010-04-22 |
20100100694 | RECORDING/REPRODUCING APPARATUS FOR PERFORMING RMW FOR LOW, RECORDING/REPRODUCING METHOD THEREFOR, AND INFORMATION STORAGE MEDIUM THEREFOR - Replacement data for updating data recorded on an information storage medium is recorded in an area for logical overwrite (LOW) replacement; replacement data for replacing a defect generated on the medium is recorded in an area for defect replacement; and, if a defect is generated in an original block recorded in a predetermined area of the medium during a read-modify-write (RMW) process for a LOW for at least partial data of an original block, a replacement block replacing the original block is recorded in the area for LOW replacement and a defect list (DFL) entry including location information of the original block and location information of the replacement block is generated to indicate the replacement state. | 2010-04-22 |
20100100695 | Storage system and remote copy control method - A storage system is provided which is capable of realizing a remote copy function for speeding up lines virtually by satisfying such demand to distribute copy data into a plurality of lines. In a storage system for connecting a local storage device and a remote storage device via a plurality of lines, the local storage device includes a remote copy program for distributing data of a plurality of logical volumes accessed from a host computer into a plurality of paths on the basis of status of the plurality of paths interposing the plurality of lines, to perform a remote copy from the local storage device to the remote storage device. Accordingly, the local storage device distributes data of the logical volumes into the plurality of lines to copy the data to the remote storage device, resulting in speeding up the lines virtually. | 2010-04-22 |
20100100696 | APPLICATION MIGRATION AND POWER CONSUMPTION OPTIMIZATION IN PARTITIONED COMPUTER SYSTEM - A storage device including a logical volume being a migration source of an application copies data stored in the logical volume being a migration source into a logical volume being a migration destination of the application. After such a copy process is started, the storage device stores the data written into the logical volume being a migration source as differential data without storing the data into the logical volume being a migration source. When the copy process is completed for the data stored in the logical volume being a migration source, a management computer starts copying of the differential data, and in a time interval after the copying of the data stored in the logical volume being a migration source is completed but before the copying of the differential data is completed, a computer being a migration destination of the application is turned ON. With such a logically-partitioned computer system, power consumption at the time of application migration can be reduced. | 2010-04-22 |
20100100697 | INFORMATION PROCESSING SYSTEM AND MANAGEMENT METHOD THEREOF - An information processing apparatus is provided capable of effectively utilizing resources in data transmission processes executed by a plurality of control units. A contents delivery apparatus includes network IFs, control units, disk drives used by the respective control units, and cache areas in which content data read by the respective control units from the respective disk drives is temporarily stored. Upon receiving a content data delivery request from a terminal device, the control unit of the contents delivery apparatus checks whether the requested data is present in the cache area, and if it is present (cache hit), replicates the data to the disk drive used by any one of other control units to notify a portal server allocating a delivery destination so that it is well prepared for a new delivery request from the terminal device. | 2010-04-22 |
20100100698 | METHOD AND APPARATUS FOR MAXIMIZING DATA RECOVERABILITY USING COUPLING UPDATES BY PARTIES - A data recovery system is disclosed that permits recovery of data in a computer memory. The system includes an update storage system, a long-term storage system, a coupling functional circuit, and a parity register. The update storage system is for providing backup storage of recently updated data. The long-term storage system is for providing backup storage of data that has not been recently updated. The coupling functional circuit is for providing a bit-wise commutative binary operation of data from the update storage system and from the long term storage system. The parity register is for maintaining parity snapshots of the output of the coupling functional circuit. | 2010-04-22 |
20100100699 | Method for Controlling Performance Aspects of a Data Storage and Access Routine - A method for improving the performance of a computerized data storage and access system includes the steps (a) providing a virtual representation of an existing data storage controller accessible to a computing system, (b) providing a configuration interface executable by an operator of the computing system, (c) using the configuration interface, reserving an amount available memory for dedicated use as a data cache and or additional storage space for storing data written to one or more disk drives representing data storage disks of the data storage and access system, (d) intercepting read and write requests to the data storage controller from the central processing unit of the computing system via the virtual representation of the controller, and (e) writing data into the reserved memory or serving data from the reserved memory in lieu of accessing a data storage disk represented by the one or more disk drives. | 2010-04-22 |
20100100700 | ADAPTIVELY PREVENTING OUT OF MEMORY CONDITIONS - A computer-implemented method of preventing an out-of-memory condition can include evaluating usage of virtual memory of a process executing within a computer, detecting a low memory condition in the virtual memory for the process, and selecting at least one functional program component of the process according to a component selection technique. The method also can include sending a notification to each selected functional program component and, responsive to receiving the notification, each selected functional program component releasing at least a portion of a range of virtual memory reserved on behalf of the selected functional program component. | 2010-04-22 |
20100100701 | OPTIMIZING DEFRAGMENTATION OPERATIONS IN A DIFFERENTIAL SNAPSHOTTER - A method for establishing and maintaining a differential snapshot of a set of files stored on a volume is disclosed. The invention achieves processing time and disk space optimizations by avoiding copy-on-write operations for logically insignificant moves of blocks, such as the block rearrangements characteristic of defragmentation utilities. A file system enhancement enabling the passing of a block copy command from the file system to lower-level drivers, is used to inform the snapshotter that a block move operation is not logically meaningful. When the logically insignificant move is of a block whose data forms part of the data captured in the snapshot virtual volume, and when the move is to a block location that is functioning as logical free space, the snapshotter can simply modify its block bitmap and update translation table entries without needing to perform a copy-on-write. | 2010-04-22 |
20100100702 | Arithmetic processing apparatus, TLB control method, and information processing apparatus - An arithmetic processing apparatus includes a main TLB that stores therein, as a page table, entries indicating correspondences between virtual and physical addresses, and a micro TLB that stores therein part of the table. The apparatus associates together the physical address stored in the main TLB, the virtual address associated with the physical address, and a context ID included in an address-translation request and registers these associated together in the micro TLB as an entry. When receiving the request, the apparatus does not translate the context ID included in the request into a context value but searches for an entry matching the virtual address and the context ID included in the request. When the entry is searched for and found, the response is the physical address included in the entry. When the entry is searched for and not found, the request is transmitted to the main TLB. | 2010-04-22 |
20100100703 | System For Parallel Computing - A system and a method for parallel computing for solving complex problems is envisaged. Particularly, hierarchical parallel computing system is envisaged by this invention, which is formed by multiple levels of groups, where each group consists of multiple processing elements. Each group of the parallel computing system models as processing element to its immediate upper layer. Thus, each processing element is hierarchically tagged to its immediate upper level, and a multi-level tier of groups are formed. In accordance with this invention, the parallel computing system operates by breaking any problem hierarchically, first across the groups and then within the groups. This hierarchical breakup of the problem helps in significantly improving the time required for processing a problem. | 2010-04-22 |
20100100704 | Integrated circuit incorporating an array of interconnected processors executing a cycle-based program - An integrated circuit | 2010-04-22 |
20100100705 | Distributed Processing System, Distributed Processing Method and Computer Program - A distributed processing system includes at least two processing elements ( | 2010-04-22 |
20100100706 | MULTIPLE PROCESSOR SYSTEM, SYSTEM STRUCTURING METHOD IN MULTIPLE PROCESSOR SYSTEM AND PROGRAM THEREOF - For flexibly setting up an execution environment according to contents of processing to be executed while taking stability or a security level into consideration, the multiple processor system includes the execution environment main control unit | 2010-04-22 |
20100100707 | DATA STRUCTURE FOR CONTROLLING AN ALGORITHM PERFORMED ON A UNIT OF WORK IN A HIGHLY THREADED NETWORK ON A CHIP - A computer-implemented method, system and computer program product for controlling an algorithm that is performed on a unit of work in a subsequent software pipeline stage in a Network On a Chip (NOC) is presented. In one embodiment, the method executes a first operation in a first node of the NOC. The first node generates payload, and then loads that payload into a message. The message with the payload is transmitted to a nanokernel that controls a second node in the NOC. The nanokernel calls an algorithm that is needed by a second operation in a second node in the NOC, which uses the algorithm to execute the second operation. | 2010-04-22 |
20100100708 | Processing device - A processing device which can execute a plurality of threads includes: an execution unit which executes a command; a supply unit which supplies a command to the execution unit; a buffer unit which holds the command supplied from the supply unit; and a control unit which manages the buffer unit. The buffer unit has a set of buffer elements. Each of the buffer elements has a data unit for storing a command and a pointer unit for defining a connection relationship between the buffer elements. The control unit has a thread allocation unit which allocates a sequence of buffer elements whose connection relationship has been defined by the pointer unit for respective threads executed by the processing device. | 2010-04-22 |
20100100709 | Instruction control apparatus and instruction control method - In a CPU having a SMT function of executing plural threads composed of a series of instructions representing processing, there are provided a decode section for decoding processing represented by instructions of plural threads, an instruction buffer for obtaining instructions from a thread and holding the instructions, and inputting the held instructions to the decode section in order in the thread, and an execution pipeline for executing processing of instructions decoded by the decode section. The decode section checks whether or not an executable condition is ready for an instruction when the instruction is decoded and requests that the instructions held in the instruction buffer and an instruction subsequent to an instruction that is not ready with an executable condition are inputted again to the decode section. | 2010-04-22 |
20100100710 | Information processing apparatus, cache memory controlling apparatus, and memory access order assuring method - According to an aspect of the embodiment, when data on a cache RAM is rewritten in a storage processing of one thread, an determination unit searches a fetch port which holds a request of another thread, checks whether a request exists whose processing is completed, whose instruction is a load type instruction, and whose target address corresponds to a target address in a storage processing. When the corresponding request is detected, the determination unit sets a re-execution request flag to all the entries of the fetch port from the next entry of the entry which holds the oldest request to the entry which holds the detected request. When the processing of the oldest request is executed, a re-execution request unit transfers a re-execution request of an instruction to an instruction control unit for the request held in the entry in which the re-execution request flag is set. | 2010-04-22 |
20100100711 | DATA PROCESSOR DEVICE AND METHODS THEREOF - A microsequencer is disclosed that controls the order in which microcode instructions are fetched from a microcode ROM. Each microcode instruction includes an execution command for execution by one or more execution units. Each microcode instruction also includes a microsequencer command to indicate the location of another microcode instruction at the microcode ROM. The microcode instruction can also include a delay field, indicating a selectable time when the associated microcode instruction is to be decoded. The delay field thereby provides more flexible control of the sequencing of microcode instructions. | 2010-04-22 |
20100100712 | Multi-Execution Unit Processing Unit with Instruction Blocking Sequencer Logic - A processing unit includes multiple execution units and sequencer logic that is disposed downstream of instruction buffer logic, and that is responsive to a sequencer instruction present in an instruction stream. In response to such an instruction, the sequencer logic issues a plurality of instructions associated with a long latency operation to one execution unit, while blocking instructions from the instruction buffer logic from being issued to that execution unit. In addition, the blocking of instructions from being issued to the execution unit does not affect the issuance of instructions to any other execution unit, and as such, other instructions from the instruction buffer logic are still capable of being issued to and executed by other execution units even while the sequencer logic is issuing the plurality of instructions associated with the long latency operation. | 2010-04-22 |
20100100713 | FAST FLOATING POINT COMPARE WITH SLOWER BACKUP FOR CORNER CASES - A floating point processor unit executes a floating point compare instruction with two operands of the same or different precision by comparing the two operands in integer format, which speeds up the execution of the floating point compare instruction significantly. The floating point processor now executes the floating point compare instruction at least twice as fast or faster (e.g., two clock cycles instead of five clock cycles in the prior art) for nearly most operand cases (e.g., 99% of all cases). Only the rare corner cases require additional operations on one of the operands and thus require additional cycles of execution time because the integer compare operation will not work for these corner cases. This is due to the fact that one operand is a single precision subnormal number in an unnormalized representation (i.e., has two representations) and the other operand is in the SP subnormal range such that the integer compare operation will fail. | 2010-04-22 |
20100100714 | System and Method of Indirect Register Access - Systems and methods are provided for managing access to registers. A system may include a set of direct registers and a set of indirect registers. The indirect registers may be accessed through the direct registers, and the direct registers may provide various features to provide faster access to the indirect registers. One of the direct registers may indicate access modes for accessing the indirect registers. The access modes may include auto-increment, auto-decrement, auto-reset, and no change modes. Based on the access mode, the currently accessed address may be automatically modified after accessing the indirect register at the address. | 2010-04-22 |
20100100715 | HANDLING DEBUGGER BREAKPOINTS IN A SHARED INSTRUCTION SYSTEM - A debugger debugs processes that execute shared instructions so a breakpoint set for one process will not cause a breakpoint to occur in the other processes. A breakpoint is set by recording the original instruction at the desired location and writing a trap instruction to the shared instructions at that location. When a process encounters the breakpoint, the process passes control to the debugger for breakpoint processing if the breakpoint was set at that location for that process. If the trap was not set at that location for that process, the cacheline containing the trap is copied to a small scratchpad memory, and the virtual memory mappings are changed to translate the virtual address of the cacheline to the scratchpad. The original instruction is then written to replace the trap instruction in the scratchpad, so the process can execute the instructions in the scratchpad thereby avoiding the trap instruction. | 2010-04-22 |
20100100716 | Conserving Power Using Predictive Modelling and Signaling - Methods and systems for conserving power using predictive models and signaling are described. Parameters of a power management policy are set based on predictions based on user activity and/or signals received from a remote computer which define a user preference. In an embodiment, the power management policy involves putting the computer into a sleep state and periodically waking it up. On waking, the computer determines whether to remain awake or to return to the sleep state dependent upon the output of a predictive model or signals that encode whether a remote user has requested that computer remain awake. Before returning to the sleep state, a wake-up timer is set and this timer triggers the computer to subsequently wake-up. The length of time that the timer is set to may depend on factors such as the request from the remote user, context sensors and usage data. | 2010-04-22 |
20100100717 | MECHANISM FOR PERFORMING FUNCTION LEVEL RESET IN AN I/O DEVICE - An I/O device having function level reset functionality includes a host interface that may include a master reset unit, a plurality of client interfaces, each corresponding to one or more functions, and a plurality of hardware resources. Each hardware resource may be associated with a respective function. In response to receiving a reset request to reset a specific function, the master reset unit may provide to each client interface, a request signal corresponding to the reset request, and a signal identifying the specific function. Each client interface having an association with the specific function may initiate a reset operation of the associated hardware resources, and also provide a client reset done signal for the specific function to the master reset unit in response to completion of the reset operations of the hardware resources. The master reset unit provides a reset done signal for the specific function to the host interface. | 2010-04-22 |
20100100718 | In-the-flow security services for guested virtual machines - Methods and apparatus provide security to guest virtual machines configured on a hardware platform. A plurality of I/O domains are also configured on the hardware platform and connect between each of the guest virtual machines and a network connected to the hardware platform or remote or local storage available to the hardware platform. In this manner, the I/O domains are configured in the flow of the guest virtual machines as they utilize available resources, for instance, and are able to filter network or block level traffic, respectively. Representatively, one filter analyzes packets exchanged to and from the network, while the other filter analyzes internal traffic and may be a block-tap, stackable driver, virus scanning application, etc. Also, the guested virtual machines communicate with the I/O domains by way of a shared memory transport. Still other features contemplate drivers, operating systems, and computer program products, to name a few. | 2010-04-22 |
20100100719 | METHOD FOR REDUCING BOOTING TIME AND COMPUTER USING THE SAME - The invention provides a method for reducing booting time and a computer using the same. The method includes the following steps. The computer is shut down. After the step of shutting down the computer, the computer is booted up to make the computer enter into a power-saving mode. Thus, when a user performs an operation to boot up the computer, the computer resumes a normal state from the power-saving mode. | 2010-04-22 |
20100100720 | COMPUTER SYSTEM HAVING DUAL BIOS PROGRAM PROTECTING FUNCTION AND CONTROL METHOD THEREOF - A dual BIOS program protecting method is provided for protecting a first BIOS program and a second BIOS program of a computer system. Firstly, a flag is switched from a first status to a second status during the refreshing of the first BIOS program. If the first BIOS program is successfully refreshed, the flag is switched from the second status to the first status. If the flag is in the second status when the computer system is booted, a first control signal is generated and the second BIOS program enters a write protection mode according to the first control signal. | 2010-04-22 |
20100100721 | METHOD AND SYSTEM OF SECURED DATA STORAGE AND RECOVERY - A method and a system of secured data storage and recovery are provided. First, a secured key and an encrypted user password of a storage device are obtained by using a controller of a storage device. Then, the secured key is encrypted by using the encrypted user password to generate a first private key, the encrypted user password is encrypted by using the secured key to generate a second private key, and data to be stored is encrypted by using the secured key. Finally, the encrypted data, the first private key, and the second private key are transmitted to a remote device for storage through a host. Thereby, the security of data storage is enhanced and data recovery mechanism is provided when the storage device is damaged or lost. | 2010-04-22 |
20100100722 | CONFIGURATION METHOD, SYSTEM AND DEVICE OF CRYPTOGRAPHICALLY GENERATED ADDRESS - A configuration method of a cryptographically generated address (CGA) is disclosed. The configuration method is used to enable a generated CGA to satisfy requirements of a network configuration, and includes the following steps. A Dynamic Host Configuration Protocol (DHCP) server receives a client configuration information sent from a client. The DHCP server generates a CGA according to the client configuration and the network configuration from the DHCP server. The DHCP server delivers the CGA to the client. The network configuration is made as a reference when the CGA is generated, which overcomes a disadvantage that the CGA generated by the client cannot satisfy the requirements of the network configuration in the prior art. Thus, the generation of CGA can be intervened at a network management level, and a management capability of the network is improved. | 2010-04-22 |
20100100723 | SERVICE APPLICATION PLATFORM AND METHOD FOR ACCESSING SERVICE APPLICATION PLATFORM - This invention provides a service application platform and a method for accessing a service application platform. The service application platform includes: a processing interface, adapted to send a service request to a service application client; the service application client, adapted to receive the service request sent from the processing interface, and to send the service request to a server; and the server, adapted to process the service request, and to provide a user with requested information. | 2010-04-22 |
20100100724 | SYSTEM AND METHOD FOR INCREASING THE SECURITY OF ENCRYPTED SECRETS AND AUTHENTICATION - In general, in one aspect, the invention relates to a method for accessing encrypted data by a client. The method includes receiving from the client by a server client information derived from a first secret wherein the client information is derived such that the server can not feasibly determine the first secret The method also includes providing to the client by the server intermediate data, which is derived responsive to the received client information, a server secret, and possibly other information. The intermediate data is derived such that the client cannot feasibly determine the server secret. The method also includes authenticating the client by a device that stores encrypted secrets and is configured not to provide the encrypted secrets without authentication. After the authenticating step, the method also includes providing the encrypted secrets to the client. The encrypted secrets | 2010-04-22 |
20100100725 | PROVIDING REMOTE USER AUTHENTICATION - Providing a remote computer user authentication service involves providing a reference to a user authentication service in a host server's source code (e.g., website source code). Further, integration code that may be used in an application programming interface (API) on the host server for interaction with a user authentication service can be provided. Additionally, a user interface (UI) for user authentication on the host server, and an authentication-test message on the host server using the UI may be provided. Also, providing authentication can comprise sending an authentication-request message to a mobile device designated by the user; and/or can comprise the user responding with information from the authentication-test message. The host server can be notified of the user's authentication after a correct response is received by the user authentication service. | 2010-04-22 |
20100100726 | System and method for unlocking content associated with media - There is presented a system and method for unlocking a content associated with media. In one aspect, the method comprises identifying the media, generating an authentication key using at least one key data from a set of key data contained in the media, determining an address in the media of at least one content unit corresponding respectively to each of the at least one key data used to generate the authentication key; requesting the at least one content unit by providing the address; receiving user data in response to the requesting; comparing the user data with the at least one key data used to generate the authentication key; and unlocking the content associated with the media if the user data matches the authentication key. | 2010-04-22 |
20100100727 | ENCRYPTION AND AUTHENTICATION SYSTEMS AND METHODS - Methods, apparatus, and systems are disclosed for, among other things, passphrase input using secure delay, passphrase input with characteristic shape display, user authentication with non-repeated selection of elements with a displayed set of elements, document authentication with embedding of a digital signature stamp within a graphical representation of the electronic document wherein the stamp comprises digits of a digital signature, and sub-hash computation using secure delay. | 2010-04-22 |
20100100728 | METHOD OF HANDLING A CERTIFICATION REQUEST - In a certification request, a user device includes an object identifier. When a certification authority generates an identity certificate responsive to receiving the certification request, the certification authority includes the object identifier, thereby allowing improved management of the identity certificate at the user device and elsewhere. | 2010-04-22 |
20100100729 | Distribution medium for professional photography - The display of very high definition still images on a high definition television is achieved through the decryption of received images within a DRM capable decryption device embedded within a high definition TV. The decryption device stores a pre-set decryption key, decrypts the incoming high definition still image content, and applies pre-set licensing parameters against the decrypted content. If the license for the encrypted content is determined to be valid the very high definition still images are displayed on the TV, otherwise the TV will display a lack of authorization message if the licensing is determined to be not valid. The embedded DRM decryption device is capable of determining and enforcing a number of licensure conditions for any and all received encrypted imagery. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract. | 2010-04-22 |
20100100730 | SYSTEM AND METHOD FOR SEARCHING AND RETRIEVING CERTIFICATES - A system and method for searching and retrieving certificates, which may be used in the processing of encoded messages. In one broad aspect, a method is provided in which a certificate search request is received, a search of one or more certificate servers for certificates satisfying the request is performed, located certificates are retrieved and processed at a first computing device to determine data that uniquely identifies each located certificate, and search result data comprising the determined data is communicated to a second device (e.g. a mobile device) for use in determining whether each located certificate is already stored on the second device. | 2010-04-22 |
20100100731 | PUSHING CERTIFICATE CHAINS TO REMOTE DEVICES - Rather than managing a certificate chain related to a newly issued identity certificate at a terminal to which a wireless device occasionally connects, a certificate server can act to determine the identity certificates in a certificate chain related to the newly issued identity certificate. The certificate server can also act to obtain the identity certificates and transmit the identity certificates towards the device that requested the newly issued identity certificate. A mail server may receive the newly issued identity certificate and the identity certificates in the certificate chain and manage the timing of the transmittal of the identity certificates. By transmitting the identity certificates in the certificate chain before transmitting the newly issued identity certificate, the mail server allows the user device to verify the authenticity of the newly issued identity certificate. | 2010-04-22 |
20100100732 | PERSONAL INFORMATION DISTRIBUTION MANAGEMENT SYSTEM, PERSONAL INFORMATION DISTRIBUTION MANAGEMENT METHOD, PERSONAL INFORMATION SERVICE PROGRAM, AND PERSONAL INFORMATION UTILIZATION PROGRAM - The present invention is intended to allow distribution of personal information to be managed on the basis of not only a personal information management policy defined by a personal information producer but also management policies of all apparatuses which handle personal information when the distribution of personal information is managed between apparatuses. In its configuration, personal information generation apparatus | 2010-04-22 |
20100100733 | System and Method for Secure Provisioning of an Information Handling System - Systems and methods for reducing problems and disadvantages associated with provisioning of information handling systems, including without limitation those associated with bare metal provisioning of information handling systems, are disclosed. A system may include a processor, and a memory and an access controller each communicatively coupled to the processor. The access controller may store an enterprise public key associated with an enterprise private key and a platform private key associated with the system. The access controller may be configured to: (i) authenticate communications received from a provisioning server communicatively coupled to the access controller based at least on an enterprise public certificate associated with the provisioning server and (ii) establish an asymmetrically cryptographic communications channel between the access controller and the provisioning server based at least on a platform public key associated with the platform private key, the platform private key, the enterprise public key, and the enterprise private key. | 2010-04-22 |
20100100734 | DIGITAL RADIOLOGY SYSTEM AND METHOD FOR IMPLEMENTING THE RADIOLOGY SYSTEM - The invention relates to a digital radiology system and a method of implementing the radiology system. The radiology system includes a mobile cassette and a fixed base station, the cassette including an X-ray image acquisition device to which the cassette is exposed, the system also including a communication interface between the cassette and the base station to enable transfer data such as the image between the cassette and the base station. The communication interface includes a removable wired link and a wireless link, both capable of transferring data and the system includes a circuit to deactivate the wireless link as soon as the wired link is set up. The method includes setting up as a priority a data interchange over the wireless link and switching the exchange over to the wired link as soon as the latter is set up. | 2010-04-22 |
20100100735 | APPARATUS AND METHOD FOR PROVIDING A PORTABLE BROADBAND SERVICE USING A WIRELESS CONVERGENCE PLATFORM - An apparatus and method for providing a portable broadband service, the method comprising enabling a first connectivity between a wireless convergence platform and an Internet gateway; enabling a second connectivity between the wireless convergence platform and at least one device; obtaining an application service through the Internet gateway using the first connectivity; and relaying the application service through the second connectivity to the at least one device. | 2010-04-22 |
20100100736 | METHOD AND SYSTEM FOR SECURE COMMUNICATION - A method and system for secure communication is provided. The method for secure communication with devices includes: obtaining a parameter for protecting a content; authenticating each other by exchanging a certificate with the device; and exchanging a key with the device using a key authenticated through the certificate to establish a secure authenticated channel with the device. Accordingly, it is possible to establish the secure authenticated channel and perform secure communication by computing a secure authenticated channel key. | 2010-04-22 |
20100100737 | SYSTEM AND METHOD FOR GENERATING A NON-REPUDIATABLE RECORD OF A DATA STREAM - A system and method for generating a non-repudiatable record of a communications data stream is provided, which is applicable to real-time and quasi-real-time data streams. A binary communication data stream is captured and segmented into defined frames. A key frame is generated for each of a number of data frames containing integrity and authentication information. The key frame is inserted into the data stream to provide an authenticated data stream. | 2010-04-22 |
20100100738 | METHOD FOR ESTABLISHING A SECURE AD HOC WIRELESS LAN - Secure communications on a network. An unauthenticated client on an network sends start packets to locate other clients. The unauthenticated client receives responses to the start packets from other clients on the network. The responses may be advertise packets that are from advertising clients that may be authenticated clients or other unauthenticated clients in authenticated mode. The unauthenticated client prioritizes the received packets so that authentication can be performed with the most desirable advertising client. Authentication packets are sent and received between the unauthenticated client and the advertising client in an attempt to authenticate. | 2010-04-22 |
20100100739 | SYSTEM AND METHOD FOR SECURE COMMUNICATION, AND A MEDIUM HAVING COMPUTER READABLE PROGRAM EXECUTING THE METHOD - A system and a method for a secure communication, and a medium having a computer readable program therefor. The system for a secure communication comprises an identification information extracting unit for extracting identification information from a request message sent from a web browser, and a response message sending unit for sending a response message corresponding to the request message to the web browser when the identification information satisfies a predetermined reference. Since a response message is sent only to a web browser that sends identification information that satisfies a predetermined reference, a secure HTTP communication can be implemented even when session key information is leaked. | 2010-04-22 |
20100100740 | System and Method for Security Association Between Communication Devices Within a Wireless Home Network - Embodiments of the application describe a method and system for discovering and authenticating communication devices and establishing a secure communication link within a wireless home network without requiring a secure channel. According to an embodiment, communication devices exchange public keys using multiple messages each including at least a portion of the public key of the sending device. The devices authenticate the receipt of the public key and establish a shared master key. The shared master key is used to further derive a session key for securing the application data between the communicating devices for a current session. | 2010-04-22 |
20100100741 | ESTABLISHING SHARED INFORMATION IN A NETWORK - A method for establishing shared information is described. The method includes estimating characteristics of a communication channel between two nodes based on signals transmitted between the nodes. The method also includes transmitting a signal from the first node to the second node, the signal being modulated with a first data sequence according to a first estimated characteristic, and transmitting a signal from the second node to the first node, the signal being modulated with a second data sequence according to a second estimated characteristic. Shared information is formed at each of the first and second nodes based on at least a portion of the first data sequence and at least a portion of the second data sequence. | 2010-04-22 |
20100100742 | Transport Stream Watermarking - Methods and apparatuses for processing and watermarking a transport stream with a message. A processed transport stream that includes processed content packets, associated carrier packets, and a watermark descriptor for a group of the associated carrier packets is created from the transport stream. The processed content data represent a first watermark value and are bounded by transport sector boundaries. The associated carrier packets include replacement watermark data that represent a second watermark value and are bounded by transport sector boundaries. These associated carrier packets are paired with processed content packets. The watermark descriptor includes synchronization data. A watermarked transport stream is created by interleaving selected processed content packets and associated carrier packets according to a watermark message. | 2010-04-22 |
20100100743 | Natural Visualization And Routing Of Digital Signatures - Embodiments are provided for securely visualizing and routing digital signatures in an electronic document generated by an application program executing on a computer system. The application program may generate an electronic document for receiving a signature graphic, and calculate a hash value from the electronic document and the signature graphic, and create a cryptographic signature from the hash value using a cryptographic encryption method. The electronic document is digitally signed by embedding the cryptographic signature therein. The application program may further collect and route digital signatures by automatically collecting signatures from individual signers, one-by-one, and identify the appropriate signature line for each signer to sign. The application program may further generate a user interface for creating and collecting digital signatures. | 2010-04-22 |
20100100744 | VIRTUAL IMAGE MANAGEMENT - Apparatus, systems, and methods may operate to create a virtual image, define usage privileges associated with the virtual image in a description file, and associate a coded summary of an encrypted version of the description file with the virtual image. Other activities may include receiving a request to access the virtual image, authenticating a transmitted version of the coded summary to determine validity of the encrypted version, and processing the encrypted version to determine whether the request to access will be granted. Additional apparatus, systems, and methods are disclosed. | 2010-04-22 |
20100100745 | METHOD OF COMMUNICATING A DIGITAL SIGNATURE TO CERTIFY A TRANSMISSION, ASSOCIATED SYSTEM AND AIRCRAFT - This invention relates to a communication method intended to ensure the receipt of digital data by at least one remote entity, and an associated system, in particular in the context of data transfer with an aircraft. | 2010-04-22 |
20100100746 | SECURE AUTHENTICATION USING HARDWARE TOKEN AND COMPUTER FINGERPRINT - A method and apparatus for secure authentication of a hardware token is disclosed. In one embodiment, a host computer fingerprint is used to generate a partial seed for a challenge-response authentication which is performed on the hardware token. In another embodiment, the host computer fingerprint is used as a personal identification number for the hardware token. | 2010-04-22 |
20100100747 | SYSTEMS AND METHODS FOR DOWNLOADING CODE AND DATA INTO A SECURE NON-VOLATILE MEMORY | 2010-04-22 |
20100100748 | ARRANGEMENT FOR AND METHOD OF PROTECTING A DATA PROCESSING DEVICE AGAINST AN ATTACK OR ANALYSIS - In order to further develop an arrangement for as well as a method of protecting at least one data processing device, in particular at least one embedded system, for example at least one chip card or smart card, against at least one attack, in particular against at least one side-channel attack, for example against at least one current trace analysis, the data processing device, in particular at least one integrated circuit of the data processing device, carrying out calculations, in particular cryptographic operations wherein an attack, for example an E[lectro]M[agnetic] radiation attack, or an analysis, for example a D[ifferential]P[ower]A[nalysis], such attack or such analysis in particular targeted on finding out a private key, is to be securely averted, it is proposed to blind all intermediate results of the calculations by at least one random variable, without inverting any operand of the calculations. | 2010-04-22 |
20100100749 | Single-Chip Computer and Tachograph - A single-chip computer includes at least one first processor core and at least one second processor core constructed on a common chip. The at least one first and the at least one second processor cores are interconnected via a processor interface. Data can be read via a separate or common memory interface from a separate or common data memory respectively and/or stored in said data memory. The single-chip computer includes an encryption and decryption unit which is assigned to the at least one processor core and which is constructed and functionally arranged between the at least one second processor core and the memory interface in such a way that the data which can be exchanged between the at least one second processor core and the data memory can be encrypted and decrypted by the encryption and decryption unit. | 2010-04-22 |
20100100750 | TECHNIQUES FOR ENSURING POWER DELIVERY OVER ONLY DATA-ACTIVE PAIRS OF DATA COMMUNICATIONS CABLING - A power delivery technique which involves connecting power sourcing equipment (PSE) with a powered device (PD) through data communications cabling (e.g., an Ethernet cable). The technique further involves negotiating an acceptable power level for the PD and a data rate for the PD, and enforcing delivery of power to the PD using only wire pairs of the data communications cabling which carry data between the PSE and the PD. As a result, the PSE does not deliver any power to the PD through wire pairs which are not data-active. | 2010-04-22 |
20100100751 | Power Management Method for a Portable Computer System and Related Power Supply Device and Portable Computer System - A power management method for a portable computer system is disclosed. The portable computer system includes a plurality of power storage devices utilized for storing power and outputting a discharge current to the portable computer system. The power management method includes receiving a power and generating a corresponding charge current for charging a power storage device of the plurality of power storage devices, and comparing the discharge current and the charge current and adjusting power consumption of the portable computer system accordingly. | 2010-04-22 |
20100100752 | System and Method for Managing Power Consumption of an Information Handling System - An AC-to-DC power adapter provides DC power to an information handling system at a first higher DC voltage or a second lower DC voltage based upon a power state of the information handling system. For example, approximately 19 Volts DC power is provided if the information handling system is in an on state or if the information handling system is charging a battery. Approximately 13 Volts DC power is provided if the information handling system is in a reduced power state, such as an ACPI S3 state, with a battery having a substantially full charge. | 2010-04-22 |
20100100753 | POWER CONTROL CIRCUIT - A power control circuit for supplying power for a computer component of a computer includes first to sixth switches. In response to the computer changing to a normal work state, a power state signal changes from low level to high level and a motherboard state signal is at high level, the fourth switch is turned on, the fifth switch is turned off, and the sixth switch is turned on, and power of the computer component is stably supplied by a system power supply. The motherboard state signal and the power state signal are at low level in response to the computer changing to a sleep state, the second switch is turned off, the first and third switches are turned on, and power of the computer component is stably supplied by a standby power supply. | 2010-04-22 |
20100100754 | AUTOMATIC POWER-UP OF PORTABLE ELECTRONIC DEVICE BASED ON TIME-DEPENDENT EVENT - A method of controlling a portable electronic device includes receiving a power-down command, determining an automatic power-up date and time based on an earliest one of a next preset power-up and a next time-dependent event reminder, entering a power-down state, monitoring a date and time, and automatically powering up at the automatic power-up date and time. | 2010-04-22 |
20100100755 | POWER MANAGEMENT METHOD FOR INPUT DEVICE - A power management method for an input device is provided, which includes the following steps: starting to count time and recording a trigger time of the input device after the input device enters a light-sleep mode; and dynamically updating a deep-sleep start time according to the trigger time. When the input device is idle over a standby time, the input device would enter the light-sleep mode and record the trigger time that the input device is restored from the light-sleep mode to an operation mode by a user operating the input device. The method dynamically updates the deep-sleep start time according to the recorded trigger time, and thus better power saving efficiency is achieved. | 2010-04-22 |
20100100756 | Power Supply Wear Leveling in a Multiple-PSU Information Handling System - In some embodiments, a method for power supply wear leveling in an information handling system including multiple power supply units (PSUs) is provided. The method includes maintaining each of multiple PSUs in one of multiple different operational states, automatically determining an accumulated on-time for each of the multiple PSUs, ranking the multiple PSUs based on the accumulated on-time determined for each PSU, and automatically changing the operational state of at least one of the PSUs based at least on the ranking of the multiple PSUs. | 2010-04-22 |
20100100757 | POWER ESTIMATING METHOD AND COMPUTER SYSTEM - In order to calculate the power of logically-partitioned areas without using a power meter in a storage system logically partitioning a storage area, there is provided a power estimating method in a computer system including a management computer and a storage system connected to the management computer and a host computer. The storage system prepares logical storage-volumes in a real area of plural disk drives. The power estimating method includes the steps of: allowing a third processor to calculate operation rates of the disk drives for access to the logical storage-volumes from operating times of the disk drives for access to the logical storage-volumes; and allowing the third processor to calculate power consumption increments of the disk drives for access to the logical storage-volumes by access types from incremental power consumption information and the calculated operation rates of the disk drives. | 2010-04-22 |
20100100758 | POWER OVER NETWORK METHODS AND SYSTEMS - Methods and systems for providing electrical power over a network configured to facilitate digital communications are described herein. In different aspects, the methods and systems may include a service provider network module configured to facilitate digital communications and having an autonomous power supply, and a network connection device operably connected to the service provider network module. The network connection device may include at least one network connection port configured to receive electrical power; and a power switching module coupled to the at least one network connection port and configured to switch from a primary power source to enable the network connection device to receive electrical power from the service provider network module via the at least one network connection port when electrical power from the primary power source is interrupted. | 2010-04-22 |