16th week of 2012 patent applcation highlights part 29 |
Patent application number | Title | Published |
20120092869 | Method & Apparatus for Lighting - A lighting fixture includes a directional light source that produces a plurality of light rays. An optical module is coupled to the directional light source to focus the plurality of light rays into a beam of light rays to be output by the lighting fixture. The angular distribution of a majority of the beam relative to a vector normal to a ceiling on or near which the fixture is to be installed is in a range of 70 to 95 degrees. A blocking structure is used to block a direct view of the beam of light when the fixture is installed such that only indirect light is primarily visible from a viewer at least in or around a working plane substantially parallel to the ceiling. | 2012-04-19 |
20120092870 | HEAT MANAGING DEVICE - It is presented a heat managing device for a light source ( | 2012-04-19 |
20120092871 | RETROFITTABLE LED MODULE WITH HEAT SPREADER - A light source includes one or more solid state light emitting devices, a heat spreader thermally coupled to the one or more light emitting devices, and a mounting carriage configured to mount the one or more solid state light emitting devices in a lighting fixture light and thermally couple the heat spreader to the lighting fixture. | 2012-04-19 |
20120092872 | LIGHT EMITTING ELEMENT AND DISPLAY DEVICE - A light emitting element includes a resonator structure which has a first reflecting member, a second reflecting member, and a light emission layer placed between the first reflecting member and the second reflecting member, and part of light resonated between the first reflecting member and the second reflecting member is transmitted through the first reflecting member or the second reflecting member in the resonator structure. A wavelength at which a resonator output spectrum from the resonator structure has a maximum value is located between a wavelength at which an inner light emission spectrum of the light emission layer has a maximum value and a wavelength at which relative luminous efficiency has a maximum value. | 2012-04-19 |
20120092873 | LED LAMP HAVING WATERPROOF STRUCTURES - An exemplary LED lamp includes a heat sink, an LED module mounted on the heat sink and a lens covering the LED module. The heat sink has a top surface and a bottom surface opposite to the top surface. The LED module is mounted on the top surface of the heat sink. A waterproof groove is defined in the top surface of the heat sink. The groove has an inner wall adjacent to the LED module and an outer wall far away from the LED module. The inner wall is higher than the outer wall. The lens has a downwardly extending flange inserted into the groove. A waterproof ring is received in the groove and pressed by the flange. | 2012-04-19 |
20120092874 | Light-guiding pillar - A light-guiding pillar has a main body and an LED mount. The main body is a strip pervious to light and has a first surface and multiple refracting grooves formed in the main body at intervals. The LED mount is pervious to light, is mounted securely on and connected integrally with the main body as a single part and has an LED hole and a reflecting surface. The LED hole is formed in the LED mount. The reflecting surface is connected to the first surface of the main body, is inclined relative to the first surface of the main body and is capable of totally reflecting light from the LED hole and making the light travel into the main body. The present invention only requires one LED to provide a wide range of illumination and to use one LED saves cost and electricity. | 2012-04-19 |
20120092875 | LIGHTING APPARATUS - A lighting apparatus is configured to expose one end of a substrate in which a electrode pad is formed, and to combine a coupling unit in which a locking ledge is formed. The other end of the substrate is placed atop one end of another lighting apparatus at which an electrode pad is exposed, and the locking ledge of the lighting apparatus is locked into a locking groove of the another lighting apparatus. | 2012-04-19 |
20120092876 | VARIABLE SHAPED LAMP SHADE OF LED LAMP - In a variable shaped lamp shade of an LED lamp, the lamp shade is made of a translucent material matched with an LED lamp strip and a lamp holder and includes at least one strip-shaped optical refraction unit having an external refractive surface, an internal refractive surface corresponding to the external refractive surface, and an assembling structure for matching the lamp holder. The external refractive surface or internal refractive surface is a curved surface without an inflection point and the curved surface has a constant or gradually changing curvature; and a non-curved surface is formed on the other side. The variable shaped lamp overcomes the problems of conventional LED lamp strips having a low illumination and a non-uniform illumination caused by a direct projection or an installation of a conventional lamp shade, and a low light utility caused by a too-large illumination range. | 2012-04-19 |
20120092877 | LAMP HOLDER, LAMP UNIT, AND VIDEO PROJECTOR - A lamp holder that holds a lamp, which is a light source for displaying an image, in a lamp housing. The lamp holder includes an elastic portion, which is held between the lamp and an inner surface of the lamp housing, and a hooking portion, which is fitted into an opening extending through the lamp housing and hooked to an outer surface of the lamp housing. | 2012-04-19 |
20120092878 | HOUSING STRUCTURE OF A LAMP - The present invention relates to a housing structure of a lamp, which includes a square base board and a plurality of sidewalls. The sidewalls extend upwardly from a periphery of the base board, and connect with each other. The sidewalls each have at least a tongue at one side thereof, and a concave at an opposite side thereof. The adjacent sidewalls are connected together by the tongue of one sidewall engaging in the concave recessed inwardly from an outer surface the other sidewall. A spot welding is applied to each of the tongues. | 2012-04-19 |
20120092879 | LAMP INCORPORATING CLIPS - A lamp includes a housing, a cover mounted on the housing, a light source received between the housing and the cover and a plurality of clips fixing the housing to the cover. Each clip has two opposite ends pressing against a top face of the housing and a bottom face of the cover, respectively, and a middle bent inwardly towards the housing. The housing includes a top wall having a plurality of slots to receive corresponding ends of the clips and a sidewall extending downwardly from the top wall to be pressed by the middles of the clips. The cover includes a bottom plate and a flange extending upwardly from the bottom plate. The flange defines a plurality of depressions adjacent to the bottom plate to receive the other ends of the clips. | 2012-04-19 |
20120092880 | Flashlight Mount - A flashlight mount includes a clamp-type positioning element and an elongate clamping element pivotally connected to an upper section of the clamp-type positioning element. To fasten a flashlight to the mount, an engaging section on a lateral side of the flashlight is inserted into a C-shaped groove on a lateral side of a fastening extension of the elongate clamping element. Once the engaging section is inserted in the C-shaped groove to the greatest extent possible, a limiting recess at one end of the flashlight is engaged with a projection at the corresponding end of the fastening extension to fix the flashlight in position to the elongate clamping element. Then, an object to be clamped is inserted into an insertion space extending laterally into the clamp-type positioning element, before a lower screw rod is rotated upward to secure the clamp-type positioning element to the object in a clamping manner. | 2012-04-19 |
20120092881 | Lighting Fixture Mounting Post - A light fixture mounting post includes an upper threaded portion for attaching the post to a light shade and a lower portion having a multiplicity of sequential taper threaded segments for attaching light fixtures to the post. The upper threaded portion has left handed threads, and an O-ring and a shaped rubber washer residing between a post nut and the shade. A post flange limits the insertion depth of the upper threaded portion through the shade. The taper threaded segments include right handed pipe threads for tightly engaging the light fixtures and reduced thickness spaces separating the taper threaded segments allowing easy shortening of the lower portion. An unthreaded shoulder adjacent to one of the reduced thickness spaces lengthens the separation of the taper threaded segments below the unthreaded shoulder from the taper threaded segments above the unthreaded shoulder which facilitates the attachment of known light fixtures. | 2012-04-19 |
20120092882 | METHOD AND DEVICE FOR ILLUMINATING ROADSIDES - A method and a device for illuminating an edge region of a roadway by headlights of a vehicle are disclosed. The vehicle includes a camera. Activating takes place of at least one additional illuminating device or a masking of an headlight that is present on the vehicle. An additional illuminated region is generated which extends in the vertical and the lateral direction with respect to the vehicle. Activating the at least one additional illuminating device or headlight masking at least one headlight present in the vehicle takes place by a navigation system of the vehicle or in response to a decrease in the speed of the vehicle and/or by an object/traffic sign detection using the camera. | 2012-04-19 |
20120092883 | VEHICULAR DUCT WITH INTEGRATED LIGHTING - A body panel for a vehicle includes an outer lens and a light engine projecting a light into the outer lens. The body panel includes a duct, which is disposed at a substantially equal vertical elevation as the outer lens. The light engine is positioned relative to the outer lens to allow the duct to pass directly behind the outer lens, at approximately the same vertical elevation, to improve air flow through the duct. | 2012-04-19 |
20120092884 | PROJECTION HEADLIGHT FOR MOTOR VEHICLES - A projection headlight for motor vehicles has a reflector device, a plurality of light sources, at least one of said light sources assigned to the reflector device. A lens device is arranged in front of the reflector device in the main radiation direction. A cover device in the area of a focal point of the lens device has a cover shaft rotatable across the main radiation direction of the rotating axis main source. The cover shaft is provided with a number of glare edges and/or glare surfaces to adjust light distributors having a number of various cut-off lines. The light sources are arranged on a common light source carrier, the carrier extending substantially perpendicular to the main radiation direction and the carrier being configured to fasten onto a flat side of a heat sink. | 2012-04-19 |
20120092885 | HEAD LAMP ASSEMBLY AND VEHICLE INCLUDING THE SAME - A head lamp assembly including a housing; a plurality of head lamp cases installed in the housing, wherein each head lamp case comprises a light emitting diode (LED) light source, and a heat sink for dissipating heat generated from the LED light source; and a plurality of ventilating fans for circulating air in the plurality of head lamp cases and installed in the plurality of head lamp cases, respectively. Accordingly, the ventilating fans installed in the head lamp cases have opposite ventilating directions, and thus air is circulated in the head lamp cases by the ventilating fans to thus improve heat dissipation effects. | 2012-04-19 |
20120092886 | Skate board Lighting System - A skateboard lighting system is provided which is mountable to a skateboard having a deck, a deck top surface, a deck bottom surface and a pair of supporting trolleys, each trolley being mounted to the deck bottom surface and defining a trolley wheel axis. The lighting system comprises a lighting system frame mountable to the deck bottom surface proximate a first trolley and at least one light mounted to the frame, the light including a first lighting element arrayed to direct light along a light axis, the light axis being substantially parallel to the trolley wheel axis. A power source is provided in electrical communication with the light. | 2012-04-19 |
20120092887 | BACKLIGHT MODULE AND DISPLAY APPARATUS - The present invention provides a backlight module and a display apparatus. The backlight module comprises a circuit board, a plurality of light sources and a reflective layer. The light sources have lighting surfaces and are electrically connected to the circuit board. The reflective layer flushes with the lighting surfaces of the light sources. Alternatively, the height difference between the reflective layer and the lighting surfaces of the light sources is less than 1 mm for reducing the height difference between the reflective layer and the lighting surfaces of the light sources. The present invention can raise the utilization rate of the reflective light. | 2012-04-19 |
20120092888 | EDGE LIGHTING BACK LIGHT MODULE - An edge lighting back light module includes a first light guide plate, at least one second light guide plate, and a plurality of light emitting devices. The first light guide plate has a light incident plane with a first thickness. The second light guide plate has a light incident plane and a light exit plane. The light exit plane of the second light guide plate faces the light incident plane of the first light guide plate, and the light exit plane of the second light guide plate has a second thickness smaller than the first thickness of the light incident plane of the first light guide plate. The light emitting devices face the light incident plane of the second light guide plate. | 2012-04-19 |
20120092889 | LIGHT DEVICE AND METHOD OF ASSEMBLING A LIGHT DEVICE - Light device ( | 2012-04-19 |
20120092890 | Surface Light Source Assembly - A surface light source assembly is disclosed. The surface light source assembly includes a light guide plate, a reflective sheet, a light diffuser sheet and a transparent cover arranged in front of the light diffuser sheet, an insert-nut embedded in the light guide plate, and a supporting frame having a vertical plate and a screw movable hole arranged on the vertical plate. In the insert-nut, a screw is screwed from an end holding frame overlapped on both ends of the supporting frame and arranged in both ends of the light guide plate via the screw movable hole. The screw can be moved in the screw movable hole depending on a heat expansion and contraction of the light guide plate. | 2012-04-19 |
20120092891 | Illuminating Device and Display Device - An illuminating device acceding to the present invention has light sources, a light guide body which emits lights incident from the light sources, and a blurring structure, and, on the surface opposing to the emission surface of the light guide body, the light deflection elements which guide lights incident from the light sources toward the emission surface are formed regularly in two-dimensional direction of the first direction and second direction. The blurring structure has a function of blurring the light deflection elements regularly formed in the two-dimensional direction, and this blurring structure converts incident lights into linear lights inclined in the direction of the angle θ with respect to the first direction. | 2012-04-19 |
20120092892 | LED LIGHT BOARD - Disclosed is a light emitting diode (LED) light board. The LED light board includes: a light guide panel (LGP) shaped as a rectangle; an LED module disposed at a lateral side of the LGP and including a plurality of LEDs; a first frame having the LED module embedded therein and coupled to one side of an edge of the LGP; a second frame coupled to the other side of the edge of the LGP perpendicular to both ends of the first frame; and a corner finishing end on which the first frame and the second frame are connected to each other and corners of the first frame and the second frame are finished. The first and second frames include a sidewall formed at one edge of the LGP, an upper wing bent on an end of a sidewall, and a lower wing bent on the other end of the sidewall. | 2012-04-19 |
20120092893 | LIGHTBAR DEVICE AND DISPLAY MODULE THEREOF - A lightbar device includes a plastic frame, a back plate, a lightbar, and at least one fixing pad. At least one positioning hole is formed on the back plate. The lightbar is slidably disposed between the back plate and the plastic frame. The fixing pad includes a base, a side board, and a first clamping portion. A recession is formed at the base. The recession is used for engaging with the positioning hole so as to fix the fixing pad onto the back plate. The side board is formed at a side of the base. The first clamping portion is formed at a position of the base opposite to the side board. The first clamping portion is used for clamping a first side of the lightbar cooperatively with the side board. | 2012-04-19 |
20120092894 | System For Regulating A Load Voltage In Power Distribution Circuits And Method For Regulating A Load Voltage In Power Distribution Circuits - The present invention refers to a system for regulating a load voltage (C) in power distribution circuits comprising at least: a regulation transformer ( | 2012-04-19 |
20120092895 | Circuit and Method for Potential-Isolated Energy Transfer with Two Output DC Voltages - A circuit for potential-isolated power transfer from a primary side to a secondary side with two secondary-side output DC voltages, wherein the absolute value of the first output DC voltage is higher than the absolute value of the second output DC voltage. The circuit comprises a transformer, which has first and second windings with a common center tap on the primary side and a third winding on the secondary side. The ratio of the number of turns of the first and second windings is a function of the ratio of the two secondary-side output DC voltages. The center tap is connected to a DC voltage source, the first winding is connected to a first transistor and the second winding is connected to a second transistor. The transistors are connected to the primary-side reference potential. The output voltages are present at two diodes connected to the secondary-side third winding. | 2012-04-19 |
20120092896 | SWITCHING POWER SUPPLY DEVICE - A system simplification can be achieved by reducing the number of sensors required to detect currents and voltages when an output current is estimated. a switching power supply device | 2012-04-19 |
20120092897 | POWER SUPPLY CONTROL DEVICE, POWER SUPPLY SYSTEM AND ELETRONIC DEVICE - An electronic device ( | 2012-04-19 |
20120092898 | ALTERNATING CURRENT TO DIRECT CURRENT POWER CONVERSION - An alternating current to direct current (AC to DC) power conversion system is provided. The system includes a rectifier configured to convert an input AC voltage to an initial pulsating DC voltage. The system also includes an inverter configured to convert the initial pulsating DC voltage to a converted AC voltage. The system further includes a plurality of transformers, each transformer including a primary winding paired to a secondary winding, wherein each of the primary windings is coupled in series with the other primary windings, wherein the series coupled primary windings are coupled to the inverter to receive respective portions of the converted AC voltage. The system also includes a plurality of bridges, each bridge coupled to a respective secondary winding configured to receive a respective portion of a transformed AC voltage from the respective secondary windings, and coupled in parallel to the other bridges to provide a combined DC output voltage. | 2012-04-19 |
20120092899 | DYNAMIC CONVERTER TOPOLOGY - Methods and apparatus of dynamic topology power converters are provided. One method includes monitoring at least one variable of the power converter and based on the at least one monitored variable, using a converter topology selected between at least a full-bridge converter topology and a half-bridge converter topology to achieve an efficient operation at a then current operational load. | 2012-04-19 |
20120092900 | CONTROLLER WITH PUNCTUATED SWITCHING CONTROL CIRCUIT - An example controller for use in a power supply includes a zero crossing detection (ZCD) circuit and a punctuated switching control circuit. The ZCD circuit is coupled to generate a ZCD signal in response to a zero-crossing of an ac input voltage of the power supply. The punctuated switching control circuit is coupled to the ZCD circuit to generate a switching signal to control a switch to regulate an output of the power supply. The punctuated switching control circuit generates the switching signal having an interval of switching and an interval of no switching in response to the ZCD signal, where the interval of switching has a beginning that is synchronized with the zero crossing of the ac input voltage and where the interval of no switching has a beginning that is synchronized with another zero crossing of the ac input voltage. | 2012-04-19 |
20120092901 | POWER MANAGEMENT IN AN ELECTROMAGNETIC TRANSPONDER - A method for managing the power in an electromagnetic transponder in the field of a terminal, including the steps of: evaluating the power consumption of the transponder circuits; and if this power consumption is below a threshold, evaluating the current coupling factor between the transponder and the terminal and, according to the current coupling: causing an increase of the transponder power consumption or causing a detuning of an oscillating circuit of the transponder. | 2012-04-19 |
20120092902 | PHASE ANGLE MEASUREMENT OF A DIMMING CIRCUIT FOR A SWITCHING POWER SUPPLY - An example controller for a switched mode power supply includes a zero-crossing detector and a drive signal generator. The zero-crossing detector is coupled to generate a zero-crossing signal representative of a phase angle of a dimmer output voltage for a half line cycle of the power supply. The drive signal generator controls switching of a switch to regulate an output of the power supply in response to a feedback signal representative of the output. The drive signal generator further controls switching of the switch to adjust dimming of the output of the power supply in response to the phase angle indicated by the zero-crossing signal. | 2012-04-19 |
20120092903 | POWER TRANSFER BETWEEN INDEPENDENT POWER PORTS UTILIZING A SINGLE TRANSFORMER - An example power delivery network includes an energy transfer element, a main power port, and a main port interface. The energy transfer element includes multiple windings, where a first power converter transfers power between a first power port and a first winding, and a second power converter transfers power between a second winding and a second power port. The main port interface is coupled cyclically reverse a dc voltage received at the main power port and provides a cyclically reversed voltage to a third winding of the energy transfer element at a fixed duty ratio, where the transfer of power between the first power port and the first winding is independent of the transfer of power between the second winding and the second power port. Also, the main power port has an effective impedance less than an effective impedance of the first power port and the second power port. | 2012-04-19 |
20120092904 | COORDINATED CONTROL OF MULTI-TERMINAL HVDC SYSTEMS - Multi-terminal HVDC systems and control methods therefore are disclosed. Methods for controlling multi-terminal HVDC systems having a plurality of converter stations may include receiving a plurality of measurements from a plurality of measurement units disposed on the HVDC system, identifying from the measurements a disruption within the HVDC system, monitoring the measurements to identify a steady-state disrupted condition for the HVDC system, calculating a new set point for at least one of the plurality of converter stations, which new set point may be based on the steady-state disrupted condition and the measurements, and transmitting the new set point to the at least one of the plurality of converter stations. In some examples, the HVDC systems may include an HVDC grid interconnecting the plurality of converter stations and a controller communicatively linked to the plurality of measurement units and the plurality of converter stations. | 2012-04-19 |
20120092905 | METHOD AND SYSTEMS FOR CONVERTING POWER - A power conversion system includes a first converter coupled to a power source, wherein the first converter includes an input side, and an output side electrically isolated from the input side. The power conversion system also includes a second converter coupled to the power source, wherein the second converter includes an input side, and an output side electrically isolated from the input side. The second converter input side is coupled in parallel with the first converter input side, and the second converter output side is coupled in series with the first converter output side. The power conversion system also includes an inverter coupled to the first converter output side and to the second converter output side, and the inverter supplies alternating current to an electrical distribution network. | 2012-04-19 |
20120092906 | ARRANGEMENT FOR EXCHANGING POWER - An arrangement for exchanging power with a three-phase electric power network comprises a Voltage Source Converter having three phase legs with each a series connection of switching cells. The three phase legs are interconnected by forming a delta-connection. The arrangement also includes a control unit configured to calculate a value for amplitude and phase position for a zero-sequence current for which, when circulated in the delta-connection circuit of the three phase legs, the balance of the total direct voltage of each of the three phase legs with respect to the other two phase legs is restored will there be an unbalance and control the semiconductor devices of switching cells of the phase legs to add such a zero-sequence current to the currents of each phase leg of the converter. | 2012-04-19 |
20120092907 | POWER SUPPLY AND SYSTEM - The invention provides a power supply comprising a switch, a voltage detector and an SPS stage. The switch is coupled to an AC source. The voltage detector detects a voltage of the AC source. The SPS stage is coupled to the switch and outputs a DC voltage. When the voltage of the AC source is larger than a predetermined voltage, the switch is turned off to isolate the AC source from the SPS stage. | 2012-04-19 |
20120092908 | Multi-Level Parallel Power Converters - Multi-level power converters are disclosed. In one embodiment, a multi-level power converter includes an input for receiving an input voltage and a converter output for providing a variable output voltage. The multi-level power converter includes a plurality of switching circuits. Each switching circuit is connected to the input in parallel with each other switching circuit. Each switching circuit includes an output. Each switching circuit is selectively operable to couple its output to the input voltage or a reference voltage. The multi-level power converter includes a parallel multi-winding autotransformer (PMA). The PMA includes a plurality of windings and a magnetic core having a plurality of magnetically connected columns. Each winding is positioned around a different one of the columns and has a beginning and an end. The output of each switching circuit is coupled to the beginning of a different winding. The end of each winding is connected to the converter output in parallel with each other winding. | 2012-04-19 |
20120092909 | POWER CONVERSION APPARATUS - According to one embodiment, a power conversion apparatus determines a peak value of circuit current in each pulse cycle and a lower limit value lower than the peak value, from a corrected output voltage value obtained by subtracting a predetermined reference voltage from an output voltage detected, and an input voltage detected. The pulse signal output unit outputs a pulse signal to the first switch when the polarity of input voltage is positive, and outputs a pulse signal to the second switch when the polarity of input voltage is negative. A pulse signal is turned on in response to start of a pulse cycle, and is kept on until a circuit current detected reaches a peak value. A pulse signal turns off when a circuit current reaches a peak value, and turns on again when a circuit current decreases to a lower limit value. | 2012-04-19 |
20120092910 | SWITCHING POWER SUPPLY APPARATUS - A switching power supply is provided to supply an AC input voltage. The supply includes a control circuit configured to detect a voltage of the AC power source in a voltage waveform, and switch elements in a synchronous rectification switching mode in synchronization with polarities of the voltage waveform when the AC input voltage is equal to or greater than a predetermined voltage value. The control unit also operates the switching without synchronization with the polarities when the AC input voltage is smaller than the predetermined voltage value. | 2012-04-19 |
20120092911 | POWER CONVERSION APPARATUS AND METHOD - According to one embodiment, a power conversion apparatus determines a peak value of circuit current in each pulse cycle, from a corrected output voltage value by subtracting a predetermined reference voltage from an output voltage detected by the output voltage detector, and an input voltage detected by the input voltage detector. The pulse signal output unit outputs a pulse signal to the first switch when the polarity of input voltage is positive, and outputs a pulse signal to the second switch when the polarity of input voltage is negative. A pulse signal turns on in synchronization with a clock signal input from the oscillator, and is kept on until the circuit current detected by the circuit current detector reaches the peak value. A pulse signal turns off when the circuit current reaches the peak value, and turns on again in synchronization with the next clock signal. | 2012-04-19 |
20120092912 | COMMUTATION METHOD OF AN ELECTRONIC POWER CONVERTER PHASE WITH REVERSE-CONDUCTING IGBTS - The invention relates to a method for commutating from a reverse-conducting IGBT (T1) operated in the diode mode to a reverse-conducting IGBT (T2) operated in the IGBT mode. According to the invention the reverse-conducting IGBT (T1) operated in the diode mode is turned off only at the instant a current starts to flow in the reverse-conducting IGBT (T2) operated in the IGBT mode. Accordingly said commutation method is event-driven, as a result of which it is less sensitive to poorly toleranced operating times. | 2012-04-19 |
20120092913 | PFC BOOSTER CIRCUIT - A power factor correction booster circuit for connection to an alternating current (AC) power source including a first circuit portion arranged to be active over a first AC half cycle of the power source, the first circuit portion including: a first AC input node in connection with a source node of a first power transistor, a first node of an inductive element in connection with a drain node of the first power transistor, a second node of the inductive element in connection with a drain node of a second power transistor, a second AC input node in connection with a source node of the second power transistor, an anode of a first semiconductor diode element in connection with the second node of the inductive element, a cathode of the first semiconductor diode element in connection with a first node of a first output capacitor element, and a second node of the first output capacitor element in connection with the second AC input node, wherein the first and second power transistors are controllable to switch the first circuit portion between a forward mode and a flyback mode, such that in the forward mode the inductive element stores energy from the AC power source, and in the flyback mode the stored energy from the inductive element is transferred to the first output capacitor through the first semiconductor diode element. | 2012-04-19 |
20120092914 | SWITCHING BRANCH FOR THREE-LEVEL RECTIFIER AND METHOD FOR CONTROLLING SWITCHING BRANCH FOR THREE-LEVEL RECTIFIER - A switching branch for a three-level rectifier and a method for controlling a switching branch for a three-level rectifier are provided. The switching branch includes a first diode and a second diode connected in series, a third diode and a fourth diode connected in series, a first controllable switch connected between a neutral DC output pole and a connection point between the first and the second diode, and a second controllable switch connected between the neutral DC output pole and a connection point between the third and the fourth diode. The switching branch includes means for controlling the first controllable switch to be in a conductive state during a reverse blocking state of the first diode and the second diode, and means for controlling the second controllable switch to be in a conductive state during a reverse blocking state of the third diode and the fourth diode. | 2012-04-19 |
20120092915 | POWER CONVERSION APPARATUS - A power conversion apparatus including: a three-level inverter including bridge circuits each including a first semiconductor switching device and a second semiconductor switching device connected in series, the bridge circuits being connected to a positive terminal and a negative terminal of a DC power supply, and switch circuits having bidirectional characteristics and connected to respective AC output terminals of the bridge circuits which are the connection points between the first semiconductor switching devices and the second semiconductor switching devices, and to an intermediate potential point of the DC power supply; and single-phase inverters each including a plurality of semiconductor switching devices and respectively connected in series to the AC output terminals of the bridge circuits. The sum of an output voltage of the three-level inverter and output voltages of the single-phase inverters is supplied to a load. | 2012-04-19 |
20120092916 | Built-In Self Test for One-Time-Programmable Memory - An apparatus and method of testing one-time-programmable memory provides one-time-programmable memory having one or more memory locations for storing data and corresponding programming circuitry for each memory location. In addition, each programming circuitry has a circuit element configured to permanently change state to store the data in the memory. The method also reads each memory location to verify that the memory location is unprogrammed and activates the programming circuitry for each memory location, which applies a test current to the programming circuitry. The test current is less than a threshold current needed to permanently change the state of the circuit element. The method then determines whether the programming circuitry is functioning properly. | 2012-04-19 |
20120092917 | ROM MEMORY DEVICE - A memory device includes a plurality of read only memory cells, a precharge circuit, and a sense amplifier. A read only memory (ROM) cell of the plurality of ROM cells is coupled to a word line and a bit line. The ROM cell comprises a transistor having a first current electrode coupled to receive a reference voltage, a second current electrode selectively coupled to the bit line based on the programmed state of the ROM cell, and a control electrode coupled to the word line. The precharge circuit is coupled to the bit line. The precharge circuit precharges the bit line to a precharge voltage, wherein the precharge voltage is less than the reference voltage. The sense amplifier is coupled to the bit line and to a power supply voltage terminal for receiving a power supply voltage, wherein the reference voltage is less than the power supply voltage. | 2012-04-19 |
20120092918 | VERIFICATION SYSTEM - A verification system of the present invention is provided to perform unidirectional or bidirectional verification between a master apparatus and a slave apparatus comprising the master apparatus having a master memory capable of storing verification key code in a non-volatile manner and the slave apparatus having a slave memory capable of storing verification key code in the non-volatile manner, wherein at least the slave memory is one of the group consisting of non-volatile logic circuit and ferroelectric an memory, both of which use hysteresis characteristics of ferroelectric components. | 2012-04-19 |
20120092919 | Resistive Memory Element and Use Thereof - A resistive memory element that includes an element body and at least a pair of electrodes opposed to each other with at least a portion of the element body interposed therebetween. The element body is made of an oxide semiconductor as a polycrystalline body, which has a composition represented by the general formula: Ti | 2012-04-19 |
20120092920 | Resistive Memory Element and Use Thereof - A resistive memory element that includes an element body and at least a pair of electrodes opposed to each other with at least a portion of the element body interposed therebetween. The element body is made of an oxide semiconductor which has a composition represented by the general formula: (Ba | 2012-04-19 |
20120092921 | SEMICONDUCTOR DEVICE - A technique for increasing rewriting current without increasing a power supply voltage and also reducing location dependency inside a memory array of a resistive state after the rewriting is provided in a resistance change memory in which the resistance value of a memory cell changes between logical values “1” and “0”. In the resistance change memory, bit lines are formed into a layered structure, the bit line select switches for connecting to the global bit line are provided at both ends of the local bit line, and a control method of the bit line select switches is changed in the writing and the reading, thereby realizing the optimum array configurations for each of them. More specifically, in the writing and the reading, two current paths are provided in parallel by turning ON the bit line select switches simultaneously. | 2012-04-19 |
20120092922 | SEMICONDUCTOR INTEGRATED CIRCUIT - Flip-flop memory cells are connected to a pair of bit lines and respectively to word lines. A word line driver outputs a word line selection pulse to one of the word lines in a word line selection period. A write circuit gives a potential difference corresponding to input data to the pair of bit lines after a start of the word line selection period. In a first operation mode, the potential difference of the pair of bit lines is reset in the word line selection period, and in the second mode, the potential difference of the pair of bit lines is reset after the word line selection period. | 2012-04-19 |
20120092923 | READ DISTRIBUTION MANAGEMENT FOR PHASE CHANGE MEMORY - Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory. | 2012-04-19 |
20120092924 | METHOD OF PROVIDING AN ERASE ACTIVATION ENERGY OF A MEMORY DEVICE - A write-once read-many times memory device is made up of first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrode. The memory device is programmed by providing a charged species from the passive layer into the active layer. The memory device may be programmed to have for the programmed memory device a first erase activation energy. The present method provides for the programmed memory device a second erase activation energy greater than the first erase activation energy. | 2012-04-19 |
20120092925 | VERTICAL CAPACITOR-LESS DRAM CELL, DRAM ARRAY AND OPERATION OF THE SAME - A vertical capacitor-less DRAM cell is described, including: a source layer having a first conductivity type, a storage layer disposed on the source layer and having a second conductivity type, an active layer disposed on the storage layer and having the first conductivity type, a drain layer disposed on the active layer and having the second conductivity type, an address gate disposed beside the active layer and separated from the same by a first gate dielectric layer, and a storage gate disposed beside the storage layer and separated from the same by a second gate dielectric layer. The DRAM cell can be written by turning on the MOSFET formed by the storage layer, the active layer, the drain layer, the first gate dielectric layer and the address gate to inject carriers into the storage layer from the active layer. | 2012-04-19 |
20120092926 | THREE DIMENSIONAL NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A three dimensional non-volatile memory structure according to an aspect of this disclosure includes a plurality of interlayer dielectric layers and a plurality of control gates alternately stacked over a substrate, a channel formed to penetrate the plurality of interlayer dielectric layers and the plurality of control gates, a tunnel insulating layer formed to surround the channel, a plurality of floating gates disposed between the plurality of interlayer dielectric layers and the tunnel insulating layer, wherein the plurality of floating gates each have a thickness greater than a corresponding one of the interlayer dielectric layers, and a charge blocking layer disposed between the plurality of control gates and the plurality of floating gates. | 2012-04-19 |
20120092927 | MEMORY SYSTEM - A memory system includes a NAND flash memory having a page buffer capable of holding a page of data and a cell array having a plurality of pages. The system also includes a plurality of memory portions electrically connected to the NAND flash memory via a data bus, and a controller for controlling the NAND flash memory and the plurality of memory portions. A width of the data bus is less than a size of the page of data. When any one of a write operation and a read operation is performed on the NAND flash memory, the controller exchanges data held in the page buffer and data held in one memory portion of the plurality of memory portions. | 2012-04-19 |
20120092928 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a memory-cell array provided between a first region and a second region, and including a plurality of memory cells; a first row decoder and a second row decoder; a first power line provided in the first region; a second power line provided in the first region; a first power-supply circuit configured to supply the first voltage to the first power line and to the second power line; a first switching circuit; and a second switching circuit. In a write operation, the first switching circuit connects the first power line and the first power-supply circuit to each other whereas the second switching circuit disconnects the second power line and the first power-supply circuit from each other. | 2012-04-19 |
20120092929 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF INCREASING WRITING SPEED - A memory cell array has a structure in which a plurality of memory cells connected with word lines and bit lines and connected in series are arranged in a matrix form. A selection transistor selects the word lines. A control circuit controls potentials of the word lines and the bit lines in accordance with input data, and controls write, read and erase operations of data with respect to the memory cell. The selection transistor is formed on a well, and a first negative voltage is supplied to a well, a first voltage (the first voltage the first negative voltage) is supplied to a selected word line and a second voltage is supplied to a non-selected word line in the read operation. | 2012-04-19 |
20120092930 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF READING DATA THEREFROM - A semiconductor memory device includes a first memory cell array having a first plane which is composed of a plurality of blocks each having a plurality of memory cells, a sense circuit which reads data the memory cells, a sequencer which receives control signals from outside, a first address register, and a second address register which receives an output address from the first address register and outputs an address signal in response to an address control signal from the sequencer. In reading from the memory cells, the sequencer reads a page n in accordance with the address stored in the second address register, then transfers an address stored in the first address register to the second address register concurrently with outputting data read from the page n to outside and reads data from an arbitrary page m in accordance with the address transferred to the second address register. | 2012-04-19 |
20120092931 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, threshold voltages of memory cells being set lowest in an erase state and sequentially set higher according to data in a program state, a plurality of bit lines connected to the memory cells, a word line connected to the memory cells, and a control circuit. In a case where a first memory cell is programmed to a first threshold voltage that is lowest among threshold voltages in the program state, the control circuit is configured to charge a first bit line connected to the first memory cell to a third voltage between a first voltage applied to a bit line when a memory cell is programmed to a second threshold voltage higher than the first threshold voltage and a second voltage applied to a bit line when a memory cell is inhibited from being programmed. | 2012-04-19 |
20120092932 | PROGRAMMING METHODS AND MEMORIES - Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. During each programming sequence, the data which is not being currently selected for programming is inhibited. Overlapping levels and/or voltage ranges can be used. | 2012-04-19 |
20120092933 | MEMORY ERASE METHODS AND DEVICES - Memory devices and erase methods for memories are disclosed, such as those adapted to discharge an erase voltage from a memory block while protecting low voltage string select gate transistors by maintaining the string select gate transistors in a turned on state during discharge. | 2012-04-19 |
20120092934 | MULTIPLEXING CIRCUIT - A multiplexing circuit includes a plurality of first circuits and a second circuit coupled to outputs of the plurality of first circuits. A first circuit of the plurality of first circuits is configured to receive a first data line as a first input and a clock signal as a second input, and provide an output signal to a first circuit output. After the first circuit is selected for use, the clock signal, a first sub-circuit of the first circuit coupled to the second circuit, and the second circuit are configured to provide a first output logic level to the output signal based on a first data logic level of the first data line; and a second sub-circuit of the first circuit coupled to the first circuit output is configured to provide a second output logic level to the output signal based on a second data logic level of the first data line. | 2012-04-19 |
20120092935 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first memory device formed on a semiconductor substrate, including a first storage unit, a source, and a drain, a second memory device, including a second storage unit, and a bit line, wherein the second memory device is connected in series between the bit line and the drain. | 2012-04-19 |
20120092936 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FOR CONTROLLING A SENSE AMPLIFIER - A semiconductor IC device includes a command decoder that provides internal read and internal write command signals in response to external command signals, and a delay control unit that is connected with the command decoder and provides an internal read command delay signal by controlling an activation timing of the internal read command signal in response to a test mode signal in a read mode. | 2012-04-19 |
20120092937 | Method and System for A Serial Peripheral Interface - A method for dual I/O data read in an integrated circuit which includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently. | 2012-04-19 |
20120092938 | SEMICONDUCTOR MEMORY - Semiconductor memory including a reference amplifier and a high-speed start-up circuit having four FETs. The reference amplifier supplies the reference voltage to a sense amplifier via a reference voltage supply line. The high-speed startup circuit has four FETs. The first FET is turned on to apply a first voltage onto a first line when the enable signal indicates deactivation. The second FET is turned on to apply ground potential onto the first line when the voltage on the reference voltage supply line is higher than a gate threshold voltage value. The third FET is turned on to generate the first voltage when the enable signal indicates activation. The fourth FET is turned off when the first line is at ground potential and is turned on to supply the first voltage from the third FET onto the reference voltage supply line when the first voltage is applied onto the first line. | 2012-04-19 |
20120092939 | SINGLE-ENDED SENSING SCHEME FOR MEMORY - A memory having a single-ended sensing scheme includes a bit line, a memory cell coupled to the bit line, and a precharge circuit. The precharge circuit is configured to precharge the bit line to a precharge voltage between a power supply voltage and a ground. | 2012-04-19 |
20120092940 | Memory Device and Read Operation Method Thereof - A read operation for a memory device. In response to an input address indicating to read data from a different page, a selected word line, first and second global bit lines and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit lines are kept precharged. A second cell current flowing through the selected word line is generated. A second reference current is generated. A second half page data is read based on the second cell current and the second reference current. | 2012-04-19 |
20120092941 | MEMORY CELL - Methods, and circuits, are disclosed for operating a programmable memory device. One method embodiment includes storing a value as a state in a first memory cell and as a complementary state in a second memory cell. Such a method further includes determining the state of the first memory cell using a first self-biased sensing circuit and the complementary state of the second memory cell using a second self-biased sensing circuit, and comparing in a differential manner an indication of the state of the first memory cell to a reference indication of the complementary state of the second memory cell to determine the value. | 2012-04-19 |
20120092942 | TECHNIQUES FOR READING A MEMORY CELL WITH ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region. | 2012-04-19 |
20120092943 | Semiconductor device and test method thereof - plurality of core chips to which chip identification information different from each other is allocated and an interface chip are layered, the plurality of core chips are commonly connected to the interface chip through a first current path including at least a through silicon via, the interface chip serially supplies an enable signal to the plurality of core chips through the first current path, and the plurality of core chips are activated based on a logic level of a bit corresponding to the chip identification information among a plurality of bits configuring the enable signal. The present invention can reduce the number of through silicon vias required to supply an enable signal. | 2012-04-19 |
20120092944 | MEMORY DEVICE HAVING A CLOCK SKEW GENERATOR - A memory device is provided with memory components and a clock skew generator, supporting at least two read and write operations that can occur coincidentally in read-read, read-write and write-write modes of operation of the memory device. The clock skew generator produces at least two stable and balanced clock channels carrying the at least two clock signals and varies relative timing of the clock signal edges so as to displace the edges in time, in those modes of operation wherein simultaneous edges would lead to detrimental loading. | 2012-04-19 |
20120092945 | COMMAND LATENCY SYSTEMS AND METHODS - Examples of command latency systems and methods are described. In some examples, phase information associated with a received command signal is stored, a received command signal is propagated through a reduced clock flip-flop pipeline and the delayed command signal is combined with the stored phase information. The reduced clock flip-flop pipeline may use a clock having a lower frequency than that used to issue the command signal. Accordingly, fewer flip-flops may be required. | 2012-04-19 |
20120092946 | MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING DISCHARGE LINES AND METHODS OF FORMING - A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit line and a discharge diode can be electrically coupled between the local bit line and the discharge line. | 2012-04-19 |
20120092947 | FUSE CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - A fuse circuit includes a plurality of fuse cells, an amplification unit, and a plurality of registers. The amplification unit is configured to sequentially amplify data stored in the fuse cells. The registers are configured to sequentially store data amplified by the amplification unit. | 2012-04-19 |
20120092948 | Concrete vibrator system and motor therefor - A concrete vibrator system with a constant speed motor, one of a set of vibrator heads with different load characteristics, and one of a set of drive shafts connecting the motor output shaft with one of the vibrator heads. A speed control circuit senses motor shaft speed and maintains constant speed. The motor is cooled by a fan mounted on the motor rotor which draws air through an inlet and exhausts air through an outlet both of which face downwardly when the motor is in use. Rain or other liquids are prevented from reaching the motor. | 2012-04-19 |
20120092949 | SYNCHRONIZED MIXING DEVICE AND METHOD - A system for mixing a fluid in a tank includes a set of mixers and a controller. The set of mixers is disposed proximal to a perimeter of the tank. The set of mixers are operable to pivot. The controller is configured to control the set of mixers to pivot from a first orientation to a second orientation. The controller is configured to control each mixer of the set of mixers to stop pivoting in a first direction in response to each respective mixer achieving a predetermined intermediate orientation and the controller is configured to control the set of mixers to continue pivoting in the first direction in response to all mixers of the set of mixers achieving the predetermined intermediate orientation. | 2012-04-19 |
20120092950 | LOW PRESSURE DROP BLENDER - A system and method for consistent and highly accurate blending of fluids; e.g. gases or liquids, without significant pressure drop. The system uses a flow meter to measure the amount of primary fluid being provided for mixing with the amount of diluent fluid controlled based on such measurement of the primary fluid amount. | 2012-04-19 |
20120092951 | MIXER FOR BIPHASIC COMPOUNDS - Mixer for biphasic compounds, including a chamber for containing a solid phase and a cartridge containing a phial of a liquid phase, said chamber and said cartridge being able to communicate through respective channels, wherein said cartridge includes an external casing made in a deformable material and said phial is of the breakable type. | 2012-04-19 |
20120092952 | METHOD AND APPARATUS FOR PRODUCING FULLY COOKED EXTRUDATES WITH SIGNIFICANTLY REDUCED SPECIFIC MECHANICAL ENERGY INPUTS - Improved extruders and methods for the extrusion cooking of comestible products such as human foods or animal feeds are provided wherein the products may be produced with very low specific mechanical energy (SME) inputs as compared with conventional processing. The methods preferably involve introduction of very high levels of steam into the extruder barrel during processing, which concomitantly reduces necessary SME inputs required to achieve desired cook and expansion levels in the products. In accordance with the invention, fully-cooked pet foods can be fabricated with SME inputs of up to about 18 kWhr/T, whereas aquatic feeds can be fabricated with SME inputs of up to about 16 kWhr/T. | 2012-04-19 |
20120092953 | MIXING PADDLE FOR ICE CREAM MACHINE - A mixing paddle for use in a conventional ice cream maker includes two vertical arms that have outer contact edges that exceed the inner diameter of the freezer bowl in which they are positioned during use. This enables the contact edges to effectively scrape ice cream ingredients from the inner wall of the bowl during use and direct the ingredients toward the center of the bowl. The mixing paddle also comprises two cross-members that have pin-wheel style shapes that move ice cream ingredients vertically during use. The combined effect of the vertical arms and the cross-members optimally and uniformly mixes the ice cream ingredients during use and ensures efficient cooling. | 2012-04-19 |
20120092954 | ULTRASONIC TRANSMITTING/RECEIVING CIRCUIT AND ULTRASONIC DIAGNOSTIC APPARATUS - An ultrasonic transmitting/receiving circuit equipped with: a semiconductor circuit element which comprises at least three terminals including a first terminal connected to a plurality of transducer elements that constitute an ultrasonic probe, a second terminal connected to a transmission signal generating circuit, and a third terminal serving as an output terminal of an amplifier of a reception signal from the transducer element, and which has a function of amplifying a signal inputted from one terminal by the other terminal and outputting the amplified signal between at least two terminals among the above-said three terminals; and a control unit which performs control so as to cause the semiconductor circuit element to perform a first function of functioning as a switch for inputting a transmission signal to the transducer element and a second function of amplifying the reception signal received from the transducer element. | 2012-04-19 |
20120092955 | System and Method for Reducing the Effects of Ghosts From the Air-Water Interface in Marine Seismic Exploration - A system mechanically alters the geometry of the surface of the water by breaking the water surface with a mechanical device. The mechanical device may comprise a plurality of propellers, a plurality of aquafoils in the shape of plows, a wire whip, or other mechanical device to reduce the coefficient of reflectivity of the air-water interface. | 2012-04-19 |
20120092956 | METHOD AND DEVICE TO ACQUIRE SEISMIC DATA - Streamer and method for deploying the streamer for seismic data acquisition related to a subsurface of a body of water. The method includes a step of releasing into the body of water, from a vessel, a body having a predetermined length together with plural detectors provided along the body; a step of towing the body and the plural detectors such that the plural detectors are submerged; and a step of configuring plural birds provided along the body, to float at a predetermined depth from a surface of the water such that a first portion of the body has a curved profile while being towed underwater. | 2012-04-19 |
20120092957 | Survey Design for Sea Bottom Seismic in Shallow Water - The various embodiments herein provide a method to acquire seismic data to estimate reservoir characteristics in a shallow sea water environment. According to an embodiment herein, a method comprises acquiring four component ocean bottom cable (4C OBC) seismic data using a hydrophone and a three component geophone by varying a time delay between the shots and spacing between the shots. A full acoustic modelling process and an elastic modelling process are applied to the acquire 4C OBC seismic data to acquire a pressure data and an inline geophone data to estimate a horizontal component data and a reflected shear wave data. The estimated horizontal component data are NMO corrected and stacked by varying sampling intervals to remove noise component in the acquired seismic data. A shear wave energy data is estimated from the acquired pressure data to estimate shear wave properties of a sea bed and a subsurface carbonate reservoir. | 2012-04-19 |
20120092958 | Estimation of anisotropy from compressional waves from array sonic waveforms in well logging - The present invention provides an improved method for estimating anisotropic formation from wave data using present-day logging tools that allow for the detection of compressional wave splitting to identify fracture direction. This methodology for analyzing compressional waveforms uses the Alford rotation method. | 2012-04-19 |
20120092959 | TECHNIQUE AND SYSTEM TO DETERMINE PROPERTIES OF A SYSTEM OF HYDRAULIC FRACTURES - A technique includes determining a magnitude and frequency distribution of seismic events attributable to hydraulic fracturing in a given stage of a well. The technique includes based on the determined magnitude and frequency distribution, predicting at least one additional magnitude and frequency distribution of seismic events attributable to hydraulic fracturing in at least one additional stage of the well. The technique includes determining at least one seismic property of a system of hydraulic fractures based at least in part on the determined additional magnitude and frequency distributions. | 2012-04-19 |
20120092960 | MONITORING USING DISTRIBUTED ACOUSTIC SENSING (DAS) TECHNOLOGY - Methods and systems are provided for performing acoustic sensing by utilizing distributed acoustic sensing (DAS) along a length of a conduit, such that the sensing is performed with the functional equivalent of tens, hundreds, or thousands of sensors. Utilizing DAS in this manner may cut down the time in performing acoustic sensing, which, therefore, may make acoustic sensing more practical and cost effective and may enable applications that were previously cost prohibitive with discrete acoustic sensors. | 2012-04-19 |
20120092961 | ANALYSIS AND FILTERING OF SURFACE WAVES IN SHALLOW WATER ENVIRONMENT USING S AND T-F-K TRANSFORM - The various embodiments of the present invention provide a method for removing a Scholte waves and similar ground roll type waves from a seismic sea bottom data in a shallow water. The method comprises acquiring seismic sea bottom data in a shallow waters, applying a time-frequency-wave number (t-f-k) transform on the acquired seismic sea bottom data, identifying a time-frequency relationship of a surface wave based on a specific wave number, identifying a frequency-wave number relationship of a surface wave based on a specific time, designing a time varying frequency-wave number filter in the time-frequency-wave number domain to separate the surface wave, applying a time varying frequency-wave number filtering process to remove an undesired energy and inversing a filtered record by applying an inverse S-Transform operation and an inverse Fourier Transform operation. | 2012-04-19 |
20120092962 | Generating an Angle Domain Common Image Gather - A technique includes processing first data indicative of a first image of a subsurface region of interest on a machine to generate second data indicative of a second image. The first image is derived from measurements of seismic waves, which propagate in a plurality of directions, and the second image is generated by partitioning the first image based on the directions. The technique includes processing the second data to determine a dip decomposition for each of the directions; and based on the dip decompositions and the directions, generating an angle domain common image gather. | 2012-04-19 |
20120092963 | PROJECTILE FOR FOCUSING A KINETIC PULSE ARRAY - The present disclosure relates to a method and system for finding and physically altering underground targets. Multiple projectiles are dispersed into the ground and determine their spatial orientation using seismic waves, and then operate as an array to locate and properly time kinetic pulses to focus seismic waves on the target. | 2012-04-19 |
20120092964 | LONG-RANGE ACOUSTICAL POSITIONING SYSTEM ON CONTINENTAL SHELF REGIONS - Methods and systems for determining a geophysical position of an object in an underwater channel are provided. Acoustic signals from at least two sources are received by a receiver of the object. The acoustic signals have a frequency corresponding to at least one waveguide mode associated with the underwater channel, where the acoustic signals are transmitted at predetermined transmission times. An arrival time for the at least one waveguide mode is determined from the received signals, based on the predetermined transmission times. The geophysical position is determined based on the arrival time and a modal group velocity for the at least one waveguide mode. | 2012-04-19 |
20120092965 | ACOUSTIC SENSOR SYSTEM FOR DETECTING ELECTRICAL CONDUCTIVITY FAULTS IN AN ELECTRICAL DISTRIBUTION SYSTEM - An acoustic sensor system is for an electrical distribution system having a number of phases. The acoustic sensor system comprises: a plurality of sets of acoustic sensors structured to detect an electrical conductivity fault of the electrical distribution system. Each of the plurality of sets includes a number of acoustic sensors. Each of the number of acoustic sensors is for a corresponding one of the number of phases of the electrical distribution system. | 2012-04-19 |
20120092966 | CLOCK DEVICE AND METHOD FOR PROCESSING A CLOCK DEVICE - The present invention relates to a clock device and a method for processing a clock device, wherein the clock device comprises a control unit which operates a display unit in a first operating mode or in a second operating mode, wherein the display unit displays the exact current time in the second operating mode and fades out the exact current time in the first operating mode. | 2012-04-19 |
20120092967 | TIMEPIECE WITH A MODULAR ANALOGUE DISPLAY - The invention relates to a timepiece with an analogue display, including a timepiece movement ( | 2012-04-19 |
20120092968 | USER INTERFACE FEATURES FOR A WATCH - A watch provides a chronographic function while the watch is in a “sport” mode. If a user activates a button relating to the chronographic function, such as a “start/lap” button, then the light for the watch will automatically activate. The light may remain active for a significantly long time, such as a period of six seconds or more. Alternately or additionally, if a user activates a button while the watch is in a “performance” or “sport” mode, then the light will automatically activate regardless of the button being activated. Still further, the chronographic function of the watch may be configured to not measure a lap time that is lower than a preset threshold value, such as, for example, three seconds. | 2012-04-19 |