16th week of 2015 patent applcation highlights part 14 |
Patent application number | Title | Published |
20150102395 | SEMICONDUCTOR DEVICE INCLUDING DECOUPLING CAPACITOR AND METHOD OF FORMING THE SAME - An integrated circuit device includes a semiconductor substrate having first and second semiconductor regions therein, a gate trench in the first semiconductor region and a gate electrode in the gate trench. The gate electrode has an upper surface below a surface of the semiconductor substrate. A semiconductor well region is provided in the second semiconductor region. A capacitor trench extends in the semiconductor well region and an upper capacitor electrode extends in the capacitor trench. An electrical interconnect (e.g., conductive plug) is provided, which is electrically connected to the upper capacitor electrode at an interface therebetween. This interface has an upper surface below the surface of the semiconductor substrate. | 2015-04-16 |
20150102396 | SEMICONDUCTOR DEVICES SUITABLE FOR NARROW PITCH APPLICATIONS AND METHODS OF FABRICATION THEREOF - Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device. | 2015-04-16 |
20150102397 | Two-Transistor Non-Volatile Memory Cell and Related Program and Read Methods - A memory device includes an N-channel transistor and a P-channel transistor. A word line is electrically connected to a drain terminal of the N-channel transistor, and a source terminal of the P-channel transistor. A first bit line is electrically connected to a source terminal of the N-channel transistor. A second bit line is electrically connected to a drain terminal of the P-channel transistor. Gate terminals of the N-channel transistor and the P-channel transistor are electrically connected and floating. | 2015-04-16 |
20150102398 | FLOATING-GATE DEVICE AND METHOD THEREFOR - Non-volatile floating gate devices and approaches involve setting or maintaining threshold voltage characteristics relative to thermal processing. In connection with various embodiments, a floating gate device includes a polycrystalline silicon material having an impurity therein. The impurity interacts with the polycrystalline material to resist changes in grain size of the polycrystalline silicon material during thermal processing, and setting charge storage characteristics relative to threshold voltages for the floating gate device. | 2015-04-16 |
20150102399 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory string includes: a first semiconductor layer formed in a columnar shape extending in a stacking direction perpendicular to a substrate; a tunnel insulating film formed surrounding a side surface of the first semiconductor layer; a charge accumulation film formed surrounding the tunnel insulating film and configured to be capable of accumulating charges; a block insulating film formed surrounding the charge accumulation film; and a plurality of first conductive layers formed surrounding the block insulating film and disposed at a predetermined interval in the stacking direction. The first semiconductor layer comprises carbon-doped silicon and being formed to have different carbon concentrations in upper and lower portions in the stacking direction. | 2015-04-16 |
20150102400 | ION IMPLANTATION-ASSISTED ETCH-BACK PROCESS FOR IMPROVING SPACER SHAPE AND SPACER WIDTH CONTROL - Disclosed herein is a semiconductor device including a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. The spacer includes a cross-section with a perimeter that includes a top curved portion and a vertical portion that is substantially perpendicular to the substrate. Further, disclosed herein, are methods associated with the fabrication of the aforementioned semiconductor device. | 2015-04-16 |
20150102401 | Vertical Semiconductor Device with Thinned Substrate - A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region. | 2015-04-16 |
20150102402 | SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREOF - A semiconductor component includes: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that includes: a gate insulating film provided on the substrate; a gate electrode provided via the film; and a pair of source-drain regions provided to sandwich the electrode, the substrate including a patterned surface in a portion where the electrode is provided, the patterned surface of the substrate including a raised portion where the film is formed to cover a surface that lies on the same plane as a surface of the pair of source-drain regions, and the electrode is formed on a top surface of the film, and the patterned surface of the substrate including a recessed portion where the film is formed to cover surfaces of a groove formed toward the interior than the surface of the pair of source-drain regions, and the electrode is formed so as to fill the groove provided with the film. | 2015-04-16 |
20150102403 | SEMICONDUCTOR DEVICE HAVING A PATTERNED GATE DIELECTRIC - In one embodiment, a semiconductor device includes an isolated trench-electrode structure. The semiconductor device is formed using a modified photolithographic process to produce alternating regions of thick and thin dielectric layers that separate the trench electrode from regions of the semiconductor device. The thin dielectric layers can be configured to control the formation channel regions, and the thick dielectric layers can be configured to reduce switching losses. | 2015-04-16 |
20150102404 | Semiconductor Device - A semiconductor device includes a transistor formed in a semiconductor substrate including a main surface. The transistor includes a source region, a drain region, a channel region, and a gate electrode. The source region and the drain region are disposed along a first direction, the first direction being parallel to the main surface. The channel region has a shape of a ridge extending along the first direction, the ridge including a top side and a first and a second sidewalls. The gate electrode is disposed at the first sidewall of the channel region, and the gate electrode is absent from the second sidewall of the channel region. | 2015-04-16 |
20150102405 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a well region, a drain region and a source region disposed in the well region, a gate electrode disposed above the well region, a thin gate insulating layer and a thick gate insulating layer disposed under the gate electrode, the thick gate insulating layer being disclosed closer to the drain region than the thin gate insulating layer, and an extended drain junction region disposed below the gate electrode. | 2015-04-16 |
20150102406 | LATERAL DOUBLE DIFFUSED METAL-OXIDE-SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A LDMOS device includes a substrate having opposite first and second surfaces; a well region in a portion of the substrate; a gate structure over a portion of the substrate; a first doped region disposed in a portion of the well region from a first side; a second doped region disposed in the well region from a second side; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a first trench in the third doped region, the first doped region, the well region, and the substrate adjacent to the first surface; a conductive contact in the first trench; a second trench in the substrate adjacent to the second surface; a first conductive layer in second trench; and a second conductive layer over the second surface of the substrate and the first conductive layer. | 2015-04-16 |
20150102407 | LATERAL DOUBLE DIFFUSED METAL-OXIDE-SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A lateral double diffused metal-oxide-semiconductor device includes: an epitaxial semiconductor layer disposed over a semiconductor substrate; a gate dielectric layer disposed over the epitaxial semiconductor layer; a gate stack disposed over the gate dielectric layer; a first doped region disposed in the epitaxial semiconductor layer from a first side of the gate stack; a second doped region disposed in the epitaxial semiconductor layer from a second side of the gate stack; a third doped region disposed in the first doping region; a fourth doped region disposed in the second doped region; an insulating layer covering the third doped region, the gate dielectric layer, and the gate stack; a conductive contact disposed in the insulating layer, the third doped region, the first doped region and the epitaxial semiconductor layer; and a fifth doped region disposed in the epitaxial semiconductor layer under the conductive contact. | 2015-04-16 |
20150102408 | Semiconductor Device - A semiconductor device with improved characteristics is provided. The semiconductor device includes a LDMOS, a source plug electrically coupled to a source region of the LDMOS, a source wiring disposed over the source plug, a drain plug electrically coupled to a drain region of the LDMOS, and a drain wiring disposed over the drain plug. The structure of the source plug of the semiconductor device is devised. The semiconductor device is structured such that the drain plug is linearly disposed to extend in a direction Y, and the source plug includes a plurality of separated source plugs arranged at predetermined intervals in the direction Y. In this way, the separation of the source plug decreases an opposed area between the source plug and the drain plug, and can thus decrease the parasitic capacitance therebetween. | 2015-04-16 |
20150102409 | FORMING ISOLATED FINS FROM A SUBSTRATE - A method of isolating a semiconductor fin from an underlying substrate including forming a masking layer around a base portion of the fin, forming spacers on a top portion of the fin above the masking layer, removing the masking layer to expose the base portion of the fin, and converting the base portion of the fin to an isolation region that electrically isolates the fin from the substrate. The base portion of the fin may be converted to an isolation region by oxidizing the base portion of the fin, using for example a thermal oxidation process. While converting the base portion of the fin to an isolation region, the spacers prevent the top portion of the fin from also being converted. | 2015-04-16 |
20150102410 | SEMICONDUCTOR DEVICE INCLUDING STRESS LAYER ADJACENT CHANNEL AND RELATED METHODS - A method for making a semiconductor device may include forming a gate on a semiconductor layer, forming sidewall spacers adjacent the gate, and forming raised source and drain regions defining a channel in the semiconductor layer under the gate. The raised source and drain regions may be spaced apart from the gate by the sidewall spacers. The method may further include removing the sidewall spacers to expose the semiconductor layer between the raised source and drain regions and the gate, and forming a stress layer overlying the gate and the raised source and drain regions. The stress layer may contact the semiconductor layer between the raised source and drain regions and the gate. | 2015-04-16 |
20150102411 | FinFET with Buried Insulator Layer and Method for Forming - A fin structure suitable for a FinFET and having a buried insulator layer is disclosed. In an exemplary embodiment, a semiconductor device comprises a substrate with a first semiconductor material and having a fin structure formed thereupon. The fin structure includes a lower region proximate to the substrate, a second semiconductor material disposed on the lower region, a third semiconductor material disposed on the second semiconductor material, and an insulating material selectively disposed on the second semiconductor material such that the insulating material electrically isolates a channel region of the fin structure and further such that the insulating material exerts a strain on the channel region. The semiconductor device further comprises an isolation feature disposed adjacent to the fin structure. | 2015-04-16 |
20150102412 | SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICE AND RELATED METHODS FOR MAKING SAME USING NON-OXIDIZING THERMAL TREATMENT - A method for making a semiconductor device may include forming, on a first semiconductor layer of a semiconductor-on-insulator (SOI) wafer, a second semiconductor layer comprising a second semiconductor material different than a first semiconductor material of the first semiconductor layer. The method may further include performing a thermal treatment in a non-oxidizing atmosphere to diffuse the second semiconductor material into the first semiconductor layer, and removing the second semiconductor layer. | 2015-04-16 |
20150102413 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a substrate with a plurality of logic cells, transistors provided in the plurality of logic cells, contact plugs connected to electrodes of the transistors, first via plugs in contact with top surfaces of the contact plugs, and first wires in contact with top surfaces of the first via plugs. The first wires may include a common conductive line connected to the plurality of logic cells through the contact plugs, and all of the first wires may be shaped like a straight line extending parallel to a specific direction. | 2015-04-16 |
20150102414 | PREVENTING EPI DAMAGE FOR CAP NITRIDE STRIP SCHEME IN A FIN-SHAPED FIELD EFFECT TRANSISTOR (FINFET) DEVICE - Approaches for forming an oxide cap to protect a semiconductor device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming an oxide cap over a subset (e.g., SiP regions) of raised source drain (RSD) structures on the set of fins of the FinFET device to mitigate damage during subsequent processing. The oxide spacer is deposited before the removal of a nitride capping layer from the FinFET device (e.g., by a hot phosphorus wash). The oxide cap on top of the RSD structures will be preserved throughout the removal of the nitride capping layer to provide hardmask protection during this process. | 2015-04-16 |
20150102415 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first and a second active regions having a first conductive type and a second conductive type, respectively, being arranged in a first direction; a gate extending in the first direction; a first and a second channel regions defined under the gate in the first and the active regions, respectively; a first low-concentration doped region, having the second conductive type, formed at sides of the gate in the first active region and a first high-concentration doped region, having the second conductive type, formed at sides of the first low-concentration doped region in the first active region; and a second low-concentration doped region, having the first conductive type, formed at sides of the gate in the second active region and a second high-concentration doped region, having the first conductive type, formed at sides of the second low-concentration doped region in the second active region. | 2015-04-16 |
20150102416 | DUAL-METAL GATE CMOS DEVICES AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a dual metal CMOS device comprising: forming a first type metal work function modulation layer in the first gate trench and the second gate trench; forming a second type work function metal diffusion source layer in the first gate trench and the second gate trench; forming a heat isolation layer that shields the region of the first type device; and thermally annealing the regions where the first type device and the second type device are located. | 2015-04-16 |
20150102417 | DOUBLE TRENCH WELL FORMATION IN SRAM CELLS - A method is provided for forming SRAM cells with low energy implants. Embodiments include forming deep trenches in a silicon substrate; forming a deep n-well or deep p-well around a bottom of each deep trench; filling the deep trenches with oxide; forming a first or second shallow trench between each pair of adjacent deep trenches; forming a first p-well or first n-well, respectively, above each deep n-well or p-well; forming a second n-well at a bottom of each first shallow trench; forming a p+ region above each second n-well on each side of each first shallow trench; filling the first shallow trenches with oxide; forming a second p-well at a bottom of each second shallow trench; filling the second shallow trenches with oxide; forming a p+ region above each second n-well on each side of each first shallow trench; and forming an n+ region above each second p-well. | 2015-04-16 |
20150102418 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE DEVICE - A semiconductor device includes a N-type field effect transistor comprising a N-channel region in a substrate. A high dielectric constant (high-k) layer is disposed on the N-channel region. A diffusion layer including a metal oxide is disposed on the high-k layer. A passivation layer is disposed on the diffusion layer, and a first metal gate is disposed on the passivation layer. The first high-k layer and the N-channel region include metal atoms of a metal element of the metal oxide. | 2015-04-16 |
20150102419 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes a first complementary semiconductor device provided on a semiconductor substrate, and including a CMOS circuit, a metal electrode provided above the first complementary semiconductor device, a semiconductor layer provided above the metal electrode, including an nMOS region and a pMOS region separated from each other, and containing Ge; and a second complementary semiconductor device including an nMOSFET provided on the first portion of the semiconductor layer and a pMOSFET provided on the second portion of the semiconductor layer. | 2015-04-16 |
20150102420 | SEMICONDUCTOR DEVICE - A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained. | 2015-04-16 |
20150102421 | Semiconductor Device - A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions. | 2015-04-16 |
20150102422 | INTEGRATED CIRCUITS INCLUDING FINFET DEVICES WITH LOWER CONTACT RESISTANCE AND REDUCED PARASITIC CAPACITANCE AND METHODS FOR FABRICATING THE SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer. | 2015-04-16 |
20150102423 | METHOD FOR FINFET SRAM RATIO TUNING - A semiconductor device and method of forming the same include a substrate having a plurality of memory cells formed thereon. A memory cell includes pass-gate transistors, pull-up transistors, and pull-down transistors. The pass-gate transistors and a portion of the pull-down transistors have different doping concentrations. | 2015-04-16 |
20150102424 | Forming Conductive STI Liners for FinFETS - An integrated circuit device includes a semiconductor substrate, isolation regions extending into the semiconductor substrate, a semiconductor strip, and a semiconductor fin overlapping and joined to the semiconductor strip. A first dielectric layer and a second dielectric layer are disposed on opposite sidewalls of the semiconductor strip. The integrated circuit device further includes a first conductive liner and a second conductive liner, wherein the semiconductor strip, the first dielectric layer, and the second dielectric layer are between the first conductive liner and the second conductive line. The first conductive liner and the second conductive liner are between, and in contact with, sidewalls of a first portion and a second portion of the isolation regions. | 2015-04-16 |
20150102425 | FLIP CHIP CONTACT (FCC) POWER PACKAGE - A power device package for containing, protecting and providing electrical contacts for a power transistor includes a top and bottom lead frames for directly no-bump attaching to the power transistor. The power transistor is attached to the bottom lead frame as a flip-chip with a source contact and a gate contact directly no-bumping attaching to the bottom lead frame. The power transistor has a bottom drain contact attaching to the top lead frame. The top lead frame further includes an extension for providing a bottom drain electrode substantially on a same side with the bottom lead frame. In a preferred embodiment, the power device package further includes a joint layer between device metal of source, gate or drain and top or bottom lead frame, through applying ultrasonic energy. | 2015-04-16 |
20150102426 | THREE-DIMENSIONAL TRANSISTOR WITH IMPROVED CHANNEL MOBILITY - The present invention relates to a semiconductor structure comprising at least a first and a second three-dimensional transistor, wherein the first transistor and the second transistor are electrically connected in parallel to each other, and wherein each transistor comprises a source and a drain, wherein the source and/or drain of the first transistor is at least partially separated from, respectively, the source and/or drain of the second transistor. The invention further relates to a process for realizing such a semiconductor structure. | 2015-04-16 |
20150102427 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A semiconductor device includes a substrate having an active region, a drain region in the active region, a source region in the active region, a gate structure, and a conductive field plate. The gate structure extends in a first direction over the active region. The gate structure is arranged between the drain region and the source region in a second direction transverse to the first direction. The conductive field plate extends in the second direction over an edge of the active region. | 2015-04-16 |
20150102428 | MERGED FIN FINFET WITH (100) SIDEWALL SURFACES AND METHOD OF MAKING SAME - A merged fin finFET and method of fabrication. The finFET includes: two or more single-crystal semiconductor fins on a top surface of an insulating layer on semiconductor substrate, each fin of the two or more fins having a central region between and abutting first and second end regions and opposite sides, top surfaces and sidewalls of the two or more fins are (100) surfaces and the longitudinal axes of the two or more fins aligned with a [100] direction; a gate dielectric layer on each fin of the two or more fins; an electrically conductive gate over the gate dielectric layer over the central region of each fin of the of two or more fins; and a merged source/drain comprising an a continuous layer of epitaxial semiconductor material on ends of each fin of the two or more fins, the ends on a same side of the conductive gate. | 2015-04-16 |
20150102429 | SEMICONDUCTOR DEVICE STRUCTURES AND METHODS OF FORMING SEMICONDUCTOR STRUCTURES - A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film having a global crystal orientation wherein the semiconductor film has a first crystal plane and second crystal plane, wherein the first crystal plane is denser than the second crystal plane and wherein the hard mask is formed on the second crystal plane. Next, the hard mask and semiconductor film are patterned into a hard mask covered semiconductor structure. The hard mask covered semiconductor structured is then exposed to a wet etch process which has sufficient chemical strength to etch the second crystal plane but insufficient chemical strength to etch the first crystal plane. | 2015-04-16 |
20150102430 | Spacer Formation with Straight Sidewall - Disclosed herein is a semiconductor device comprising a first dielectric disposed over a channel region of a transistor formed in a substrate and a gate disposed over the first dielectric. The semiconductor device further includes a second dielectric disposed vertically, substantially perpendicular to the substrate, at an edge of the gate, and a spacer disposed proximate to the second dielectric. The spacer includes a cross-section with a perimeter that includes a top curved portion and a vertical portion substantially perpendicular to the substrate. The perimeter further includes a discontinuity at an interface of the top curved portion with the vertical portion. Further, disclosed herein are methods associated with the fabrication of the aforementioned semiconductor device. | 2015-04-16 |
20150102431 | MECHANISMS FOR FORMING GATE DIELECTRIC LAYER - Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a nitride buffer layer over the semiconductor substrate, and the nitride buffer layer is in an amorphous state. The semiconductor device also includes a crystalline gate dielectric layer over the nitride buffer layer and a gate electrode over the crystalline gate dielectric layer. | 2015-04-16 |
20150102432 | Method of Improving Getter Efficiency by Increasing Superficial Area - The present disclosure relates to a method of gettering that provides for a high efficiency gettering process by depositing a gettering material on a roughened substrate surface, and an associated apparatus. In some embodiments, the method is performed by providing a substrate into a processing chamber having residual gases. One or more cavities are formed in the substrate at locations between bonding areas on a top surface of the substrate. Respective cavities have roughened interior surfaces that vary in a plurality of directions. A getter layer is deposited into the one or more cavities. The roughened interior surfaces of the one or more cavities enable the substrate to more effectively absorb the residual gases, thereby increasing the efficiency of the gettering process. | 2015-04-16 |
20150102433 | PACKAGE STRUCTURE HAVING MEMS ELEMENT - A package structure having at least an MEMS element is provided, including a chip having electrical connecting pads and the MEMS element; a lid disposed on the chip to cover the MEMS element and having a metal layer provided thereon; first sub-bonding wires electrically connecting to the electrical connecting pads; second sub-bonding wires electrically connecting to the metal layer; an encapsulant disposed on the chip, wherein the top ends of the first and second sub-bonding wires are exposed from the encapsulant; and metallic traces disposed on the encapsulant and electrically connecting to the first sub-bonding wires. The package structure advantageously features reduced size, relatively low costs, diverse bump locations, and an enhanced EMI shielding effect. | 2015-04-16 |
20150102434 | MICROELECTROMECHANICAL DEVICE WITH PROTECTION FOR BONDING AND PROCESS FOR MANUFACTURING A MICROELECTROMECHANICAL DEVICE - A microelectromechanical device includes: a substrate; a semiconductor die, bonded to the substrate and incorporating a microstructure; an adhesive film layer between the die and the substrate; and a protective layer between the die and the adhesive film layer. The protective layer has apertures, and the adhesive film layer adheres to the die through the apertures of the protective layer. | 2015-04-16 |
20150102435 | MEMS MICROPHONE WITH MEMBRANE ANTENNAS - A MEMS microphone. The microphone includes a backplate, a membrane, and a plurality of antennas. The backplate has a plurality of acoustic apertures. The membrane is parallel to the backplate and is positioned a distance from the backplate. The plurality of antennas are connected to the membrane and extend toward the backplate. In addition, the plurality of antennas are positioned entirely within spaces defined by the plurality of acoustic apertures. | 2015-04-16 |
20150102436 | Pre-Molded MEMS Device Package with Conductive Shell - A MEMS lead frame package body encloses a MEMS device enclosed in an internal cavity formed by the mold body and cover. A conductive internal shell with a connection window sits in the cavity. The MEMS device is mounted in the shell and electrically coupled to the lead frame through wire bonds directed through the connection window. To accommodate a MEMS microphone, an acoustic aperture extends through the mold body aligned with a hole in the internal shell. | 2015-04-16 |
20150102437 | MEMS SENSOR DEVICE WITH MULTI-STIMULUS SENSING AND METHOD OF FABRICATION | 2015-04-16 |
20150102438 | MAGNETIC RANDOM ACCESS MEMORY WITH PERPENDICULAR INTERFACIAL ANISOTROPY - The present invention is directed to an MRAM element comprising a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween. The magnetic free layer structure has a variable magnetization direction substantially perpendicular to the layer plane thereof. The magnetic reference layer structure includes a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated from the first magnetic reference layer by a first non-magnetic perpendicular enhancement layer. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer plane thereof. The second magnetic reference layer has a multilayer structure comprising a first magnetic reference sublayer formed adjacent to the first non-magnetic perpendicular enhancement layer and a second magnetic reference sublayer separated from the first magnetic reference sublayer by an intermediate metallic layer. | 2015-04-16 |
20150102439 | MAGNETIC RANDOM ACCESS MEMORY WITH PERPENDICULAR ENHANCEMENT LAYER - The present invention is directed to an MRAM element comprising a plurality of magnetic tunnel junction (MTJ) memory elements. Each of the memory elements comprises a magnetic reference layer structure, which includes a first and a second magnetic reference layers with a tantalum perpendicular enhancement layer interposed therebetween, an insulating tunnel junction layer formed adjacent to the first magnetic reference layer opposite the tantalum perpendicular enhancement layer, and a magnetic free layer formed adjacent to the insulating tunnel junction layer. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer planes thereof. | 2015-04-16 |
20150102440 | MAGNETIC TUNNELING JUNCTION DEVICES, MEMORIES, ELECTRONIC SYSTEMS, AND MEMORY SYSTEMS, AND METHODS OF FABRICATING THE SAME - Provided is a magnetic tunneling junction device including a fixed magnetic structure; a free magnetic structure; and a tunnel barrier between the fixed magnetic structure and the free magnetic structure, at least one of the fixed magnetic structure and the free magnetic structure including a perpendicular magnetization preserving layer, a magnetic layer between the perpendicular magnetization preserving layer and the tunnel barrier, and a perpendicular magnetization inducing layer between the perpendicular magnetization preserving layer and the magnetic layer. | 2015-04-16 |
20150102441 | MAGNETIC RANDOM ACCESS MEMORY HAVING PERPENDICULAR ENHANCEMENT LAYER AND THIN REFERENCE LAYER - The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto. | 2015-04-16 |
20150102442 | SOLID-STATE IMAGING DEVICE, METHOD OF FORMING MICROLENS IN SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - A solid-state imaging device comprises an imaging pixel located in a light receiving region, the imaging pixel being a component of a unit pixel that is one of a plurality of unit pixels arranged in an array direction. A phase difference detection pixel is located in the light receiving region and is a component of the unit pixel, and has a corresponding photodiode with an upper surface. A first microlens corresponds to the imaging pixel, and a second microlens corresponding to the phase difference detection pixel. The second microlens has a first bottom surface in the array direction and a second bottom surface in a direction diagonal to the array direction, the second bottom surface being closer to the upper surface of the photodiode than the first bottom surface. | 2015-04-16 |
20150102443 | Infrared Sensor Device and Method for Producing an Infrared Sensor Device - An infrared sensor device includes at least one sensor element formed in a semiconductor substrate, an SOI wafer that defines a gap below and around the sensor element, and a suspension device that is configured to suspend the sensor element in the SOI wafer. The sensor element is substantially arranged below the suspension device, thereby achieving a high sensitivity, low thermal capacity, low thermal coupling to the substrate and a high image refresh rate. | 2015-04-16 |
20150102444 | LIGHT SENSORS HAVING DIELECTRIC OPTICAL COATING FILTERS - Light sensors including dielectric optical coatings to shape their spectral responses, and methods for fabricating such light sensors in a manner that accelerates lift-off processes and increases process margins, are described herein. In an embodiment, a light sensor includes a photodetector sensor region formed in a semiconductor substrate, a dielectric optical coating filter covering the photodetector sensor region, and dummy dielectric optical coating features beyond the photodetector sensor region, wherein the dummy dielectric optical features include one or more dummy corners, dummy islands and/or dummy rings. Alternatively, or additionally, the dielectric optical coating filter includes chamfered corners, which improves the thermal reliability of the dielectric optical coating. | 2015-04-16 |
20150102445 | ALIGNMENT MARKS AND ALIGNMENT METHODS FOR ALIGNING BACKSIDE COMPONENTS TO FRONTSIDE COMPONENTS IN INTEGRATED CIRCUITS - An imaging system may include an imager integrated circuit with frontside components such as imaging pixels and backside components such as color filters and microlenses. The imager integrated circuit may be mounted to a carrier wafer with alignment marks. Bonding marks on the carrier wafer and the imager integrated circuit may be used to align the carrier wafer accurately to the imager integrated circuit. The alignment marks on the carrier wafer may be read, by fabrication equipment, to align backside components of the imager integrated circuit, such as color filters and microlenses, with backside components of the imager integrated circuit, such as photodiodes. | 2015-04-16 |
20150102446 | SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS - A solid-state imaging device includes a plurality of photoelectric conversion portions each provided in a semiconductor substrate and receives incident light through a light sensing surface, and a pixel separation portion provided to electrically separate a plurality of pixels. At least a pinning layer and a light shielding layer are provided in an inner portion of a trench provided on a side portion of each of the photoelectric conversion portions in an incident surface side, the trench includes a first trench and a second trench formed to be wider than the first trench in a portion shallower than the first trench, the pinning layer is formed in an inner portion of the first trench to cover an inside surface of the second trench, and the light shielding layer is formed to bury an inner portion of the second trench at least via the pinning layer. | 2015-04-16 |
20150102447 | METHOD FOR PRODUCING PHOTOSENSITIVE INFRARED DETECTORS - A method for producing at least one photosensitive infrared detector by assembling a first electronic component including plural photodiodes sensitive to infrared radiation and a second electronic component including at least one electronic circuit for reading the plurality of photodiodes, an infrared detector, and an assembly for producing such a detector, the method including: production, on each one of the first and second components, of a connection face formed at least partially by a silicon oxide (SiO2)-based layer; bonding the first component and the second component by the connection faces thereof, thus performing the direct bonding of the two components. The method can simplify hybridization of heterogeneous components for producing an infrared detector. | 2015-04-16 |
20150102448 | IMAGE PICKUP DEVICE, METHOD OF MANUFACTURING IMAGE PICKUP DEVICE, AND ELECTRONIC APPARATUS - Provided is an image pickup device, including: a first trench provided between a plurality of pixels in a light-receiving region of a semiconductor substrate, the semiconductor substrate including the light-receiving region and a peripheral region, the light-receiving region being provided with the plurality of pixels each including a photoelectric conversion section; and a second trench provided in the peripheral region of the semiconductor substrate, wherein the semiconductor substrate has a variation in thickness between a portion where the first trench is provided and a portion where the second trench is provided. | 2015-04-16 |
20150102449 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a semiconductor device that can suppress a leakage current more than has been achieved before. A semiconductor device | 2015-04-16 |
20150102450 | STRUCTURE AND METHOD FOR FORMING INTEGRAL NITRIDE LIGHT SENSORS ON SILICON SUBSTRATES - A semiconductor integrated circuit has one or more integral nitride-type sensors. In one embodiment, an integral nitride-type sensor and a coplanar supplemental circuit are formed from a common silicon substrate base. In another embodiment, an integral nitride-type sensor and a supplemental circuit are integrated in a vertical orientation. | 2015-04-16 |
20150102451 | NANOSCALE SILICON SCHOTTKY DIODE ARRAY FOR LOW POWER PHASE CHANGE MEMORY APPLICATION - Methods and devices associated with a phase change memory include Schottky diodes operating as selectors having a low turn-on voltage, low sneak current and high switching speed. A method of forming a semiconductor device includes providing a semiconductor substrate having a diode array region and a peripheral device region, forming an N+ buried layer in the diode array region, forming a semiconductor epitaxial layer on the N+ buried layer, and forming deep trench isolations through the epitaxial layer and the N+ buried layer along a first direction. The method also includes forming shallow trench isolations in the diode array region and in the peripheral region along a second line direction. The method also includes forming an N− doped region between the deep and shallow trench isolations and forming a metal silicide on a surface of the N− doped region. | 2015-04-16 |
20150102452 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes, in a termination region, a p− type breakdown voltage holding region that is an impurity region formed in a predetermined depth direction from a substrate surface of an n− type substrate, a first insulating film formed on the n− type substrate so as to cover at least the p− type breakdown voltage holding region, a first field plate formed on the first insulating film, a second insulating film formed so as to cover the first field plate and the first insulating film, and a second field plate formed on the second insulating film. The first insulating film is thicker in a corner portion than in an X-direction straight portion and a Y-direction straight portion. | 2015-04-16 |
20150102453 | Fabricating Shallow-Trench Isolation Semiconductor Devices To Reduce Or Eliminate Oxygen Diffusion - A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide. | 2015-04-16 |
20150102454 | FORMING FINS OF DIFFERENT MATERIALS ON THE SAME SUBSTRATE - A semiconductor substrate may be formed by providing an providing a semiconductor-on-insulator (SOI) substrate including a base semiconductor layer, a buried insulator layer above the base semiconductor layer, and a SOI layer comprising a first semiconductor material above the buried insulator layer; forming an isolation region in the SOI layer isolating a first portion of the SOI layer from a second portion of the SOI layer; removing the second portion of the SOI layer to expose a portion of the buried insulator layer; forming a hole in the exposed portion of the buried insulator layer to expose a portion of the base semiconductor layer; and forming a semiconductor layer made of a second semiconductor material on the exposed portion of the base semiconductor layer, so that the replacement semiconductor layer covers the exposed region of the buried insulator layer. | 2015-04-16 |
20150102455 | METHOD OF FABRICATING DUAL TRENCH ISOLATED SELECTIVE EPITAXIAL DIODE ARRAY - Methods and devices associated with phase change memory include diodes operating as selector switches having a large driving current and high switching speed. A method of forming a semiconductor device includes providing a semiconductor substrate, defining a diode array region and a peripheral region on the semiconductor substrate, forming an N+ buried layer in the diode array region by performing an ion implantation process and an annealing process. The method also includes forming a semiconductor epitaxial layer on the N+ buried layer, forming deep trench isolations through the epitaxial layer and the N+ buried layer into a portion of the substrate in the first direction, and forming shallow trench isolations in the diode array region and in the peripheral region in the second direction. The shallow trench isolation has a depth equal to or greater than a thickness of the epitaxial layer. | 2015-04-16 |
20150102456 | AMORPHORUS SILICON INSERTION FOR STI-CMP PLANARITY IMPROVEMENT - A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a first cushion layer, a second cushion layer and an insulating filler. The first cushion layer is peripherally enclosed by the semiconductor substrate, the second cushion layer is peripherally enclosed by the first cushion layer, and insulating filler is peripherally enclosed by the second cushion layer. A method for fabricating the semiconductor device is also provided herein. | 2015-04-16 |
20150102457 | SEMICONDUCTOR DEVICE - A polysilicon resistor includes a high resistance conductor, a low resistance conductor adjacent to one end portion of the high resistance conductor, and a low resistance conductor adjacent to the other end portion of the high resistance conductor. Of the high resistance conductor, a width of a first place reacting most actively when a current flows into a polysilicon fuse is narrowest. Of the high resistance conductor, a width of a second place serving as an interface with each of the low resistance conductors is widest. The width of the high resistance conductor increases gradually from the first place toward the second place. | 2015-04-16 |
20150102458 | E-FUSE STRUCTURE OF SEMICONDUCTOR DEVICE - Provided is an e-fuse structure of a semiconductor device. the e-fuse structure may include a fuse link formed of a first metal material to connect a cathode with an anode, a capping dielectric covering a top surface of the fuse link, and a dummy metal plug penetrating the capping dielectric and being in contact with a portion of the fuse link. The dummy metal plug may include a metal layer and a barrier metal layer interposed between the metal layer and the fuse link. The barrier metal layer may be formed of a second metal material different from the first metal material. | 2015-04-16 |
20150102459 | Metal Insulator Metal Capacitor and Method for Making the Same - A semiconductor device includes one or more metal-insulator-metal (MiM) capacitors. The semiconductor device includes a bottom electrode, a dielectric layer located above, and in physical contact with, the bottom electrode, a top electrode located above, and in physical contact with, the dielectric layer, a first top contact contacting the top electrode, a first bottom contact contacting the bottom electrode from a top electrode direction, a first metal bump connecting to the top contact, and a second metal bump connecting to the bottom contact. The top electrode has a smaller area than the bottom electrode. The bottom electrode, the dielectric layer, and the top electrode is a MiM capacitor. Top electrodes of a number of MiM capacitors and bottom electrodes of a number of MiM capacitors are daisy chained to allow testing of the conductivity of the electrodes. | 2015-04-16 |
20150102460 | SEMICONDUCTOR STRUCTURES INCLUDING MOLYBDENUM NITRIDE, MOLYBDENUM OXYNITRIDE OR MOLYBDENUM-BASED ALLOY MATERIAL, AND METHOD OF MAKING SUCH STRUCTURES - A semiconductor structure may include a first electrode over a substrate, a high-K dielectric material over the first electrode, and a second electrode over the high-K dielectric material, wherein at least one of the first electrode and the second electrode may include a material selected from the group consisting of a molybdenum nitride (Mo | 2015-04-16 |
20150102461 | Cost Effective Method of Forming Embedded DRAM Capacitor - A high capacitance embedded metal interconnect capacitor and associated fabrication processes are disclosed for using a directional barrier metal formation sequence in a dual damascene copper process to form multi-layer stacked copper interconnect structure having reduced barrier metal layer formation at the bottom of each via hole so that the multi-layer stacked copper interconnect structure may be readily removed and replaced with high capacitance MIM capacitor layers. | 2015-04-16 |
20150102462 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - A semiconductor device includes a substrate and a plurality of storage nodes on the substrate and extending in a vertical direction relative to the substrate. A lower support pattern is in contact with the storage nodes between a bottom and a top of the storage nodes, the lower support pattern spaced apart from the substrate in the vertical direction, and the lower support pattern having a first maximum thickness in the vertical direction. An upper support pattern is in contact with the storage nodes above the lower support pattern relative to the substrate, the upper support pattern spaced apart from the lower support pattern in the vertical direction, and the lower support pattern having a second maximum thickness in the vertical direction that is greater than the first maximum thickness of the lower support pattern. | 2015-04-16 |
20150102463 | HIGH-K AND METAL FILLED TRENCH-TYPE EDRAM CAPACITOR WITH ELECTRODE DEPTH AND DIMENSION CONTROL - Partial removal of organic planarizing layer (OPL) material forms a plug of OPL material within an aperture that protects underlying material or electronic device such as a deep trench capacitor during other manufacturing processes. The OPL plug thus can absorb any differences or non-uniformity in, for example, etch rates across the chip or wafer and preserve recess dimensions previously formed. control of a lateral component of later removal of the OPL plug by etching also can increase tolerance of overlay error in forming connections and thus avoid loss in manufacturing yield. | 2015-04-16 |
20150102464 | CAPACITOR WITH HOLE STRUCTURE AND MANUFACTURING METHOD THEREOF - Disclosed herein are a capacitor with a hole structure and a manufacturing method thereof. A capacitor with a hole structure includes: a substrate layer having a plurality of through-holes formed therein; a lower electrode layer including a first conductive layer having a low specific resistance and a second conductive layer having a specific resistance higher than that of the first conductive layer, the first conductive layer being formed on an inner wall of the through-hole and the second conducive layer being formed on the first conductive layer; a thin film dielectric layer formed on the lower electrode layer; and an upper electrode layer including a third conductive layer and a fourth conductive layer having a specific resistance lower than that of the third conductive layer, the third conductive layer being formed on the thin film dielectric layer and the fourth conductive layer being formed on the third conductive layer. | 2015-04-16 |
20150102465 | Material quality, suspended material structures on lattice-mismatched substrates - Suspended structures are provided using selective etch technology. Such structures can be protected on all sides when the selective undercut etch is performed, thereby providing excellent control of feature geometry combined with superior material quality. | 2015-04-16 |
20150102466 | SEMICONDUCTOR-ON-INSULATOR STRUCTURE AND METHOD OF FABRICATING THE SAME - Methods for forming a layer of semiconductor material and a semiconductor-on-insulator structure are provided. A substrate including one or more devices or features formed therein is provided. A seed layer is bonded to the substrate, where the seed layer includes a crystalline semiconductor structure. A first portion of the seed layer that is adjacent to an interface between the seed layer and the substrate is amorphized. A second portion of the seed layer that is not adjacent to the interface is not amorphized and maintains the crystalline semiconductor structure. Dopant implantation is performed to form an N-type conductivity region or a P-type conductivity region in the first portion of the seed layer. A solid-phase epitaxial growth process is performed to crystallize the first portion of the seed layer. The SPE growth process uses the crystalline semiconductor structure of the second portion of the seed layer as a crystal template. | 2015-04-16 |
20150102467 | METHOD OF DICED WAFER TRANSPORTATION - Methods of dicing semiconductor wafers, and transporting singulated die, are described. In an example, a method of dicing a wafer having a plurality of integrated circuits thereon involves dicing the wafer into a plurality of singulated dies disposed above a dicing tape. The method also involves forming a water soluble material layer over and between the plurality of singulated dies, above the dicing tape. | 2015-04-16 |
20150102468 | CHIP-STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A chip-stacked semiconductor package includes a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface; a second chip having a second front surface, a second back surface, a second connection member and a first through-silicon via (TSV) electrically connected to the second connection member, the second back surface opposite to the second front surface, and the second connection member on the second front face; and a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first connection member of the first chip and the second connection member of the second chip being symmetric with respect to each other. | 2015-04-16 |
20150102469 | SEMICONDUCTOR STRUCTURE INCLUDING LATERALLY DISPOSED LAYERS HAVING DIFFERENT CRYSTAL ORIENTATIONS AND METHOD OF FABRICATING THE SAME - A semiconductor structure includes a substrate and first and second crystalline semiconductor layers. The first crystalline semiconductor layer has a first crystal orientation, and includes a crystallized amorphous region formed on the substrate. The second crystalline semiconductor layer is formed on the substrate, is laterally disposed of the first crystalline semiconductor layer, and has a second crystal orientation different from the first crystal orientation. A method of fabricating the semiconductor structure is also disclosed. | 2015-04-16 |
20150102470 | Semiconductor Film with Adhesion Layer and Method for Forming the Same - Presented herein is a method for forming a semiconductor film using an adhesion layer, comprising providing an oxide layer disposed over a substrate, forming at least one adhesion layer over the oxide layer, and forming a film layer over the at least one adhesion layer in a same process step as the forming the at least one adhesion layer. Forming the at least one adhesion layer further comprises at least forming a first adhesion layer over the oxide layer and forming a second adhesion layer over the first adhesion layer. Forming the first adhesion layer comprises providing the terminating gas at a substantially constant first flow rate, and wherein the forming the second adhesion layer comprises ramping a flow rate of the terminating gas to a zero flow rate from the first flow rate. | 2015-04-16 |
20150102471 | SEMICONDUCTOR-ON-INSULATOR STRUCTURE AND METHOD OF FABRICATING THE SAME - Methods for forming a layer of semiconductor material are provided. A substrate is provided. An amorphous layer is formed over the substrate, where the amorphous layer includes a semiconductor or a semiconductor alloy. A seed wafer is bonded to the amorphous layer, where the seed wafer includes a crystalline semiconductor structure. A solid-phase epitaxial (SPE) growth process is performed to crystallize the amorphous layer, where the SPE growth process uses the crystalline semiconductor structure of the seed wafer as a crystal template. The seed wafer is debonded from the structure. | 2015-04-16 |
20150102472 | SEMICONDUCTOR DEVICE WITH SHIELDING LAYER IN POST-PASSIVATION INTERCONNECT STRUCTURE - A semiconductor device includes a semiconductor substrate, a dielectric layer, a passivation layer, a protective layer, a post-passivation interconnect (PPI) structure, and a shielding layer. The semiconductor substrate has electrical circuitry. The dielectric layer is formed on the semiconductor substrate. The passivation layer is formed on the dielectric layer. The first protective layer is formed on the passivation layer. The PPI structure is disposed on the first protective layer and has a signal line and a ground line. The shielding layer is disposed over the semiconductor substrate and between the signal line and the electrical circuitry. The shielding layer is substantially equi-potentially connected to the ground line of the PPI structure. | 2015-04-16 |
20150102473 | CHIP PACKAGE AND PACKAGING METHOD - A chip package and a packaging method are provided, which relates to the field of communications technologies, and is invented to implement high-frequency electromagnetic interference shielding and effectively improve chip performance. The package includes a package substrate and a metal cap covering the package substrate, where a silicon chip placement area is arranged on an upper surface of the package substrate, multiple first conductive parts are arranged in a peripheral area of the silicon chip placement area, and an edge of the metal cap is in contact with the package substrate and electrically connected to the multiple first conductive parts, where at least a portion of first conductive parts in the multiple first conductive parts are electrically connected to a grounding part by using the metal cap, and the grounding part is arranged on the package substrate, and configured to ground the package substrate. | 2015-04-16 |
20150102474 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MOUNTING STRUCTURE AND POWER SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of die pad sections, a plurality of semiconductor chips, each of which is arranged in each of the die pad sections, a resin encapsulation portion having a recess portion for exposing at least a portion of the die pad sections, the resin encapsulation portion configured to cover the die pad sections and the semiconductor chips, and a heat radiation layer arranged in the recess portion. The heat radiation layer includes an elastic layer exposed toward a direction in which the recess portion is opened. The heat radiation layer directly faces at least a portion of the die pad sections. The elastic layer overlaps with at least a portion of the die pad sections when seen in a thickness direction of the heat radiation layer. | 2015-04-16 |
20150102475 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - The invention discloses a package structure for better heat-dissipation or EMI performance. A first conductive element and a second conductive element are both disposed between the top lead frame and the bottom lead frame. The first terminal of the first conductive element is electrically connected to the bottom lead frame, and the second terminal of the first conductive element is electrically connected to the top lead frame. The third terminal of the second conductive element is electrically connected to the bottom lead frame, and the fourth terminal of the second conductive element is electrically connected to the top lead frame. In one embodiment, a heat dissipation device is disposed on the top lead frame. In one embodiment, the molding compound is provided such that the outer leads of the top lead frame are exposed outside the molding compound. | 2015-04-16 |
20150102476 | QUAD FLAT NO LEAD PACKAGE AND PRODUCTION METHOD THEREOF - The present invention discloses a quad flat no lead package and a production method thereof. The quad flat no lead package comprises a lead frame carrier consisting of a carrier pit and three circles of leads arranged around the carrier pit, wherein the three circles of leads respectively consist of a plurality of leads that are disconnected mutually; an IC chip is adhered in the carrier pit; and an inner lead chemical nickel and porpezite plated layer is plated on all the leads; the inner lead chemical nickel and porpezite plated layer is arranged in the same direction as the IC chip; the IC chip is connected with the inner lead chemical nickel and porpezite plated layer through a bonding wire; and the IC chip, the ends of all the leads plated with the inner lead chemical plating nickel and palladium metal layers and the bonding wire are all packaged in a plastic package. The quad flat no lead package is manufactured through the following steps of: thinning and scribing a wafer; manufacturing a lead frame; loading the chip; performing pressure welding and plastic packaging; performing post-curing; printing; electroplating; separating the leads; separating a product; and testing/braiding. According to the package, the problems of few leads, long welding wire, high welding cost and limited frequency application during single-face packaging of the existing normal quad flat no lead package are solved. | 2015-04-16 |
20150102477 | X-LINE ROUTING FOR DENSE MULTI-CHIP-PACKAGE INTERCONNECTS - X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of conductive traces is disposed above the substrate. A first pair of ground traces is disposed in a first of the plurality of layers of conductive traces. A signal trace is disposed in a second of the plurality of layers of conductive traces, below the first layer. A second pair of ground traces is disposed in a third of the plurality of layers of conductive traces, below the first layer. The first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective. | 2015-04-16 |
20150102478 | SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING SEMICONDUCTOR PACKAGE - Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact pads disposed on the first surface of the package substrate by insulated wire bonds. A cap is disposed over the first surface of the package substrate. The cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds. The insulated wire bonds are directly exposed to an environment through at least one access port of the package. | 2015-04-16 |
20150102479 | Electrically insulating thermal interface on the discontinuity of an encapsulation structure - Method for manufacturing an electronic semiconductor package, in which method an electronic chip ( | 2015-04-16 |
20150102480 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device comprising a cooler in which, by improving the shape of the connecting portions of an inlet/outlet of a coolant or the like, the pressure loss in the connecting portion or the like can be reduced. | 2015-04-16 |
20150102481 | SINTERED BACKSIDE SHIM IN A PRESS PACK CASSETTE - Within a cassette of a press pack module, a conductive shim is bonded to the backside of a device die by a layer of sintered metal. The die, sintered metal, and shim together form a sintered assembly. The cassette is compressed between a metal top plate member and a metal bottom plate member such that the backside of the assembly is pressed against the top plate member, and such that the frontside of the assembly is pressed against another shim. A central portion of the frontside surface of the die is contacted on the bottom by the other shim, but there is no shim contacting a peripheral portion of the frontside surface. Despite there being no shim in contact with the peripheral portion of the frontside surface, the peripheral portion is in good thermal contact with the top plate member through the sintered metal and the bonded conductive shim. | 2015-04-16 |
20150102482 | Mechanism for Forming Patterned Metal Pad connected to Multiple Through Silicon Vias (TSVs) - Various embodiments of mechanisms for forming through a three-dimensional integrated circuit (3DIC) structure are provided. The 3DIC structure includes an interposer bonded to a die and a substrate. The interposer has a conductive structure with through silicon vias (TSVs) connected to a patterned metal pad and a conductive structure on opposite ends of the TSVs. The pattern metal pad is embedded with dielectric structures to reduce dishing effect and has regions over TSVs that are free of the dielectric structures. The conductive structure has 2 or more TSVs. By using a patterned metal pad and 2 or more TSVs, the reliability and yield of the conductive structure and the 3DIC structure are improved. | 2015-04-16 |
20150102483 | MICROELECTRONIC PACKAGE WITH STRESS-TOLERANT SOLDER BUMP PATTERN - A microelectronic package includes larger diameter solder bumps and smaller diameter solder bumps for coupling an interposer to a packaging substrate. The larger diameter solder bumps are positioned on a peripheral surface of the interposer and the smaller diameter solder bumps are positioned on a center surface of the interposer. The solder bumps positioned in the peripheral region can more reliably withstand the higher mechanical stresses that occur in this peripheral region during operation of the microelectronic package. | 2015-04-16 |
20150102484 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A package structure is disclosed, which includes: a first substrate; a build-up layer formed on and electrically connected to the first substrate and having a cavity; at least an electronic element disposed in the cavity and electrically connected to the first substrate; a stack member disposed on the build-up layer so as to be stacked on the first substrate; and an encapsulant formed between the build-up layer and the stack member. The build-up layer facilitates to achieve a stand-off effect and prevent solder bridging. | 2015-04-16 |
20150102485 | NON-CONDUCTIVE FILM AND NON-CONDUCTIVE PASTE INCLUDING ZINC PARTICLES, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A non-conductive material layer, selected from a non-conductive film and a non-conductive polymer paste, and containing a dispersion of zinc (Zn) particles is disclosed, together with semiconductor packages including the non-conductive material layer. The non-conductive material layer contains zinc (Zn) particles having an average particle diameter of about 1 nm to about 200 nm in a non-conductive polymer base material of a film type, and a semiconductor package includes the non-conductive film. By using the non-conductive film and/or the non-conductive paste containing the zinc dispersion, e a semiconductor package having excellent electric connection properties and high reliability may be manufactured through simple processes at low manufacturing costs. | 2015-04-16 |
20150102486 | Method for Mounting a Chip and Chip Package - Provided is a method of mounting a chip. The method includes: forming a bump at one surface of a cavity formed concavely in an inner direction of a substrate; performing a coining process to flatten a surface of the bump; coating a solder material on the bump subjected to the coining process; and bonding a chip and the bump by melting the solder material, wherein an electrode portion or a metal portion is formed on a bottom of the chip. For a metal substrate according to the present invention, wherein a vertical insulating layer is included, since the electrode portion of the chip and the electrode portion of the substrate have to be electrically connected, the metal substrate is bonded to the electrode portion of the chip using the bump additionally formed on the metal substrate, so the heat generated in the chip can be rapidly transferred to the substrate, and the junction temperature of the chip can be decreased, thereby enhancing the light efficiency and the. In addition, cracking due to the difference of thermal expansion coefficient between solder materials can be prevented by sealing the bonding portion of the chip using the solder materials. Further, since oxidation of the bonding portion is prevented by blocking the contact with the outside, the chip packaging process can be performed without an additional process of filling an inert gas into the internal space wherein the chip is mounted. | 2015-04-16 |
20150102487 | STRESS BUFFER STRUCTURES IN A MOUNTING STRUCTURE OF A SEMICONDUCTOR DEVICE - A semiconductor device includes a bonding pad on a substrate. The semiconductor device further includes a passivation layer covering a peripheral portion of the bonding pad while exposing a middle portion of the bonding pad. Additionally, the semiconductor device includes a stress buffer layer over the passivation layer where the stress buffer layer exposes a portion of the bonding pad, and where a wall of the stress buffer layer extends, in steps, upwardly from the exposed portion of the bonding pad. Furthermore, the semiconductor device includes an under-bump metallurgy (UBM) layer over the stress buffer layer, where the UBM layer contacts a portion of the bonding pad. | 2015-04-16 |
20150102488 | PRINTED CIRCUIT BOARD USING SOLDER COATING BALL - Disclosed herein a printed circuit board comprising: a plurality of pads formed on a substrate; a solder resist (SR) pattern enclosing a region of the pad and burying another circuit pattern; and a solder pattern including a metal pattern therein using a solder and formed on an upper surface of each of the pads. | 2015-04-16 |
20150102489 | SEMICONDUCTOR DEVICE INCLUDING A BUFFER LAYER STRUCTURE FOR REDUCING STRESS - A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire coupling part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer | 2015-04-16 |
20150102490 | SEMICONDUCTOR DEVICE HAVING AN AIRBRIDGE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of forming an airbridge extending from a conductive area of the semiconductor device are provided. The semiconductor device includes a device pattern formed on a semiconductor substrate, a seed layer formed on the device pattern, and an airbridge formed on the seed layer, where the airbridge includes a plated conductive material and defines an opening exposing a portion of the device pattern. The semiconductor device further includes an adhesion layer formed on the airbridge layer and extending over at least a portion of sidewalls of the opening defined by the airbridge, and an insulating layer formed on the adhesion layer, where the adhesion layer enhances adhesion of the insulating layer to the plated conductive material of the airbridge. | 2015-04-16 |
20150102491 | Semiconductor Device Including A Contact Plug With Barrier Materials - Disclosed herein is a semiconductor device that comprises a plug including an upper portion, a lower portion and a side surface and comprising tungsten, a barrier metal comprising tungsten nitride and covering the side surface and the lower portion of the contact plug, a conductive layer, and a barrier layer comprising titanium and intervening between the barrier metal and the first conductive layer. | 2015-04-16 |
20150102492 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, and a multilayered wiring formed in a prescribed area within the insulating film. The multilayered wiring includes a dual damascene wiring positioned on at least one layer of the multilayered wiring. The dual damascene wiring includes an alloy having copper as a principal component. A concentration of at least one metallic element contained as an added component of the alloy in a via connected to the dual damascene wiring is 10% or more higher in a via connected to a wiring whose width exceeds by five or more times a diameter of the via than that in another via connected to another wiring of a smallest width in a same upper wiring layer of the multilayered wiring. | 2015-04-16 |
20150102493 | Die and Chip - A die according to an embodiment includes a contact pad configured to provide an electrical contact to a circuit element included in the die, a lateral edge closest to the contact pad and a cover layer including a protective structure, the protective structure including at least one elongated structure, wherein the cover layer includes an opening providing access to the contact pad to couple the contact pad electrically to an external contact, wherein the protective structure is arranged between the lateral edge and the contact pad. Using an embodiment may reduce a danger of contamination of a top side of a die during fabrication and packaging a chip. | 2015-04-16 |
20150102494 | METHOD FOR FORMING VOIDS AND STRUCTURE WITH VOIDS FORMED USING THE SAME - A method for forming voids corresponding to pads of SMT components is provided. The method comprises following steps: One or more condition parameters are inputted into a searching unit. The searching unit searches all of the pads with reference to the condition parameters to obtain a pre-selected group of pads. A judgment unit is provided to determine whether each pad of the pre-selected group of pads meets a pre-determined processing requirement to generate a to-be-processed group of pads. An execution unit executes a void formation step with reference to corner coordinates of each of the to-be-processed group of pads, so as to form at least a void at the portion of a contact surface corresponding to a corner of the pad. In an embodiment, four voids which are related to respective corners of each pad of the to-be-processed group are formed at the contact surface accordingly. | 2015-04-16 |