16th week of 2009 patent applcation highlights part 40 |
Patent application number | Title | Published |
20090098625 | SYSTEM AND METHOD FOR SEQUESTERING CARBON DIOXIDE AND BIOLOGICAL CONVERSION OF CARBON DIOXIDE THROUGH PHYTOGENIC PROCESSING INTO BIOGAS AND OXYGEN - A method for converting carbon dioxide into various gases is disclosed. The method comprises the use of naturally-occurring methanogenic bacteria, like that contained in peat moss, to convert carbon dioxide into various gases through bioconversion utilizing phytogenic processes. | 2009-04-16 |
20090098626 | NUCLEIC ACIDS ENCODING MODIFIED CYTOCHROME P450 ENZYMES AND METHODS OF USE THEREOF - The present invention provides nucleic acids comprising nucleotide sequences encoding modified cytochrome P450 enzymes; as well as recombinant vectors and host cells comprising the nucleic acids. The present invention further provides methods of producing a functionalized compound in a host cell genetically modified with a nucleic acid comprising nucleotide sequences encoding a modified cytochrome P450 enzyme. | 2009-04-16 |
20090098627 | Method of immobilizing a protein or molecule via a mutant dehalogenase that is bound to an immobilized dehalogenase substrate and linked directly or indirectly to the protein or molecule - A mutant hydrolase optionally fused to a protein of interest is provided. The mutant hydrolase is capable of forming a bond with a substrate for the corresponding nonmutant (wild-type) hydrolase which is more stable than the bond formed between the wild-type hydrolase and the substrate and has at least two amino acid substitutions relative to the wild-type hydrolase. Substrates for hydrolases comprising one or more functional groups are also provided, as well as methods of using the mutant hydrolase and the substrates of the invention. Also provided is a fusion protein capable of forming a stable bond with a substrate and cells which express the fusion protein. | 2009-04-16 |
20090098628 | Methods and Devices for Microencapsulation of Cells - Devices for the microencapsulation of cells include a first chamber for containing a cell-solution suspension. A plate covers one end of the first chamber. The plate has a plurality of apertures. A second chamber is provided for receiving encapsulated cells. The second chamber is separated from the first chamber by the plate. Cells from the first chamber are encapsulated by passing through the apertures in the plate and into the second chamber when pressure is applied to the cell-solution suspension. | 2009-04-16 |
20090098629 | NOVEL GENE EXPRESSED IN PROSTATE CANCER - A novel testis-specific gene expressed in human prostate cancer, designated 22P4F11, is described. Analysis of 22P4F11 mRNA expression in normal prostate, prostate tumor xenografts, and a variety of normal tissues indicates that the expression of this gene is testis specific in normal tissues. The 22P4F11 gene is also expressed in human prostate tumors, in some cases at high levels. A full length cDNA encoding 22P4F11 is provided. The 22P4F11 transcript and/or protein may represent a useful diagnostic marker and/or therapeutic target for prostate cancer. | 2009-04-16 |
20090098630 | FUSION PROTEIN, GENE RELATED TO FUSION PROTEIN, VECTOR, TRANSFORMANTS, AND ANTI-INFLAMMATORY MEDICINAL COMPOSITION - Fusion protein comprises a thioredoxin and human serum albumin. The thioredoxin comprises a protein comprising the amino acid sequence shown in SEQ. ID. No. 1, or the like, the human serum albumin comprises a protein comprising the amino acid sequence shown in SEQ. ID. No. 2, or the like. The fusion protein of the invention allows the activity of thioredoxin to be maintained over a long period of time. It is thus possible to provide a protein preparation that is stable over long periods of time. | 2009-04-16 |
20090098631 | Novel glutamic acid decarboxylase (GAD) proteins and methods of use - The invention relates to novel Glutamic Acid Decarboxylases (GAD). More specifically, novel DNA and protein sequences relating to GAD. Additionally, the invention discloses a novel composition and related methods for treating neurodegenerative diseases such as Parkinson's disease, Alzheimer's disease, epilepsy, and the like, using viral and non-viral delivery systems that deliver therapeutic agents to specific regions of the brain. More specifically, using an adeno-associated viral vector to deliver a nucleotide sequence encoding a novel glutamic acid decarboxylase (GAD) to specific regions of the brain that are over stimulated or disinhibited in various diseases, including neurodegenerative diseases. | 2009-04-16 |
20090098632 | Compositions comprising viruses and methods for concentrating virus preparations - A composition is disclosed comprising virus in a formulation comprising a polyhydroxy hydrocarbon buffered to maintain a pH in a range from about 7 to about 8.5 at a temperature in the range from about 2° C. to 27° C. Methods for concentrating and purifying virus preparations are also disclosed. | 2009-04-16 |
20090098633 | HMGN2 peptides and related molecules that selectively home to tumor blood vessels and tumor cells - The present invention provides a conjugate which contains a therapeutic moiety linked to a homing molecule that selectively homes to tumor blood vessels and tumor cells and that specifically binds the receptor bound by peptide KDEPQRRSARLSAKPAPPKPEPKPKKAPAKK (SEQ ID NO: 9). Methods of directing a conjugate of the invention to tumor blood vessels and tumor cells and of using a conjugate to treat cancer also are provided. | 2009-04-16 |
20090098634 | SCLEROPROTEIN OF AN ADENO ASSOCIATED VIRUS WITH MODIFIED CHROMATOGRAPHIC PROPERTIES, THE PRODUCTION THEREOF AND USE OF THE SAME - The invention relates to a scleroprotein of an adeno-associated virus which contains at least one mutation. Said mutation causes the chromatographic properties to be modified. The invention also relates to the production of said scleroprotein and the use thereof. | 2009-04-16 |
20090098635 | METHOD FOR SUPPLY OF STARTER CULTURES HAVING A CONSISTENT QUALITY - The present invention relates to the field of producing starter cultures. In particular, a method for customers in need of a starter culture with a consistent quality, is provided. Specifically, the method involves the use of subsets of a stock inoculum material, which comprises a concentrate of starter culture organism cells to be propagated for direct inoculation of a cultivation medium, to obtain a starter culture whereby the conventional stepwise preparation of inoculum material for the production of a starter culture can be avoided. This novel method can be used for the manufacturing of starter cultures for the food, feed or pharmaceutical industry. Furthermore, the method is useful in the cultivation of cells expressing desired products, such as primary and secondary metabolites, including e.g. enzymes and flavours. | 2009-04-16 |
20090098636 | FUNGAL CELL WALL SYNTHESIS GENE - A reporter system reflecting the transport process that transports GPI-anchored proteins to the cell wall was constructed and compounds inhibiting this process were discovered. Further, genes conferring resistance to the above compounds were identified and methods of screening for compounds that inhibit the activity of the proteins encoded by these genes were developed. Therefore, through the novel compounds, the present invention showed that antifungal agents having a novel mechanism, i.e. inhibiting the process that transports GPI-anchored proteins to the cell wall, could be achieved. | 2009-04-16 |
20090098637 | Circulation of algal broth by thermally-induced convection - The present invention provides a method of circulating algae in growing containers using thermally-induced convection techniques. In particular, a method of growing algae by providing a thermal gradient in algae containing medium is disclosed. | 2009-04-16 |
20090098638 | INCREASED FIBER HYDROLYSIS BY PROTEASE ADDITION - Novel fiber processing methods and the products obtained therefrom are disclosed. Methods may include thermochemical and/or enzymatic hydrolysis of fiber feedstocks including distillers' dried grains, distillers' dried grains with solubles, soyhull, miscanthus and switchgrass. Enzymatic hydrolysis includes hydrolysis with cellulase, hemicellulase, and protease. | 2009-04-16 |
20090098639 | APPARATUS FOR EXECUTION OF TREATMENT OPERATIONS IN CONNECTION WITH COLOURING OF TISSUE SPECIMENS ON OBJECT GLASSES - An apparatus for automatic execution of different treatment operations in connection with staining of tissue specimens on microscope slides, wherein the apparatus ( | 2009-04-16 |
20090098640 | METHOD AND APPARATUS FOR PREPARING CELLS FOR MICROTOME SECTIONING AND ARCHIVING NUCLEIC ACIDS AND PROTEINS - A method and apparatus for embedding cells that utilizes a flow-through embedding technique maximizes the efficiency of extractions and decreases time for embedding the cell fragments, minimizes cell loss, and automatically positions cell samples at the position in which a microtome blade will section them. The apparatus includes a cell flow pathway defined by an inflow tube for delivering cell fragments from a cell sample to a sample port. The sample port is in fluid communication with a tissue cassette having attached thereto a filter. The cell flow pathway is in communication with a reagent flow pathway for delivering the reagents through the sample port to the cassette. The apparatus is configured such that the application of pressure directs the cell fragments from the cell sample through the cell flow pathway, and effects delivery of the reagents through the reagent flow pathway. The apparatus produces an embedded cell block having concentrated cells near the plane of the block to be sectioned in a quick and efficient manner. | 2009-04-16 |
20090098641 | Incubator humidity control - An incubator | 2009-04-16 |
20090098642 | Incubator - An incubator including a temperature-controlled room adjusted to a predetermined environment condition for culturing a sample of an incubation container at inside of the temperature-controlled room, the incubator including a shifting mechanism for moving a position of the incubation container at inside of the temperature-controlled room by a motor, a temperature adjusting section for adjusting a temperature at inside of the temperature-controlled room, an operating information generating section for generating operating information with regard to a position of operating and a time period of operating the motor prior to operating the motor, an estimated variation outputting section for outputting an estimation variation of a temperature state by operating the motor based on the operating information, and a controlling section for controlling the temperature adjusting section to cancel a temperature change of an amount of the estimated variation in synchronism with operating the motor. | 2009-04-16 |
20090098643 | MULTILAYER CIRCUIT DEVICES AND MANUFACTURING METHODS USING ELECTROPLATED SACRIFICIAL STRUCTURES - A multilayer circuit includes a dielectric base substrate, conductors formed on the base substrate and a vacuum deposited dielectric thin film formed over the conductors and the base substrate. The vacuum deposited dielectric thin film is patterned using sacrificial structures formed by electroplating techniques. Substrates formed in this manner enable significant increases in circuit pattern miniaturization, circuit pattern reliability, interconnect density and significant reduction of over-all substrate thickness. | 2009-04-16 |
20090098644 | DIAGNOSTIC TEST UNIT WITH A CONTAINER FOR TEST CARRIERS - The invention concerns a diagnostic test unit for analysing a body fluid comprising a test carrier (test tape | 2009-04-16 |
20090098645 | Cell culture article and methods thereof - Disclosed is a cell culture article including: a substrate; a tie-layer attached to at least the substrate; and a bio-compatible layer attached to at least the tie layer, the bio-compatible layer having been obtained from surface oxidation of a polymer layer. Also disclosed are methods for making the cell culture article and methods for performing an assay of a ligand with the article. | 2009-04-16 |
20090098646 | Staining and Sticking System - The staining and sticking system is composed of a staining device and a sticking device, which is provided separately from the staining device, is capable of lightening the staining and sticking work and can be downsized. The staining and sticking system comprises the staining device | 2009-04-16 |
20090098647 | Recombinant antigens for the detection of coxiella burnetii - The invention relates to a method for the detection of prior exposure to | 2009-04-16 |
20090098648 | HIGH-TITER RETROVIRAL PACKAGING CELLS - The present invention relates to non-replicative recombinant retrovirus packaging cells able to grow in suspension in a serum-free medium. In particular, the present invention relates to a human embryonic 293SF-based cell line stably expressing gag and pol gene products from the murine Moloney leukemia virus (MLV) and either the feline RD114 env gene, the gibbon ape leukemia virus (GLV) env gene, or the amphotropic 4070Aenv gene. This particular combination allows the production of high titer of non-replicative retrovirus pseudotyped and prevents the recombination of plasmids. The recombinant retroviruses produced from these cells are safer and easier to produce for clinical use in gene therapy. | 2009-04-16 |
20090098649 | NEWLY ESTABLISHED CELL LINES FROM MARUCA VITRATA - The present invention relates to | 2009-04-16 |
20090098650 | COMPOSITIONS FOR THE IN VITRO DERIVATION AND CULTURE OF EMBRYONIC STEM (ES) CELL LINES WITH GERMLINE TRANSMISSION CAPABILITY AND FOR THE CULTURE OF ADULT STEM CELLS - The present invention describes novel compositions for deriving, maintaining and growing pluripotent and germ-line competent mammalian embryonic stem cells. The compositions of this invention refer to compositions comprising a 1) conditioned medium of a cell line expressing limited amounts of Leukemia Inhibitory Factor (LIF), 2) conditioned medium from a cell line transfected with mammalian LIF and 3) a medium supplemented with recombinant rabbit LIF. The present invention describes novel compositions for deriving, maintaining and growing adult human stem cells and/or adult early progenitor cells, preferably under stroma-free conditions and without added LIF and/or cytokines or growth factors. The media of the present invention are used for the generation of pluripotent and germ-line competent embryonic stem cells of mammals of which these cells were not obtained up to now. The media of the present invention are used for the generation of adult human stem cells and/or adult early progenitor cells. The present invention is also directed to a novel rabbit LIF and to nucleotides encoding the rabbit LIF and methods for the expression of recombinant rabbit LIF in the | 2009-04-16 |
20090098651 | CARDIOMYOCYTE CULTURE SUPPORT - It is an objective of this invention to provide a cardiomyocyte culture support used for obtaining cardiomyocytes having a controlled orientation of beating that are thus available for myocardial regenerative therapy, and to provide a method for producing the same. | 2009-04-16 |
20090098652 | SELF ASSEMBLING PEPTIDE SYSTEMS AND METHODS - The present invention provides a self-assembling peptide system which utilizes a bioactive sequence which enhances transfection efficiency. In particular, the present invention provides compositions and methods for transfecting aggregates of cells at a higher efficiency. | 2009-04-16 |
20090098653 | Transgenomic Mitochondria, Transmitochondrial Cells and Organisms, and Methods of Making and Using - The invention provides transgenomic mitochondria, transmitochondrial cells and organisms, and the materials and methods for making such mitochondria, cells, and organisms. | 2009-04-16 |
20090098654 | Selectable genetic marker for use in pasteurellaceae species - The present invention provides a nucleic acid encoding nicotinamide phosphoribosyltransferase (NadV) from a V-factor independent bacterium and provides methods for using the gene as a selection marker for constructing recombinant bacteria from V-factor dependent bacteria. The method is an improvement over methods which rely on nucleic acids which confer antibiotic resistance for constructing recombinant bacteria. Methods for constructing attenuated recombinant | 2009-04-16 |
20090098655 | Detection Apparatus and Methods - A chemical cell ( | 2009-04-16 |
20090098656 | Mercury Ionic Gas Standard Generator For A Continuous Emissions Monitoring System - A mercury ionic gas standard generator for use in the continuous emissions monitoring of exhaust flue gas streams is disclosed. More specifically, the mercury ionic gas standard generator uses a reservoir being coated with an inert silicon-based coating for transporting a volume of an aqueous ionic mercury solution to a liquid mass flow controller and vaporizer. | 2009-04-16 |
20090098657 | METHOD AND ASSEMBLY FOR DETERMINING THE TEMPERATURE OF A TEST SENSOR - An assembly determines an analyte concentration in a sample of body fluid. The assembly includes a test sensor having a fluid-receiving area for receiving a sample of body fluid, where the fluid-receiving area contains a reagent that produces a measurable reaction with an analyte in the sample. The assembly also includes a meter having a port or opening configured to receive the test sensor; a measurement system configured to determine a measurement of the reaction between the reagent and the analyte; and a temperature-measuring system configured to determine a measurement of the test-sensor temperature when the test sensor is received into the opening. The meter determines a concentration of the analyte in the sample according to the measurement of the reaction and the measurement of the test-sensor temperature. | 2009-04-16 |
20090098658 | Microchip and Method of Using the Same - A microchip includes fluid circuits therein, formed by uniting together at least a first substrate that is a transparent substrate and a second substrate having grooves provided at the substrate surface and/or through holes penetrating in a thickness direction. The fluid circuits include a liquid reagent receptacle unit to store a liquid reagent, a quantification unit to quantify the liquid reagent or specimen, and an overflow liquid storage unit connected to the quantification unit to store the liquid reagent or specimen overflowing from the quantification unit during quantification. There is also provided a method of using the microchip. | 2009-04-16 |
20090098659 | METHOD OF PATTERNING PARTICLES ON AN ARBITRARY SUBSTRATE AND CONDUCTING A MICROFLUIDIC INVASION ASSAY - A method is provided for sequentially patterning different particle populations on spatially defined regions in microfluidic device. The microfluidic device has a channel and a plurality of access ports therein. Each access port has an input and an output communicating with the channel. The method includes the step of depositing a drop of a first suspension on the input of a first access port. The first suspension includes a plurality of particles. A drop of a second suspension is deposited on the input of a second access port. The second suspension includes a plurality of particles. The particles in the first and second suspensions settle onto and are patterned along corresponding spaced portions of the channel. | 2009-04-16 |
20090098660 | Method for the Purification of Antibodies - A method for the purification of immunoglobulins by ion exchange chromatography is described. The chromatographic method uses a weak ion exchange resin and a single step elution process for the purification of an immunoglobulin. Additionally a method for the determination of the salt concentration for the single step elution of an immunoglobulin from an ion exchange resin is described. | 2009-04-16 |
20090098661 | Method for Determination of Sample Using Agglutination Reaction of Immunological Microparticle, and Kit for the Determination - A method for determining an analyte in a sample, includes the steps of: (a) mixing the analyte and a first specific binding substance, the first specific binding substance being a substance that can specifically bind to the analyte; (b) adding microparticles having a second specific binding substance bound thereto to a mixture obtained in the step (a) and mixing therewith, the second specific binding substance being a substance that can specifically bind to the first specific binding substance; and (c) determining an agglutination reaction of the microparticles in a mixture obtained in the step (b). | 2009-04-16 |
20090098662 | DETERMINING THE PRESENCE OR AMOUNT OF A METAL-LABELLED SPECIES - A method for determining the presence or amount of a metal-labelled species in a sample may include causing the metal of the metal-labelled species in the sample to form a soluble electrochemically-active complex which is stable relative to moieties present or potentially present in the sample which will form an insoluble and/or electrochemically-inactive complex with the metal, and electrochemically measuring the formed complex to provide an indication of the presence or amount of the metal-labelled species. | 2009-04-16 |
20090098663 | NOVEL WATER-SOLUBLE NANOCRYSTALS COMPRISING A POLYMERIC COATING REAGENT, AND METHODS OF PREPARING THE SAME - Disclosed is a water soluble nanocrystal comprising a nanocrystal core comprising at least one metal M1 selected from an element of main group II, subgroup VIIA, subgroup VIIIA, subgroup IB, subgroup IIB, main group III or main group IV of the periodic system of the elements (PSE), at least one element A selected from main group V or main group VI of the PSE, a capping reagent attached to the surface of the core of the nanocrystal, and a water soluble polymer covalently coupled with the capping reagent to form a water soluble polymer shell over the nanocrystal core. Also disclosed are compositions comprising such nanocrystals and uses of such nanocrystals. | 2009-04-16 |
20090098664 | FERROELECTRIC THIN FILM DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a method of manufacturing a ferroelectric thin film device, and, more particularly, to a method of manufacturing a ferroelectric thin film device having high crystallinity, good surface roughness and high deposition efficiency through on-axis type sputtering, and to a ferroelectric thin film device manufactured using the method. The method of manufacturing a ferroelectric thin film device includes: depositing an SrRuO | 2009-04-16 |
20090098665 | METHODOLOGY OF IMPLEMENTING ULTRA HIGH TEMPERATURE (UHT) ANNEAL IN FABRICATING DEVICES THAT CONTAIN SIGE - Exemplary embodiments provide methods for implementing an ultra-high temperature (UHT) anneal on silicon germanium (SiGe) semiconductor materials by co-implanting carbon into the SiGe material prior to the UHT anneal. Specifically, the carbon implantation can be employed to increase the melting point of the SiGe material such that an ultra high temperature can be used for the subsequent anneal process. Wafer warpage can then be reduced during the UHT anneal process and potential lithographic mis-alignment for subsequent processes can be reduced. Exemplary embodiments further provide an inline control method, wherein the wafer warpage can be measured to determine the litho-mis-alignment and thus to control the fabrication process. In various embodiments, the disclosed methods can be employed for the fabrication of source/drain extension regions and/or source/drain regions of transistor devices, and/or for the fabrication of base regions of bipolar transistors. | 2009-04-16 |
20090098666 | CHIP PACKAGE ASSEMBLY USING CHIP HEAT TO CURE AND VERIFY - Methods of assembling a chip package are disclosed that employ heat from test pattern operation of the chip to cure a thermal interface material. The methods may also simultaneously verify thermal performance of the package using the heat from test pattern operation. Further, the heat may be used to cure the sealing material and/or underfill material, where they are used. | 2009-04-16 |
20090098667 | Method For Picking Up Semiconductor Chips From A Wafer Table And Method For Mounting Semiconductor Chips On A Substrate - The invention relates to a method for picking up semiconductor chips from a wafer table and, optionally, their mounting on a substrate by means of a pick-and-place system. The position and orientation of the semiconductor chip to be mounted next are determined by means of a first camera and made available in the form of positional data relating to a first system of coordinates. The position and orientation of the substrate place on which the semiconductor chip will be mounted are determined by means of a second camera and made available in the form of positional data relating to a second system of coordinates. The conversion of coordinates of the first or second system of coordinates into coordinates of motion of the pick-and-place system occurs by means of two fixed mapping functions and two changeable correction vectors. The correction vectors are readjusted on the occurrence of a predetermined event. | 2009-04-16 |
20090098668 | Method and Apparatus to Facilitate Testing of Printed Semiconductor Devices - A printing platform receives ( | 2009-04-16 |
20090098669 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS - A semiconductor device manufacturing method and a semiconductor device manufacturing apparatus which enable to detect an etching end-point with high accuracy are provided. In etching of a lower layer formed on a semiconductor wafer using a mask which comprises a plurality of patterns extending in a predetermined direction (line-and-space patterns) and contains at least one of a metal layer and an electrically-conductive metal compound layer, the surface of the semiconductor wafer is irradiated with inspection light, the etching is performed while monitoring the intensity of the polarized light component perpendicular to the predetermined extending direction of the line-and-space patterns and the etching is terminated at the time the intensity of the polarized light component reaches a reflected light intensity corresponding to a desired remaining thickness of the lower layer. | 2009-04-16 |
20090098670 | SEMICONDUCTOR DEVICE FOR MONITORING CURRENT CHARACTERISTIC AND MONITORING METHOD FOR CURRENT CHARACTERISTIC OF SEMICONDUCTOR DEVICE - A method for monitoring current characteristics of a semiconductor device includes forming an isolation layer and a well area over a substrate, and then forming a P+ area and an N+ area spaced apart by the isolation layer to define active areas, and then forming a gate oxide layer over the substrate including the P+ area and the N+ area, and then forming a polysilicon layer over one of the N+ area and the P+ area, and then connecting a electronic measuring probe to one of the N+ area and the P+ area and connecting a power terminal to the polysilicon layer, and then measuring the current characteristics of the semiconductor device using the polysilicon layer as a power pad and one of the N+ area and the P+ area as a pad. | 2009-04-16 |
20090098671 | Nanotube assembly including protective layer and method for making the same - Nanotube assemblies and methods for manufacturing the same, including one or more protective layers. A nanotube assembly may include a substrate, a nanotube array, formed on the substrate, and a protective layer, formed on a first area of the substrate where the nanotube array is not, the protective layer reducing the formation of nanocones, and promoting the formation of nanotubes, which make up the nanotube array. | 2009-04-16 |
20090098672 | Method for making a heat dissipating device for LED installation - A method for making a heat dissipating device for LED installation, comprising the steps of a) preparing a thermal member having a metal surface, b) covering at least a part of the metal surface of the thermal member with a electrically insulative thermal conductivity layer, and c) providing multiple conducting layers at the electrically insulative thermal conductive layer for the installation of LED (light emitting diode) chips. | 2009-04-16 |
20090098673 | THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A TFT array panel-including a substrate, a gate line having a gate electrode, a gate insulating layer formed on the gate line, a data line having a source electrode and a drain electrode spaced apart from the source electrode, a passivation layer formed on the data line and the drain electrode, and a pixel electrode connected to the drain electrode is provided. The TFT array panel further includes a protection layer including Si under at least one of the gate insulating layer and the passivation layer to enhance reliability. | 2009-04-16 |
20090098674 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To realize high performance and low power consumption of a semiconductor device by controlling electric characteristics of a transistor in accordance with a required function. Further, to manufacture such a semiconductor device with high yield and high productivity without complicating a manufacturing process. An impurity element imparting one conductivity type is added to a semiconductor substrate in order to control the threshold voltage of a transistor included in the semiconductor device, before separating a semiconductor layer of the transistor from the semiconductor substrate and transferring the semiconductor layer to a supporting substrate that is a substrate having an insulating surface. | 2009-04-16 |
20090098675 | Method for manufacturing semiconductor light-emitting device - A method of manufacturing a semiconductor light-emitting device includes steps of forming a vertical cavity structure including a layer to be oxidized on a semiconductor substrate, and then forming a circular groove having a depth which penetrates at least the layer to be oxidized from an upper surface of the vertical cavity structure, thereby forming a columnar mesa whose side face is surrounded by the groove, oxidizing the layer to be oxidized from the side face of the mesa, thereby forming a current confinement layer, and forming a mask layer covering at least a central region of the upper surface of the mesa and exposing at least an edge of the upper surface and the side face of the mesa to an external, and then etching at least the edge of the upper surface and the side face of the mesa by using the mask layer as a mask. | 2009-04-16 |
20090098676 | METHOD OF MANUFACTURING LIGHT EMITTING DIODE - A method of manufacturing a light emitting diode includes forming an active layer of a nitride semiconductor on a first conductive type of a nitride semiconductor layer, thermally treating the active layer at a first temperature, and forming a second conductive type of a nitride semiconductor layer on the active layer at a second temperature lower than the first temperature. | 2009-04-16 |
20090098677 | GROUP III-V NITRIDE-BASED SEMICONDUCTOR SUBSTRATE, GROUP III-V NITRIDE-BASED DEVICE AND METHOD OF FABRICATING THE SAME - A group III-V nitride-based semiconductor substrate has: a first layer made of GaN single crystal; and a second layer formed on the first layer, the second layer made of group III-V nitride-based semiconductor single crystal represented by Al | 2009-04-16 |
20090098678 | VACUUM JACKETED ELECTRODE FOR PHASE CHANGE MEMORY ELEMENT - A memory device having a vacuum jacket around the first electrode element for improved thermal isolation. The memory unit includes a first electrode element; a phase change memory element in contact with the first electrode element; a dielectric fill layer surrounding the phase change memory element and the first electrode element, wherein the dielectric layer is spaced from the first electrode element to define a chamber between the first electrode element and the dielectric fill layer; and wherein the phase change memory layer is sealed to the dielectric fill layer to define a thermal isolation jacket around the first electrode element. | 2009-04-16 |
20090098679 | CMOS SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE SAME AS WELL AS DRIVE METHOD OF CMOS SOLID-STATE IMAGING DEVICE - A CMOS solid-state imaging device configured to restrain the occurrence of white spots and dark current caused by pixel defects, and also to increase the saturation signal amount. | 2009-04-16 |
20090098680 | BACKPLANE STRUCTURES FOR SOLUTION PROCESSED ELECTRONIC DEVICES - There is provided a backplane for an organic electronic device. The backplane has a TFT substrate having a multiplicity of electrode structures thereon; a bank structure defining pixel areas over the electrode structures; and a thin layer of insulative inorganic material between the electrode structures and the bank structures. The bank structure is removed from and not in contact with the electrode structures by a distance of at least 0.1 microns. | 2009-04-16 |
20090098681 | PROCESS FOR MANUFACTURING A CBRAM MEMORY HAVING ENHANCED RELIABILITY - The invention relates to a process for manufacturing a plurality of CBRAM memories, each comprising a memory cell in a chalcogenide solid electrolyte, an anode, and a cathode, the process comprising implementing a sublayer of a high thermal conductivity material, higher than 1.3 W/m/K, which covers the set of contacts, then providing, on said sublayer, a triple layer comprising a chalcogenide layer, then an anodic layer, and a layer with second contacts ( | 2009-04-16 |
20090098682 | Method for Singulating a Group of Semiconductor Packages that Contain a Plastic Molded Body - A method for singulating a group of semiconductor packages containing a plastic molded body. The singulation of the semiconductor packages is effected along a predetermined separation area, wherein, in the predetermined separation area, a metallic layer extending over at least a partial section of the predetermined separation area has to be cut through in addition to a plastic layer formed of a material of the molded body. The method includes the steps of: making a groove into the predetermined separation area of the semiconductor packages by laser engraving, wherein at least a part of the metallic layer extending in the predetermined singulation area is removed, and subsequent separation of the semiconductor packages by mechanical sawing cut along the predetermined separation area. | 2009-04-16 |
20090098683 | METHOD FOR CUTTING SOLID-STATE IMAGE PICKUP DEVICE - A method for cutting a solid-state image pickup device with high accuracy and high quality is provided which does not cause any chipping and prevents damages to a wafer surface. A temporary bonding agent is coated to a back surface of a glass cover plate which is opposite to the surface having a spacer, and a transparent protective wafer having a surface to which an adhesive sheet having a reducible adhesive strength is attached is adhered to the surface of the glass cover plate to which the temporary bonding agent is coated, with the adhesive sheet facing to the glass cover plate surface. The adhered glass cover plate and protective wafer are cut from the surface of the glass cover plate to the temporary bonding agent. After a CCD wafer is bonded to the cut glass cover plate, the protective wafer, the adhesive sheet, and the temporary bonding agent are peeled off, and the CCD wafer is cut to obtain individual chips. In this way, a cutting of a solid-state image pickup device with high accuracy and high quality is achieved without any damage to a wafer surface. | 2009-04-16 |
20090098684 | Method of Producing a Thin Semiconductor Chip - A method of fabricating a semiconductor chip includes the providing an adhesive layer on the outer area of the active surface of a device wafer and attaching a rigid body to the active surface by the adhesive layer. The device wafer is thinned by treating the passive surface of the device wafer. A first backing tape is connected to the passive surface of the device wafer. The outer portion of the rigid body is separated from the central portion of the rigid body and the outer portion of the device wafer is separated from the central portion of the device wafer. The central portion of the rigid body, the outer portion of the device wafer and the outer portion of the rigid body are removed from the first backing tape. The device wafer may be diced into semiconductor chips. | 2009-04-16 |
20090098685 | Low Cost Hermetically Sealed Package - Disclosed herein is a device package that comprises a device having a top substrate that is disposed on a supporting surface of a package substrate. A package frame contacts the top surface of the top substrate and top surface of the package substrate, and hermetically seals the device between the top surfaces of the top substrate and package substrate. The device can be a semiconductor device, a microstructure such as a microelectromechanical device, or other devices. | 2009-04-16 |
20090098686 | METHOD OF FORMING PREMOLDED LEAD FRAME - A method of forming a pre-molded lead frame having increased stand-offs includes the steps of attaching a first tape to a first side of the lead frame and a second tape to a second side of the lead frame. The taped lead frame is placed in a mold and a first flow of mold compound is initiated. The first flow of the mold compound fills a space between the first tape and an upper mold chase of the mold. A second flow of the mold compound then is initiated. The second flow of the mold compound fills the spaces between a die pad and leads of the lead frame. The first and second tapes then are removed from the lead frame. Improved stand-offs are provided because the first tape was depressed by the first flow of the mold compound. | 2009-04-16 |
20090098687 | Integrated circuit package including wire bonds - It has been found that integrated packages having dies with at least 10 bonding pads separated by a pitch of 65 μm or less are susceptible to corrosion upon wire bonding to these pads and subsequent encapsulation in a passivating material. In particular, crevices are potentially formed between the bonding wire and bonding pad that are not passivated and that promote corrosion. Avoidance of crevice formation through, for example, appropriately choosing the bonding pad and wire configuration substantially avoids such corrosion. | 2009-04-16 |
20090098688 | IMPRINT METHOD, CHIP PRODUCTION PROCESS, AND IMPRINT APPARATUS - An imprint method is constituted by a step of curing a resin material formed on a substrate in a state in which an imprint pattern of a mold is in contact or proximity with the resin material, and a step of parting the mold from the cured resin material. The parting is effected while irradiating an entire area in which the imprint pattern of the mold is formed and the cured resin material with an electromagnetic wave for ionizing gaseous molecules in an atmosphere in which the mold and the cured resin material are placed. | 2009-04-16 |
20090098689 | ELECTRICAL FUSE AND METHOD OF MAKING - A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a substrate, forming a trench feature in the substrate, depositing fuse material in the trench feature, depositing compressive stress liner material over the fuse material, and patterning the compressive stress liner material. | 2009-04-16 |
20090098690 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To realize high 2 performance and low power consumption of a semiconductor device by controlling electric characteristics of a transistor in accordance with a required function. Further, to manufacture such a semiconductor device with high yield and high productivity without complicating a manufacturing process. An impurity element imparting one conductivity type is added to a first semiconductor wafer in order to control the threshold voltage of a transistor included in the semiconductor device, before separating a single crystal semiconductor layer used as a channel formation region of the transistor from the first semiconductor wafer and transferring the single crystal semiconductor layer to a second semiconductor wafer. | 2009-04-16 |
20090098691 | MANUFACTURING PROCESS OF THIN FILM TRANSISTOR - A thin film transistor includes a gate, a gate insulator layer, a channel layer, a source, a drain, and an ohmic contact layer. The gate insulator layer covers the gate; the channel layer is disposed on the gate insulator layer above the gate; the source and the drain are disposed on the channel layer; the ohmic contact layer is disposed between the channel layer and the source and drain. The ohmic contact layer is constituted by a number of film layers. As mentioned above, the thin film transistor has an ohmic contact layer constituted by a number of film layers. When the thin film transistor is turned off, the current leakage thereof is lowered than that of a conventional thin film transistor. | 2009-04-16 |
20090098692 | Method for Fabricating a Semiconductor Gate Structure - A method of making a semiconductor device is disclosed. A mask if formed over a first and a second region of a semiconductor body, and a vertical diffusion barrier is formed in a region between the first and second regions. A mask is then formed over the second region and the first region is left unmasked. The semiconductor body is exposed to a dopant, so that the first region is doped and the second region is blocked from the dopant by the mask and by the vertical diffusion barrier. | 2009-04-16 |
20090098693 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: forming a first region and a second region at a main surface of a semiconductor substrate; forming a gate insulating film containing Hf or Zr and oxygen on the first region and the second region; forming a first metallic film on the gate insulating film; forming a second metallic film on the first metallic film; removing a portion of the second metallic film; forming a third metallic film on the second metallic film and a portion of the first metallic film exposed by removing the portion of the second metallic film; and thermally treating so that constituent elements of the second metallic film is diffused into the gate insulating film via the first metallic film. | 2009-04-16 |
20090098694 | CD GATE BIAS REDUCTION AND DIFFERENTIAL N+ POLY DOPING FOR CMOS CIRCUITS - A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of polysilicon comprising gates. A first pattern is used to protect a plurality of PMOS devices and a first n-type implant is performed to dope the gates and source/drain regions for a plurality of NMOS devices. A second pattern is used to protect the PMOS devices and the sources/drains and gates for a portion of the plurality of NMOS devices and a second n-type implant is performed to dope the gates of the other NMOS devices. | 2009-04-16 |
20090098695 | DIFFERENTIAL OFFSET SPACER - A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted. The fabrication of the integrated circuit is then completed. | 2009-04-16 |
20090098696 | Fabrication Process of a Semiconductor Device Having a Capacitor - A method of manufacturing a semiconductor device includes forming a first trench in a capacitor device region of a semiconductor substrate, forming a capacitor insulation film over a sidewall surface of the first trench, forming a semiconductor film to cover the first trench, a resistor device region of the semiconductor substrate and a logic device region of the semiconductor substrate, introducing a first impurity element into the semiconductor film formed over the first trench, patterning the semiconductor film to form a top electrode in the capacitor device region, a resistor in the resistor device region and a gate electrode in the logic device region, annealing the semiconductor substrate, and introducing a second impurity element in the resistor. | 2009-04-16 |
20090098697 | Ferroelectric capacitor and ferroelectric memory with Ir-Ru alloy electrode and method of manufacturing the same - A ferroelectric capacitor comprises a first electrode comprising an alloy of Ir and Ru, a ferroelectric layer disposed on the first electrode, and a second electrode disposed on the ferroelectric layer. A ferroelectric memory comprises a substrate and a plurality of memory cells arranged on the substrate. Each memory cell comprises a first electrode comprising an alloy of Ir and Ru, a ferroelectric layer disposed on the first electrode, and a second electrode disposed on the ferroelectric layer. | 2009-04-16 |
20090098698 | MEMORY DEVICE AND FABRICATION THEREOF - A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar dielectric layer is lower than top surface level of the filling electrode layer. A vertical transistor is disposed at the upper portion of the trench, comprising a doped region disposed in a portion of the trench adjacent to the trench. A buried conductive layer interposed between the vertical transistor and the trench capacitor, wherein the cross section of the buried conductive layer is H shaped. The trench capacitor and the doping region of vertical transistor are electrically connected through the H shaped buried conductive layer. | 2009-04-16 |
20090098699 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device. In one example embodiment of the present invention, a method for manufacturing a semiconductor device includes various steps. First, a gate pattern is formed on a substrate. Next, a first oxide layer is formed on the gate pattern. Then, a second oxide layer, a first silicon nitride layer, and a second silicon nitride layer are sequentially formed over the substrate and the first oxide layer. Next, a first etching process is performed to remove horizontal portions of the first and second silicon nitride layers. Then, source/drain regions are formed in the substrate. Next, the vertical portions first and second silicon nitride layers are removed. Then, a third silicon nitride layer is formed over the second oxide layer. Finally, a second etching process is performed to remove horizontal portions of the third silicon nitride layer and the second oxide layer. | 2009-04-16 |
20090098700 | METHOD OF FABRICATING A NON-VOLATILE MEMORY DEVICE - A method of fabricating a non-volatile memory device prevents the threshold voltage of a program-inhibited cell from rising by preventing hot carriers, generated in a semiconductor substrate near a select line, from being injected into a floating gate of the program-inhibited cell. The program-inhibited cell shares a word line adjacent to the select line such that a trench is formed in the semiconductor substrate between the select line and the adjacent word line to increase a distance between the select line and the word line. | 2009-04-16 |
20090098701 | Method of manufacturing an integrated circuit - The present invention provides a method of manufacturing an integrated circuit comprising the steps of: providing a semiconductor substrate, etching at least one trench into a surface of said semiconductor substrate, performing an ion implantation step, wherein a direction of said ion implantation step is parallel to a vertical centre line of said trench, and performing a single oxidation step to form a first oxide layer with a first layer thickness covering a bottom of said at least one trench and a second oxide layer with a second layer thickness covering the sidewalls of said at least one trench, wherein said first layer thickness differs from said second layer thickness. | 2009-04-16 |
20090098702 | Method to Form CMOS Circuits Using Optimized Sidewalls - A method of forming reduced width STI field oxide elements using sidewall spacers on the isolation hardmask to reduce the STI trench width is disclosed. The isolation sidewall spacers are formed by depositing a conformal layer of spacer material on the isolation hardmask and performing an anisotropic etch. The isolation sidewall spacers reduce the exposed substrate width during the subsequent STI trench etch process, leading to a reduced STI trench width. A method of forming the isolation sidewall spacers of a material that is easily removed from the isolation hardmask to provide an exposed shoulder width on the substrate defined by the sidewall thickness is also disclosed. | 2009-04-16 |
20090098703 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING RESISTORS - A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region are provided. A first semiconductor pattern and a second semiconductor pattern are sequentially stacked in the first hole. A first resistor having the same crystalline structure as the second semiconductor pattern is provided in the second hole. | 2009-04-16 |
20090098704 | METHOD FOR MANUFACTURING SOI SUBSTRATE - A method is demonstrated to manufacture SOI substrates with high throughput while resources can be effectively used. The present invention is characterized by the feature in which the following process A and process B are repeated. The process A includes irradiation of a surface of a semiconductor wafer with cluster ions to form a separation layer in the semiconductor wafer. The semiconductor wafer and a substrate having an insulating surface are then overlapped with each other and bonded, which is followed by thermal treatment to separate the semiconductor wafer at or around the separation layer. A separation wafer and an SOI substrate which has a crystalline semiconductor layer over the substrate having the insulating surface are simultaneously obtained by the process A. The process B includes treatment of the separation wafer for reusing, which allows the separation wafer to be successively subjected to the process A. | 2009-04-16 |
20090098705 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device according to one embodiment includes: forming a gate electrode by shaping a semiconductor film formed above a semiconductor substrate; forming a protective film on a side face of the gate electrode by plasma discharge of a first gas or a second gas, the first gas containing at least one of HBr, Cl | 2009-04-16 |
20090098706 | Methods of Forming Integrated Circuit Devices Having Ion-Cured Electrically Insulating Layers Therein - Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×10 | 2009-04-16 |
20090098707 | Method for producing bonded wafer - In a method for producing a bonded wafer by bonding a wafer for active layer to wafer for support layer and then thinning the wafer for active layer, a terrace grinding for forming a terrace portion is carried out prior to a step of exposing the oxygen ion implanted layer to thereby leave an oxide film on a terrace portion of the wafer for support layer. | 2009-04-16 |
20090098708 | METHOD FOR PRODUCING A THIN CHIP COMPRISING AN INTEGRATED CIRCUIT - In a method for producing a very thin chip including an integrated circuit, a circuit structure is produced in a defined section of a semiconductor wafer. The defined wafer section is subsequently released from the semiconductor wafer. For this purpose, the wafer section is firstly freed such that it is held only via local web-like connections on the remaining semiconductor wafer, which web-like connections are arranged at a lateral periphery of the wafer section. The web-like connections are subsequently severed. | 2009-04-16 |
20090098709 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a method of manufacturing a semiconductor device, which prevents impurities from entering an SOI substrate. A source gas including one or plural kinds selected from a hydrogen gas, a helium gas, or halogen gas are excited to generate ions, and the ions are added to a bonding substrate to thereby form a fragile layer in the bonding substrate. Then, a region of the bonding substrate that is on and near the surface thereof, i.e., a region ranging from a shallower position than the fragile layer to the surface is removed by etching, polishing, or the like. Next, after attaching the bonding substrate to a base substrate, the bonding substrate is separated at the fragile layer to thereby form a semiconductor film over the base substrate. After forming the semiconductor film over the base substrate, a semiconductor element is formed using the semiconductor film. | 2009-04-16 |
20090098710 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An SOI substrate having a single crystal semiconductor layer with high surface planarity is manufactured. A semiconductor substrate is doped with hydrogen, whereby a damaged region which contains large quantity of hydrogen is formed. After a single crystal semiconductor substrate and a supporting substrate are bonded together, the semiconductor substrate is heated, whereby the single crystal semiconductor substrate is separated in the damaged region. While a heated high-purity nitrogen gas is sprayed on a separation plane of the single crystal semiconductor layer separated from the single crystal semiconductor substrate, laser beam irradiation is performed. By irradiation with a laser beam, the single crystal semiconductor layer is melted, whereby planarity of the surface of the single crystal semiconductor layer is improved and re-single-crystallization is performed. | 2009-04-16 |
20090098711 | MICROMACHINE DEVICE PROCESSING METHOD - A micromachine device processing method for dividing a functional wafer, which has micromachine devices formed in a plurality of regions demarcated by streets formed in a lattice pattern on a face of the functional wafer, along the streets into the individual micromachine devices, each micromachine device having a moving portion and an electrode, comprising: a cap wafer groove forming step of forming dividing grooves, which have a depth corresponding to a finished thickness of a cap wafer for protecting the face of the functional wafer, along regions in one surface of the cap wafer which correspond to areas of the electrodes of the micromachine devices; a cap wafer joining step of joining the one surface of the cap wafer subjected to the cap wafer groove forming step to the face of the functional wafer at peripheries of the moving portions; a cap wafer grinding step of grinding the other surface of the cap wafer joined to the face of the functional wafer to expose the dividing grooves to the outside; and a cutting step of cutting the functional wafer and the cap wafer subjected to the cap wafer grinding step along the streets. | 2009-04-16 |
20090098712 | SUBSTRATE DIVIDING METHOD - A method of dividing a substrate | 2009-04-16 |
20090098713 | OBJECT CUTTING METHOD - An object cutting method which can reliably remove particles remaining on cut sections of chips is provided. An expandable tape | 2009-04-16 |
20090098714 | Method for forming III-nitrides semiconductor epilayer on the semiconductor substrate - GaN layer on semiconductor substrate is grown by using GaN nanorod buffer layer. Firstly, semiconductor substrate is cleaned and thermally degassed to remove the contaminant in the growth chamber. After the above step, the GaN nanorods layer is grown under the N-rich condition. Then, GaN epilayer is overgrown on the GaN nanorods layer under the Ga-rich condition for forming Group of III-Nitrides semiconductor layer on the semiconductor substrate. | 2009-04-16 |
20090098715 | Process for manufacturing silicon wafers for solar cell - A process for manufacturing silicon wafers for solar cell is disclosed wherein one first breaks the refined metallurgical silicon, then remove visible impurities, then performs chemical cleaning and then places the silicon into a crystal growing furnace. Gallium or gallium phosphide is added to the silicon, where the concentration of gallium atoms should be in the range from 5 ppma to 14 ppma. Crystal growth is initiated, followed by subdivision and inspection after the crystal rods or crystal bars have grown, yielding the desired silicon wafers. With this solution, the refined metallurgical silicon can be used for manufacturing of solar cells, so as to reduce the cost of materials, and it is conducive to the universal application of silicon solar cells. | 2009-04-16 |
20090098716 | METHOD FOR MAKING A SELF-CONVERGED MEMORY MATERIAL ELEMENT FOR MEMORY CELL - A self-converged memory material element is created during the manufacture of a memory cell comprising a base layer, with a bottom electrode, and an upper layer having a third, planarization stop layer over the base layer, a second layer over the third layer, and the first layer over the second layer. A keyhole opening is formed through the upper layer to expose the bottom electrode. The first layer has an overhanging portion extending into the opening. A dielectric material is deposited into the keyhole opening so to create a self-converged void within the keyhole opening. An anisotropic etch forms a sidewall of the dielectric material in the keyhole opening with an electrode hole aligned with the void and exposing the bottom electrode. A memory material is deposited into the electrode hole in contact with the bottom electrode and is planarized down to the third layer to create the memory material element. | 2009-04-16 |
20090098717 | CO-SPUTTER DEPOSITION OF METAL-DOPED CHALCOGENIDES - The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (Ge | 2009-04-16 |
20090098718 | Multiple mask and method for producing differently doped regions - In order to produce doping regions (DG) in a substrate (S) having different dopings with the aid of a single mask (DM) different mask regions are provided which have elongated mask openings (MO) having different orientations relative to the spatial direction of an oblique implantation. The substrate is rotated between the first and second oblique implantations, wherein during the first oblique implantation maximum and minimum shadings in the different mask regions are opposite one another and the conditions are precisely reversed during the second oblique implantation after the rotation of the substrate. | 2009-04-16 |
20090098719 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - An object of the invention is to provide a method for manufacturing a silicon carbide semiconductor device having constant characteristics with reduced variations in forward characteristics. The method for manufacturing the silicon carbide semiconductor device according to the invention includes the steps of: (a) preparing a silicon carbide substrate; (b) forming an epitaxial layer on a first main surface of the silicon carbide substrate; (c) forming a protective film on the epitaxial layer; (d) forming a first metal layer on a second main surface of the silicon carbide substrate; (e) applying heat treatment to the silicon carbide substrate at a predetermined temperature to form an ohmic junction between the first metal layer and the second main surface of the silicon carbide substrate; (f) removing the protective film; (g) forming a second metal layer on the epitaxial layer; and (h) applying heat treatment to the silicon carbide substrate at a temperature from 400° C. to 600° C. to form a Schottky junction of desired characteristics between the second metal layer and the epitaxial layer. | 2009-04-16 |
20090098720 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A manufacturing method of a semiconductor device of the present invention includes the steps of forming a first insulating film over a substrate, forming a semiconductor film over the first insulating film, oxidizing or nitriding the semiconductor film by conducting a plasma treatment to the semiconductor film under a condition of an electron density of 1×10 | 2009-04-16 |
20090098721 | METHOD OF FABRICATING A FLASH MEMORY - A method of fabricating a flash memory includes providing a semiconductor substrate with STIs and an active area between two adjacent STIs along a first direction; successively forming a floating-gate insulating layer, a conductive layer, a dielectric layer, a control gate, and a cap layer on the semiconductor substrate; forming spacers on the sidewalls of the cap layer and the control gate; removing the dielectric layer, the conductive layer, and the floating-gate insulating layer not covered by the spacers and the cap layer; performing a selective epitaxial growth process to form an epitaxial layer on the exposed semiconductor substrate in the active area; and forming a source in the epitaxial layer and the semiconductor substrate in the active area. | 2009-04-16 |
20090098722 | METHOD OF FORMING A SEMICONDUCTOR MEMORY DEVICE - A method of forming a semiconductor memory device includes forming a tunnel insulating layer on a semiconductor substrate, and forming a silicon layer, including metal material, on the tunnel insulating layer. Accordingly, an increase in the strain energy of the conductive layer may be prohibited and, therefore, the growth of grains constituting the conductive layer may be prevented. Furthermore, a threshold voltage distribution characteristic and electrical properties of a semiconductor memory device may be improved. | 2009-04-16 |
20090098723 | Method Of Forming Metallic Bump On I/O Pad - The method mainly contains the following steps. First, an UBM is formed on a top side of a semiconductor's I/O pad. An isolative layer and a metallic foil are sequentially arranged in this order on the UBM. Then, a via is formed to expose the top surface of the UBM. Subsequently, a thin metallic layer is formed in the via and a resist is formed on the metallic foil. Then, by using the metallic foil and the thin metallic layer as an electrode to conduct electrical current, a metallic bump is formed using electroplating in the via on the top side of the UBM. Finally, the resist and the metallic foil are removed and the formation of the metallic bump is completed. | 2009-04-16 |
20090098724 | Method Of Forming Metallic Bump And Seal For Semiconductor Device - The method mainly contains the following steps. First, an UBM is formed on a top side of a semiconductor's I/O pad. An isolative layer and a metallic foil are sequentially arranged in this order on the UBM. Then, a via is formed to expose the top surface of the UBM. Subsequently, a thin metallic layer is formed in the via and a resist is formed on the metallic foil. Then, by using the metallic foil and the thin metallic layer as an electrode to conduct electrical current, a metallic bump is formed using electroplating in the via on the top side of the UBM. Finally, the resist and the metallic foil are removed and the formation of the metallic bump is completed. Optionally coating on bump may be needed for certain chosen bump materials. | 2009-04-16 |