16th week of 2009 patent applcation highlights part 14 |
Patent application number | Title | Published |
20090096021 | SEMICONDUCTOR DEVICE HAVING DEEP TRENCH CHARGE COMPENSATION REGIONS AND METHOD - In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers. | 2009-04-16 |
20090096022 | LATERAL DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE - An exemplary lateral diffused metal oxide semiconductor device includes a first-type substrate, a gate oxide film disposed on the first-type substrate, a poly gate disposed on the gate oxide film, a first second-type slightly doped region formed in the first-type substrate and acting as a well, a first first-type highly doped region formed in the well and acting as a body, a first second-type highly doped region formed in the body and acting as a source, a second second-type highly doped region formed in the well and acting as a drain, a second first-type highly doped region formed in the body, and a first fist-type doped region formed in the body and is beneath the source. | 2009-04-16 |
20090096023 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device that eliminates the cause of increase in leakage current and therefore suppresses power increase in a highly integrated circuit by forming a shallow junction using a dopant-containing oxide film after etching a semiconductor substrate in source and drain regions. | 2009-04-16 |
20090096024 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a method for manufacturing a semiconductor device, a semiconductor film formed over an insulator is doped with an impurity element to a depth less than the thickness of the semiconductor film, thereby forming an impurity doped layer; a metal silicide layer is formed on the impurity doped layer; the metal silicide layer and the semiconductor film are etched to form a recessed portion; and a layer which is not doped with the impurity element and is located at the bottom of the recessed portion of the semiconductor film is thinned to make a channel formation region. Further, a gate electrode is formed in the recessed portion over the thinned non impurity doped layer, with an insulating film interposed therebetween. | 2009-04-16 |
20090096025 | Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer - Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed. | 2009-04-16 |
20090096026 | METHOD OF FABRICATING HIGH VOLTAGE FULLY DEPLETED SOI TRANSISTOR AND STRUCTURE THEREOF - A method of fabricating a high voltage fully depleted silicon-on-insulator (FD SOI) transistor, the FD SOI transistor having a structure including a region within a body on which a gate structure is disposed. The region includes a channel separating the source region and the drain region. Above the source region is disposed a carrier recombination element, which abuts the gate structure and is electrically connected to the region via the channel. The drain region is lightly doped and ballasted to increase breakdown voltage. The FD SOI may be fabricated by forming a body with a thin silicon layer disposed on a buried oxide (BOX). Alternatively, the body may be formed using a partially depleted (PD) SOI where the region formed therein has a reduced thickness in comparison to the overall thickness of the PD SOI. | 2009-04-16 |
20090096027 | Power Semiconductor Device - A power semiconductor device comprising a first group of power transistor cells arranged in a first area of the power semiconductor device and a second group of power transistor cells arranged in a second area of the power semiconductor device. The first group of power transistor cells has an overall cell density different from that of the second group of power transistor cells such that the first and second groups of power transistor cells have different charge carrier densities. | 2009-04-16 |
20090096028 | Transistor of the I-MOS Type Comprising Two Independent Gates and Method of Using Such a Transistor - The transistor comprises a source ( | 2009-04-16 |
20090096029 | Semiconductor Device and Manufacturing Method Thereof - Disclosed is a semiconductor device wherein the switching speed of a transistor is increased. Specifically disclosed is a semiconductor device comprising a semiconductor layer formed on a part of an insulating layer, a first transistor formed on a lateral face of the semiconductor layer and having a first gate insulating film, a first gate electrode and two first impurity layers forming a source and a drain, and a second transistor formed on another lateral face of the semiconductor layer and having a second gate insulating film, a second gate electrode and two second impurity layers forming a source and a drain. | 2009-04-16 |
20090096030 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device in which an insulating region surrounding an element region is provided in an end portion of a semiconductor region with a super junction structure. Since a depletion layer in the element region ends in the insulating region, the end portion of the element region is not formed in a curved surface shape. In other words, the depletion layer has no curved surface in which internal electric fields are concentrated. For this reason, there is no need to take a measure to cause the depletion layer to spread in a horizontal direction by proving a terminal region. Since the terminal region is unnecessary, a chip size can be reduced. Alternatively, an area of the element region can be expanded. | 2009-04-16 |
20090096031 | DIFFERENTIAL POLY DOPING AND CIRCUITS THEREFROM - A method of fabricating a CMOS integrated circuit and integrated circuits therefrom includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon including layer on the gate dielectric. A portion of the polysilicon layer is masked, and pre-gate etch implant of a first dopant type into an unmasked portion of the polysilicon layer is performed, wherein masked portions of the polysilicon layer are protected from the first dopant. The polysilicon layer is patterned to form a plurality of polysilicon gates and a plurality of polysilicon lines, wherein the masked portion includes at least one of the polysilicon lines which couple a polysilicon gate of a PMOS device to a polysilicon gate of an NMOS device. Fabrication of the integrated circuit is then completed, wherein the integrated circuit includes at least one first region formed in the masked portion lacking the first dopant in the polysilicon gates from the pre-gate etch implant and at least one second region formed in the unmasked portion having the first dopant in the polysilicon gates from the pre-gate etch implant. | 2009-04-16 |
20090096032 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes first and second active regions on a semiconductor substrate, separated by an element isolation region; a line-shaped electrode disposed from over the first to over the second active region via the element isolation region; first and second FETs including a gate insulating film on the first and second active regions, respectively, a gate electrode composed of the line-shaped electrode and a source/drain region. Parts of the line-shaped electrode over the first and second active regions are formed of different materials. The line-shaped electrode includes a diffusion restraining region having thickness in a direction perpendicular to the substrate thinner than that over the first and second active regions. The diffusion restraining region is over the element isolation region and spans the whole width of the line-shaped electrode in the gate length direction. | 2009-04-16 |
20090096033 | ISOLATION TRENCH WITH ROUNDED CORNERS FOR BiCMOS PROCESS - A semiconductor device comprising a first transistor device on or in a semiconductor substrate and a second transistor device on or in the substrate. The device further comprises an insulating trench located between the first transistor device and the second transistor device. At least one upper corner of the insulating trench is a rounded corner in a lateral plane of the substrate. | 2009-04-16 |
20090096034 | Partially and Fully Silicided Gate Stacks - Metal-oxide semiconductor (MOS) devices and techniques for the fabrication thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate; and at least one n-channel field effect transistor (NFET) having a gate stack over the substrate. The NFET gate stack comprises an NFET gate stack metal gate layer; a first NFET gate stack silicon layer over the NFET gate stack metal gate layer; a second NFET gate stack silicon layer over a side of the first NFET gate stack silicon layer opposite the NFET gate stack metal gate layer, wherein an interface is defined between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer; and an NFET gate stack silicide region that extends through the interface between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer. | 2009-04-16 |
20090096035 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - A method for manufacturing a semiconductor device has forming a first insulating film on a semiconductor substrate, forming an electrode layer on said first insulating film, etching said electrode layer, said first insulating film and said semiconductor substrate of a first predetermined region to form a trench, burying an element-isolating insulating film in said trench, forming a second insulating film on said element-isolating insulating film and above said electrode layer, etching said second insulating film, said electrode layer and said element-isolating insulating film of a second predetermined region to form a gate pattern and a dummy pattern, forming a third insulating film for covering said gate pattern and said dummy pattern, and planarizing said third insulating film using said second insulating film as a stopper. | 2009-04-16 |
20090096036 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided. | 2009-04-16 |
20090096037 | SEMICONDUCTOR DEVICE HAVING RECESSED FIELD REGION AND FABRICATION METHOD THEREOF - A semiconductor device including an active region formed on a semiconductor substrate, and a field region adjacent to the active region, which is able to increase a width of the active region through use of a field recess portion at one surface side of the field region. The field recess portion may be laterally adjacent to a portion of the active region, thereby resulting in an increase of a width of the active region. A gate insulating film and a gate electrode may be formed on the field region and the active region, the gate insulating film and the gate electrode being formed in the field recess portion. The width of the active region may be a channel width. | 2009-04-16 |
20090096038 | POWER MOSFET ARRAY - A power metal-oxide-semiconductor field-effect transistor (MOSFET) array structure is provided. The power MOSFET array is disposed under a gate pad, and space under the gate pad can be well used to increase device integration. When the array and the conventional power MOSFET array disposed under the source pad are connected to an array pair by using circuit connection region, the same gate pad and source pad can be shared, so as to achieve an objective of increasing device integration. | 2009-04-16 |
20090096039 | HIGH-VOLTAGE DEVICE AND MANUFACTURING METHOD OF TOP LAYER IN HIGH-VOLTAGE DEVICE - A high-voltage device including a first conductive type substrate, a gate, a second conductive type well, a second conductive type source region, a second conductive type drain region, conductive layers, and a first conductive type top layer. The gate is disposed on the substrate, and the well is disposed in the substrate at one side of the gate. The source region is disposed in the substrate at the other side of the gate. The drain region is disposed in the well of the substrate. The conductive layers are disposed on the substrate between the gate and the drain region. The top layer is disposed in the well of the substrate, and the well is below the conductive layers. One portion of the top layer near the gate has a thickness greater than that of the other portion of the top layer away from the gate. | 2009-04-16 |
20090096040 | Sensor geometry for improved package stress isolation - The sensor geometry for improved package stress isolation is disclosed. A counterbore on the backing plate improves stress isolation properties of the sensor. The counterbore thins the wall of the backing plate maintaining the contact area with the package. The depth and diameter of the counterbore can be adjusted to find geometry for allowing the backing plate to absorb more package stresses. Thinning the wall of the backing plate make it less rigid and allows the backing plate to absorb more of the stresses produced at the interface with the package. The counterbore also keeps a large surface area at the bottom of the backing plate creating a strong bond with the package. | 2009-04-16 |
20090096041 | SEMICONDUCTOR DEVICE - A semiconductor device is designed such that a semiconductor sensor chip having a diaphragm for detecting pressure variations based on the displacement thereof is fixed onto the upper surface of a substrate having a rectangular shape, which is covered with a cover member so as to form a hollow space embracing the semiconductor sensor chip between the substrate and the cover member. Herein, the substrate is sealed with a molded resin such that chip connection leads packaging leads are partially exposed externally of the molded resin; the chip connection leads are electrically connected to the semiconductor sensor chip and are disposed in line along one side of the semiconductor sensor chip; and the packaging leads are positioned opposite the chip connection leads by way of the semiconductor sensor chip. Thus, it is possible to downsize the semiconductor device without substantially changing the size of the semiconductor sensor chip. | 2009-04-16 |
20090096042 | MAGNETIC ELEMENT HAVING REDUCED CURRENT DENSITY - A memory device includes a fixed magnetic layer, a tunnel barrier layer over the fixed magnetic layer, and a free magnetic structure formed over the tunnel barrier layer, wherein the free magnetic structure has layers or sub-layers that are weakly magnetically coupled. Thus, a low programming voltage can be used to avoid tunnel barrier breakdown, and a small pass transistor can be used to save die real estate. | 2009-04-16 |
20090096043 | MRAM with means of controlling magnetic anisotropy - We describe the manufacturing process for and structure of a CPP MTJ MRAM unit cell that utilizes transfer of spin angular momentum as a mechanism for changing the magnetic moment direction of a free layer. The strength of the switching field, H | 2009-04-16 |
20090096044 | Spin-Wave Architectures - Nano-scale and multi-scale computational architectures using spin waves as a physical mechanism for device interconnection are provided. Solid-state spin-wave computing devices using nano-scale and multi-scale computational architectures comprised of a plurality of inputs and a plurality of outputs are described where such devices are configured to simultaneously transmit data elements from the inputs to the outputs by using spin-waves of differing frequencies. These devices include but are not limited to a spin-wave crossbar, a spin-wave reconfigurable mesh, a spin-wave fully-interconnected cluster, a hierarchical multi-scale spin-wave crossbar, a hierarchical multi-scale spin-wave reconfigurable mesh and a hierarchical multi-scale spin-wave fully-interconnected cluster. | 2009-04-16 |
20090096045 | MAGNETORESISTIVE DEVICE AND NONVOLATILE MAGNETIC MEMORY EQUIPPED WITH THE SAME - A fast and very low-power-consuming nonvolatile memory. A nonvolatile magnetic memory includes a high-output tunnel magnetoresistive device, in which spin-transfer torque is used for writing. A tunnel magnetoresistive device has a structure such that a ferromagnetic film of a body-centered cubic structure containing Co, Fe, and B, a MgO insulator film of a rock-salt structure oriented in (100), and a ferromagnetic film are stacked. | 2009-04-16 |
20090096046 | SEMICONDUCTOR DEVICE FOR RADIATION DETECTION - The invention provides a semiconductor device ( | 2009-04-16 |
20090096047 | IMAGING MODULE PACKAGE - An exemplary imaging module package includes a substrate, an imaging sensor chip set on the substrate, a housing positioned on the substrate, and a lens module. The housing includes a first chamber enclosing the imaging sensor chip therein, a second chamber coaxially extending from the first chamber for receiving the lens module therein, and a shoulder between the first and second chambers. The shoulder abuts against a top surface of the imaging sensor chip. | 2009-04-16 |
20090096048 | OPTICAL DEVICE AND MANUFACTURING METHOD THEREOF AND SEMICONDUCTOR DEVICE - An optical device includes a base and an optical element. The base has a through hole in a center and includes leads and a resin. Each lead has an L-shaped cross-section and is formed by an inner lead extending from the center toward a peripheral edge and an outer lead connected to the inner lead and extending downward. The optical element is provided under the base so as to correspond to the through hole. Electrode pads of the optical element are connected to the leads of the base through bumps, respectively. The resin is formed so as to cover respective inner ends of the leads and respective front surfaces of the inner leads and to fill a gap between adjacent leads, and respective outer ends of the leads and respective front surfaces of the outer leads are exposed. | 2009-04-16 |
20090096049 | SOLID STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND IMAGING APPARATUS - A solid state imaging device having a light sensing section that performs photoelectric conversion of incident light includes: an insulating layer formed on a light receiving surface of the light sensing section; a layer having negative electric charges formed on the insulating layer; and a hole accumulation layer formed on the light receiving surface of the light sensing section. | 2009-04-16 |
20090096050 | Image Sensor and Method for Manufacturing the Same - Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a semiconductor substrate including a unit pixel, first to third color filters provided on the semiconductor substrate, a first micro-lens provided on each of the first and third color filters, and a second micro-lens provided on the second color filter, in which an outer periphery of the first micro-lens has a square shape, and an upper portion of the first micro-lens has a semi-spherical or convex shape. | 2009-04-16 |
20090096051 | SOLID STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING SAME, AND SOLID STATE IMAGING MODULE - A solid state imaging device includes: an imaging device substrate with an imaging device section formed on a first major surface side thereof; a backside interconnect electrode provided on a second major surface side of the imaging device substrate and electrically connected to the imaging device section, the second major surface being on the opposite side of the first major surface; a circuit substrate provided with a circuit substrate electrode opposed to the second major surface; a connecting portion electrically connecting the backside interconnect electrode to the circuit substrate electrode; and a light shielding layer provided coplanar with the backside interconnect electrode or on the circuit substrate side of the backside interconnect electrode. | 2009-04-16 |
20090096052 | SEMICONDUCTOR DEVICE FOR RADIATION DETECTION - The invention provides a semiconductor device ( | 2009-04-16 |
20090096053 | Schottky Barrier Semiconductor Device and Method for Manufacturing the Same - A silicon carbide Schottky barrier semiconductor device provided with a Ta electrode as a Schottky electrode, in which the Schottky barrier height is controlled to a desired value in a range where power loss is minimized without increasing the n factor. The method for manufacturing the silicon carbide Schottky barrier semiconductor device includes the steps of depositing Ta on a crystal face of an n-type silicon carbide epitaxial film, the crystal face having an inclined angle in the range of 0° to 10° from a (000-1) C face, and carrying out a thermal treatment at a temperature range of 300 to 1200° C. to form the Schottky electrode. | 2009-04-16 |
20090096054 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device including a semiconductor substrate is provided. The semiconductor substrate includes a substrate having an insulating surface, and a plurality of stacks over the substrate having an insulating surface. Each of the plurality of stacks includes a bonding layer over the substrate having an insulating surface, an insulating layer over the bonding layer, and a single crystal semiconductor layer over the insulating layer. The substrate having an insulating surface has a depression, and the depression is provided between one of the plurality of stacks and another adjacent one of the plurality of stacks. | 2009-04-16 |
20090096055 | METHOD TO FORM CMOS CIRCUITS WITH SUB 50NM STI STRUCTURES USING SELECTIVE EPITAXIAL SILICON POST STI ETCH - An STI field oxide element in an IC which includes a layer of epitaxial semiconductor on sidewalls of the STI trench to increase the width of the active area adjacent to the STI trench and decrease a width of dielectric material in the STI trench is disclosed. STI etch residue is removed from the STI trench surface prior to growth of the epitaxial layer. The epitaxial semiconductor composition is matched to the composition of the adjacent active area. The epitaxial semiconductor may be undoped or doped to match the active area. The STI trench with the epitaxial layer is compatible with common STI passivation and fill processes. The thickness of the as-grown epitaxial semiconductor layer is selected to provide a desired active area width or a desired STI dielectric width. | 2009-04-16 |
20090096056 | ON-CHIP COOLING SYSTEMS FOR INTEGRATED CIRCUITS - Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. The cooling pipes system does not include any solid or liquid material. Given any first point and any second point in the cooling pipes system, there exists a continuous path which connects the first and second points and which is totally within the cooling pipes system. A first portion of the cooling pipes system overlaps the transistor. A second portion of the cooling pipes system is higher than the substrate and lower than a top interconnect layer. The second portion is in direct physical contact with a surrounding ambient. | 2009-04-16 |
20090096057 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate where an isolation region and a plurality of active regions are defined, an anti-interference layer formed over the substrate in the isolation region, and a gate line simultaneously crossing the active region and the anti-interference layer. | 2009-04-16 |
20090096058 | PINCHED POLY FUSE - An electrical fuse has a region of a first conductivity type in a continuous type polysilicon of a second conductivity type that is opposite the first conductivity type. In one embodiment of the invention the PN junction between the region and the poly fuse is reverse biased. | 2009-04-16 |
20090096059 | FUSE STRUCTURE INCLUDING MONOCRYSTALLINE SEMICONDUCTOR MATERIAL LAYER AND GAP - A fuse structure, a method for fabricating the fuse structure and a method for programming a fuse within the fuse structure each use a fuse material layer that is used as a fuse, and located upon a monocrystalline semiconductor material layer in turn located over a substrate. At least part of the monocrystalline semiconductor material layer is separated from the substrate by a gap. Use of the monocrystalline semiconductor material layer, as well as the gap, provides for enhanced uniformity and reproducibility when programming the fuse. | 2009-04-16 |
20090096060 | Antifuse structures, antifuse array structures, methods of manufacturing the same - Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of antifuse structures arranged in an array. | 2009-04-16 |
20090096061 | Semiconductor device having high frequency wiring and dummy metal layer at multilayer wiring structure - A semiconductor device includes, a metal wiring, which functions as an inductor or transformer, formed on a first portion of a semiconductor substrate, a plurality of first dummy layers formed in a first density on the first portion of the semiconductor substrate, a plurality of second dummy layers formed in a second density on a second portion of the semiconductor substrate, the second portion surrounding the first portion, and a plurality of third dummy layers formed in a third density higher than the first and second densities on a third portion of the semiconductor substrate, the third portion surrounding the second portion. | 2009-04-16 |
20090096062 | STACK CAPACITOR IN SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A stack capacitor in a semiconductor device includes a first capacitor formed on and/or over a semiconductor substrate and a second capacitor formed on and/or over the first capacitor. The first and second capacitors each have a multi-layer laminated structure which includes a lower electrode, a capacitor dielectric layer and an upper electrode. At least two of the lower electrodes and the upper electrodes are arranged vertically with respect to each other to have the same width and/or surface area. | 2009-04-16 |
20090096063 | Semiconductor apparatus with decoupling capacitor - A lead frame type of semiconductor apparatus includes a die pad on which a semiconductor chip is mounted; ground terminals which are to be grounded; power supply terminals which are connected to a power supply; inner leads connected to the ground terminals and power supply terminals, in which a pair of adjacent inner leads for power supply terminal and ground terminal are extended inwardly; a chip capacitor mounting pad which is provided at inner ends of the extended inner leads; and a chip capacitor which is mounted on the chip capacitor mounting pad so that a decoupling capacitor is provided. | 2009-04-16 |
20090096064 | METHOD OF FORMING POLY PATTERN IN R-STRING OF LCD DRIVE IC AND STRUCTURE OF THE SAME - A method of forming a poly pattern for minimizing a change in a storage value in the R-string pattern of the LCD panel drive IC (LDI) that includes depositing a poly silicon layer used as a resistor in a R-string structure over a semiconductor substrate; and then forming a poly silicon layer pattern having interconnected H-shaped cross-sections; and then forming a silicide-anti blocking area (SAB) layer over the poly silicon layer pattern and then patterning the SAB layer to thereby form SAB layer patterns over portions of the poly silicon layer pattern while exposing other portions of the poly silicon layer pattern; and then forming a silicide layer over the exposed portions of the poly silicon layer pattern. Therefore, although the size of the SAB pattern is reduced due to problems caused in processing steps, the poly line that occupies most of the resistance does not change so that a change in the resistance is entirely reduced. | 2009-04-16 |
20090096065 | ELECTRICAL ISOLATION OF MONOLITHIC CIRCUITS USING A CONDUCTIVE THROUGH-HOLE IN THE SUBSTRATE - A monolithic electronic chip including: a substrate; a first circuit formed on a first circuit portion of the substrate; a second circuit formed on a second circuit portion of the substrate; and at least one conductive impedance tap formed a through-hole in the substrate. The substrate includes first and second opposing surfaces and at least one through-hole extending from the first surface to the second surface. Each of the circuit portions is disposed on one or both of the opposing surfaces. Each conductive impedance tap is coupled to the surface of the through-hole it is formed in to electrically couple the substrate to a reference voltage. The impedance between each circuit and the reference voltage via the conductive impedance tap(s) is less than the crosstalk impedance between the first circuit and the second circuit via the substrate. | 2009-04-16 |
20090096066 | Structure and Method for Device-Specific Fill for Improved Anneal Uniformity - Disclosed is a design structure embodiment of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures having semiconductor materials with different thicknesses such that approximately the same overall ratio between the semiconductor material with the different thicknesses is achieved within each region and, optimally, each sub-region. | 2009-04-16 |
20090096067 | METHOD OF FABRICATING A METAL OXYNITRIDE THIN FILM THAT INCLUDES A FIRST ANNEALING OF A METAL OXIDE FILM IN A NITROGEN-CONTAINING ATMOSPHERE TO FORM A METAL OXYNITRIDE FILM AND A SECOND ANNEALING OF THE METAL OXYNITRIDE FILM IN AN OXIDIZING ATMOSPHERE - After the surface of the substrate is cleaned, an interface layer or an antidiffusion film is formed. A metal oxide film is built upon the antidiffusion film. Annealing is done in an NH | 2009-04-16 |
20090096068 | System and Method for Stabilizing an Amplifier - In one embodiment of the present invention, a semiconductor circuit including an amplifier disposed on a semiconductor substrate is disclosed. A first bond wire coupled to an input of the amplifier, a second bond wire coupled to an output of the amplifier, and a third bond wire coupled in series with the first bond wire. A third bond wire is disposed on the semiconductor substrate so that a mutual inductance between the second bond wire and the third bond wire at least partially cancels a mutual inductance between the first bond wire and the second bond wire. | 2009-04-16 |
20090096069 | Cof board - A COF board includes an insulating layer, and a terminal portion formed on the insulating layer. The terminal portion includes a first lead extending in a longitudinal direction, and a second lead extending in the longitudinal direction, and having a smaller length in the longitudinal direction than a length of the first lead in the longitudinal direction. The first leads are arranged in spaced-apart relation in a direction perpendicular to the longitudinal direction. The second leads are arranged in the direction perpendicular to the longitudinal direction to be interposed between the mutually adjacent first leads such that, when the mutually adjacent first leads are projected in an adjacent direction thereof, overlap portions where the second leads overlap with the first leads and non-overlap portions where the second leads do not overlap with the first leads are formed. Dummy leads are provided at the non-overlap portions. | 2009-04-16 |
20090096070 | Semiconductor package and substrate for the same - A semiconductor package is revealed with a special designed substrate. The substrate has a plurality of fingers, a dummy metal pattern, and at least a peripheral slot penetrating through the substrate. The dummy metal pattern is aligned to two opposing sides of the peripheral slot and is electrically isolated from the fingers. A chip is disposed on the substrate and is electrically connected to the fingers. An encapsulant is completely filled the peripheral slot. The peripheral slot can enhance the mold flow and eliminate the mold flash. The shape of the dummy metal pattern aligned to the peripheral slot is used to offer stiffening edges to prevent the substrate from warpage and from breakage at peripheries, to enhance the thermal stress resistance due to thermal cycles, and to avoid damages to the chip. | 2009-04-16 |
20090096071 | SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE HAVING THE SAME - A semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. According to the present invention, even if a mechanical stress or a thermal stress is applied to an interconnection, a crack does not occur in the interconnection or the interconnection is not disconnected. Therefore, a reliability of the semiconductor package is improved. | 2009-04-16 |
20090096072 | Package for a power semiconductor device - A package for a semiconductor die includes a die attach pad that provides an attachment surface area for the semiconductor die, and tie bars connected to the die attach pad. The die attach pad is disposed in a first general plane and the tie bars are disposed in a second general plane offset with respect to the first general plane. A molding compound encapsulates the semiconductor die in a form having first, second, third and fourth lateral sides, a top and a bottom. The tie bars are exposed substantially coincident with at least one of the lateral sides. The form includes a discontinuity that extends along the at least one of the lateral sides, the discontinuity increasing a creepage distance measured from the tie bars to the bottom of the package. | 2009-04-16 |
20090096073 | SEMICONDUCTOR DEVICE AND LEAD FRAME USED FOR THE SAME - A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame. | 2009-04-16 |
20090096074 | Semiconductor device - Disclosed herewith is a semiconductor device, which includes a semiconductor chip; a lead device that includes an island for mounting the semiconductor chip and having an area smaller than that of the semiconductor chip at its contact surface, as well as plural hanging leads for supporting the island and coming in contact partially with the semiconductor chip; a mounting material provided on a contact surface between each of the island and hanging leads and the semiconductor chip so as to adhere the semiconductor chip to the island and the hanging leads; and sealing resin for sealing the semiconductor chip. The modulus of elasticity of the mounting material is lower than that of the sealing resin. The mounting material is further coated on the back surfaces of the contact surfaces of the island and the hanging leads. | 2009-04-16 |
20090096075 | STACKED SEMICONDUCTOR PACKAGE THAT PREVENTS DAMAGE TO SEMICONDUCTOR CHIP WHEN WIRE-BONDING AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package includes a substrate having first and second contact pads. A first stacked package group is disposed on the substrate, and the first stacked package group includes first semiconductor chips stacked in a stair form to expose first edge bonding pads. First conductive wires are used to electrically couple the first edge bonding pads and the first contact pads. An adhesive member is disposed on the uppermost first semiconductor chip, and a second stacked package group is disposed on the adhesive member. The second stacked package group includes second semiconductor chips that are stacked in a stair form to expose second edge bonding pads. When the second stacked package group is disposed on the adhesive member, the bottommost second semiconductor chips is aligned with the uppermost first semiconductor chip. Second conductive wires are used to electrically couple the second edge bonding pads and the second contact pads. | 2009-04-16 |
20090096076 | STACKED SEMICONDUCTOR PACKAGE WITHOUT REDUCTION IN STATA STORAGE CAPACITY AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package includes a semiconductor chip module including at least two semiconductor chips with a semiconductor chip body having an upper surface, a lower surface, side surfaces coupling the upper surface and the lower surface, and a circuit part. The semiconductor chips include pads coupled to the circuit part and disposed at an edge of the upper surface. A recess parts are concavely formed in the side surfaces corresponding to each pad. Conductive connection patterns cover the recess parts, and each conductive connection pattern is electrically connected to a corresponding bonding pad. The semiconductor chip module is disposed on a substrate, and the contact pads of the semiconductor substrate are electrically connected to the conductive connection patterns. The stacked semiconductor package provides an improved structure that can contain a plurality of stacked semiconductor chips with no reduction in data storage capacity. | 2009-04-16 |
20090096077 | Tenon-and-mortise packaging structure - A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least one tenon projection, and the lower surface forms a mortise slot corresponding to the tenon projection in shape, size, and position, so that two carriers can be stacked on and jointed to each other by coupling the tenon projection to the corresponding mortise slot. The tenon projection and the mortise slot have conduction portions, respectively. When the tenon projection and the mortise slot are engaged with each other, the conduction portions are electrically connected with each other. At least one chip is embedded in the carrier. The chip has an active surface and a back side respectively and electrically connected with the top and the lower surfaces of the carrier. | 2009-04-16 |
20090096078 | Semiconductor device and method for manufacturing a semiconductor device - A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region. | 2009-04-16 |
20090096079 | SEMICONDUCTOR PACKAGE HAVING A WARPAGE RESISTANT SUBSTRATE - A semiconductor package is presented having a substrate, a semiconductor chip, an under-fill material, and a solder resist pattern. The substrate having a substrate body, wiring lines which are located on a first surface of the substrate body and which have connection pad parts, and ball lands which are located on a second surface of the substrate body, facing away from the first surface, and which are electrically connected with the wiring lines. The semiconductor chip having bumps which are electrically connected with the respective connection pad parts. The under-fill material filling a space between the substrate and the semiconductor chip. The solder resist pattern is located on the first surface and has first openings which expose the connection pad parts and has at least one second opening which exposes a portion of the substrate body to provide an enhancement of adhesion force between the under-fill material and the substrate body. | 2009-04-16 |
20090096080 | SEMICONDUCTOR PACKAGE, ELECTRONIC PART AND ELECTRONIC DEVICE - Even when a substrate on which a semiconductor package has been mounted is made curved, stress upon electrical connections is mitigated, thereby eliminating faulty connections and improving connection reliability. A semiconductor chip has electrodes on a second face thereof. Support blocks, capable of bending and flexing, are placed at two locations on a peripheral edge of a first face of the semiconductor chip. An interposer is placed so as to span the support blocks with the support blocks interposed between itself and the semiconductor chip, and has a wiring pattern in a flexible resin film. Two end portions of the interposer are folded back onto the side of the second face of the semiconductor chip, and the wiring pattern thereof is electrically connected to the electrodes of the semiconductor chip. | 2009-04-16 |
20090096081 | Semiconductor device - A semiconductor device includes a substrate, at least one semiconductor element mounted on the substrate, a resin housing for housing the semiconductor element, the resin housing having a cover thereon, at least one pin provided and standing in the resin housing, and at least one printed substrate disposed inside the resin housing or outside the resin housing. The printed substrate and the cover of the resin housing are positioned by the pin. | 2009-04-16 |
20090096082 | High speed electrical interconnects and method of manufacturing thereof - A high speed electrical interconnection system is provided. The interconnection system comprises one or more electrical signal lines, or differential pairs of signal lines, and an inhomogeneous dielectric system. The dielectric system further comprises a homogeneous dielectric layer interposed between the electrical signal lines, and electrical conducting planes including a periodic array etched in the conducting material of the conducting plane. The inhomogeneous dielectric system exhibits a lower dielectric constant as compared to the dielectric constant of the homogeneous dielectric layer, resulting in lower microwave loss, reduced signal propagation delay, reduced signal skew, and increased signal bandwidth. The interconnection system may be implemented for connecting one or more high speed electron elements on-chip, off-chip, chip-chip connection on multilayer printed circuit boards, high speed die-package, high speed connectors, and high speed electric cables. | 2009-04-16 |
20090096083 | Connecting structure for connecting at least one semiconductor component to a power semiconductor module - A connecting structure comprising a connecting device for electrically conductive connection to at least one semiconductor component and a filler. The connecting device is a film composite comprising at least two electrical films with an insulating film therebetween. The electrically conductive films are inherently structured and thus form conductor tracks. At least one semiconductor component is assigned to at least one cutout in the respective conductive film, wherein the filler is situated between the connecting device and the assigned semiconductor component. | 2009-04-16 |
20090096084 | Semiconductor chip packages having reduced stress - A structure and a method for forming the same. The structure includes (i) a carrier substrate which includes substrate pads, (ii) a chip physically attached to the carrier substrate, and (iii) a first frame physically attached to the carrier substrate. A CTE (coefficient of thermal expansion) of the first frame is substantially lower than a CTE of the carrier substrate. | 2009-04-16 |
20090096085 | Thermally Enhanced Wafer Level Package - A method of forming a package structure includes providing a plurality of dies; attaching the plurality of dies onto a heat-dissipating plate; and sawing the heat-dissipating plate into a plurality of packages, each including one of the plurality of dies and a piece of the heat-dissipating plate. | 2009-04-16 |
20090096086 | Cooling system for semiconductor devices - In one embodiment, the present invention includes a socket for a semiconductor package, where the socket has a frame with a segmented design, where socket streets are located between the segments. One or more of the streets may include a conduit to enable thermal transfer during operation of the semiconductor package. Other embodiments are described and claimed. | 2009-04-16 |
20090096087 | MICROELECTRONIC ASSEMBLY AND METHOD OF PREPARING SAME - A microelectronic assembly includes a die ( | 2009-04-16 |
20090096088 | SEALED WAFER PACKAGING OF MICROELECTROMECHANICAL SYSTEMS - Multiple microelectromechanical systems (MEMS) on a substrate are capped with a cover using a layer that may function as a bonding agent, separation layer, and hermetic seal. A substrate has a first side with multiple MEMS devices. A cover is formed with through-holes for vias, and with standoff posts for layer registration and separation. An adhesive sheet is patterned with cutouts for the MEMS devices, vias, and standoff posts. The adhesive sheet is tacked to the cover, then placed on the MEMS substrate and heated to bond the layers. The via holes may be metalized with leads for circuit board connection. The MEMS units may be diced from the substrate after sealing, thus protecting them from contaminants. | 2009-04-16 |
20090096089 | METHOD FOR PRODUCING A THIN SEMICONDUCTOR CHIP COMPRISING AN INTEGRATED CIRCUIT - In a method for producing a thin film chip including an integrated circuit, a semi-conductor wafer having a first surface is provided. At least one cavity is produced under a defined section of the first surface by means of porous silicon. A circuit structure is produced in the defined section. The defined wafer section is subsequently released from the semiconductor wafer by severing local web-like connections, which hold the wafer section above the cavity and on the remaining semiconductor wafer. | 2009-04-16 |
20090096090 | Photolithography Process and Photomask Structure Implemented in a Photolithography Process - In a photolithography process, a photoresist layer is formed on a substrate. A photomask is aligned over the substrate to transfer pattern images defined in the photomask on the substrate. The photomask includes first and second patterns of different light transmission rates, and a dummy pattern surrounding the second pattern having a light transmission rate lower than that of the first pattern. The substrate is exposed to a light radiation through the photomask. The photoresist layer then is developed to form the pattern images. The dummy pattern is dimensionally configured to allow light transmission, but in a substantially amount so that the dummy pattern is not imaged during exposure. | 2009-04-16 |
20090096091 | SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns. | 2009-04-16 |
20090096092 | Bump I/O Contact for Semiconductor Device - A bump contact electrically connects a conductor on a substrate and a contact pad on a semiconductor device mounted to the substrate. The first end of an electrically conductive pillar effects electrical contact and mechanical attachment of the pillar to the contact pad with the pillar projecting outwardly from the semiconductor device. A solder crown reflowable at a predetermined temperature into effecting electrical contact and mechanical attachment with the conductor is positioned in axial alignment with the second end of the pillar. A diffusion barrier electrically and mechanically joins the solder bump to the second end of the pillar and resists electro-migration into the first end of the solder crown of copper from the pillar. One diffusion barrier takes the form of a 2-20 micron thick control layer of nickel, palladium, titanium-tungsten, nickel-vanadium, or tantalum nitride positioned between the pillar and the solder crown. | 2009-04-16 |
20090096093 | INTER-CONNECTING STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD OF THE SAME - The interconnecting structure for a semiconductor die assembly comprises a build-up layers having RDL formed therein formed over a die having die pads formed thereon, wherein the RDL is coupled to the die pads; an isolation base having ball openings attached over the build-up layer to expose ball pads within the build-up layers; and conductive balls placed into the ball openings of the isolation base and attached on the ball pads within the build-up layers. | 2009-04-16 |
20090096094 | SEMICONDUCTOR DEVICE - In a wafer level CSP package, with respect to signal wiring | 2009-04-16 |
20090096095 | Semiconductor device and method of manufacturing the same - Provided is a semiconductor device having a substrate, a semiconductor chip flip-chip mounted on the substrate, and a stacked film provided in a gap between the substrate and the semiconductor chip. The stacked film is composed of a protective film covering the surface of the substrate, and an underfill film formed between the solder resist film and the semiconductor chip. The protective film is roughened on the contact surface brought into contacting said underfill film. | 2009-04-16 |
20090096096 | SEMICONDUCTOR DEVICE AND CIRCUIT DEVICE HAVING THE SAME MOUNTED THEREON - A semiconductor device has a semiconductor chip, terminals formed at a prescribed terminal pitch on the bottom side of the semiconductor chip, and columnar post electrodes formed on the terminals. The post electrodes are formed of two different metals, the side bonded with the terminals is constituted by first metallic portions while the side on which solder bumps is formed are constituted by second metallic portions. A dimension in the width direction of the first metallic portions is formed smaller than a dimension in the width direction of the second metallic portions. | 2009-04-16 |
20090096097 | Semiconductor device and manufacturing method of the same - Semiconductor device | 2009-04-16 |
20090096098 | INTER-CONNECTING STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD OF THE SAME - The interconnecting structure for a semiconductor die assembly comprises a build-up layers having RDL formed therein formed over a die having die pads formed thereon, wherein the RDL is coupled to the die pads; an isolation base having ball openings attached over the build-up layer to expose ball pads within the build-up layers; and conductive balls placed into the ball openings of the isolation base and attached on the ball pads within the build-up layers. | 2009-04-16 |
20090096099 | PACKAGE SUBSTRATE AND METHOD FOR FABRICATING THE SAME - A package substrate and a method for fabricating the same are provided according to the present invention. The package substrate includes: a substrate body with a die attaching side and a ball implanting side lying opposite each other, having a plurality of wire bonding pads and a plurality of solder ball pads respectively, and having a first insulating passivation layer and a second insulating passivation layer respectively, wherein a plurality of first apertures and a plurality of second apertures are formed in the first insulating passivation layer and the second insulation passivation layer respectively to corresponding expose the wire bonding pads and the solder ball pads; a chemical plating metal layer formed on the wire bonding pads and solder ball pads respectively; and a wire bonding metal layer formed on a surface of the chemical plating metal layer of the wire bonding metal layer. | 2009-04-16 |
20090096100 | SEMICONDUCTOR APPARATUS, MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS, AND JOINT MATERIAL - A die bonding portion is metallically bonded by well-conductive Cu metal powders with a maximum particle diameter of about 15 μm to 200 μm and adhesive layers of Ag, and minute holes are evenly dispersed in a joint layer. With this structure, the reflow resistance of about 260° C. and reliability under thermal cycle test can be ensured without using lead. | 2009-04-16 |
20090096101 | BRIDGE FOR SEMICONDUCTOR INTERNAL NODE - A method and apparatus for forming connections within a semiconductor device is disclosed. The semiconductor device incorporates a contact bridge between transistor contacts in close proximity. The contact bridge comprises a plurality of metal pillars each having a lower end in electrical contact with first and second transistor elements, respectively; one or more intermediate metal pillars disposed between and in electrical contact with an upper end of the metal pillars; and one or more separation regions of dielectric disposed below the intermediate metal pillar and between the lower ends of the first and second metal pillars. | 2009-04-16 |
20090096102 | CONDUCTOR STRUCTURE INCLUDING MANGANESE OXIDE CAPPING LAYER - A microelectronic structure includes a dielectric layer located over a substrate. The dielectric layer is separated from a copper containing conductor layer by an oxidation barrier layer. The microelectronic structure also includes a manganese oxide layer located aligned upon a portion of the copper containing conductor layer not adjoining the oxidation barrier layer. A method for fabricating the microelectronic structure includes sequentially forming and sequentially planarizing within an aperture within a dielectric layer an oxidation barrier layer, a manganese containing layer (or alternatively a mobile and oxidizable material layer) and finally, a planarized copper containing conductor layer (or alternatively a base material layer comprising a material less mobile and oxidizable than the mobile and oxidizable material layer) to completely fill the aperture. The manganese layer and the planarized copper containing conductor layer are then thermally oxidized to form a manganese oxide layer self aligned to a portion of the copper containing conductor layer not adjoining the oxidation barrier layer. | 2009-04-16 |
20090096103 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING BARRIER METAL LAYER THEREOF - A method for forming a barrier metal layer includes forming a metal compound film composed of a first metal and a second metal on sidewalls of a contact hole, and then selectively etching the metal compound film and then simultaneously forming a barrier metal layer and a first metal seed layer on sidewalls of the contact hole by performing a thermal treatment process on the metal compound film. Accordingly, the process time can be shortened because the sputtering process can be reduced by forming a barrier metal layer and a copper seed layer by reaction between the second metal material and an underlying insulating film by performing the thermal treatment process. | 2009-04-16 |
20090096104 | Semiconductor device having crack stop structure - Example embodiments relate to semiconductor devices having a single body crack stop structure configured to reduce or prevent crack propagation and/or moisture penetration. A semiconductor substrate according to example embodiments may include an active region and a crack stop region surrounding the active region. Interlayer insulating layers may be sequentially stacked on the semiconductor substrate. The interlayer insulating layers may include first dual damascene patterns and a first opening. The first dual damascene patterns may be formed in the interlayer insulating layers so as to be perpendicular to the surface of the semiconductor substrate while exposing a first portion of the semiconductor substrate. The first opening may be formed in the crack stop region and may extend through the interlayer insulating layers to expose a second portion of the semiconductor substrate. First dual damascene metal wirings may be formed in the first dual damascene patterns and may contact the exposed first portion of the semiconductor substrate. A single body first crack stop structure may be formed in the first opening so as to contact the exposed second portion of the semiconductor substrate. | 2009-04-16 |
20090096105 | CONTACT STRUCTURE OF A WIRES AND METHOD MANUFACTURING THE SAME, AND THIN FILM TRANSISTOR SUBSTRATE INCLUDING THE CONTACT STRUCTURE AND METHOD MANUFACTURING THE SAME - In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads. | 2009-04-16 |
20090096106 | ANTIREFLECTIVE COATINGS - A method of forming a feature in a substrate comprising the steps of: forming a dielectric layer on a substrate; forming an antireflective coating over the dielectric layer; forming a photoresist pattern over the antireflective coating; etching the dielectric layer through the patterned photoresist; and removing the antireflective coating and the photoresist, wherein the antireflective coating is a film represented by the formula Si | 2009-04-16 |
20090096107 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device, an element forming region and a metal wiring layer are covered with a passivation layer on a semiconductor substrate which is cut out in a rectangular shape. At four corners of the device, the passivation layer is provided with corner non-wiring regions formed directly on the semiconductor substrate. Thus, crack generation on the passivation layer due to heat stress can be suppressed. | 2009-04-16 |
20090096108 | STRUCTURE AND METHODS OF FORMING CONTACT STRUCTURES - Methods and a structure. A method of forming contact structure includes depositing a silicide layer onto a substrate; depositing an electrically insulating layer over a first surface of the silicide layer; forming a via through the insulating layer extending to the first surface; depositing an electrically conductive layer covering a bottom and at least one vertical wall of the via; removing the conductive layer from the bottom; and filling the via with aluminum directly contacting the silicide layer. A structure includes: a silicide layer disposed on a substrate; an electrically insulating layer disposed over the silicide layer; an aluminum plug extending through the insulating layer and directly contacting the silicide layer; and an electrically conductive layer disposed between the plug and the insulating layer. Also included is a method where an aluminum layer grows selectively from a silicide layer and at least one sidewall of a trench. | 2009-04-16 |
20090096109 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes: a first insulation film formed over a semiconductor substrate; and a plurality of first interconnects selectively formed in the first insulation film. A plurality of gaps are formed in part of the first insulation film located between adjacent ones of the first interconnects so that each of the gaps has a cylindrical shape extending vertically to a principal surface of the semiconductor substrate. A cap film is formed of metal or a material containing metal in upper part of each of the first interconnects. | 2009-04-16 |
20090096110 | METHOD FOR MANUFACTURING A STACKED SEMICONDUCTOR PACKAGE, AND STACKED SEMICONDUCTOR PACKAGE - A method for manufacturing a stacked semiconductor package where a plurality of semiconductor chips are stacked on a substrate, including: forming insulating layers at portions of a wafer corresponding to sides of the plurality of semiconductor chips when the plurality of semiconductor chips are in the wafer; processing the wafer so as to obtain the plurality of semiconductor chips; subsequently stacking the plurality of semiconductor chips on the substrate such that the insulating layers formed at the sides of the plurality of semiconductor chips are respectively positioned at the same side as one another; and forming a wiring over the insulating layers formed at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips are electrically connected with the substrate. | 2009-04-16 |
20090096111 | Semiconductor device and method of manufacturing the same - In a semiconductor device, a first semiconductor chip is stacked on a wiring substrate and has first electrode pads disposed at predetermined positions on an upper surface thereof. A second semiconductor chip is stacked on the first semiconductor chip through an insulating member in an offset manner so that the first electrode pads are exposed. Support members support a back surface of a protruding portion of the second semiconductor chip through the insulating member. | 2009-04-16 |
20090096112 | INTEGRATED CIRCUIT UNDERFILL PACKAGE SYSTEM - An integrated circuit underfill package system including providing a substrate having a dispense port, attaching a first integrated circuit die on the substrate, and supplying an underfill to the dispense port when the substrate and the first integrated circuit die are inverted. | 2009-04-16 |
20090096113 | SOI on Package Hypersensitive Sensor - A hypersensitive semiconductor die structure is disclosed, in which flip-chip packaging is used in conjunction with a modified SOI die in which a thick silicon support substrate has been removed to increase sensitivity of the sensing device. Rather than being located beneath layers of interconnects and dielectric, the disclosed structure places the sensing devices close to the surface, more closely exposed to the environment in which sensing is to occur. The structure also allows for the placement of sensing films on nearer to the sensing devices and/or an oxide layer overlying the sensing devices. | 2009-04-16 |
20090096114 | Epoxy Resin Composition and Semiconductor Device - An epoxy resin composition for encapsulating a semiconductor chip according to this invention comprises (A) a crystalline epoxy resin, (B) a phenol resin represented by general formula (1): | 2009-04-16 |
20090096115 | Semiconductor package and method for fabricating the same - A semiconductor package and a method for fabricating the same are disclosed. The present invention discloses mounting and electrically connecting a semiconductor chip to a chip carrier, forming an interfacial layer or a heat-dissipating member having the interfacial layer on the semiconductor chip, and forming an encapsulant for covering the semiconductor chip, the interfacial layer or the heat dissipating member. The method further includes cutting the encapsulant along edges of the interfacial layer, and removing the redundant encapsulant on the interfacial layer so as to expose the semiconductor chip or the heat-dissipating member without forming burr or heavily wearing cutting tools. | 2009-04-16 |
20090096116 | ALIGNMENT MARK AND MEHTOD FOR FORMING THE SAME - The invention is directed to an alignment mark in a material layer in an alignment region of a wafer. The alignment mark comprises a plurality of sub-marks. Each of the sub-mark comprises a first element and a plurality of second elements. The second elements are embedded in the first element and a first top surface of the first element is at the same height as a second top surface of each of the second elements. | 2009-04-16 |
20090096117 | RETRIEVABLE DIFFUSER MODULE WITH TRUSS CONSTRUCTION - A diffuser module and system for diffusing gas into liquid such as in aeration/mixing of wastewater. Each module has a header pipe and diffusers which receive gas from the header pipe. Each header pipe is equipped with a truss for enhanced structural strength and resistance to bending. The truss may take the form of a buoyancy/ballast pipe connected with the header pipe by purlins. | 2009-04-16 |
20090096118 | Portable heater and humidifier apparatus - A portable heater and humidifier apparatus is provided. The apparatus includes a housing with an inlet for receiving air from an area exterior to the housing. The housing includes an air passage disposed therein with a ceramic heating element located inside the air passage. The air passage includes a partition stationed between the ceramic heating element and a heater outlet that is used to exhaust heated air. A fan within the housing is used to direct air from outside of the housing into the air passage. The fan then directs the air through the ceramic heating element. A portion of the heated air continues to flow within the air passage until the heated air is exhausted from a heater outlet. The remaining heated air is diverted to a humidifier through an aperture located within the air passage. The heated air is then combined with fine water droplets generated by the humidifier to emit water vapor or mist from a humidifier outlet. | 2009-04-16 |
20090096119 | Method for Producing Single- or Multi-Layered Fiber Preforms by the TFP Process as Well as a Fixing Thread and Backing Layer - Disclosed is a method for producing single- or multi-layered fiber performs by the TFP process with fiber strands which are aligned substantially such that they are oriented with the flux of force, are laid on at least one backing layer and are attached by at least one fixing thread. After completion of the TFT process, at least one fiber preform is introduced into a fixing device to secure the position of the fiber strands and the fixing threads and/or the backing layers are at least partially removed. As a result of the preferably complete removal of the fixing threads and/or the backing layer from the fiber preform, the latter has virtually ideal mechanical, quasi isotropic properties. In a preferred variant, the fixing threads and/or the backing layers are formed by a water-soluble material, so that they can be completely dissolved by water as the solvent and flushed out. | 2009-04-16 |
20090096120 | PROBE SENSOR AND METHOD FOR A POLYMERIC PROCESS - A method for processing a polymeric article, by introducing ingredients including a polymeric material for forming a polymeric article into an apparatus including a wall surface over which the polymeric material travels in at least a fluidic state, and an orifice through which the ingredients exit the apparatus. The ingredients are mixed while in the apparatus to form a polymeric ingredients mixture. A corrosion response of the wall surface of the apparatus is monitored with at least one resistance corrosion sensing probe that is flush mounted with the interior wall surface. The polymeric mixture is solidified after it exits the orifice for forming the polymeric article and mitigating corrosion detected by the monitoring step. | 2009-04-16 |