15th week of 2010 patent applcation highlights part 44 |
Patent application number | Title | Published |
20100093099 | DETECTION OF BLOOD PLASMA DANSHENSU AND SALVIANOLID ACID B DISSIPATING BLOOD STASIS BOTANICAL - A detection method of blood plasma danshensu and salvianolic acid B of dissipating blood stasis botanical is disclosed. The method includes: (1) pretreating mammalian plasma sample: applying the plasma with medicine to small column of Waters Oasis HLB activated by methanol and water; after leaching and eluting, drying and enriching the eluent; after redissolving with mobile phase, measuring by UPLC/MS; (2) UPLC/MS measuring: UPLC condition: chromatographic column: Acquity UPLC BEH C | 2010-04-15 |
20100093100 | PROFILING METHOD USEFUL FOR CONDITION DIAGNOSIS AND MONITORING, COMPOSITION SCREENING, AND THERAPEUTIC MONITORING - The presently-disclosed subject matter includes methods and systems for identifying biomarkers of interest, diagnosing and/or monitoring conditions of interest, assessing the efficacy of a treatment program, and composition screening. Exemplary methods include providing a sample of interest, fractionating the sample, generating thermograms, and comparing thermograms. | 2010-04-15 |
20100093101 | METHOD FOR DETERMINING THE CONTENT OF METALLIC ELEMENTS IN FISCHER-TROPSCH WAXES - The invention provides a method for determining the content of metallic elements in Fischer-Tropsch waxes by Inductively Coupled Plasma (ICP), wherein digestion of one or more samples of the waxes is carried out in an open vessel microwave digestion system. The invention further provides a sampling protocol for use with the method. | 2010-04-15 |
20100093102 | MESOPOROUS METAL OXIDE MATERIALS FOR PHOSPHOPROTEOMICS - The present invention provides methods and materials for isolating, purifying, and/or enriching the concentration of compounds having one or more phosphate groups and/or derivatives thereof, including but not limited to phosphorylated peptides and/or phosphorylated proteins. In some aspects, the present invention provides nanostructured enrichment materials, such as metal oxide mesoporous materials, that selectively and reversibly bind with phosphorylated compounds with high specificity and are capable of controlled release of phosphorylated compounds bound to their active surfaces. Mesoporous materials of the present invention also provide enrichment materials having large active surface areas that provide for higher loading capacities for phosphorylated peptides and proteins relative to conventional affinity based methods. Nanostructured metal oxide mesoporous enrichment materials of the present invention are also compatible with implementation via a variety of separation platforms including flow through separation systems, elution based separation systems, column chromatography and affinity chromatography. | 2010-04-15 |
20100093103 | DETECTION OF BLOOD PLASMA SCHIZADRIN B OF DISSIPATING BLOOD STASIS BOTANICAL - A detection method of blood plasma schizadrin B of dissipating blood stasis botanical is disclosed. The method includes: (1) extracting schizadrin B from plasma of mammalian administered dissipating blood stasis botanical by ethyl acetate with the volume ratio 1:4, whirling 3-5 mins, centrifugating at 9600 rpm for 10 mins, drying and enriching the upper layer at 25-30° C., and redissolving with mobile phase; (2) UPLC/MS measuring: UPLC condition: chromatographic column: Acquity UPLC BEH C | 2010-04-15 |
20100093104 | Method and apparatus for positioning nano-particles - A method of positioning a sample at a desired location relative to a magnetic sensor, for measurement of magnetic characteristics of the sample. A sample mounting substrate is provided, and an amphifunctional molecule is bound to the sample mounting substrate at the desired location. The amphifunctional molecule has a portion for binding to the sample mounting substrate, and a portion for capturing the sample. The sample is then provided for capture by the amphifunctional molecule. | 2010-04-15 |
20100093105 | MICROFLUIDIC DEVICE USING CENTRIFUGAL FORCE, METHOD OF MANUFACTURING THE MICROFLUIDIC DEVICE AND SAMPLE ANALYZING METHOD USING THE MICROFLUIDIC DEVICE - Provided is a microfluidic device including: a sample chamber; at least one analyzing unit receiving a sample from the sample chamber and detecting components contained in the sample according to a reaction of the sample and a reagent; and a denaturation detection chamber determining the storage condition of the microfluidic device, wherein the denaturation detection chamber accommodates a material whose light absorption changes according to the temperature and the water thereof | 2010-04-15 |
20100093106 | Amine-Reactive Biosensor - Described are methods, articles of manufacture, and kits for coupling an analyte-binding molecule to the surface of a biosensor through formation of amide bonds. One amide bond is formed between a first carboxyl group on a polymer and a first reflecting surface comprising an aminoalkyl moiety. A second amide bond is formed between a second carboxyl group on the polymer and an amine group on an analyte-binding molecule to be coupled. The present invention thus provides for covalent attachment of the analyte-binding molecule to the biosensor, thus providing advantages over non-covalent attachment methods of the prior art. These advantages include the ability to couple without using bio tin (which, in some instances can alter functional properties of a molecule) the ability to improve the fidelity with which a binding or dissociation reaction that takes place on the surface of the biosensor represents a solution phase reaction, and the ability to regenerate the sensor by stripping ligands from the covalently bound analyte-binding molecule. | 2010-04-15 |
20100093107 | POLYMER-PROTEIN SUBSTRATES FOR IMMUNOSORBENT FLUORESCENCE ASSAYS - The present invention relates to antigen-capture substrates useful for orienting capture antibodies for immunosorbent antigen determination. | 2010-04-15 |
20100093108 | Lung cancer diagnotic assay - A diagnostic assay for determining presence of lung cancer in a patient depends, in part, on ascertaining the presence of an antibody associated with lung cancer using random polypeptides. The assay predicted lung cancer prior to evidence of radiographically detectable cancer tissue. | 2010-04-15 |
20100093109 | PIEZO DISPENSING OF A DIAGNOSTIC LIQUID INTO MICROFLUIDIC DEVICES - Assays in which samples of biological fluids are dispensed into the inlet port of a microfluidic device are improved in the accuracy and repeatability by dispensing the biological sample and/or associated liquids in small droplets and at timed intervals to control the operation of the microfluidic device. | 2010-04-15 |
20100093110 | Ferroelectric passive memory cell, device and method of manufacture thereof - A first passive ferroelectric memory element comprising a first electrode system and a second electrode system, wherein said first electrode system is at least partly insulated from said second electrode system by an element system comprising at least one ferroelectric element, wherein said first electrode system is a conductive surface, or a conductive layer; wherein said second electrode system is an electrode pattern or a plurality of isolated conductive areas in contact with, for read-out or data-input purposes only, a plurality of conducting pins isolated from one another. | 2010-04-15 |
20100093111 | METHOD FOR MANUFACTURING ELECTRONIC DEVICE USING PLASMA REACTOR PROCESSING SYSTEM - To enable change of a concentration of atmosphere in a process chamber and realize a plasma reaction process required for manufacturing a liquid crystal device and a semiconductor device with a high yield at a low cost. | 2010-04-15 |
20100093112 | LASER ANNEALING METHOD AND LASER ANNEALING APPARATUS - An embodiment of the invention provides a laser annealing method, including the steps of radiating a laser beam to an amorphous film on a substrate while scanning the laser beam for the amorphous film, crystallizing the amorphous film, detecting a light quantity of laser beam reflected from the substrate and a scanning speed of the laser beam while the radiation and the scanning of the laser beam are carried out for the amorphous film, and controlling a radiation level and the scanning speed of the laser beam based on results of comparison of the light quantity of laser beam reflected from the substrate, and the scanning speed of the laser beam with respective preset references. | 2010-04-15 |
20100093113 | SEMICONDUCTOR MANUFACTURING APPARATUS - A semiconductor manufacturing apparatus includes: an ion source and a beam line for introducing an ion beam into a target film which is formed over a wafer with an insulating film interposed therebetween; a flood gun for supplying the target film with electrons for neutralizing charges contained in the ion beam; a rotating disk for subjecting the target film to mechanical scanning of the ion beam in two directions composed of r-θ directions; a rear Faraday cage for measuring the current density produced by the ion beam; a disk-rotational-speed controller and a disk-scanning-speed controller for changing the scanning speed of the target film; and a beam current/current density measuring instrument for controlling, according to the current density, the scanning speed of the target film. | 2010-04-15 |
20100093114 | METHOD OF SEARCHING FOR KEY SEMICONDUCTOR OPERATION WITH RANDOMIZATION FOR WAFER POSITION - A method of searching for the key semiconductor operation with randomization for wafer position, comprising: recording the wafer position and the wafer yields of a plurality of wafer ID respectively corresponding to a plurality of semiconductor operations; establishing a matrix model which describes the matrix set for wafer yields of the plurality of wafer ID; analyzing the matrix model, further computing the matrix set for wafer yields of the wafer ID, thereby acquiring the weightings of the randomized wafer positions in such semiconductor operations; and searching for a key semiconductor operation among the plurality of semiconductor operations; herein, by using a local regression model to estimate the wafer position effect, computing the weighting of the position effect in each semiconductor operation based on the estimated position effect and the randomized wafer yield, higher weighting thereof indicates the key semiconductor operation having greater position effect in the aforementioned semiconductor process. | 2010-04-15 |
20100093115 | ETCH TOOL PROCESS INDICATOR METHOD AND APPARATUS - A method for providing a process indicator for an etching chamber is provided. A wafer with a blanket etch layer is provided into the etching chamber. A blanket etch is performed on the blanket etch layer. A blanket deposition layer is deposited over the blanket etch layer after performing the blanket etch has been completed. A thickness of the blanket etch layer and a thickness of the blanket deposition layer is measured. The measured thicknesses are used to determine a process indicator. | 2010-04-15 |
20100093116 | DIMENSION PROFILING OF SIC DEVICES - There is provided a method for dimension profiling of a semiconductor device. The method involves incorporating a feature comprising a detectable element into the device, and thereafter detecting the detectable element to determine a dimension of the feature. This information can be used for the determination of a dimension of buried channels, and also for end-point detection of CMP processes. | 2010-04-15 |
20100093117 | Method for making liquid crystal display screen - A method for making a liquid crystal display screen is provided. The method includes the following steps. A touch panel and a thin film transistor panel are provided, and the touch panel includes at least one TP carbon nanotube layer. The thin film transistor panel includes a plurality of thin film transistors; each of the thin film transistors comprises a TFT carbon nanotube layer. A first polarizer is applied on a surface of the touch panel. Additionally, a liquid crystal layer is provided to be placed between the first polarizer and the thin film transistor panel. | 2010-04-15 |
20100093118 | METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING DEVICE - Semiconductor laser elements are formed on a common substrate. Au plating is formed on principal surfaces of the semiconductor laser elements. The semiconductor laser elements are mounted on a package with solder applied to the Au plating. Areas opposed to each other across a light-emitting area of each semiconductor laser element are designated first and second areas. Average thickness of the Au plating is different in the first and second areas of each semiconductor laser element. | 2010-04-15 |
20100093119 | RESIN COMPOSITION FOR PRINTING PLATE - Disclosed is a polymer having excellent solvent resistance which can be produced by using a polycarbonate diol having a repeating unit represented by the formula (1) and/or (2), having a hydroxyl group at both termini, and having a number average molecular weight of from 300 to 50,000: | 2010-04-15 |
20100093120 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light emitting device and a method of manufacturing the same are provided. The light emitting device comprises a substrate, a gate electrode positioned on the substrate, a first insulating layer positioned on the substrate comprising the gate electrode, an amorphous silicon layer positioned on the first insulating layer so that a predetermined area thereof corresponds to the gate electrode, ohmic layers that positioned on a predetermined area of the amorphous silicon layer, the ohmic layers defining a source area and a drain area, a source electrode or a drain electrode electrically connected to any one of the ohmic layers and a cathode that is electrically connected to the other one of the ohmic layers, a second insulating layer positioned on the substrate comprising the source electrode or the drain electrode and the cathode, the second insulating layer comprising an opening exposing a portion of the cathode, an emitting layer positioned within the opening, and an anode positioned on the substrate comprising the emitting layer. | 2010-04-15 |
20100093121 | SYSTEM AND METHOD FOR DIFFERENTIATING PICTURES AND TEXTS - A dual emitting device includes a transparent substrate and an array of pixels. The array of pixels is disposed on the transparent, and each pixel of the array includes at least one first sub-pixel and at least one second sub-pixel. The first sub-pixel includes a first OLED driven by a first TFT, and a first sheltering layer on the first OLED. The second sub-pixel includes a second OLED driven by a second TFT, and a second sheltering layer formed between the transparent substrate and the second OLED. | 2010-04-15 |
20100093122 | THIN FILM PATTERNING METHOD AND METHOD FOR MANUFACTURING A LIQUID CRYSTAL DISPLAY DEVICE - A thin film patterning method comprising: depositing a first thin film and applying a photoresist layer on the first thin film; exposing and developing the photoresist layer to define first, second and third regions, wherein the photoresist layer in the first region is thicker than that in the second region, and no photoresist layer is left in the third region; over-etching to remove the first thin film in the third region and form an over-etched region in the peripheral region of the first region; removing a part of the photoresist layer to expose the first thin film in the second region; depositing a second thin film so that the first thin film contacts the second thin film in the second region; and lifting off the photoresist layer to remove the second thin film in the first region and exposing the substrate in the over-etched region of the first region. | 2010-04-15 |
20100093123 | LIGHT EMITTING DEVICE HAVING LIGHT EXTRACTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A nitride-based light emitting device capable of achieving an enhancement in emission efficiency and an enhancement in reliability is disclosed. The light emitting device includes a semiconductor layer, and a light extracting layer arranged on the semiconductor layer and made of a material having a refractive index equal to or higher than a reflective index of the semiconductor layer. | 2010-04-15 |
20100093124 | METHOD OF PRODUCING A GROUP III NITRIDE CRYSTAL - There is provided a method capable of obtaining an aluminum-based group III nitride crystal layer having a smooth surface and high crystallinity by employing only HVPE in which inexpensive raw materials can be used to reduce production costs and high-speed film formation is possible without employing MOVPE. | 2010-04-15 |
20100093125 | METHOD FOR TEMPERATURE COMPENSATION IN MEMS RESONATORS WITH ISOLATED REGIONS OF DISTINCT MATERIAL - MEMS resonators containing a first material and a second material to tailor the resonator's temperature coefficient of frequency (TCF). The first material has a different Young's modulus temperature coefficient than the second material. In one embodiment, the first material has a negative Young's modulus temperature coefficient and the second material has a positive Young's modulus temperature coefficient. In one such embodiment, the first material is a semiconductor and the second material is a dielectric. In a further embodiment, the quantity and location of the second material in the resonator is tailored to meet the resonator TCF specifications for a particular application. In an embodiment, the second material is isolated to a region of the resonator proximate to a point of maximum stress within the resonator. In a particular embodiment, the resonator includes a first material with a trench containing the second material. | 2010-04-15 |
20100093126 | METHOD FOR MANUFACTURING A POLY-CRYSTAL SILICON PHOTOVOLTAIC DEVICE USING HORIZONTAL METAL INDUCED CRYSTALLIZATION - A method for manufacturing a poly-crystal silicon photovoltaic device using horizontal metal induced crystallization comprises the steps of forming at least one layer of an amorphous silicon thin film on a substrate, forming at least one groove of which depth is less than or equal to that of the thin film on the amorphous silicon thin film, and horizontally crystallizing the amorphous silicon thin film by forming a metal layer on an upper portion of the groove. Since a crystal shape and a growth direction of the photovoltaic device can be adjusted by the method, a poly-crystal silicon thin film for improving current flow can be formed at a low-temperature. | 2010-04-15 |
20100093127 | Inverted Metamorphic Multijunction Solar Cell Mounted on Metallized Flexible Film - A method of manufacturing a mounted solar cell by providing a metallic flexible film having a predetermined coefficient of thermal expansion; and attaching the semiconductor solar cell to the metallic film, the coefficient of thermal expansion of the semiconductor body closely matching the predetermined coefficient of thermal expansion of the metallic film. | 2010-04-15 |
20100093128 | METHOD FOR MANUFACTURING IMAGE SENSOR - In a method for manufacturing an image sensor, readout circuitry is formed in a first substrate. A first interlayer dielectric is formed over the first substrate. An interconnection is formed at the first interlayer dielectric, and the interconnection is electrically connected to the readout circuitry. A second interlayer dielectric is formed over the interconnection. A via hole exposing an upper side of the interconnection is formed by etching a portion of the second interlayer dielectric using a photoresist pattern as an etch mask. A contact plug is formed in the via hole, while leaving the photoresist pattern. The photoresist pattern is then removed. An image sensing device is formed over the contact plug. | 2010-04-15 |
20100093129 | SEMICONDUCTING INK FORMULATION - A semiconducting ink formulation comprises a semiconducting material; a first solvent; and a second solvent which is miscible with the first solvent, has a surface tension equal to or greater than the surface tension of the first solvent, and in which the semiconducting material has a solubility of less than 0.1 wt % at room temperature The surface tension of the ink formulation can be controlled, allowing the formation of semiconducting layers in organic thin film transistors, including top-gate transistors. | 2010-04-15 |
20100093130 | Methods of forming multi-level cell of semiconductor memory - Provided is a method of forming a semiconductor memory cell in which in order to store two bits or more data in a memory cell, three or more bottom electrode contacts (BECs) and phase-change materials (GST) have a parallel structure on a single contact plug (CP) and set resistances are changed depending on thicknesses (S), lengths (L) or resistivities (ρ) of the three or more bottom electrode contacts, so that a reset resistance and three different set resistances enable data other than in set and reset states to be stored. Also, a method of forming a memory cell in which three or more phase-change materials (GST) have a parallel structure on a single bottom electrode contact, and the phase-change materials have different set resistances depending on composition ratio or type, so that four or more different resistances can be implemented is provided. | 2010-04-15 |
20100093131 | BONDING APPARATUS AND BONDING METHOD - A bonding apparatus ( | 2010-04-15 |
20100093132 | CHIP MODULE FOR COMPLETE POWER TRAIN - A chip module is disclosed. It includes a circuit substrate, a semiconductor die comprising a power transistor mounted on the circuit substrate, and a passive electronic component. The passive electronic component is in electrical communication with the semiconductor die, and is in thermal communication with the semiconductor die. | 2010-04-15 |
20100093133 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - The electronic device comprises a first substrate | 2010-04-15 |
20100093134 | SEMICONDUCTOR PACKAGE HAVING INSULATED METAL SUBSTRATE AND METHOD OF FABRICATING THE SAME - Provided is a semiconductor package in which an adhesion force between an insulation metal substrate and a molding member is increased by removing a solder mask layer from the insulation metal substrate and a method of fabricating the semiconductor package. The semiconductor package includes an insulation metal substrate that includes a base member, an insulating layer disposed on the base member, and conductive patterns formed on the insulating layer. Semiconductor chips are arranged on the conductive patterns. Solder mask patterns are arranged on the conductive patterns to surround the semiconductor chips. Leads are electrically connected to the conductive patterns through wires. A sealing member is arranged on an upper surface and side surfaces of the substrate to cover portions of the leads, the wires, the semiconductor chips, and the solder mask patterns. | 2010-04-15 |
20100093135 | STRATIFIED UNDERFILL METHOD FOR AN IC PACKAGE - A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board. | 2010-04-15 |
20100093136 | PROCESS FOR MANUFACTURING A CHARGE-BALANCE POWER DIODE AND AN EDGE-TERMINATION STRUCTURE FOR A CHARGE-BALANCE SEMICONDUCTOR POWER DEVICE - An embodiment of a process for manufacturing a semiconductor power device envisages the steps of: providing a body made of semiconductor material having a first top surface; forming an active region with a first type of conductivity in the proximity of the first top surface and inside an active portion of the body; and forming an edge-termination structure. The edge-termination structure is formed by: a ring region having the first type of conductivity and a first doping level, set within a peripheral edge portion of the body and electrically connected to the active region; and a guard region, having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface and connecting the active region to the ring region. The process further envisages the steps of: forming a surface layer having the first type of conductivity on the first top surface, also at the peripheral edge portion, in contact with the guard region; and etching the surface layer in order to remove it above the edge portion in such a manner that the etch terminates inside the guard region. | 2010-04-15 |
20100093137 | Thin Film Transistor Structure and Method of Fabricating the Same - In a thin film transistor (TFT) structure, formation of a spacer layer is used for isolating the NI junction from an insulating layer comprising a nitride, so as to decrease the amount of current leakage and improve the electric characteristics of TFT. In a back-channel etching (BCE) type TFT device, the spacer layer (comprising an oxide layer) is substantially formed at the sidewalls of the channel regions to isolate the insulating layer (comprising silicon nitride) from the NI junctions. In an etch-stop TFT device, the spacer layer (comprising an oxide layer) is substantially formed at the sidewalls of the etch-stop layer to isolate the insulating layer (i.e. etch-stop layer) from the NI junctions. | 2010-04-15 |
20100093138 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to obtain a transistor with a high ON current including a silicide layer without increasing the number of steps. A semiconductor device comprising the transistor includes a first region in which a thickness is increased from an edge on a channel formation region side and a second region in which a thickness is more uniform than that of the first region. The first and second region are separated by a line which is perpendicular to a horizontal line and passes through a point where a line, which passes through the edge of the silicide layer and forms an angle θ (0°<θ<45°) with the horizontal line, intersects with an interface between the silicide layer and an impurity region, and the thickness of the second region to a thickness of a silicon film is 0.6 or more. | 2010-04-15 |
20100093139 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device with improved reliability which includes a metal silicide layer formed by a salicide process. After forming gate electrodes, an n | 2010-04-15 |
20100093140 | GATED RESONANT TUNNELING DIODE - A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region. An insulating layer is formed on the body with the insulating layer extending over the quantum well region and at least a portion of the barrier region, and a control electrode region is formed on the insulating layer. | 2010-04-15 |
20100093141 | METHOD OF MANUFACTURING A TRANSISTOR AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - In a method of manufacturing a transistor, a gate structure is formed on a substrate. First impurities are implanted into the substrate to form an impurity region at an upper portion of the substrate adjacent to the gate structure. An epitaxial layer is formed on the impurity region. An insulation layer having an opening partially exposing the epitaxial layer is formed on the substrate. Second impurities are implanted into a portion of the epitaxial layer exposed by the opening. | 2010-04-15 |
20100093142 | METHOD OF FABRICATING DEVICE - A method of fabricating a device is described. A substrate having at least two isolation structures is provided. A first oxide layer and a first conductive layer are sequentially formed on the substrate between the isolation structures. A first nitridation process is performed to form a first nitride layer on the surface of the first conductive layer and a first oxynitride layer on the surface of the isolation structures. A second oxide layer is formed on the first nitride layer and first oxynitride layer. A densification process is performed to oxidize the first oxynitride layer on the surface of the isolation structures. A second nitride layer and a third oxide layer are sequentially formed on the second oxide layer. A second nitridation process is performed to form a third nitride layer on the surface of the third oxide layer. A second conductive layer is formed on the third nitride layer. | 2010-04-15 |
20100093143 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device including a semiconductor substrate; a plurality of memory cell transistors aligned in a predetermined direction on the semiconductor substrate, each memory cell transistor provided with a first gate electrode including a floating gate electrode comprising a polycrystalline silicon layer of a first thickness, a control gate electrode provided above the floating gate electrode, and an inter-gate insulating film between the floating and the control gate electrode; a pair of select gate transistors on the semiconductor substrate with a pair of second gate electrodes neighboring in alignment with the first gate electrode, each second gate electrode including a lower-layer gate electrode comprising the polycrystalline silicon layer of the first thickness, an upper-layer gate electrode provided above the lower-layer gate electrode; a polyplug of the first thickness situated between the second gate electrodes of the pair of select gate transistors; and a metal plug provided on the polyplug. | 2010-04-15 |
20100093144 | SEMICONDUCTOR DEVICE UTILIZING A METAL GATE MATERIAL SUCH AS TUNGSTEN AND METHOD OF MANUFACTURING THE SAME - Known drawbacks associated with use of tungsten as a gate material in a semiconductor device are prevented. A gate oxide layer, a polysilicon layer, and a nitride layer are sequentially formed on a semiconductor substrate having a isolation layer for defining the active region. A groove is formed by etching the nitride layer. A metal nitride layer is formed to an U shape in the groove, and then a metal layer is formed to bury the groove. A hard mask layer is formed for defining a gate forming region on the nitride layer, the metal nitride layer, and the metal layer. A metal gate is formed by etching the nitride layer, the polysilicon layer, and the gate oxide layer using the hard mask layer as an etch barrier. | 2010-04-15 |
20100093145 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF FOR REDUCING THE AREA OF THE MEMORY CELL REGION - A structure is adopted for a layout of an SRAM cell which provides a local wiring | 2010-04-15 |
20100093146 | METHOD OF MANUFACTURING MULTI-CHANNEL TRANSISTOR DEVICE AND MULTI-CHANNEL TRANSISTOR DEVICE MANUFACTURED USING THE METHOD - A multi-channel transistor device and a method of manufacturing the same are provided. The method of a manufacturing a multi-channel transistor device includes defining an active region in a semiconductor substrate by forming an isolation layer exposing an upper side portion of the active region. An active expanding region is formed on the exposed upper side portion of the active region by selective epitaxial growth (SEG). A portion of the active region is selectively etched to define first channel bars in the active expanding region that extend between first and second laterally separated portions of the active region and a second channel bar that is an unetched portion of the active region. A portion of the isolation layer is selectively removed such as to expose side portions of the second channel bar and bottom surface portions of the first channel bars. A gate is formed on the first and second channel bars with a gate dielectric layer between the gate and the channel bars. A source/drain region is formed in a region of the active expanding region adjacent to the gate, thereby resulting in a multi-channel transistor structure. | 2010-04-15 |
20100093147 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE - A method for forming a semiconductor device includes providing a substrate having at least a gate positioned thereon, forming at least a recess in the substrate adjacent to the gate, performing a first selective epitaxial growth (SEG) process to form a first epitaxial layer in the recess, performing an etching process to remove a portion of the first epitaxial layer to expose the substrate, and performing a second SEG process to form a second epitaxial layer on the first epitaxial layer. | 2010-04-15 |
20100093148 | SILICON GERMANIUM HETEROSTRUCTURE BARRIER VARACTOR - Methods and heterostructure barrier varactor (HBV) diodes optimized for application with frequency multipliers at providing outputs at submillimeter wave frequencies and above. The HBV diodes include a silicon-containing substrate, an electrode over the silicon-containing substrate, and one or more heterojunction quantum wells of alternating layers of Si and SiGe of one or more electrodes of the diode. Each SiGe quantum well preferably has a floating SiGe layer between adjacent SiGe gradients followed by adjacent Si layers, such that, a single homogeneous structure is provided characterized by having no distinct separations. The plurality of Si/SiGe heterojunction quantum wells may be symmetric or asymmetric. | 2010-04-15 |
20100093149 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A conductive film is formed to extend from a bottom and a sidewall of a recess formed in an interlayer insulating film onto a top surface of the interlayer insulating film. Dry etching of the conductive film is performed such that a portion of the conductive film remains on the bottom and sidewall of the recess. The dry etching is also performed such that a deposition film is formed on a top portion of the recess. | 2010-04-15 |
20100093150 | METHOD OF MANUFACTURING CAPACITOR - One capacitor fabrication process of the invention comprises a noble metal layer formation step of forming a noble metal layer on one surface of a substrate, a dielectric layer formation step of forming a dielectric layer on the noble metal layer, a metal foil formation step of forming a metal foil of 10 μm or greater in thickness on the dielectric layer, a separation step of separating the noble metal layer from the dielectric layer at an interface, and an electrode layer formation step of forming an electrode layer on the second surface of the dielectric layer separated off by the separation step, wherein the second surface faces away from the first surface of the dielectric layer with the metal foil formed thereon. | 2010-04-15 |
20100093151 | OXIDE ETCH WITH NH4-NF3 CHEMISTRY - The present invention generally provides apparatus and methods for selectively removing various oxides on a semiconductor substrate. One embodiment of the invention provides a method for selectively removing an oxide on a substrate at a desired removal rate using an etching gas mixture. The etching gas mixture comprises a first gas and a second gas, and a ratio of the first gas and a second gas is determined by the desired removal rate. | 2010-04-15 |
20100093152 | METHOD OF BONDING TWO SUBSTRATES - The invention relates to a method of forming a structure comprising a thin layer of semiconductor material transferred from a donor substrate onto a second substrate, wherein two different atomic species are co-implanted under certain conditions into the donor substrate so as to create a weakened zone delimiting the thin layer to be transferred. The two different atomic species are implanted so that their peaks have an offset of less than 200 Å in the donor substrate, and the substrates are bonded together after roughening at least one of the bonding surfaces. | 2010-04-15 |
20100093153 | MANUFACTURING METHOD OF SOI SUBSTRATE - To prevent, in the case of irradiating a single crystal semiconductor layer with a laser beam, an impurity element from being taken into the single crystal semiconductor layer at the time of laser irradiation. In a manufacturing method of an SOI substrate, a single crystal semiconductor substrate and a base substrate are prepared; an embrittlement region is formed in a region at a predetermined depth from a surface of the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with accelerated ions; the single crystal semiconductor substrate and a base substrate are bonded to each other with an insulating layer interposed therebetween; a single crystal semiconductor layer is formed over the base substrate with the insulating layer interposed therebetween by heating the single crystal semiconductor substrate to cause separation using the embrittlement region as a boundary; an oxide film formed on the single crystal semiconductor layer is removed; and at least a surface of the single crystal semiconductor layer is melted by irradiating the surface of the single crystal semiconductor layer with a laser beam after the removal of the oxide film. The number of times the single crystal semiconductor layer is melted by the irradiation with the laser beam is one. | 2010-04-15 |
20100093154 | DICING/DIE BONDING FILM - A dicing die-bonding film in which the adhesive properties during the dicing step and the peeling properties during the pickup step are controlled so that both become good, and a production method thereof, are provided. The dicing die-bonding film in the present invention is a dicing die-bonding film having a pressure-sensitive adhesive layer on a base material and a die bond layer on the pressure-sensitive adhesive layer, in which the arithmetic mean roughness X (μm) on the pressure-sensitive adhesive layer side in the die bond layer is 0.015 μm to 1 μm, the arithmetic mean roughness Y (μm) on the die bond layer side in the pressure-sensitive adhesive layer is 0.03 μm to 1 μm, and the absolute value of the difference of the X and Y is 0.015 or more. | 2010-04-15 |
20100093155 | DICING/DIE-BONDING FILM, METHOD OF FIXING CHIPPED WORK AND SEMICONDUCTOR DEVICE - A dicing/die-bonding film including a pressure-sensitive adhesive layer ( | 2010-04-15 |
20100093156 | METHOD FOR PRODUCTION OF SILICON WAFER FOR EPITAXIAL SUBSTRATE AND METHOD FOR PRODUCTION OF EPITAXIAL SUBSTRATE - A method for producing a silicon wafer for epitaxial substrate which includes a first step of performing thermal oxidization on a silicon wafer containing boron atoms no less than 1E19 atoms/cm | 2010-04-15 |
20100093157 | METHOD FOR PRODUCING GROUP III NITRIDE-BASED COMPOUND SEMICONDUCTOR CRYSTAL - A GaN single crystal | 2010-04-15 |
20100093158 | Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors and fabricating such devices - A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and may have, at any point along a longitudinal section of such a semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be a single crystal and may be free-standing. Such a semiconductor may be either lightly n-doped, heavily n-doped, lightly p-doped or heavily p-doped. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and a variety of assembling techniques may be used to fabricate devices from such a semiconductor. Two or more of such a semiconductors, including an array of such semiconductors, may be combined to form devices, for example, to form a crossed p-n junction of a device. Such devices at certain sizes may exhibit quantum confinement and other quantum phenomena, and the wavelength of light emitted from one or more of such semiconductors may be controlled by selecting a width of such semiconductors. Such semiconductors and device made therefrom may be used for a variety of applications. | 2010-04-15 |
20100093159 | SEPARATE INJECTION OF REACTIVE SPECIES IN SELECTIVE FORMATION OF FILMS - Methods and apparatuses for selective epitaxial formation of films separately inject reactive species into a CVD chamber. The methods are particularly useful for selective deposition using volatile combinations of precursors and etchants. Formation processes include simultaneous supply of precursors and etchants for selective deposition, or sequential supply for cyclical blanket deposition and selective etching. In either case, precursors and etchants are provided along separate flow paths that intersect in the relatively open reaction space, rather than in more confined upstream locations. | 2010-04-15 |
20100093160 | METHODS OF FORMING NANO-DEVICES USING NANOSTRUCTURES HAVING SELF-ASSEMBLY CHARACTERISTICS - Provided are methods of forming nano-devices. One of the methods includes forming a nano-scale self-assembly material layer on a substrate formed of at least one layer, forming a mask layer on the self-assembly material layer, performing a surface treatment process on the substrate using the mask layer as a mask, and removing the self-assembly material layer. | 2010-04-15 |
20100093161 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - On one face of a semiconductor wafer | 2010-04-15 |
20100093162 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device wherein semiconductor elements (e.g., transistors) respectively formed in multiple independent wells have the same characteristics with the number of production process steps being reduced. A P-type well as an area of a first conductivity type is formed on a semiconductor substrate. Then, second and fourth wells as two regions of a second conductivity type are formed apart from each other in the P-type well, and a first buried well of N-type as a first buried region of the second conductivity type to connect the second and fourth wells is formed at the bottom of a third well (part of the area of the first conductivity type) sandwiched between the second and fourth wells. In this way, a triple well is formed on the semiconductor substrate. | 2010-04-15 |
20100093163 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a method for manufacturing a semiconductor device which includes a step of forming one optional impurity region in a semiconductor substrate at a place apart from the surface thereof, and in the method described above, ion implantation is performed a plurality of times while the position of an end portion of a mask pattern used for ion implantation is changed. | 2010-04-15 |
20100093164 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips. With such a manufacturing method, a reverse-blocking semiconductor device having high reliability can be formed. | 2010-04-15 |
20100093165 | Method of fabricating integrated circuit semiconductor device having gate metal silicide layer - Provided is a method of fabricating an integrated circuit semiconductor device. The method may include forming a plurality of gate patterns spaced apart from each other on a semiconductor substrate, the plurality of gate patterns including gate electrodes and gate capping patterns. After an interlayer insulating layer is formed to insulate the gate patterns, the interlayer insulating layer and the gate capping patterns may be planarized by etching until top surfaces of the gate electrodes are exposed. Gate metal silicide layers may be selectively formed on the gate electrodes. | 2010-04-15 |
20100093166 | Methods of manufacturing a semiconductor device - In a method of manufacturing a semiconductor device, a mask pattern is formed on an active region of a substrate. An exposed portion of the substrate is removed to form a trench in the substrate. A preliminary first insulation layer is formed on a bottom and sidewalls of the trench and the mask pattern. A plasma treatment is performed on the preliminary first insulation layer using fluorine-containing plasma to form a first insulation layer including fluorine. A second insulation layer is formed on the first insulation layer to fill the trench. A thickness of a gate insulation layer adjacent to an upper edge of the trench may be selectively increased, and generation of leakage current may be reduced. | 2010-04-15 |
20100093167 | Methods of Fabricating Field Effect Transistors Having Protruded Active Regions - Provided are a field effect transistor, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor may have a structure in which a double gate field effect transistor and a recess channel array transistor are formed in a single transistor in order to improve a short channel effect which occurs as field effect transistors become more highly integrated, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor can exhibit stable device characteristics even when more highly integrated in such a manner that both the length and width of a channel increase and particularly the channel can be significantly long, and can be manufactured simply. | 2010-04-15 |
20100093168 | AIR GAP INTERCONNECTS USING CARBON-BASED FILMS - A method of forming an interconnect structure comprising: forming a sacrificial inter-metal dielectric (IMD) layer over a substrate, wherein the sacrificial IMD layer comprising a carbon-based film, such as amorphous carbon, advanced patterning films, porous carbon, or any combination thereof; forming a plurality of metal interconnect lines within the sacrificial IMD layer; removing the sacrificial IMD layer, with an oxygen based reactive process; and depositing a non-conformal dielectric layer to form air gaps between the plurality of metal interconnect lines. The metal interconnect lines may comprise copper, aluminum, tantalum, tungsten, titanium, tantalum nitride, titanium nitride, tungsten nitride, or any combination thereof. Carbon-based films and patterned photoresist layers may be simultaneously removed with the same reactive process. Highly reactive hydrogen radicals processes may be used to remove the carbon-based film and simultaneously pre-clean the metal interconnect lines prior to the deposition of a conformal metal barrier liner. | 2010-04-15 |
20100093169 | THROUGH SUBSTRATE VIA PROCESS - A through substrate via (TSV) process is provided. A substrate having a first side and a second side opposite the first side is provided. A plurality of holes is formed in the substrate at the first side. A first dielectric layer is formed on a sidewall and a bottom of the holes. A second dielectric layer is formed in the holes, wherein a material of the second dielectric layer is different from that of the first dielectric layer. A semiconductor device and an interconnect are formed on the substrate at the first side. At least a portion of the substrate at the second side is removed to expose the second dielectric layer in the holes. The second dielectric layer is removed. A conductive layer is formed in the holes. | 2010-04-15 |
20100093170 | METHOD FOR FORMING TUNGSTEN MATERIALS DURING VAPOR DEPOSITION PROCESSES - In one embodiment, a method for forming a tungsten material on a substrate surface is provide which includes positioning a substrate within a deposition chamber, heating the substrate to a deposition temperature, and exposing the substrate sequentially to diborane and a tungsten precursor gas to form a tungsten nucleation layer on the substrate during an atomic layer deposition (ALD) process. The method further provides exposing the substrate to a deposition gas comprising hydrogen gas and the tungsten precursor gas to form a tungsten bulk layer over the tungsten nucleation layer during a chemical vapor deposition (CVD) process. Examples are provided which include ALD and CVD processes that may be conducted in the same deposition chamber or in different deposition chambers. | 2010-04-15 |
20100093171 | FABRICATION CUBIC BORON NITRIDE CONE-MICROSTRUCTURES AND THEIR ARRAYS - A conical structure of cubic Boron Nitride (cBN) is formed on a diamond layered substrate. A method of forming the cBN structure includes steps of (a) forming diamond nuclei on a substrate, (b) growing a layer of diamond film on the substrate, (c) depositing a cBN film on said diamond layer, (d) pre-depositing nanoscale etching masks on the the cBN film, and (e) etching the the deposited cBN film. In particular, though not exclusively, the cubic Boron Nitride structure has great potential applications in probe analytical and testing techniques including scanning probe microscopy (SPM) and nanoindentation, nanomechanics and nanomachining in progressing microelectromechanical system (MEMS) and nanoelectyromechanical system (NEMS) devices, field electron emission, vacuum microelectronic devices, sensors and different electrode systems including those used in electrochemistry. | 2010-04-15 |
20100093172 | METHOD OF FORMING FINE PATTERNS OF A SEMICONDUCTOR DEVICE - A method of forming fine patterns of a semiconductor device includes forming a plurality of first mask patterns on a substrate such that the plurality of first mask patterns are separated from one another by a space located therebetween, in a direction parallel to a main surface of the substrate, forming a plurality of capping films formed of a first material having a first solubility in a solvent on sidewalls and a top surface of the plurality of first mask patterns. The method further includes forming a second mask layer formed of a second material having a second solubility in the solvent, which is less than the first solubility, so as to fill the space located between the plurality of first mask patterns, and forming a plurality of second mask patterns corresponding to residual portions of the second mask layer which remain in the space located between the plurality of first mask patterns, after removing the plurality of capping films and a portion of the second mask layer using the solvent. | 2010-04-15 |
20100093173 | METHOD OF FORMING PATTERNS OF SEMICONDUCTOR DEVICE - A method in the fabrication of a semiconductor device simultaneously forms different patterns on the same level of the device. The device has a first area and a second area. A low density mask pattern of at least one relatively wide topographic feature is formed on the second area, a plurality of relatively narrow topographic features is formed on the first area, first spacers are formed on side walls of the narrow topographic features in the first area, the relatively narrow topographic features are removed, and the patterns of the first spacers and the relatively wide topographic feature(s) are simultaneously transcribed in the first and second areas, respectively. | 2010-04-15 |
20100093174 | METHOD OF MANUFACTURING LOW-K DIELECTRIC FILM, AND FORMATION OF AIR-GAP USING THE LOW-K DIELECTRIC FILM - A dielectric film, a method of manufacturing a dielectric film and a method of forming an air-gap. A method of manufacturing a low-k dielectric film may include introducing TMS and 3,3-dimethyl-1-butene into a plasma deposition reactor, polymerizing TMS and 3,3-dimethyl-1-butene using plasma generated in a reactor to deposit an insulation film over a substrate disposed in a reactor and/or subjecting a deposited insulation film to heat treatment concurrently with an inductively coupled plasma (ICP) process. A dielectric film may have a dielectric constant up to approximately 3. A method of forming an air-gap may include depositing a first insulation film over a surface of a patterned substrate, depositing a decahydronaphthalene layer over a portion of a first insulation film, subjecting a patterned substrate to a polishing process, forming a second insulation film, and/or subjecting a second insulation film to heat treatment concurrently with an ICP process. | 2010-04-15 |
20100093175 | Methods Of Forming Patterns Utilizing Lithography And Spacers - Some embodiments include methods of forming patterns. A first set of features is photolithographically formed over a substrate, and then a second set of features is photolithographically formed over the substrate. At least some of the features of said second set alternate with features of the first set. Spacer material is formed over and between the features of the first and second sets. The spacer material is anisotropically etched to form spacers along the features of the first and second sets. The features of the first and second sets are then removed to leave a pattern of the spacers over the substrate. | 2010-04-15 |
20100093176 | METHOD OF FORMING A SACRIFICIAL LAYER - The present disclosure provides a method for making a semiconductor device. The method includes forming a material layer on a substrate; forming a sacrificial layer on the material layer, where the material layer and sacrificial layer each as a thickness less than 100 angstrom; forming a patterned photoresist layer on the sacrificial layer; applying a first wet etching process to etch the sacrificial layer to form a patterned sacrificial layer using the patterned photoresist layer as a mask; applying a second wet etching process to etch the first material layer; and applying a third wet etching process to remove the patterned sacrificial layer. | 2010-04-15 |
20100093177 | METHOD OF CLEANING SEMICONDUCTOR WAFER AND SEMICONDUCTOR WAFER - A silicon wafer surface other than a defect is oxidized by ozone to form a silicon oxide film. A hydrofluoric acid is sprayed and subsequently a cleaning gas is sprayed onto the surface of the silicon wafer. | 2010-04-15 |
20100093178 | Si ETCHING METHOD - A Si etching method includes: arranging a silicon substrate or a substrate having a silicon layer in a processing chamber; generating a plasma of an etching gas in the processing chamber; and etching the silicon substrate by the plasma. The etching gas is a gaseous mixture including a Br | 2010-04-15 |
20100093179 | PATTERN FORMING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A pattern forming method includes preparing a target object including silicon with an initial pattern formed thereon and having a first line width; performing a plasma oxidation process on the silicon surface inside a process chamber of a plasma processing apparatus and thereby forming a silicon oxide film on a surface of the initial pattern; and removing the silicon oxide film. The pattern forming method is arranged to repeatedly perform formation of the silicon oxide film and removal of the silicon oxide film so as to form an objective pattern having a second line width finer than the first line width on the target object. | 2010-04-15 |
20100093180 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device according to one embodiment includes: forming a first opening pattern and a second opening pattern larger in size than the first opening pattern in a first film formed above a semiconductor substrate and in a second film on the first film, the second film comprising a material different from the first film; forming a blocking film on the second film, the blocking film substantially blocking only the first opening pattern between the first and second opening patterns of the second film; and selectively applying isotropic etching to an inner side face of the second opening pattern of the first film after forming the blocking film, thereby enlarging only the size of the second opening pattern between the size of the first opening pattern and the size of the second opening pattern of the first film. | 2010-04-15 |
20100093181 | PURGE STEP-CONTROLLED SEQUENCE OF PROCESSING SEMICONDUCTOR WAFERS - A method of processing semiconductor substrates includes: depositing a film on a substrate in a reaction chamber; evacuating the reaction chamber without purging the reaction chamber; opening a gate valve and replacing the substrate with a next substrate via the transfer chamber wherein the pressure of the transfer chamber is controlled to be higher than that of the reaction chamber before and while the gate valve is opened; repeating the above steps and removing the substrate from the reaction chamber; and purging and evacuating the reaction chamber, and cleaning the reaction chamber with a cleaning gas. | 2010-04-15 |
20100093182 | LASER CRYSTALLIZATION METHOD FOR AMORPHOUS SEMICONDUCTOR THIN FILM - A laser crystallization method in which an amorphous silicon thin film | 2010-04-15 |
20100093183 | UNIT FOR SUPPLYING CHEMICAL LIQUID AND APPARATUS AND METHOD FOR TREATING SUBSTRATE USING THE SAME - Provided are a unit for supplying chemical liquid, and apparatus and method for treating a substrate using the unit. A pre-wet, photoresist, and edge bead removal nozzles are mounted on a single nozzle body. Therefore, the equipment installing space can be saved as compared with a case where the nozzles are installed on respective nozzle arms, thereby making better use of a space for installing equipments. | 2010-04-15 |
20100093184 | Method for making a metal oxide layer - A method for making a metal oxide layer includes: (a) exposing a substrate having oxygen-containing reaction sites to an environment of a first precursor of an organometallic compound, which contains a metal atom and ligand groups, so as to form a chemisorption layer of the first precursor on the substrate; (b) exposing the chemisorption layer on the substrate to a non-free radical environment of a second precursor after step (a) so as to remove the ligand groups of the chemisorption layer that are unreacted in step (a) and so as to convert the chemisorption layer into a metal oxide layer; and (c) after step (b), exposing the metal oxide layer on the substrate to a free radical-containing gas containing free radicals so as to remove the ligand groups of the chemisorption layer that are left unreacted in step (b). | 2010-04-15 |
20100093185 | METHOD FOR FORMING SILICON OXIDE FILM, PLASMA PROCESSING APPARATUS AND STORAGE MEDIUM - The present invention provides a method for forming a silicon oxide film, with a substantially uniform film thickness and without being so influenced by dense sites and scattered sites in a pattern provided on an object to be processed, while keeping advantageous points of a plasma oxidation process performed under a lower-pressure and lower-oxygen-concentration condition. In this method, plasma of a processing gas is applied to a surface of the object having a concavo-convex pattern, in a processing chamber of a plasma processing apparatus, so as to oxidize silicon on the surface of the object, thereby forming the silicon oxide film. The plasma is generated under the condition that a ratio of oxygen in the processing gas is within a range of 0.1% to 10% and pressure is within a range of 0.133 Pa to 133.3 Pa. This plasma oxidation process is performed, with a plate, having a plurality of through-holes formed therein, being provided between a region for generating the plasma in the processing chamber and the object to be processed. | 2010-04-15 |
20100093186 | METHOD FOR FORMING SILICON OXIDE FILM, PLASMA PROCESSING APPARATUS AND STORAGE MEDIUM - The present invention provides a method for forming a silicon oxide film, with a substantially uniform film thickness and without being so influenced by dense sites and scattered sites in a pattern provided on an object to be processed, while keeping advantageous points of a plasma oxidation process performed under a lower-pressure and lower-oxygen-concentration condition. In this method, plasma of a processing gas is applied to a surface of the object having a concavo-convex pattern, in a processing chamber of a plasma processing apparatus, so as to oxidize silicon on the surface of the object, thereby forming the silicon oxide film. The plasma is generated under the condition that a ratio of oxygen in the processing gas is within a range of 0.1% to 10% and pressure is within a range of 0.133 Pa to 133.3 Pa. This plasma oxidation process is performed, with a plate, having a plurality of through-holes formed therein, being provided between a region for generating the plasma in the processing chamber and the object to be processed. | 2010-04-15 |
20100093187 | Method for Depositing Conformal Amorphous Carbon Film by Plasma-Enhanced Chemical Vapor Deposition (PECVD) - Methods and apparatus for depositing an amorphous carbon layer on a substrate are provided. In one embodiment, a deposition process includes positioning a substrate in a substrate processing chamber, introducing a hydrocarbon source having a carbon to hydrogen atom ratio of greater than 1:2 into the processing chamber, introducing a plasma initiating gas selected from the group consisting of hydrogen, helium, argon, nitrogen, and combinations thereof into the processing chamber, with the hydrocarbon source having a volumetric flow rate to plasma initiating gas volumetric flow rate ratio of 1:2 or greater, generating a plasma in the processing chamber, and forming a conformal amorphous carbon layer on the substrate. | 2010-04-15 |
20100093188 | HINGE STRUCTURE WITH ELECTRICAL CONNECTOR - A hinge structure with an electrical connector is connected to a first body of an electronic device through a support frame. A pivot portion of the hinge structure is connected to a second body of the electronic device and includes a rotating shaft connected to the support frame, such that the first body is capable of rotating relative to the second body. The electrical connector is a power input connector disposed on the support frame, such that a power line is inserted in the power input connector to electrically connect to the electronic device. | 2010-04-15 |
20100093189 | CONNECTOR ASSEMBLY HAVING SIGNAL AND COAXIAL CONTACTS - A connector assembly includes a housing and contacts. The housing is configured to mate with a mating connector. The contacts are in the housing and configured to electrically connect the connector assembly with the mating connector. The contacts are arranged in a coaxial signal contact pattern. The coaxial signal contact pattern includes a center signal contact surrounded by contacts electrically connected to an electrical ground in a manner to emulate a coaxial connection with the mating connector. | 2010-04-15 |
20100093190 | ELECTRICAL CONNECTION BODY - In an electrical connection body, a carrier is formed with a through-hole and a wall portion formed upright by a groove portion on both sides of the through-hole, and a connector is provided with a first beam on one end of a connecting portion and a second beam on the other end of the connecting portion, and is also provided with regulating portions on both sides of the connecting portion on the side of the first beam. The regulating portions come into contact with the wall portion to regulate the axial rotation of the connector. The first beam and the second beam are bent with respect to the connecting portion and come into contact with respective opening portions of the through-hole, to thereby regulate the movement of the connector in the forming direction of the through-hole. | 2010-04-15 |
20100093191 | ELECTRICAL CONTACT WITH STOPPER AND ELECTRICAL CONNECTOR HAVING THE SAME - An electrical contact ( | 2010-04-15 |
20100093192 | CONNECTION STRUCTURE BETWEEN SIGNAL TRANSMITTING BOARDS - A connection structure between signal transmitting boards includes a flexible signal transmitting board and a generic signal transmitting board. The generic signal transmitting board has a transmitting base which defines a limiting opening. The flexible signal transmitting board has a flexible base positioned at a side of the transmitting base. The flexible base defines a positioning slice which extends to the other side of the transmitting base via the limiting opening for locating the generic signal transmitting board and the flexible signal transmitting board together. | 2010-04-15 |
20100093193 | CONNECTOR ASSEMBLY HAVING A COMPRESSIVE COUPLING MEMBER - A connector assembly includes a housing, a contact and a compressive coupling member. The housing has a mating interface and a mounting interface on opposing sides of the housing. The mounting interface is configured to engage a first substrate when the housing is mounted to the first substrate. The mating interface is configured to mate with a mating connector that is mounted to a second substrate. The housing is configured to engage and interconnect the substrates in a parallel arrangement. The contact extends between and protrudes from the interfaces of the housing and is configured to provide an electrical connection between the substrates. The compressive coupling member is configured to extend through the substrates and the housing in a direction transverse to the interfaces. The coupling member is configured to apply a compressive force to the housing to secure the housing with the mating connector to electrically and mechanically interconnect the substrates. | 2010-04-15 |
20100093194 | CONNECTOR ASSEMBLY WITH VARIABLE STACK HEIGHTS HAVING POWER AND SIGNAL CONTACTS - A connector assembly includes a housing, a signal contact and a power contact. The housing has a mounting body and a mating body coupled together and separated by a gap. The gap permits air to flow between the lower and mating bodies. The mating body is configured to engage an upper substrate and the mounting body is configured to engage a lower substrate to mechanically interconnect the upper and lower substrates. The signal contact extends between and protrudes from the mating and mounting bodies and is configured to communicate a data signal between the mating and mounting bodies. The power contact extends between and protrudes from the mating and mounting bodies and is configured to communicate electrical power between the upper and lower substrates. The housing separates the upper and lower substrates by a predetermined stack height. | 2010-04-15 |
20100093195 | CONNECTOR ASSEMBLY HAVING MULTIPLE CONTACT ARRANGEMENTS - A connector assembly includes a housing and substantially identical contacts. The housing is configured to mate with a mating connector. The contacts are arranged in a plurality of sets in the housing. The contacts are configured to electrically couple with the mating connector. Each set of contacts is arranged to communicate a different type of data signal with the mating connector. Optionally the contacts are formed as substantially identical pins. The different sets of contacts may concurrently communicate the different types of data signals. | 2010-04-15 |
20100093196 | SOCKET CONNECTOR HAVING CONTACTS ARRANGED BETWEEN STANDOFFS - An electrical connector assembly ( | 2010-04-15 |
20100093197 | CONNECTION DEVICE - The invention relates to contact pins for providing an electrical connection between electronic devices. In one aspect the pin is adapted to be inserted into a hole of a circuit carrier and the pin comprises at least three portions; namely a contact termination portion, an electrical contact portion and a mechanical fastening portion. The mechanical fastening portion preferably allows a fastening of the contact pin without any soldering. | 2010-04-15 |
20100093198 | Safety protection structure for universal sockets - A safety protection structure for universal sockets, comprising: a second module; a second slant to contact the second pin of a 3-pin plug; a sliding chute configured in parallel to the movement direction of the second module; a third module; a third slant to contact the third pin of a 3-pin plug, and matching the sliding chute of the second module. The sliding chute is configured to ensure that the third and the second module are relatively independent and movable. The second module and third module are respectively configured with a surface area to block the second pin and third pin of the 3-pin plug at the same time. In this configuration, the insulation board is closed when the pin of the plug is inserted incorrectly preventing the pin from contacting the conducting plate in the socket, and the insulation boards in the jacks not inserted with the pins remain closed. | 2010-04-15 |