15th week of 2011 patent applcation highlights part 6 |
Patent application number | Title | Published |
20110084296 | Light Emitting Diode and Manufacturing Method Thereof - A light emitting diode manufacturing method introduces a transparent enclosure to improve the uniformity of coating phosphor, so as to achieve the purposes of enhancing the uniform color temperature and the light emitting efficiency. The manufacturing method is used extensively for packaging various types of light emitting diode chips and mass production. | 2011-04-14 |
20110084297 | MOLDED RESIN PRODUCT, SEMICONDUCTOR LIGHT-EMITTING SOURCE, LIGHTING DEVICE, AND METHOD FOR MANUFACTURING MOLDED RESIN PRODUCT - A molded resin product or the like that is provided with a phosphor layer made of gel-like or rubber-like resin that can maintain its shape for a long period and that can be implemented easily. The molded resin product (phosphor layer | 2011-04-14 |
20110084298 | LIGHT EMITTING DIODE AND METHOD FOR MAKING SAME - A light emitting diode comprises a heat conductive layer, a semiconductor layer disposed above the heat conductive substrate and consisting of a p-type semiconductor layer, an active layer and an n-type semiconductor layer, a transparent electrode layer, a current blocking layer and an electrode contact pad. The p-type semiconductor layer has first concaves located on its surface distant from the active layer. The n-type semiconductor layer has second concaves located on its surface distant from the active layer. The transparent electrode layer is located on the surface of the n-type semiconductor layer except the second concaves. The current blocking layer is located in the first concaves of the p-type semiconductor layer. The electrode contact pad is located on the surface of the transparent electrode layer. The density of the second concaves decrease with distance from the electrode contact pad. | 2011-04-14 |
20110084299 | LED LIGHT SOURCE AND MANUFACTURING METHOD FOR THE SAME - An LED light source can include protection members to protect bonding wires. The LED can include a substrate including electrode patterns, a sub mount substrate located on the substrate, at least one flip LED chip mounted on the sub mount substrate and a phosphor rein covering the LED chip. The bonding wires can connect each of the electrode patterns to conductor patterns connecting to electrodes of the LED chip. The protection members can be located so as to surround both sides of the bonding wires. In addition, because each height of the protection members is higher than each maximum height of the bonding wires and is lower than a height of the phosphor resin, the protection members can protect the bonding wires from external pressure while the light flux is not reduced. Thus, the disclosed subject matter can provide a reliable LED light source having a favorable light distribution. | 2011-04-14 |
20110084300 | LIGHT EMITTING DIODE DEVICE, LIGHT EMITTING APPARATUS AND METHOD OF MANUFACTURING LIGHT EMITTING DIODE DEVICE - Provided is a light emitting diode device. The light emitting diode device includes a light emitting diode chip having a first surface on which first and second electrodes are disposed, and a second surface opposing the first surface, a wavelength conversion portion including fluorescent substances and covering the first surface and side surfaces of the light emitting diode chip, wherein the side surfaces denote surfaces placed between the first and second surfaces, and first and second electricity connection portions each including a plating layer, respectively connected to the first and second electrodes, and exposed to the outside of the wavelength conversion portion. Accordingly, the light emitting diode device, capable of enhancing luminous efficiency and realizing uniform product characteristics in terms of the emission of white light, is provided. Further, a process for easily and efficiently manufacturing the above light emitting diode device is provided. | 2011-04-14 |
20110084301 | PACKAGE-INTEGRATED THIN FILM LED - LED epitaxial layers (n-type, p-type, and active layers) are grown on a substrate. For each die, the n and p layers are electrically bonded to a package substrate that extends beyond the boundaries of the LED die such that the LED layers are between the package substrate and the growth substrate. The package substrate provides electrical contacts and conductors leading to solderable package connections. The growth substrate is then removed. Because the delicate LED layers were bonded to the package substrate while attached to the growth substrate, no intermediate support substrate for the LED layers is needed. The relatively thick LED epitaxial layer that was adjacent the removed growth substrate is then thinned and its top surface processed to incorporate light extraction features. There is very little absorption of light by the thinned epitaxial layer, there is high thermal conductivity to the package because the LED layers are directly bonded to the package substrate without any support substrate therebetween, and there is little electrical resistance between the package and the LED layers so efficiency (light output vs. power input) is high. The light extraction features of the LED layer further improves efficiency. | 2011-04-14 |
20110084302 | WAVELENGTH CONVERTED LIGHT EMITTING DIODE WITH REDUCED EMISSION OF UNCONVERTED LIGHT - A method for the manufacture of a wavelength converted light emitting device is provided. A light curable coating material is arranged on the outer surface of a wavelength converted light emitting diode. The light curable coating material is cured, in positions where a high intensity of unconverted LED-light encounters the curable coating material. The method can be used to selectively stop unconverted light from exiting the device, leading to a wavelength converted LED essentially only emitting converted light. | 2011-04-14 |
20110084303 | RADIANT HEAT STRUCTURE FOR PIN TYPE POWER LED - The present invention relates to the heat-radiation structure of a pin-type power Light Emitting Diode (LED). The heat-radiation structure includes an LED device, first and second lead frames, a mold unit, and a heat sink. The first lead frame is electrically connected to the LED device, and extended forward to the outside in order to supply power to the LED device. The second lead frame is provided to face the first lead frame, and extended forward to the outside. The mold unit includes the LED device, and molds the upper portions of the first and second lead frames out transparent material. The heat sink is provided at a bottom of the mold unit so that the lead frames penetrate therethrough, fixed into any of the two lead frames, and configured to receive heat from the lead frame which comes into contact therewith and to radiate the heat to the outside. | 2011-04-14 |
20110084304 | LIGHT EMITTING DEVICE AND METHOD OF FORMING THE SAME - An embodiment of present invention discloses a light-emitting device comprising a first multi-layer structure comprising a first lower layer; a first upper layer; and a first active layer able to emit light under a bias voltage and positioned between the first lower layer and the first upper layer; a second thick layer neighboring the first multi-layer structure; a second connection layer associated with the second thick layer; a connective line electrically connected to the second connection layer and the first multi-layer structure; a substrate; and two or more ohmic contact electrodes between the first multi-layer structure and the substrate. | 2011-04-14 |
20110084305 | NITRIDE-BASED SEMICONDUCTOR LIGHT EMITTING DIODE - A nitride-based semiconductor LED includes a substrate; an n-type nitride semiconductor layer formed on the substrate; an active layer and a p-type nitride semiconductor layer that are sequentially formed on a predetermined region of the n-type nitride semiconductor layer; a transparent electrode formed on the p-type nitride semiconductor layer; a p-electrode pad formed on the transparent electrode, the p-electrode pad being spaced from the outer edge line of the p-type nitride semiconductor layer by 50 to 200 μm; and an n-electrode pad formed on the n-type nitride semiconductor layer. | 2011-04-14 |
20110084306 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device and corresponding method of manufacture, where the semiconductor light emitting device includes a light emitting structure, a second electrode layer, an insulating layer, and a protrusion. The light emitting structure comprises a second conductive semiconductor layer, an active layer under the second conductive semiconductor layer, and a first conductive semiconductor layer under the active layer. The second electrode layer is formed on the light emitting structure. The insulating layer is formed along the circumference of the top surface of the light emitting structure. The protrusion protrudes from the undersurface of the insulating layer to the upper part of the first conductive semiconductor layer. | 2011-04-14 |
20110084307 | METHOD FOR PRODUCING GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE, GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND LAMP - One object of the present invention is to provide a method for producing a group III nitride semiconductor light-emitting device which has excellent productivity and produce a group III nitride semiconductor light-emitting device and a lamp, a method for producing a group III nitride semiconductor light-emitting device, in which a buffer layer ( | 2011-04-14 |
20110084308 | SEMICONDUCTOR ARRANGEMENT AND A METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor arrangement is disclosed. The method comprises forming at least one trench in a dielectric layer, thereby exposing a portion of a semiconductor substrate, forming a silicon-germanium buffer layer at least on the bottom of the at least one trench, forming a germanium seed layer on the silicon-germanium buffer layer and forming a germanium layer on the germanium seed layer. A semiconductor arrangement is also disclosed. The semiconductor arrangement comprises a semiconductor substrate, a dielectric layer disposed above the semiconductor substrate, at least one trench in the dielectric layer exposing a portion of the semiconductor substrate, a silicon-germanium buffer layer disposed above at least the bottom of the at least one trench, a germanium seed layer disposed above the silicon-germanium buffer layer and a germanium layer disposed above the germanium seed layer. | 2011-04-14 |
20110084309 | METHOD FOR ENHANCING THE RELIABILITY OF A P-CHANNEL SEMICONDUCTOR DEVICE AND A P-CHANNEL SEMICONDUCTOR DEVICE MADE THEREOF - A method for forming a semiconductor device is disclosed. The device includes a control electrode on a semiconductor P-channel layer having at least a gate dielectric layer. The gate dielectric layer has an exponentially decreasing density of defect levels E | 2011-04-14 |
20110084310 | METHOD FOR OBTAINING A STRUCTURED MATERIAL WITH THROUGH OPENINGS, IN PARTICULAR NITRIDES OF TYPE III SEMICONDUCTORS STRUCTURED ACCORDING TO PHOTONIC CRYSTAL PATTERNS - A method of manufacture of a optical, photonic or optoelectronic component, including a so-called photonic slab or membrane that is traversed, in at least one internal region and according to a predetermined pattern, by a plurality of through openings having a micrometric or sub-micrometric transverse dimension, the method having the following steps: structuring of the surface of a substrate by an etching that produces holes in the substrate according to the pattern; depositing at least one layer of the photonic material forming the slab or membrane, by anisotropic epitaxial growth on the structured surface of the substrate around the opening of the holes. | 2011-04-14 |
20110084311 | Group III-V semiconductor device with strain-relieving interlayers - According to one exemplary embodiment, a group III-V semiconductor device includes at least one transition layer situated over a substrate. The group III-V semiconductor device further includes a first strain-relieving interlayer situated over the at least one transition layer and a second strain-relieving interlayer situated over the first strain-relieving interlayer. The group III-V semiconductor device further includes a first group III-V semiconductor body situated over the second strain-relieving interlayer. The first and second strain-relieving interlayers comprise different semiconductor materials so as to reduce a strain in the first group III-V semiconductor body. The second strain-relieving interlayer can be substantially thinner than the first strain-relieving interlayer. | 2011-04-14 |
20110084312 | Methods for Cell Boundary Encroachment and Layouts Implementing the Same - A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device. | 2011-04-14 |
20110084313 | Methods for Manufacturing Dense Integrated Circuits - One inventive aspect relates to a method for forming integrated circuits and circuits obtained therewith. The method of forming a circuit pattern in a device layer of a semiconductor substrate comprises decomposing the circuit pattern in two constituent orthogonal subpatterns. The method further comprises transferring the pattern of a first subpattern to a hard mask layer overlying the device layer. The method further comprises transferring the pattern of the other subpattern to a photosensitive layer overlying the patterned hard mask layer. The method further comprises patterning the device layer using the patterned hard mask layer and the patterned photosensitive layer as a mask. The method further comprises removing the patterned hard mask layer and the patterned photosensitive layer. Furthermore memory or logic circuits obtained using the above technique are described. | 2011-04-14 |
20110084314 | SYSTEM COMPRISING A SEMICONDUCTOR DEVICE AND STRUCTURE - A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern. | 2011-04-14 |
20110084315 | SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL) - A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner. | 2011-04-14 |
20110084316 | PICKUP DEVICE AND METHOD FOR MANUFACTURING THE SAME - A pickup device according to the present invention includes a photoelectric conversion portion, a charge holding portion configured to include a first semiconductor region, and a transfer portion configured to include a transfer gate electrode that controls a potential between the charge holding portion and a sense node. A second semiconductor region is disposed on a surface of a semiconductor region between the control electrode and the transfer gate electrode. A third semiconductor region is disposed below the second semiconductor region. An impurity concentration of the third semiconductor region is higher than the impurity concentration of the first semiconductor region. | 2011-04-14 |
20110084317 | BACK-ILLUMINATED TYPE SOLID-STATE IMAGING DEVICE - A back-illuminated type solid-state imaging device including (a) a semiconductor layer on a front surface side of a semiconductor substrate with an insulation film between them; (b) a photoelectric conversion element that constitutes a pixel in the semiconductor substrate; (c) at least part of transistors that constitute the pixel in the semiconductor film; and (d) a rear surface electrode to which a voltage is applied on the rear surface side of the semiconductor substrate, wherein, (1) a semiconductor layer of an opposite conduction type to a charge accumulation portion of the photoelectric conversion element is formed in the semiconductor substrate under the insulation film, and (2) the same voltage as the voltage applied to the rear surface electrode is applied to the semiconductor layer. | 2011-04-14 |
20110084318 | DEPLETED TOP GATE JUNCTION FIELD EFFECT TRANSISTOR (DTGJFET) - A junction field effect transistor semiconductor device and method can include a top gate interposed between a source region and a drain region, and which can extend across an entire surface of the channel region from the source region to the drain region. Top gate doping can be configured such that the top gate can remain depleted throughout operation of the device. An embodiment of a device so configured can be used in precision, high-voltage applications. | 2011-04-14 |
20110084319 | Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current - A method (and semiconductor device) of fabricating a TFET device provides a source region having at least a portion thereof positioned underneath a gate dielectric. In one embodiment, the TFET includes an N+ drain region and a P+ source region in a silicon substrate, where the N+ drain region is silicon and the P+ source region is silicon germanium (SiGe). The source region includes a first region of a first type (e.g., P+ SiGe) and a second region of a second type (undoped SiGe), where at least a portion of the source region is positioned below the gate dielectric. This structure decreases the tunneling barrier width and increases drive current (Id). | 2011-04-14 |
20110084320 | SEMICONDUCTOR DEVICE INCLUDING METAL SILICIDE LAYER AND METHOD FOR MANUFACTURING THE SAME - A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating later connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon. | 2011-04-14 |
20110084321 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to provide a semiconductor device where, even in a case of stacking a plurality of semiconductor elements provided over a substrate, the stacked semiconductor elements can be electrically connected through the substrate, and a manufacturing method thereof. According to one feature of the present invention, a method for manufacturing a semiconductor device includes the steps of selectively forming a depression in an upper surface of a substrate or forming an opening which penetrates the upper surface through a back surface; forming an element group having a transistor so as to cover the upper surface of the substrate and the depression, or the opening; and exposing the element group formed in the depression or the opening by thinning the substrate from the back surface. A means for thinning the substrate can be performed by partially removing the substrate by performing grinding treatment, polishing treatment, etching by chemical treatment, or the like from the back surface of the substrate. | 2011-04-14 |
20110084322 | CMOS IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - Disclosed is a CMOS image sensor and a manufacturing method thereof. According to an aspect of the present invention, each pixel of CMOS image sensor includes a photo detector that includes an electon Collection layer doped with a concentration of 5×10 | 2011-04-14 |
20110084323 | Transistor Performance Modification with Stressor Structures - A transistor structure with stress enhancement geometry aligned above the channel region. Also, a transistor structure with stress enhancement geometries located above and aligned with opposite sides of the channel region. Furthermore, methods for fabricating integrated circuits containing transistors with stress enhancement geometries. | 2011-04-14 |
20110084324 | RADIATION HARDENED MOS DEVICES AND METHODS OF FABRICATION - Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a bird's beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the bird's beak region and terminating at the inner edge of the bird's beak region, a gate crossing the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the guard region. A variation of a local oxidation of silicon process is used with an additional bird's beak implantation mask as well as minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density. | 2011-04-14 |
20110084325 | DRAM STRUCTURE WITH A LOW PARASITIC CAPACITANCE AND METHOD OF MAKING THE SAME - An oxide spacer for stack DRAM gate stack is described, including: a semiconductor substrate with a memory array region and a periphery region, a plurality of gates disposed within the memory array region and the periphery region respectively, a silicon oxide spacer disposed on the gates, where the polysilicon contact plugs are formed by polysilicon deposition and chemical mechanical polish. After polysilicon contact plugs are formed, a silicon oxide layer is deposited to isolate the contacts and gate. The silicon oxide layer on top of contact plug is removed by chemical mechanical polish achieve planarization. | 2011-04-14 |
20110084326 | Densely-Paced Films of Lanthanide Oxide Nanoparticles Via Electrophoretic Deposition - A method of forming a film of lanthanide oxide nanoparticles. In one embodiment of the present invention, the method includes the steps of: (a) providing a first substrate with a conducting surface and a second substrate that is positioned apart from the first substrate, (b) applying a voltage between the first substrate and the second substrate, (c) immersing the first substrate and the second substrate in a solution that comprises a plurality of lanthanide oxide nanoparticles suspended in a non-polar solvent or apolar solvent for a first duration of time effective to form a film of lanthanide oxide nanoparticles on the conducting surface of the first substrate, and (d) after the immersing step, removing the first substrate from the solution and exposing the first substrate to air while maintaining the applied voltage for a second duration of time to dry the film of lanthanide oxide nanoparticles formed on the conducting surface of the first substrate. | 2011-04-14 |
20110084327 | 3-D ELECTRICALLY PROGRAMMABLE AND ERASABLE SINGLE-TRANSISTOR NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile memory device includes a source region, a drain region, and a channel region therebetween. The channel region has a length extending from the source region to the drain region and a channel width in the direction perpendicular to the channel length direction. The device includes a floating gate positioned between the source and the drain in the channel length direction. The width of the floating gate is less than the channel width. A control gate covers a top surface and a side surface of the floating gate. The control gate also overlies an entirety of the channel region. Erasure of the cell is accomplished by Fowler-Nordheim tunneling from the floating gate to the control gate. Programming is accomplished by electrons migrating through an electron concentration gradient from a channel region underneath the control gate into a channel region underneath the floating gate and then injecting into the floating gate. | 2011-04-14 |
20110084328 | NON-VOLATILE MEMORY HAVING NANO CRYSTALLINE SILICON HILLLOCKS FLOATING GATE - A method for making a non-volatile memory device provides a semiconductor substrate including a surface region and a tunnel dielectric layer overlying the surface region. Preferably the tunnel dielectric layer is a high-K dielectric, characterized by a dielectric constant higher than 3.9. The method forms a source region within a first portion and a drain region within a second portion of the semiconductor substrate. The method includes forming a first and second nanocrystalline silicon structures overlying the first and second portions between the source region and the drain region to form a first and second floating gate structures while maintaining a separation between the first and second nanocrystalline silicon structures. The method includes forming a second dielectric layer overlying the first and second floating gate structures. The method also includes forming a control gate structure overlying the first and second floating gate structures. | 2011-04-14 |
20110084329 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a semiconductor layer including a cell region and a peripheral region, a cell region gate structure disposed in the cell region of the semiconductor layer, and wherein the cell region gate structure includes a tunneling insulating layer and a first blocking insulating layer, a second blocking insulating layer, and a third blocking insulating layer. The non-volatile memory device further includes a peripheral region gate structure formed in the peripheral region of the semiconductor layer. The peripheral region gate structure includes a first peripheral region insulating layer including a same material as a material included in the tunneling insulating layer and a second peripheral region insulating layer including a same material as a material included in the third blocking insulating layer. | 2011-04-14 |
20110084330 | LOCAL INTERCONNECT HAVING INCREASED MISALIGNMENT TOLERANCE - A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area. | 2011-04-14 |
20110084331 | SEMICONDUCTOR DEVICE - A semiconductor device has a substrate, a source region formed on the surface portion of the substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, a second insulating layer formed on the gate electrode, a body section connected with the source region, penetrating through the first insulating layer, the gate electrode and the second insulating layer, and containing a void, a gate insulating film surrounding the body section, and formed between the body section and the gate electrode, and a drain region connected with the body section. | 2011-04-14 |
20110084332 | TRENCH TERMINATION STRUCTURE - A trench MOS device includes a base semiconductor substrate, an epitaxial layer grown on the base semiconductor substrate, a first trench in the epitaxial layer, and a stepped trench comprising a second trench and a third trench in the epitaxial layer. There is a mesa between the first trench and the stepped trench. There is a spacer on a the sidewall of the second trench, wherein the third trench having a depth below the spacer. There is a dielectric layer extending along sidewalls and bottom walls of the second trench and the third trench. There is also a metal layer extending over the first trench, over a sidewall of the stepped trench and a portion of the bottom of the stepped trench. | 2011-04-14 |
20110084333 | POWER DEVICES WITH SUPER JUNCTIONS AND ASSOCIATED METHODS MANUFACTURING - Power devices with super junctions and associated methods of manufacturing are disclosed herein. In one embodiment, a method for forming a power device includes forming an epitaxial layer on a substrate material and forming a trench in the epitaxial layer. The trench has a first sidewall, a second sidewall, and a bottom between the first and second sidewalls. The method also includes forming an insulation material on at least one of the first and second sidewalls of the trench and diffusing a dopant into the epitaxial layer via at least one of the first and second sidewalls of the trench via the insulation material. | 2011-04-14 |
20110084334 | BILATERAL CONDUCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A bilateral conduction semiconductor device and a manufacturing method thereof are provided. The bilateral conduction semiconductor device includes an epitaxial layer having a first conductive type and a first trench, a first gate conductive layer disposed on a sidewall of the first trench, a second gate conductive layer disposed opposite to the first gate conductive layer, and a doped region having the first conductive type. The doped region is disposed in the epitaxial layer between the first gate conductive layer and the second gate conductive layer, and a doped concentration of the doped region is larger than a doped concentration of the epitaxial layer. | 2011-04-14 |
20110084335 | SEMICONDUCTOR DEVICE WITH DRAIN VOLTAGE PROTECTION AND MANUFACTURING METHOD THEREOF - A power semiconductor device with drain voltage protection includes a semiconductor substrate, at least a trench gate transistor device and at least a trench ESD protection device. An upper surface of the semiconductor substrate has a first trench and a second trench. The trench gate transistor device is disposed in the first trench and the semiconductor substrate. The trench ESD protection device is disposed in the second trench, and includes a first doped region, a second doped region and a third doped region. The first doped region and the third doped region are respectively electrically connected to a drain and a gate of the trench gate transistor device. | 2011-04-14 |
20110084336 | SEMICONDUCTOR DEVICE WITH STRESSED FIN SECTIONS, AND RELATED FABRICATION METHODS - A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections. | 2011-04-14 |
20110084337 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - As for a semiconductor device which is typified by a display device, it is an object to provide a highly reliable semiconductor device to which a large-sized or high-definition screen is applicable and which has high display quality and operates stably. By using a conductive layer including Cu as a long lead wiring, an increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased. | 2011-04-14 |
20110084338 | Semiconductor Device and Method of Manufacturing Same - An object is to reduce the adverse influence which a portion of a gate insulating layer where the thickness has decreased, that is, a step portion, has on semiconductor element characteristics so that the reliability of the semiconductor element is improved. A semiconductor layer is formed over an insulating surface; a side surface of the semiconductor layer is oxidized using wet oxidation to form a first insulating layer; a second insulating layer is formed over the semiconductor layer and the first insulating layer; and a gate electrode is formed over the semiconductor layer and the first insulating layer with the second insulating layer interposed therebetween. | 2011-04-14 |
20110084339 | SEMICONDUCTOR DEVICE AND METHOD OF ELECTROSTATIC DISCHARGE PROTECTION THEREFOR - A semiconductor device comprises at least one switching element. The at least one switching element comprises a first channel terminal, a second channel terminal and a switching terminal, the switching element being arranged such that an impedance of the switching element between the first and second channel terminals is dependant upon a voltage across the switching terminal and the first channel terminal. The semiconductor device further comprises a resistance element operably coupled between the first channel terminal of the at least one switching element and a reference node, and a clamping structure operably coupled between the switching terminal of the switching element and the reference node. The resistance element and the clamping structure are arranged such that, when current flowing through the at least one switching element, between the first and second channel terminals, exceeds a threshold current value, a voltage drop across the resistance element exceeds a difference between (i) a clamping voltage of the clamping structure and (ii) a switching voltage threshold of the at least one switching element, causing the impedance between the first and second channel terminals of the at least one switching component to increase. | 2011-04-14 |
20110084340 | Voids in STI Regions for Forming Bulk FinFETs - An integrated circuit structure includes a substrate; two insulation regions over the substrate, with one of the two insulation regions including a void therein; and a first semiconductor strip between and adjoining the two insulation regions. The first semiconductor strip includes a top portion forming a fin over top surfaces of the two insulation regions. | 2011-04-14 |
20110084341 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate having a rectangular shape, and a via hole that has an elliptic shape or a track shape having a linear portion in a long-axis direction of the track shape, a long axis of the elliptic shape or the track shape being arranged in a long-side direction of the substrate. | 2011-04-14 |
20110084342 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Latchup is prevented from occurring accompanying increasingly finer geometries of a chip. NchMOSFET N | 2011-04-14 |
20110084343 | Monolithic IC and MEMS microfabrication process - Monolithic IC/MEMS processes are disclosed in which high-stress silicon nitride is used as a mechanical material while amorphous silicon serves as a sacrificial layer. Electronic circuits and micro-electromechanical devices are built on separate areas of a single wafer. The sequence of IC and MEMS process steps is designed to prevent alteration of partially completed circuits and devices by subsequent high process temperatures. | 2011-04-14 |
20110084344 | MEMS DEVICE WITH A COMPOSITE BACK PLATE ELECTRODE AND METHOD OF MAKING THE SAME - A method of fabricating MEMS device includes: providing a substrate with a first surface and a second surface. The substrate includes at least one logic region and at least one MEMS region. The logic region includes at least one logic device positioned on the first surface of the substrate. Then, an interlayer material is formed on the first surface of the substrate within the MEMS region. Finally, the second surface of the substrate within the MEMS region is patterned. After the pattern process, a vent pattern is formed in the second surface of the substrate within the MEMS region. The interlayer material does not react with halogen radicals. Therefore, during the formation of the vent pattern, the substrate is protected by the interlayer material and the substrate can be prevented from forming any undercut. | 2011-04-14 |
20110084345 | Apparatuses for generating electrical energy - Electrical energy generation apparatuses, in which a solar battery device and a piezoelectric device are combined in a single body by using a plurality of nano wires formed of a semiconductor material having piezoelectric properties. | 2011-04-14 |
20110084346 | Pressure sensor and method of manufacturing the same - The present invention provides a pressure sensor and a method of manufacturing the same, which can change resistance to load smoothly in a relatively small load range and detect the pressure to the extent of relatively large load range. An uneven layer | 2011-04-14 |
20110084347 | MAGNETIC TUNNEL JUNCTION DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a magnetic tunnel junction device and a manufacturing method thereof. The magnetic tunnel junction device includes i) a first magnetic layer having an switchable magnetization direction, ii) a nonmagnetic layer provided on the first magnetic layer, iii) a second magnetic layer provided on the nonmagnetic layer and having a fixed magnetization direction, iv) an oxidation-preventing layer provided on the second magnetic layer, v) a third magnetic layer provided on the oxidation-preventing layer and fixing the magnetization direction of the second magnetic layer through magnetic coupling with the second magnetic layer, and vi) an antiferromagnetic layer provided on the third magnetic layer and fixing a magnetization direction of the third magnetic layer. | 2011-04-14 |
20110084348 | MAGNETORESISTANCE ELEMENT, METHOD OF MANUFACTURING THE SAME, AND STORAGE MEDIUM USED IN THE MANUFACTURING METHOD - An embodiment of the invention provides a magnetoresistance element with an MR ratio higher than that of the related art. | 2011-04-14 |
20110084349 | THERMOELECTRIC CONVERSION DEVICE - The thermoelectric conversion efficiency of a thermoelectric conversion device is increased by increasing the figure of merit of a spin-Seebeck effect element. | 2011-04-14 |
20110084350 | SOLID STATE IMAGE CAPTURE DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a solid state image capture device includes a multilayered interconnect layer, a semiconductor substrate, a pillar diffusion layer and an insulating member. The multilayered interconnect layer includes an interconnect. The semiconductor substrate is provided on the multilayered interconnect layer and the semiconductor substrate has a through-trench. The pillar diffusion layer is formed in the semiconductor substrate around the through-trench. In addition, an insulating member is filled into the through-trench. | 2011-04-14 |
20110084351 | BACK-ILLUMINATED TYPE SOLID-STATE IMAGING DEVICE - A back-illuminated type solid-state imaging device including (a) a semiconductor layer on a front surface side of a semiconductor substrate with an insulation film between them; (b) a photoelectric conversion element that constitutes a pixel in the semiconductor substrate; (c) at least part of transistors that constitute the pixel in the semiconductor film; and (d) a rear surface electrode to which a voltage is applied on the rear surface side of the semiconductor substrate, wherein, (1) a semiconductor layer of an opposite conduction type to a charge accumulation portion of the photoelectric conversion element is formed in the semiconductor substrate under the insulation film, and (2) the same voltage as the voltage applied to the rear surface electrode is applied to the semiconductor layer. | 2011-04-14 |
20110084352 | BACK-ILLUMINATED TYPE SOLID-STATE IMAGING DEVICE - A back-illuminated type solid-state imaging device is provided in which an electric field to collect a signal charge (an electron, a hole and the like, for example) is reliably generated to reduce a crosstalk. | 2011-04-14 |
20110084353 | TRENCH SCHOTTKY RECTIFIER DEVICE AND METHOD FOR MANUFACTURING THE SAME - A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage. | 2011-04-14 |
20110084354 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - In a semiconductor device according to the present invention, an electrode layer and a recessed part are formed on a surface of a semiconductor substrate. Further, in the semiconductor substrate, a RESURF layer that is in contact with a bottom surface of the recessed part and the electrode layer is formed. In addition, an insulating film is formed on an upper surface of the semiconductor substrate so as to fill the recessed part. Moreover, a field plate electrode is formed on the insulating film above the recessed part. | 2011-04-14 |
20110084355 | Isolation Structure For Semiconductor Device - A semiconductor device is provided. The semiconductor device includes a substrate, an isolation feature disposed on the substrate, and an active area disposed adjacent the isolation feature. The isolation feature may be a shallow trench isolation feature. The STI feature has a first width at the top of the feature and a second width at the bottom of the feature. The first width is less than the second width. Methods of fabricating a semiconductor device is also provided. A method includes forming shallow trench isolation features and then growing an epitaxial layer adjacent the STI features to form an active region. | 2011-04-14 |
20110084356 | LOCAL BURIED LAYER FORMING METHOD AND SEMICONDUCTOR DEVICE HAVING SUCH A LAYER - The present invention discloses a method of forming a local buried layer ( | 2011-04-14 |
20110084357 | Self Aligned Air-Gap in Interconnect Structures - An integrated circuit structure comprising an air gap and methods for forming the same are provided. The integrated circuit structure includes a conductive line; a self-aligned dielectric layer on a sidewall of the conductive line; an air-gap horizontally adjoining the self-aligned dielectric layer; a low-k dielectric layer horizontally adjoining the air-gap; and a dielectric layer on the air-gap and the low-k dielectric layer. | 2011-04-14 |
20110084358 | Apparatus and Method for Through Silicon via Impedance Matching - Methods and apparatuses for matching impedances in a flip-chip circuit assembly are presented. An apparatus for matching impedances in a flip-chip circuit assembly may include a first circuit associated with a first die and a through silicon via (TSV) coupling the first circuit to a second circuit. The apparatus may further include a first impedance matching inductor interposed between the TSV and the second circuit. A method for matching impedances in a flip-chip circuit assembly may include providing a die having a first circuit, and forming a TSV over the die. The method may further include providing a second circuit and forming a first impedance matching inductor interposed between the TSV and second circuit. | 2011-04-14 |
20110084359 | SEMICONDUCTOR DEVICE - A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor. | 2011-04-14 |
20110084360 | EMBEDDED SERIES DEEP TRENCH CAPACITORS AND METHODS OF MANUFACTURE - Trench capacitors and methods of manufacturing the trench capacitors are provided. The trench capacitors are very dense series capacitor structures with independent electrode contacts. In the method, a series of capacitors are formed by forming a plurality of insulator layers and a plurality of electrodes in a trench structure, where each electrode is formed in an alternating manner with each insulator layer. The method further includes planarizing the electrodes to form contact regions for a plurality of capacitors. | 2011-04-14 |
20110084361 | SEMICONDUCTOR DEVICES HAVING RESISTORS - A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region are provided. A first semiconductor pattern and a second semiconductor pattern are sequentially stacked in the first hole. A first resistor having the same crystalline structure as the second semiconductor pattern is provided in the second hole. | 2011-04-14 |
20110084362 | Active Diode Having No Gate and No Shallow Trench Isolation - An active diode with fast turn-on time, low capacitance, and low turn-on resistance may be manufactured without a gate and without a shallow trench isolation region between doped regions of the diode. A short conduction path in the active diode allows a fast turn-on time, and a lack of gate oxide reduces susceptibility of the active diode to extreme voltages. The active diode may be implemented in integrated circuits to prevent and reduce damage from electrostatic discharge (ESD) events. Manufacturing the active diode is accomplished by depositing a salicide block between doped regions of the diode before salicidation. After the salicide layers are formed on the doped regions, the salicide block is removed. | 2011-04-14 |
20110084363 | Compound Semiconductor Substrate, Semiconductor Device, and Processes for Producing Them - A compound semiconductor substrate | 2011-04-14 |
20110084364 | WAFER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a wafer, a first chip region and a second chip region are separated from each other by a dicing region. The dicing region includes: a first center region; a first intermediate region located on the first chip region's side of the first center region; a second intermediate region located on the second chip region's side of the first center region; a first outer region located on the first chip region's side of the first intermediate region; and a second outer region located on the second chip region's side of the second intermediate region. Surfaces of the first and second intermediate regions are respectively covered by bank-shaped resin films extending in a longitudinal direction of the dicing region. Respective surfaces of the first center region, the first outer region and the second outer region are not covered by resin films. | 2011-04-14 |
20110084365 | Through Silicon Via (TSV) Wire Bond Architecture - A through silicon via architecture for integrated circuits is provided. The integrated circuit (IC) includes a substrate with a top surface and a bottom surface with circuitry formed on the top surface, a plurality of bonding pads formed along a periphery of the bottom surface, and a backside metal layer (BML) formed on the bottom surface and electrically coupled to a second subset of bonding pads in the plurality of bonding pads. A first subset of bonding pads in the plurality of bonding pads is electrically coupled to circuitry on the top surface with through silicon vias (TSV). The BML distributes electrical signals provided by the second subset of bonding pads. | 2011-04-14 |
20110084366 | Epitaxial Wafer and Production Method Thereof - The epitaxial layer defects generated from voids of a silicon substrate wafer containing added hydrogen are suppressed by a method for producing an epitaxial wafer by: | 2011-04-14 |
20110084367 | EPITAXIAL WAFER AND METHOD OF PRODUCING THE SAME - A method of producing an epitaxial wafer, comprising: implanting oxygen ions from a surface of a silicon wafer, thereby forming an ion implanted layer in a surface layer of the silicon wafer; after forming the ion implanted layer, implanting boron ions from the surface of the silicon wafer to the whole area in the ion implanted layer; performing heat treatment of the silicon wafer after implanting boron ions, thereby forming a thinning-stopper layer including a mixture of silicon particles, silicon oxides, and boron, and forming an active layer in the silicon wafer on the surface side of the thinning-stopper layer; and forming an epitaxial layer on the surface of the silicon wafer after the heat treatment. | 2011-04-14 |
20110084368 | OVERMOLDED SEMICONDUCTOR PACKAGE WITH A WIREBOND CAGE FOR EMI SHIELDING - According to one exemplary embodiment, an overmolded package includes a component situated on a substrate. The overmolded package further includes an overmold situated over the component and the substrate. The overmolded package further includes a wirebond cage situated over the substrate and in the overmold, where the wirebond cage surrounds the component, and where the wirebond cage includes a number of wirebonds. The wirebond cage forms an EMI shield around the component. According to this exemplary embodiment, the overmolded package further includes a conductive layer situated on a top surface of the overmold and connected to the wirebond cage, where the conductive layer forms an EMI shield over the component. | 2011-04-14 |
20110084369 | DEVICE INCLUDING A SEMICONDUCTOR CHIP AND A CARRIER AND FABRICATION METHOD - A description is given of a method. In one embodiment the method includes providing a semiconductor chip with semiconductor material being exposed at a first surface of the semiconductor chip. The semiconductor chip is placed over a carrier with the first surface facing the carrier. An electrically conductive material is arranged between the semiconductor chip and the carrier. Heat is applied to attach the semiconductor chip to the carrier. | 2011-04-14 |
20110084370 | SEMICONDUCTOR PACKAGE AND PROCESS FOR FABRICATING SAME - A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier. | 2011-04-14 |
20110084371 | MODULAR LOW STRESS PACKAGE TECHNOLOGY - A protective modular package cover has first and second fastening sections located at opposing first and second ends with one or more subassembly receiving sections disposed thereto and is configured to fasten the protective modular package cover to a core. Each fastening section has a foot surface located on a bottom surface of a fastening section and configured to make contact with the core, a mounting hole configured to receive a fastener, and a torque element. Each subassembly receiving section is configured to receive a subassembly and has a cross member formed along the underside of the protective modular package cover. Activation of the first torque element transfers a downward clamping force generated at the fastening element to a top surface of one or more subassemblies disposed in the one or more subassembly receiving sections via the cross member of each of the one or more subassembly receiving sections. | 2011-04-14 |
20110084372 | PACKAGE CARRIER, SEMICONDUCTOR PACKAGE, AND PROCESS FOR FABRICATING SAME - A package carrier includes: (1) a dielectric layer; (2) a first electrically conductive pattern, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer, and including a plurality of first pads; (3) a plurality of first electrically conductive posts, extending through the dielectric layer, wherein each of the first electrically conductive posts includes a first electrically conductive post segment connected to at least one of the first pads and a second electrically conductive post segment connected to the first electrically conductive post segment, and a lateral extent of the first electrically conductive post segment is different from a lateral extent of the second electrically conductive post segment; and (4) a second electrically conductive pattern, disposed adjacent to a second surface of the dielectric layer, and including a plurality of second pads connected to respective ones of the second electrically conductive post segments. | 2011-04-14 |
20110084373 | INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING AN OFFSET STACKED CONFIGURATION AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: providing a base package including a first integrated circuit coupled to a base substrate by an electrical interconnect formed on one side; and mounting an offset package over the base package, the offset package electrically coupled to the base substrate via a system interconnect. | 2011-04-14 |
20110084374 | SEMICONDUCTOR PACKAGE WITH SECTIONED BONDING WIRE SCHEME - A semiconductor package includes a carrier substrate having thereon at least one bond finger; a semiconductor die mounted on a top surface of the carrier substrate; at least one active bond pad disposed on the semiconductor die; at least one dummy bond pad disposed on the semiconductor die; a first bonding wire extending between the at least one active bond pad and the at least one dummy bond pad; a second bonding wire extending between the at least one dummy bond pad and the at least one bond finger; and a molding compound encapsulating at least the semiconductor die. | 2011-04-14 |
20110084375 | SEMICONDUCTOR DEVICE PACKAGE WITH INTEGRATED STAND-OFF - A semiconductor device includes a substrate having first and second major surfaces and conductive traces, and solder balls attached to the second major surface of the substrate. A semiconductor die including an integrated circuit (IC) is attached to one of the major surfaces of the substrate. The IC is electrically connected to the solder balls by the conductive traces. The substrate includes an integrally molded stand-off feature that prevents the solder balls near the corners and the sides of the substrate from being knocked off during handling. The stand-off feature also maintains a predetermined distance between the substrate and a printed circuit board (PCB) when the substrate is attached to the PCB, and then a reflow process is performed. The stand-off feature also prevents open connections between the solder balls and the PCB that may be caused by warping of the PCB or the weight of the semiconductor die. The semiconductor device may include a stiffener ring attached to the second major surface of the substrate and surrounding the conductive balls. | 2011-04-14 |
20110084376 | MODULAR LOW STRESS PACKAGE TECHNOLOGY - A protective modular package assembly with one or more subassemblies, each having a base element, a sidewall element coupled to the base element, and a semiconductor device disposed within and coupled to the sidewall element and the base element; a protective modular package cover having fastening sections located at opposing ends of the cover, torque elements disposed on the opposing ends and configured to fasten the cover to a core, and subassembly receiving sections disposed between the fastening sections with each subassembly receiving section operable to receive a subassembly and having a cross member along the underside of the cover; and an adhesive layer configured to affix subassemblies to respective subassembly receiving sections. The torque elements are configured to transfer a downward clamping force generated at the fastening elements to a top surface of the subassemblies via the cross member of each of the one or more subassembly receiving sections. | 2011-04-14 |
20110084377 | SYSTEM FOR SEPARATING A DICED SEMICONDUCTOR DIE FROM A DIE ATTACH TAPE - A system is disclosed for ejecting a semiconductor die from a tape to which the die is affixed during the wafer dicing process. In embodiments, the system includes an ejector tool including a support table, ejector pins and a pick-up arm. The support table is connected to a vacuum source for creating a negative pressure at an interface between the tape and support table. The support table further includes an aperture with one or more chamfered sidewalls. The vacuum source is connected to the aperture so that, upon placement of the tape on the support table with a die centered over the aperture, the vacuum source pulls a portion of the tape around the edges of the semiconductor die away from the die and into the space created by the chamfered edges. | 2011-04-14 |
20110084378 | SEMICONDUCTOR PACKAGE WITH INTEGRATED INTERFERENCE SHIELDING AND METHOD OF MANUFACTURE THEREOF - An integrated electromagnetic interference (EMI) shield for a semiconductor module package. The integrated EMI shield includes a plurality of wirebond springs electrically connected between a ground plane in the substrate of the package and a conductive layer printed on the top of the package mold compound. The wirebond springs have a defined shape that causes a spring effect to provide contact electrical connection between the tops of the wirebond springs and the conductive layer. The wirebond springs can be positioned anywhere in the module package, around all or some of the devices included in the package, to create a complete EMI shield around those devices. | 2011-04-14 |
20110084379 | SEMICONDUCTOR DEVICE HAVING IMPROVED HEAT SINK - The semiconductor device includes a substrate, a first semiconductor element, a second semiconductor element, a first heat sink and a second heat sink. The first and the second semiconductor elements are provided on the substrate. The maximum power consumption of the first semiconductor element is lower than that of the second semiconductor element. The first heat sink is fixed to the first semiconductor element. The second heat sink is fixed to the second semiconductor element. The first heat sink is spaced apart from the second heat sink. | 2011-04-14 |
20110084380 | SEMICONDUCTOR PACKAGES HAVING PASSIVE ELEMENTS MOUNTED THEREONTO - A semiconductor package onto which a plurality of passive elements is mounted. A substrate includes a first surface and a second surface. A semiconductor chip is on one of the first surface and the second surface of the substrate. A plurality of passive elements are on the substrate. The plurality of passive elements include a plurality of first passive elements and a plurality of second passive elements that are taller than the plurality of first passive elements. The plurality of first passive elements are on at least one of the first surface and the second surface, and at least two of the plurality of second passive elements are on the second surface. | 2011-04-14 |
20110084381 | Chip Having A Metal Pillar Structure - The present invention relates to a chip having a metal pillar structure. The chip includes a chip body, at least one chip pad, a first passivation layer, an under ball metal layer and at least one metal pillar structure. The chip body has an active surface. The chip pad is disposed on the active surface. The first passivation layer is disposed on the active surface, and has at least one first opening so as to expose part of the chip pad. The under ball metal layer is disposed on the chip pad. The metal pillar structure is disposed on the under ball metal layer, and includes a metal pillar and a solder. The metal pillar is disposed on the under ball metal layer. The solder is disposed on the metal pillar, and the maximum diameter formed by the solder is shorter than or equal to the diameter of the metal pillar. Therefore, when the pitch between two adjacent metal pillar structures of the chip is a fine pitch, the defect of solder bridge can be avoided, so that the yield rate is improved. | 2011-04-14 |
20110084382 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package is disclosed. The package includes a carrier substrate and at least two semiconductor chips thereon. Each semiconductor chip includes a plurality of conductive pads. A position structure is disposed on the carrier substrate to fix locations of the semiconductor chips at the carrier substrate. A fill material layer is formed on the carrier substrate, covers the semiconductor chips and the position structure, and has a plurality of openings correspondingly exposing the conductive pads. A redistribution layer (RDL) is disposed on the fill material layer and is connected to the conductive pads through the plurality of openings. A protective layer covers the fill material layer and the RDL. A plurality of conductive bumps is disposed on the protective layer and is electrically connected to the RDL. A fabrication method of the chip package is also disclosed. | 2011-04-14 |
20110084383 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a first circuit base member including a surface having multiple first electrodes formed thereon, a second circuit base member being provided above the first circuit base member and having first through holes and second through holes formed respectively above the first electrodes, a semiconductor package provided above the second circuit base member, and multiple first bumps provided inside the first through holes and the second through holes to connect the first electrodes to the semiconductor package. | 2011-04-14 |
20110084384 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate, a semiconductor chip that is bonded to one of the faces of the substrate via bumps, and has a device formation face facing the one of the faces, and a resin that fills the space between the device formation face of the semiconductor chip and the one of the faces of the substrate. The resin includes: a first resin that is formed in a formation region of bumps placed on the outermost circumference of the bumps, and is formed inside the formation region, and a second resin that is formed outside the first resin. The thermal expansion coefficient of the substrate is higher than the thermal expansion coefficient of the first resin. The thermal expansion coefficient of the second resin is higher than the thermal expansion coefficient of the first resin. | 2011-04-14 |
20110084385 | Semiconductor device and information processing system including the same - A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured. | 2011-04-14 |
20110084386 | Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask - A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion. An encapsulant is deposited between the die and substrate. | 2011-04-14 |
20110084387 | DESIGNS AND METHODS FOR CONDUCTIVE BUMPS - Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer. | 2011-04-14 |
20110084388 | REDUCING UNDERFILL KEEP OUT ZONE ON SUBSTRATE USED IN ELECTRONIC DEVICE PROCESSING - Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate with a die attach area, and forming a layer on the substrate outside of the die attach area. The layer may be formed from a fluoropolymer material. The method also includes coupling a die to the substrate in the die attach area, wherein a gap remains between the die and the die attach area. The method also includes placing an underfill material in the gap and adjacent to the layer on the substrate. Examples of fluoropolymer materials which may be used include polytetrafluoroethylene (PTFE) and perfluoroalkoxy polymer resin (PFA). Other embodiments are described and claimed. | 2011-04-14 |
20110084389 | Semiconductor Device - The present invention relates to a semiconductor device. The semiconductor device includes a substrate and a chip. The chip is electrically connected to the substrate. The chip includes a chip body, at least one chip pad, a first passivation, an under ball metal layer and at least one metal pillar structure. The chip pad is disposed adjacent to an active surface of the chip body. The first passivation is disposed adjacent to the active surface, and exposes part of the chip pad. The under ball metal layer is disposed adjacent to the chip pad. The metal pillar structure contacts the under ball metal layer to form a first contact surface having a first diameter. The metal pillar structure is electrically connected to a substrate pad of the substrate to form a second contact surface having a second diameter. The ratio of the first diameter to the second diameter is between 0.7 and 1.0. As a result, the first contact surface and the second contact surface have an equivalent bonding force, which prevents the metal pillar structure from cracking due to a shear stress. Thus, the structure strength of the semiconductor device is enhanced and the semiconductor device can pass the reliability test. | 2011-04-14 |
20110084390 | Chip Design with Robust Corner Bumps - An integrated circuit structure includes a semiconductor chip, which includes a corner, a side, and a center. The semiconductor chip further includes a plurality of bump pad structures distributed on a major surface of a substrate; a first region of the substrate having formed thereon a first bump pad structure having a first number of supporting metal pads associated with it; and a second region of the substrate having formed thereon a second bump structure having a second number of supported metal pads associated with it, the second number being greater than the first number. | 2011-04-14 |
20110084391 | Reducing Device Mismatch by Adjusting Titanium Formation - An integrated circuit structure includes a semiconductor substrate; a first titanium layer over the semiconductor substrate, wherein the first titanium layer has a first thickness less than 130 Å; a first titanium nitride layer over and contacting the first titanium layer; and an aluminum-containing layer over and contacting the first titanium nitride layer. | 2011-04-14 |
20110084392 | Electronic Structures Including Conductive Layers Comprising Copper and Having a Thickness of at Least 0.5 Micrometers - An electronic structure may include a conductive pad on a substrate, and an insulating layer on the substrate and on the conductive pad. The insulating layer may have a via therein so that a portion of the conductive pad opposite the substrate is free of the insulating layer. A conductive layer comprising copper may be on the portion of the conductive pad free of the insulating layer, on sidewalls of the via, and on surface portions of the insulating layer surrounding the via opposite the substrate and the conductive pad, and the conductive layer comprising copper may have a thickness of at least approximately 1.0 μm. A conductive barrier layer may be on the conductive layer comprising copper, and the conductive barrier layer may include at least one of nickel, platinum, palladium, and/or combinations thereof. A solder layer may be on the conductive barrier layer, the conductive layer comprising copper and the solder layer may comprise different materials, and the conductive barrier layer may be between the conductive layer comprising copper and the solder layer. | 2011-04-14 |
20110084393 | METHOD OF FORMING ELECTRODEPOSITED CONTACTS - A contact metallurgy structure comprising a patterned dielectric layer having vias on a substrate; a silicide layer of cobalt and/or nickel located at the bottom of vias; a contact layer comprising Ti located in vias on top of the silicide layer; a diffusion layer located in vias and on top of the contact layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer comprises at least one member selected from the group consisting of copper, ruthenium, rhodium platinum, palladium, iridium, rhenium, tungsten, gold, silver and osmium and alloys thereof. When the metal fill layer comprises rhodium, the diffusion layer is not required. Optionally a seed layer for the metal fill layer can be employed. | 2011-04-14 |
20110084394 | Semiconductor Structure - A semiconductor structure is provided. The semiconductor structure includes a substrate, a dielectric layer, a pad structure and a protection structure. The dielectric layer is disposed on the substrate. The pad structure is disposed in the dielectric layer. The pad structure includes a plurality of first metal layers and a plurality of plugs which are electrically connected to each other vertically. There is no contact plug disposed between the pad structure and the substrate. The protection structure is disposed in the dielectric layer and encompasses the pad structure. | 2011-04-14 |
20110084395 | Semiconductor package substrate and semiconductor device having the same - A semiconductor device includes a semiconductor chip and a package substrate on which the semiconductor chip is mounted. The package substrate has internal terminals connected to the semiconductor chip, front surface wirings connected to the internal terminals, rear surface wirings connected to external electrodes, and contacts connecting the front surface wiring and rear surface wiring. Out of the plurality of contact, some contacts included in the wirings for signal transmission are disposed near the internal terminals. Thus, a signal led out from the semiconductor chip is immediately taken away from the chip mounting surface of the package substrate. This reduces the floating capacitance between the wirings on the package substrate and chip, thereby improving the signal quality. | 2011-04-14 |