15th week of 2011 patent applcation highlights part 41 |
Patent application number | Title | Published |
20110087802 | SYNCHRONIZING STRUCTURED WEB SITE CONTENTS - Techniques to synchronize structured web site content are described. An apparatus may include a server having a server synchronization module to identify structured content types shared by the server and a client, and synchronize structured content corresponding to the structured content types. Other embodiments are described and claimed. | 2011-04-14 |
20110087803 | METHOD AND SYSTEM FOR PROCESSING CORRECTION FIELD INFORMATION - A method and system for processing correction field information are provided. The method includes: receiving a packet, and obtaining a first correction value carried by the packet; obtaining first time information and second time information; obtaining a second correction value according to the first correction value and the first time information; setting the second correction value in the packet; setting the second time information in the packet; obtaining third time information and fourth time information; obtaining a third correction value according to the second correction value, the second time information, the third time information, and the fourth time information; and setting the third correction value in the packet. The processing of the time information and the processing of the correction field information are performed with a set of processing mechanism, and the implementation is simpler. | 2011-04-14 |
20110087804 | PERIPHERAL DEVICE AND DEVICE CONNECTION SYSTEM - A peripheral device includes: an input/output block connected to a device subject to connection; a communication block configured to communicate with a device subject to communication; and a conversion block configured, if the device subject to communication is a storage device, to convert a storage access command output by the device subject to connection to the input/output block into a communication command that is transferred between the communication block and the device subject to communication, wherein the communication block transmits the communication command generated by the conversion block to the device subject to communication and transfers, with the device subject to communication, one of data that is written by the device subject to connection to the device subject to communication and data that is read from the device subject to communication. | 2011-04-14 |
20110087805 | Multi-mode dongle for peripheral devices and associated methods - Methods and systems are described for utilizing multi-mode dongles with peripheral devices. The multi-mode dongles are configured to provide standard mode signals for a standard mode of operation and alternate mode signals for an alternate mode of operation, for example, where a host information handling system is unable to provide the alternate mode signals to the peripheral device. The multi-mode dongle receives mode control signals from a host information handling system and automatically switches from a standard mode of operation to an alternate mode of operation, where the alternate mode signals are provided to the peripheral device, based upon the mode control signals. In one embodiment, the multi-mode dongle can be configured for a universal serial bus (USB) port, and the alternate mode signals can be associated with charging a consumer electronics (CE) device. | 2011-04-14 |
20110087806 | Dual-Mode Data Transfer of Uncompressed Multimedia Contents or Data Communications - A system and corresponding method for transferring data. Data may be selectively communicated via a USB port of a device. An indication of a device type may be received at the USB port from an external interface. USB protocol data or uncompressed high definition media data may be caused to be selectively supplied to the USB port as a function of the indication. The selected data may be transmitted via the USB port to an external interface. The uncompressed high definition media data may include at least one lane of media data or multimedia data in accordance with a DisplayPort standard. In some embodiments, either USB protocol data or multimedia data comprising audio data and uncompressed high definition video data may be caused to be selectively supplied to the USB port as a function of the indication. The indication may be a data format signal. | 2011-04-14 |
20110087807 | SYSTEMS AND METHODS OF MEDIA MANAGEMENT, SUCH AS MANAGEMENT OF MEDIA TO AND FROM A MEDIA STORAGE LIBRARY, INCLUDING REMOVABLE MEDIA - A system and method for determining media to be exported out of a media library is described. In some examples, the system determines a media component to be exported, determines the media component is in the media library for a specific process, and exports the media component after the process is completed. | 2011-04-14 |
20110087808 | DIRECT ACCESS MEMORY CONTROLLER WITH MULTIPLE SOURCES, CORRESPONDING METHOD AND COMPUTER PROGRAM - This direct access memory controller ( | 2011-04-14 |
20110087809 | Reduced latency barrier transaction requests in interconnects - Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, the interconnect circuitry comprising: at least one input for receiving transaction requests from the at least one initiator device; at least one output for outputting transaction requests to the at least one recipient device; at least one path for transmitting the transaction requests between the at least one input and the at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some of said transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some of said transaction requests that occur after said barrier transaction request in said stream of transaction requests; wherein said control circuitry comprises a response signal generator, said response signal generator being responsive to receipt of said barrier transaction request to issue a response signal, said response signal indicating to upstream blocking circuitry that any transaction requests delayed in response to said barrier transaction request can be transmitted further. | 2011-04-14 |
20110087810 | METHOD OF PROGRAMMING THE DEFAULT CABLE INTERFACE SOFTWARE IN AN INDICIA READING DEVICE - An indicia reading apparatus includes an interconnect cable and an indicia reading device. The indicia reading device is configured so that, if the indicia reader device is not configured to any interconnect cable and detects an indicia which does not contain one of a plurality of specified sequences of data elements that the indicia reading device will recognize and use to configure itself to operate with the interconnect cable, the indicia reading device will indicate to the user of the indicia reading device that the indicia reading device needs to be configured to operate with the interconnect cable. | 2011-04-14 |
20110087811 | Semiconductor device, control method for the semiconductor device and information processing system including the same - The core chips each include a timing control circuit that outputs a timing signal synchronized with the outputting of parallel data to the interface chip. The interface chip includes a data input circuit that captures parallel data in synchronization with the timing signal. With this arrangement, the timing to output the parallel data and the timing to capture the parallel data are both synchronized with the timing signal generated in the core chips. Therefore, even if there is a difference in operation speed between each core chip and the interface chip, the parallel data can be accurately captured on the interface chip side. | 2011-04-14 |
20110087812 | MULTI-MASTER BI-DIRECTIONAL I2C BUS BUFFER - Systems and methods are disclosed that promote communication in an I2C Bus. These systems and methods can include at least two groups, wherein each of the two groups comprise at least one I2C communication units, and wherein each of the I2C communication units within a group are coupled together. These systems and methods can also comprises a connector that creates a connection between at least two groups of units and controls the flow of data by altering at least one signal that is transmitted between the at least two groups. | 2011-04-14 |
20110087813 | SYSTEM AND METHOD OF SENDING AND RECEIVING DATA AND COMMANDS USING THE TCK AND TMS OF IEEE 1149.1 - A system and method that use the TCK and TMS to transmit address and data. IEEE 1149.1 based tools can use the system and method without modification to make IEEE 1149.1 TAPs appear and disappear, add compliance-enable circuits without pins and broadcast commands to IEEE P1687 instruments. The system and method use Test-Logic-Reset sequences with Run-Test-Idle to enable an on/off switch of various DFT capabilities. IEEE 1149.1 compliant TAP interfaces disappear to pass-through wires using the system and method. The sequences communicate an “address” which enables one or more of the TAP interfaces and a “command”. The system and method has benefits for IEEE P1687 instrument chains and on-chip routing of the P1687 network. | 2011-04-14 |
20110087814 | Enhanced I/O Performance in a Multi-Processor System Via Interrupt Affinity Schemes - Disclosed herein is a method for improving Input/Output (I/O) performance in a host system having multiple CPUs. Under this method, various interrupt affinity schemes are provided, which associate multiple processors, interrupts, and I/O channels for sending the interrupts, thereby allowing the interrupts to be almost evenly loaded among the multiple I/O channels and processors. Also, data locality (“warm cache”) can be achieved through the interrupt affinity schemes that associate each interrupt to its source processor, namely, the processor originating the I/O request that results in the interrupt. | 2011-04-14 |
20110087815 | Interrupt Masking for Multi-Core Processors - Technologies are generally described herein for handling interrupts within a multi-core processor. A core specific interrupt mask (“CIM”) can be adapted to influence the assignment of interrupts to particular processor cores in the multi-core processor. Available processor cores can be identified by evaluating the CIM. An interrupt with an interrupt service routine (“ISR”) that is received by the multi-core processor can be assigned to one or more of the available processor cores identified by the CIM. | 2011-04-14 |
20110087816 | COMPUTER SYSTEM AND CONTROL METHOD THEREOF - A computer system and a control method thereof, the computer system including: a processor which executes a program; a communication unit which communicates with an external device; a main body which is provided with the processor. A cover which can be opened and shut with regard to the main body; an open/shut sensor which senses whether the cover is open or shut; and a controller which interrupts an operation of the communication unit if the open/shut sensor senses that the cover is shut. | 2011-04-14 |
20110087817 | INFORMATION PROCESSING APPARATUS, IMAGE FORMING APPARATUS AND INFORMATION PROCESSING METHOD - According to an aspect of the invention, an information processing apparatus includes a main board, an expanded CPU board connector, an external device connector, a detection unit. A first CPU is mounted on the main board. The expanded CPU board connector is disposed on the main board. An expanded CPU board is connectable to the expanded CPU board connector. A second CPU is mounted on the expanded CPU board. The external device connector is disposed on the main board. An external device is connected to the external device connector. The detection unit detects that the expanded CPU board is installed to the expanded CPU board connector. The first CPU controls the information processing apparatus to change a master of control of the information processing apparatus from the first CPU to the second CPU. | 2011-04-14 |
20110087818 | SINGLE LINE DOCK STATUS AUTOIDENTIFICATION - A single line docking station characteristic identifier is disclosed. In one embodiment, a portable computing device can include a dock detector circuit having an interface pin configured to be coupled to a docking station via a single line dock connection, where the dock detector circuit is configured to determine a characteristic of the docking station using a passive component in the docking station when the portable computing device is connected to the docking station via the single line dock connection. The dock detector circuit can include a resistor and a Schmitt trigger, while the passive component in the docking station can include a capacitor, for example. | 2011-04-14 |
20110087819 | Barrier transactions in interconnects - Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, said interconnect circuitry comprising: at least one input for receiving transaction requests from said at least one initiator device; at least one output for outputting transaction requests to said at least one recipient device; at least one path for transmitting said transaction requests between said at least one input and said at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some transaction requests that occur after said bather transaction request in said stream of transaction requests; wherein said bather transaction request comprising an indicator indicating which of said transaction requests within said stream of transaction requests comprise said at least some transaction requests whose ordering is to be maintained. | 2011-04-14 |
20110087820 | QUEUE SHARING AND RECONFIGURATION IN PCI EXPRESS LINKS - In one embodiment an electronic device comprises at least one processor, at least one PCI express link, a virtual channel/sub-link flow control module, and a memory module communicatively connected to the one or more processors and comprising logic instructions which, when executed on the one or more processors configure the one or more processors to determine, in an electrical device, whether a virtual channel/sub-link is inactive, and in response to a determination that at least one virtual channel/sub-link is inactive, reallocate queue space from the at least one inactive channel to at least one active channel. | 2011-04-14 |
20110087821 | APPARATUS TO ACCESS MULTI-BANK MEMORY - A method of controlling access to a multi-bank memory, and an apparatus to perform the method, is provided. For the access control, a stride register is provided to store stride values determined by a processor during a run time. A memory controller controls access to a logical block in row and column directions, in an interleaved manner, the logical block having a width determined according to the stride values stored in the stride register. Accordingly, simultaneous access to a plurality of pieces of data at successive addresses adjacent in the row and column directions may be made. | 2011-04-14 |
20110087822 | VIRTUALIZING PHYSICAL MEMORY IN A VIRTUAL MACHINE SYSTEM - A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine. | 2011-04-14 |
20110087823 | APPARATUS AND METHOD FOR PRODUCING IDS FOR INTERCONNECTED DEVICES OF MIXED TYPE - A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR-, AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input are fed to one device of the serial interconnection configuration. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. | 2011-04-14 |
20110087824 | FLASH MEMORY ACCESSING APPARATUS AND METHOD THEREOF - A flash memory accessing apparatus is disclosed. The flash memory accessing apparatus includes a controller, a first channel memory set and a second channel memory set. The first channel memory set includes a first flash memory and at least one first memory expanding socket. The second channel memory set includes a second flash memory and at least one second memory expanding socket. The controller determines the accessing method to be implemented on the first memory and second flash memory according to whether there is any flash memory inserted into the first memory expanding socket and the second memory expanding socket. | 2011-04-14 |
20110087825 | Electronic Device with Removable USB Flash Drive and USB Flash Drive with Added Functionality - A USB flash drive for removable connection to another device such as a cell phone, camera, computer, gaming system and photo printer, for example. In one embodiment, a cell phone having a USB port is provided wherein the USB flash drive configured to connect into a slot in the cell phone housing. A user may then quickly transfer data downloaded to the USB flash drive when connected to the cell phone, and another device such as a photo printer, for example. One or more optional additional functionality is incorporated into the USB flash drive such as, for example, a camera, internet card and MP3 player. | 2011-04-14 |
20110087826 | FLASH MEMORY ACCESSING APPARATUS AND ACCESSING METHOD THEREOF - A flash memory accessing apparatus is disclosed. The flash memory accessing apparatus includes a memory controller, a first open NAND flash interface (ONFI) and an expanding flash memory module. The first ONFI is used for connecting a main flash memory module. The memory controller obtains a detecting result by, detecting whether the main flash memory module and the expanding flash memory module are single side or double side. The memory controller further configures an accessing method of the main flash memory module and the expanding flash memory module according to the detecting result. | 2011-04-14 |
20110087827 | DATA WRITING METHOD FOR A FLASH MEMORY, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data writing method for writing data from a host system into a flash memory chip is provided. The method includes configuring a plurality of logical page addresses, grouping the logical page addresses into a plurality of logical blocks, and recording the data dispersion degree of each of the logical blocks. The method also includes receiving write-in data from the host system, identifying a logical block that a logical page address to be written by the host system belongs to, and writing the write-in data into the flash memory chip according to the data dispersion degree of the logical block, wherein the data dispersion degree of each of the logical blocks is not larger than a logical block data dispersion degree threshold value. Accordingly, the method can effectively reduce the time for executing a host write command. | 2011-04-14 |
20110087828 | METHOD FOR ENHANCING PERFORMANCE OF ACCESSING A FLASH MEMORY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for enhancing performance of accessing a Flash memory, which includes a plurality of blocks and is positioned in a memory device, includes: during writing data into the Flash memory, establishing/updating at least one linking table in a random access memory (RAM) of the memory device, wherein regarding the Flash memory, the linking table indicates linking relationships between logical addresses and physical addresses, or indicates linking relationships between physical addresses and logical addresses; and writing the linking table into the Flash memory only when it is detected that a flush cache command is sent from a host device. An associated memory device and a controller thereof are also provided, where the controller includes: a read only memory (ROM) arranged to store a program code; and a microprocessor arranged to execute the program code to control the access to the Flash memory. | 2011-04-14 |
20110087829 | DATA STORAGE DEVICE AND DATA ACCESS METHOD - The invention provides a data storage device. In one embodiment, the data storage device comprises a storage medium, a random access memory, and a controller. The storage medium stores a plurality of link tables. The random access memory comprises a plurality of storage units respectively corresponding to a plurality of logical address ranges. The controller receives a target logical address from the host, determines a target link table corresponding to a logical address set comprising the target logical address, determines a target storage unit corresponding to a logical address range comprising the target logical address, determines whether the target storage unit has stored the target link table, and when the target storage unit has stored the target link table, determines a target physical address mapped to the target logical address according to a mapping relationship stored in the target link table, and accesses data stored in the storage medium according to the target physical address. | 2011-04-14 |
20110087830 | SYSTEM, METHOD AND APPARATUS FOR EMBEDDED FIRMWARE CODE UPDATE - A wireless module is provided for wirelessly updating code to any appropriate peripheral device and may allow for wireless communication with the desired peripheral device to update an operating software code. The wireless module has the similar size, shape, and form factor as the current Memory Stick™. In one embodiment, the method of updating code to the wireless module and/or the desired peripheral devices includes providing a fail-safe code to the peripheral device, updating the peripheral device with a new code utilizing the wireless module, and executing a primary code for operation of the peripheral device. Further, the wireless module may be provided to any number of peripheral devices compatible with the Memory Stick™ removable data storage media. The wireless module is removably connected to the desired peripheral device and provides the peripheral device with a fail-safe system, method and apparatus for updating the embedded operational software code without recalling and servicing the peripheral device. | 2011-04-14 |
20110087831 | MEMORY SYSTEM AND METHOD OF WRITING INTO NONVOLATILE SEMICONDUCTOR MEMORY - A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first to p-th (p being natural number smaller than n) addresses into the first original block. The controller writes data which has a first write address of one of the first to p-th addresses into the first subblock when the controller receives request to write data having the first write address and data having the first write address exists in the first original block. | 2011-04-14 |
20110087832 | WEAR LEVELING IN STORAGE DEVICES BASED ON FLASH MEMORIES AND RELATED CIRCUIT, SYSTEM, AND METHOD - A wear leveling solution is proposed for use in a storage device based on a flash memory. The flash memory includes a plurality of physical blocks, which are adapted to be erased individually. A corresponding method starts with the step for erasing one of the physical blocks. One of the physical blocks being allocated for storing data is selected; this operation is performed in response to the reaching of a threshold by an indication of a difference between a number of erasures of the erased physical block and a number of erasures of the selected physical block. At least the data of the selected physical block being valid is copied into the erased physical block. The selected physical block is then erased. | 2011-04-14 |
20110087833 | LOCAL NONVOLATILE WRITE-THROUGH CACHE FOR A DATA SERVER HAVING NETWORK-BASED DATA STORAGE, AND RELATED OPERATING METHODS - A data server, a host adapter system for the data server, and related operating methods facilitate data write and read operations for network-based data storage that is remotely coupled to the data server and for non-network-based data storage in a locally attached cache device. The host adapter system includes a local storage controller module and a network storage controller module. The local storage controller module is utilized for a locally attached, nonvolatile, write-through cache device of the data server. The network storage controller module is utilized for a network-based data storage architecture of the data server. The storage controller modules support concurrent writing of data to the local cache storage and the network-based storage architecture. The storage controller modules also support reading of server-maintained data from the local cache storage and the network-based storage architecture. | 2011-04-14 |
20110087834 | Memory Package Utilizing At Least Two Types of Memories - A memory system and methods for memory manage are presented. The memory system includes a volatile memory electrically connected to a high-density memory; a memory controller that expects data to be written or read to or from the memory system at a bandwidth and a latency associated with the volatile memory; a directory within the volatile memory that associates a volatile memory address with data stored in the high-density memory; and redundant storage in the high-density memory that stores a copy of the association between the volatile memory address and the data stored in the high-density memory. The methods for memory management allow writing to and reading from the memory system using a first memory read/write interface (e.g. DRAM interface, etc.), though data is stored in a device of a different memory type (e.g. FLASH, etc.). | 2011-04-14 |
20110087835 | Semiconductor memory device and data processing system - To include a plurality of core chips to which different pieces of chip information from each other are given in advance. A first refresh command is divided into a plurality of second refresh commands having different timings from each other, and a refresh operation is performed on a core chip for which a count value of the second refresh commands and at least a portion of the chip information match each other. With this configuration, even when the second refresh command is commonly supplied to a plurality of core chips, it is possible to shift a timing for the refresh operation in each of the core chips. Therefore, it is possible to reduce a peak current at the time of the refresh operation. | 2011-04-14 |
20110087836 | STORAGE UNIT AND MEMORY SYSTEM - A storage unit includes: a random access memory device and a storage device to be accessed using an address in units of word and sector, respectively; and a storage controller controlling accesses to the random access memory device and the storage device according to the addresses designated via a bus. The storage controller includes first and second interface functions for access to data stored on the storage device and the random access memory designated using the sector address and the word address provided via the bus, respectively, a function of using the random access memory device as a first disk cache and determining data to be saved in the random access memory device in response to the access by the first interface function, and functions of transferring the data designated using the sector address by repeating register access and by a bus master function as continuous word-sized data through the bus. | 2011-04-14 |
20110087837 | SECONDARY CACHE FOR WRITE ACCUMULATION AND COALESCING - A method for efficiently using a large secondary cache is disclosed herein. In certain embodiments, such a method may include accumulating, in a secondary cache, a plurality of data tracks. These data tracks may include modified data and/or unmodified data. The method may determine if a subset of the plurality of data tracks makes up a full stride. In the event the subset makes up a full stride, the method may destage the subset from the secondary cache. By destaging full strides, the method reduces the number of disk operations that are required to destage data from the secondary cache. A corresponding computer program product and apparatus are also disclosed and claimed herein. | 2011-04-14 |
20110087838 | Memory Device and Operation Method Therefor - Provided is a MLC (Multi-level cell) memory device, comprising: a memory array, including a plurality of groups each storing a plurality of bits; and an inverse bit storage section, storing a first inverse bit data including a plurality of inverse bits, the plurality of bits in the same group in the memory array being related to a respective inverse bit. | 2011-04-14 |
20110087839 | APPARATUSES, METHODS AND SYSTEMS FOR A SMART ADDRESS PARSER - The apparatus, methods and systems for a smart address parser (hereinafter, “SAP”) described herein implement a text parser whereby users may enter a text string, such as manually via an input field. The SAP processes the input address string to extract address elements for storage, display, reporting, and/or use in a wide variety of back-end applications. In various embodiments and implementations, the SAP may facilitate: separation and identification of address components regardless of the order in which they are supplied in the input address string; supplementation of missing address information; correction and/or recognition of misspelled terms, abbreviations, alternate names, and/or the like variants of address elements; recognition of unique addresses based on minimal but sufficient input identifiers; and/or the like. | 2011-04-14 |
20110087840 | EFFICIENT LINE AND PAGE ORGANIZATION FOR COMPRESSION STATUS BIT CACHING - One embodiment of the present invention sets forth a technique for performing a memory access request to compressed data within a virtually mapped memory system comprising an arbitrary number of partitions. A virtual address is mapped to a linear physical address, specified by a page table entry (PTE). The PTE is configured to store compression attributes, which are used to locate compression status for a corresponding physical memory page within a compression status bit cache. The compression status bit cache operates in conjunction with a compression status bit backing store. If compression status is available from the compression status bit cache, then the memory access request proceeds using the compression status. If the compression status bit cache misses, then the miss triggers a fill operation from the backing store. After the fill completes, memory access proceeds using the newly filled compression status information. | 2011-04-14 |
20110087841 | PROCESSOR AND CONTROL METHOD - A processor includes a first processing unit that has a first memory and performs processing, a second processing unit that performs processing, a second memory that holds status information specifying a status of data held in the first memory, and a control unit that outputs a request for reading out the data of the first address to the first processing unit upon receiving a first access request for data of a first address from the second processing unit when first status information of the data of the first address indicates that the data of the first address is held in the first memory in an exclusive state or an owned state and that allows the second processing unit to access data of the first address included at the second memory upon receiving a no-data-modification notification indicating the data of the first address is not modified by the first processing unit. | 2011-04-14 |
20110087842 | PRE-FETCHING CONTENT ITEMS BASED ON SOCIAL DISTANCE - Retrieving content items based on a social distance between a user and content providers. The social distance is determined based on, for example, user interaction with the content providers. The content providers are ranked, for the user, based on the determined social distance. Prior to a request from the user, the content items are pre-fetched based on the ranked content providers and constraints such as storage space, bandwidth, and battery power level of a computing device of the user. In some embodiments, additional content items are retrieved, or retrieved content items are deleted, as a variable-size cache on the computing device fills or changes size. | 2011-04-14 |
20110087843 | Monitoring cache usage in a distributed shared cache - An apparatus, method, and system are disclosed. In one embodiment the apparatus includes a cache memory, which a number of sets. Each of the sets in the cache memory have several cache lines. The apparatus also includes at least one process resource table. The process resource table maintains a cache line occupancy count of a number of cache lines. Specifically, the cache line occupancy count for each cache line describes the number of cache lines in the cache storing information utilized by a process running on a computer system. Additionally, the process resource table stores the occupancy count of less cache lines than the total number of cache lines in the cache memory. | 2011-04-14 |
20110087844 | CONTENT NETWORK GLOBAL REPLACEMENT POLICY - This invention is related to content delivery systems and methods. In one aspect of the invention, a content provider controls a replacement process operating at an edge server. The edge server services content providers and has a data store for storing content associated with respective ones of the content providers. A content provider sets a replacement policy at the edge server that controls the movement of content associated with the content provider, into and out of the data store. In another aspect of the invention, a content delivery system includes a content server storing content files, an edge server having cache memory for storing content files, and a replacement policy module for managing content stored within the cache memory. The replacement policy module can store portions of the content files at the content server within the cache memory, as a function of a replacement policy set by a content owner. | 2011-04-14 |
20110087845 | BURST-BASED CACHE DEAD BLOCK PREDICTION - The present disclosure generally relates to cache memory systems and/or techniques to identify dead cache blocks in cache memory systems. Example systems may include a cache memory that is accessible by a cache client. The cache memory may include a plurality of storage locations for a first cache block, with a most recently used position location in the cache memory. A cache controller may be configured to predict whether the first cache block stored in the cache memory is identified as a dead cache block based on a cache burst of the first cache block. The cache burst may comprise a first access of the first cache block by a cache client and any subsequent contiguous accesses of the first cache block following the first access by the cache client while the first cache block is in a most recently used position of the cache set. | 2011-04-14 |
20110087846 | Accessing a Multi-Channel Memory System Having Non-Uniform Page Sizes - A method includes predicting a memory access pattern of each master of a plurality of masters. The plurality of masters can access a multi-channel memory via a crossbar interconnect, where the multi-channel memory has a plurality of banks The method includes identifying a page size associated with each bank of the plurality of banks The method also includes assigning at least one bank of the plurality of banks to each master of the plurality of masters based on the memory access pattern of each master. | 2011-04-14 |
20110087847 | MULTIPLE-PORT MEMORY SYSTEMS AND METHODS - Systems and methods for improved multiple-port memory are provided. In one embodiment, a processing system comprises: at least one processing core; a peripheral bus; and a memory for storing digital data, the memory divided into a first and a second partition of memory segments. The memory includes a first port coupled to the peripheral bus providing read access and write access only to the first partition, wherein the first partition stores peripheral data associated with one or more peripheral components coupled to the peripheral bus; a second port coupled to the at least one processor providing read-only access to only the second partition, wherein the second partition stores executable code for the at least one processing core; and a third port coupled to the at least one processor providing read access and write access to the entire first partition and the second partition. | 2011-04-14 |
20110087848 | METHODS AND SYSTEMS FOR IMPLEMENTING A VIRTUAL STORAGE NETWORK - Embodiments of the invention provide systems and methods for implementing a virtual Storage Area Network (SAN) in software. According to one embodiment, a method for implementing a virtual SAN can comprise defining an application for accessing a computing grid for storing information wherein defining the application for accessing the computing grid for storing the information comprises defining a resource and defining one or more state objects for the resource, wherein the one or more state objects are handled independent from the resource. For example, the computing grid can comprise an Oracle Coherence grid. Such a computing grid can maintain a primary copy and a backup copy of the information and provides the backup of the information if the primary copy is unavailable. The information stored on the computing grid can be accessed via the application. | 2011-04-14 |
20110087849 | METHOD AND APPARATUS FOR IMPLEMENTING INTERLEAVING AND DE-INTERLEAVING AT SECOND TIME - A method for second interleaving is disclosed. The method comprises: generating an interleaving address preset in an interleaving matrix for each input data, and writing the data into the interleaving matrix according to the interleaving address; initializing the interleaving address and reading out the data from the interleaving matrix according to the interleaving address; judging whether the reading operation on a column of data in the interleaving matrix is completed or not, if completed, then calculating the interleaving address of the next column in the interleaving matrix according to inter-column replacement rules; otherwise, obtaining the interleaving address by adding its own value to the column spacing; judging whether the reading operations on all data are completed or not, if completed, then the second interleaving ending; otherwise, returning to the step of reading out the data from the interleaving matrix according to the interleaving address, and repeating the above operation. A method for second de-interleaving and the corresponding apparatus for second interleaving and de-interleaving are also disclosed. | 2011-04-14 |
20110087850 | STORAGE APPARATUS AND METHOD FOR STORAGE APPARATUS - A storage apparatus includes a storage module, a memory having areas storing data to be copied to the storage device, a saving buffer for temporarily saving the data stored in the areas, a control module for executing receiving a write request including the data to be stored in the storage apparatus, storing the data included in the write request to the storage module and one area, saving the data stored in the one area to the saving buffer when the number of areas which the copying is executed is not less than the threshold value, copying the data stored in the one area to the storage device or writing the saved data stored in the saving buffer to the one area when the number of areas which the copying is executed is less than the threshold value, determining the threshold value in accordance with an amount of the write request. | 2011-04-14 |
20110087851 | SYSTEMS AND METHODS FOR COMBINING DATA STREAMS IN A STORAGE OPERATION - Described herein are systems and methods for multiplexing pipelined data for backup operations. Various data streams are combined such as by multiplexing by a multiplexing module. The multiplexing module combines the data from the various data streams received by receiver module(s) into a single stream of chunks. The multiplexing module may combine data from multiple archive files into a single chunk. Additional modules perform other operations on the chunks of data to be transported such as encryption, compression, etc. The data chunks are transmitted via a transport channel to a receive pipeline that includes a second receiver module and other modules. The data chunks are then stored in a backup medium. The chunks are later retrieved and separated such as by demultiplexing for restoring to a client or for further storage as auxiliary copies of the separated data streams or archive files. | 2011-04-14 |
20110087852 | METHOD OF AND SYSTEM FOR CONTROLLING THE PROGRAMMING OF MEMORY DEVICES - In order to further develop a method of and a system ( | 2011-04-14 |
20110087853 | Storage Device, Substrate, Liquid Container, System and Control Method of Storage Device - A storage device includes a nonvolatile storage section; and a control section that controls the nonvolatile storage section, wherein the control section includes an access control section that outputs a clock for access control for performing access control of a read/write of the nonvolatile storage section, and performs access control of the read/write to the nonvolatile storage section, and a masking process section that performs the masking process of a reset signal on the basis of the clock for access control from the access control section, and supplies the reset signal after the masking process to the access control section. | 2011-04-14 |
20110087854 | TIERED DATA MANAGEMENT METHOD AND SYSTEM FOR HIGH PERFORMANCE DATA MONITORING - A method for managing memory in a system for an application, comprising: assigning a first block (i.e., a big block) of the memory to the application when the application is initiated, the first block having a first size, the first block being assigned to the application until the application is terminated; dividing the first block into second blocks (i.e., intermediate blocks), each second block having a same second size, a second block of the second blocks for containing data for one or more components of a single data structure to be accessed by one thread of the application at a time; and, dividing the second block into third blocks (i.e., small blocks), each third block having a same third size, a third block of the third blocks for containing data for a single component of the single data structure. | 2011-04-14 |
20110087855 | Method and Apparatus for Protecting Data Using Variable Size Page Stripes in a FLASH-Based Storage System - Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of using variable size page stripes in the memory system. The controller is configured to store data such that each page stripe comprises a plurality of data pages, with each data page in the page stripe being stored in a different FLASH memory chip. The controller is also configured to maintain one or more buffers containing information reflecting blocks of memory within the FLASH memory chips that have been erased and are available for information storage, and to dynamically determine the number of data pages to be included in a page stripe based on the information in the one or more buffers such that a first page stripe and a second page stripe can have different numbers of data pages. | 2011-04-14 |
20110087856 | Memory Device with Serial Protocol and Corresponding Method of Addressing - The memory device comprises a physical memory plane (PMP) comprising m first physical lines (RGP | 2011-04-14 |
20110087857 | AUTOMATIC PAGE PROMOTION AND DEMOTION IN MULTIPLE PAGE SIZE ENVIRONMENTS - Functionality can be implemented in a virtual memory manager (VMM) to allow small pages (e.g., 4 KB) to be coalesced into large pages (e.g., 64 KB), so that a single free list can be maintained for the large pages (“maintained pages”). When a process requests a small page, the VMM can associate a maintained page with a memory segment accessible by the process. Then, the maintained page can be divided to form a set of small pages (“fragments”). The fragments can become available pages in a broken page list. The VMM can satisfy the request by allocating one of the fragments in the broken page list. If the process requests additional small pages, the additional requests can be satisfied from the broken page list. When the process terminates, the fragments in the broken page list become a maintained page and can be returned to the free list. | 2011-04-14 |
20110087858 | Memory management unit - A data processing apparatus is provided comprising a plurality of master devices configured to issue memory access requests including virtual addresses. A memory management unit is configured to receive memory access requests and to translate a virtual address included in a memory access request from a requesting master device into a physical address indicating a storage location in memory. The memory management unit has an internal storage unit having a plurality of entries wherein indications of corresponding virtual address portions and physical address portions are stored. The memory management unit is configured to select an entry of the internal storage unit in dependence on the virtual address and an identifier of the requesting master device. Conflict between the master devices in their usage of the internal storage unit is thus avoided. | 2011-04-14 |
20110087859 | SYSTEM CYCLE LOADING AND STORING OF MISALIGNED VECTOR ELEMENTS IN A SIMD PROCESSOR - The present invention provides efficient transfer of misaligned vector elements between a vector register file and data memory in a single clock cycle. One vector register of N elements can be loaded from memory with any memory element address alignment during a single clock cycle of the processor. Also, a partial segment of vector register elements can be loaded into a vector register in a single clock cycle with any element alignment from data memory. The present invention comprises properly partitioned multiple multi-port data memory modules in conjunction with a crossbar and address generation circuit. A preferred embodiment of the present invention uses a dual-issue processor containing both a RISC-type scalar processor and a vector/SIMD processor, whereby one scalar and one SIMD instruction are executed every clock cycle, and the RISC processor handles program flow control and also loading and storing of vector registers. | 2011-04-14 |
20110087860 | PARALLEL DATA PROCESSING SYSTEMS AND METHODS USING COOPERATIVE THREAD ARRAYS - Parallel data processing systems and methods use cooperative thread arrays (CTAs), i.e., groups of multiple threads that concurrently execute the same program on an input data set to produce an output data set. Each thread in a CTA has a unique identifier (thread ID) that can be assigned at thread launch time. The thread ID controls various aspects of the thread's processing behavior such as the portion of the input data set to be processed by each thread, the portion of an output data set to be produced by each thread, and/or sharing of intermediate results among threads. Mechanisms for loading and launching CTAs in a representative processing core and for synchronizing threads within a CTA are also described. | 2011-04-14 |
20110087861 | System for High-Efficiency Post-Silicon Verification of a Processor - A post-silicon validation technique is able to craft randomized executable code, with known final outcomes, as a verification test that is executable on a hardware, such as a prototype microprocessor. A verification device is able to generate the test, in the form of programs, in such a way that at the end of the execution, the initial state of the test hardware is restored. Therefore, the final state of such a reversible program is known a priori. The technique may use a program generation algorithm, agnostic to any particular instruction set on the test hardware. In some examples, that algorithm is executed on the test hardware to generate the verification test, which is then executed on that test hardware. In other examples, the verification test is generated on another processor coupled to the test hardware. In either case, the verification test may contain initial and inverse operations determined from the test hardware. | 2011-04-14 |
20110087862 | Multiprocessor resource optimization - Embodiments include a device and a method. In an embodiment, a method applies a first resource management strategy to a first resource associated with a first processor and executes an instruction block in a first processor. The method also applies a second resource management strategy to a second resource of a similar type as the first resource and executes the instruction block in a second processor. The method further selects a resource management strategy likely to provide a substantially optimum execution of the instruction group from the first resource management strategy and the second resource management strategy. | 2011-04-14 |
20110087863 | DATA PROCESSING APPARATUS HAVING A PARALLEL PROCESSING CIRCUIT INCLUDING A PLURALITY OF PROCESSING MODULES, AND METHOD FOR CONTROLLING THE SAME - In an apparatus which includes a plurality of processing modules connected via a ring-shape bus, if a plurality pieces of pipeline processing to be processed in a different order is allocated to a plurality of processing modules, the transfer efficiency may decrease when an amount of data transferred from one of the processing modules to a post-stage module exceeds a processing capacity of the post-stage module. Accordingly, a module positioned on the preceding side in the pipeline processing controls a transmission interval of processed data so that the post-stage module can receive the data processed by the preceding module. | 2011-04-14 |
20110087864 | PROVIDING PIPELINE STATE THROUGH CONSTANT BUFFERS - One embodiment of the present invention sets forth a technique for providing state information to one or more shader engines within a processing pipeline. State information received from an application accessing the processing pipeline is stored in constant buffer memory accessible to each of the shader engines. The shader engines can then retrieve the state information during execution. | 2011-04-14 |
20110087865 | Intermediate Register Mapper - A method, processor, and computer program product employing an intermediate register mapper within a register renaming mechanism. A logical register lookup determines whether a hit to a logical register associated with the dispatched instruction has occurred. In this regard, the logical register lookup searches within at least one register mapper from a group of register mappers, including an architected register mapper, a unified main mapper, and an intermediate register mapper. A single hit to the logical register is selected among the group of register mappers. If an instruction having a mapper entry in the unified main mapper has finished but has not completed, the mapping contents of the register mapper entry in the unified main mapper are moved to the intermediate register mapper, and the unified register mapper entry is released, thus increasing a number of unified main mapper entries available for reuse. | 2011-04-14 |
20110087866 | PERCEPTRON-BASED BRANCH PREDICTION MECHANISM FOR PREDICTING CONDITIONAL BRANCH INSTRUCTIONS ON A MULTITHREADED PROCESSOR - A multithreaded microprocessor includes an instruction fetch unit including a perceptron-based conditional branch prediction unit configured to provide, for each of one or more concurrently executing threads, a direction branch prediction. The conditional branch prediction unit includes a plurality of storages each including a plurality of entries. Each entry may be configured to store one or more prediction values. Each prediction value of a given storage may correspond to at least one conditional branch instruction in a cache line. The conditional branch prediction unit may generate a separate index value for accessing each storage by generating a first index value for accessing a first storage by combining one or more portions of a received instruction fetch address, and generating each other index value for accessing the other storages by combining the first index value with a different portion of direction branch history information. | 2011-04-14 |
20110087867 | PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION - A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed. | 2011-04-14 |
20110087868 | CHANGING THE PERSONALITY OF A DEVICE BY INTERCEPTING REQUESTS FOR PERSONALITY INFORMATION - A method and system for a target to adopt the personality of a source without loading the personality information of the source onto the target is provided. The personality system extracts personality information from the source and stores the personality information on a removable storage medium. The storage medium is then connected to the target. The personality system intercepts requests of the target to retrieve personality information, which but for the interception would be serviced based on personality information of the target. When a request is intercepted, the personality system retrieves the personality information from the connected storage medium, rather than from the personality information of the target. The personality system then replies to the request with the retrieved personality information. | 2011-04-14 |
20110087869 | IMAGE FORMING APPARATUS, IMAGE FORMING SYSTEM, AND METHOD OF CONFIGURING IMAGE FORMING APPARATUS - According to one embodiment, there is provided an image forming apparatus including a configuration creating unit, a storage, a timer, a schedule management unit, and a configuration processing unit. The configuration creating unit creates machine configuration information in accordance with the contents of a machine configuration input by a user. The storage stores the machine configuration information created by the configuration creating unit. The timer measures the present date and time. The schedule management unit retrieves machine configuration information that is to be applied to the image forming apparatus based on the present date and time measured by the timer and the schedule of the machine configuration information stored in the storage. The configuration processing unit applies machine configuration information retrieved by the schedule management unit as the machine configuration information to be applied to the image forming apparatus. | 2011-04-14 |
20110087870 | COMPUTING DEVICE WITH DEVELOPER MODE - Methods and apparatus for implementing modes of operation of computing device are disclosed. An example apparatus includes a mode-selection input device having a first state and a second state. The example apparatus also includes firmware operably coupled with the mode-selection input device. In the example apparatus, when the mode-selection input device is in the first state, the firmware is configured to cause the computing device to operate in a first mode of operation, a user mode. In the example apparatus, when the mode-selection input device is in the second state, the firmware is configured to cause the computing device to operate in second mode of operation, a developer mode. | 2011-04-14 |
20110087871 | CONSUMER ELECTRONIC DEVICE AND METHOD OF CONTROLLING A CONSUMER ELECTRONIC DEVICE - A method and apparatus for controlling a consumer electronics (CE) device, are provided. The method includes determining, when a touch is sensed, whether the touch corresponds to a booting request, and performing a booting operation when the touch is a booting request; and controlling the CE device to operate in a sleep mode when an operation start signal is not received until the booting operation is completed, and controlling the CE device to operate in a normal mode when an operation start signal is received before the booting operation is completed. The apparatus includes a touch sensing unit; which senses a touch to the CE device; a determining unit which determines whether the touch sensed by the touch sensing unit corresponds to a booting request; a booting unit, and a control unit controlling the CE device. | 2011-04-14 |
20110087872 | Firmware Verified Boot - Methods and apparatus for verifying a boot process of a computing system are disclosed. An example computer-implemented method includes reading, by a computing system during a boot process, a header section of a read-write portion of firmware of the computing system. The example method further includes generating, using a first cryptographic hash algorithm, a message digest corresponding with the header. The example method also includes decrypting, using a first public-key, an encrypted signature corresponding with the header. The example method still further includes comparing the message digest corresponding with the header and the decrypted signature corresponding with the header. In the event the message digest corresponding with the header and the decrypted signature corresponding with the header match, the example method includes continuing the boot process. In the event the message digest corresponding with the header and the decrypted signature corresponding with the header do not match, the example method includes halting the boot process. | 2011-04-14 |
20110087873 | INFORMATION PROCESSING APPARATUS AND ITS CONTROL METHOD - An information processing apparatus includes: a first recording medium that stores a first system controller for allowing to execute boot processing of the information processing apparatus and is accessed by using a first access path in a tree structure or by using a second access path based on a first conversion table representing a correspondence between the first and second access path; a memory disk generation section allowing to secure a memory disk section that operates as a second recording medium and is accessed by using a third access path; a conversion table generation section allowing to generate a second conversion table representing a correspondence between the second and third access path; and a duplication controller allowing to copy the first system controller onto the memory disk section as a second system controller and allowing to duplicate the first and second system controllers based on the second conversion table. | 2011-04-14 |
20110087874 | ITEM-LEVEL RESTORATION AND VERIFICATION OF IMAGE LEVEL BACKUPS - Systems and methods for item-level restoration from and verification of an image level backup without fully extracting it. The method receives backup parameters and selection of an image level backup to restore or verify and initializes virtual storage. The method attaches the virtual storage to a hypervisor to launch a virtual machine (VM) to test and restore data objects. The method stores VM virtual disk data changes resulting from restoration and verification in a changes storage. The method optionally reconfigures VMs to use an isolated network. The method optionally uses a routing appliance to provide access to VMs running in the isolated network from a production network. The method determines if the VM operating system (OS) is able to start using restored copies of selected data objects and tests applications associated with selected data objects. The method displays restoration and test results in an interface and automatically delivers the results. | 2011-04-14 |
20110087875 | PERFORMANCE ADJUSTMENT APPARATUS AND METHOD OF INFORMATION PROCESSING APPARATUS - A performance adjustment apparatus connected to an information processing apparatus includes a performance adjustment unit that controls operation processing performance of an operation processing apparatus of the information processing apparatus based on a specified performance adjustment value, a performance type list information management unit that manages performance type list information comprising a plurality of pairs of a performance type and a performance adjustment value, a performance type specification unit that specifies a performance type in the performance type list information managed by the performance type list information management unit and changes the performance type, a performance adjustment value setting unit that obtains a performance adjustment value corresponding to the performance type specified by the performance type specification unit from the performance type list information management unit, and sets the obtained performance adjustment value in the performance adjustment unit. | 2011-04-14 |
20110087876 | Dynamic Analytical Differentiator For Obfuscated Functions In Complex Models - Systems and methods are provided for providing secure transmission of software code, which includes a mathematical function, from a first computer to a second computer so that the mathematical function's content cannot be determined at the second computer. A method includes generating a secure container, where the secure container includes an encrypted representation of the mathematical function and metadata identifying the mathematical function encrypted in the secure container. The method further includes providing the secure container from the first computer to the second computer over a communication transmission medium, where the secure container is accessed at the second computer using the metadata to identify the mathematical function, and where the mathematical function contained within the secure container is decrypted and incorporated into program code in a compiled form so that the mathematical function can be used but the mathematical function's content cannot be determined at the second computer. | 2011-04-14 |
20110087877 | SYSTEM, DEVICE AND METHOD FOR SECURELY TRANSFERRING DATA ACROSS A NETWORK - A method, system, server device and computer program product for securely transferring data from one or more non-subscribers to a subscriber or subscriber-defined destination, via a network, are provided. Access is provided, to one or more non-subscriber, to a network location indicator (NLI) and a private data transfer conduit is established, accessible via the NLI and configured to accept data from the non-subscribers. Data received at the conduit is transformed into secured data and transferred to the subscriber or subscriber-defined destination. In some embodiments, access to the NLI may be provided by accepting a request from a subscriber and sending, upon receipt of the request, a notification to at least one non-subscriber. | 2011-04-14 |
20110087878 | ENABLING QoS FOR MACsec PROTECTED FRAMES - Embodiments associated with enabling Quality of Service (QoS) for MACsec protected frames are described. One example method includes identifying a security indicator in an encrypted network communication and selectively forwarding the encrypted network communication according to a QoS policy. The example method may also include selectively storing a control packet security indicator sniffed from a control packet network communication in response to determining that a match exists between a control packet identification field and a QoS database entry. | 2011-04-14 |
20110087879 | Communication network with secure access for portable users - A communication network includes a local area network (LAN) and a wireless access point coupled to the LAN. In one embodiment, each access point includes a medium access control (MAC) stage, and a radio frequency (RF) transmitter/receiver for communicating unsecure message data via RF links with users of associated wireless devices. An optical transmitter/receiver in the access point enables the users to communicate secure message data over the LAN via free space optical (FSO) links with the users. The MAC stage operates (i) to direct unsecure data from the LAN to the wireless device users and to direct unsecure data from the users to the LAN, via the RF transmitter/receiver; and (ii) to direct secure data from the LAN to the wireless device users and to direct secure data from the users to the LAN, via the optical transmitter/receiver. An integrated VoIP/FSO portable handset is also disclosed. | 2011-04-14 |
20110087880 | REVOCATION OF CREDENTIALS IN SECRET HANDSHAKE PROTOCOLS - According to a general aspect, a computer-implemented method for a first user to verify an association with a second user through a secret handshake protocol includes maintaining information about a reusable identification handle for the first user, where the information about the reusable identification handle is provided by a trusted third party, maintaining information about a reusable credential for the first user, where the information about the reusable credential is provided by a trusted third party, and maintaining information about a matching reference for verifying an association with another user, where the information about the matching reference is provided by a trusted third party. Information based on the reusable identification handle and based on the reusable credential is transmitted to a potential peer. First information based on a reusable identification handle for the second user is received, and second information based on a reusable credential for the second user is received. A first comparison of a combination of the first information and the second information is performed with the matching reference to determine whether the second user's credentials match the first users matching reference. A second comparison of the first information with information published on a revocation list is performed to determine whether the second user's credentials have been revoked from usage. Based on the first comparison and the second comparison, a determination is made whether or not to verify the association of second user with the first user. | 2011-04-14 |
20110087881 | APPARATUS AND METHOD FOR MONITORING CERTIFICATE ACQUISITION - A system that incorporates teachings of the present disclosure may include, for example, a set-top-box (STB) having a controller to transmit a request to a remote management server for status information associated with a x.509 certificate intended for the STB, wherein at least one of the STB and the remote management server operate in an interactive television (iTV) network, and receive the status information associated with the x.509 certificate from the remote management server, wherein events associated with the status information are received by the remote management server from at least one of the STB, a certificates proxy, an external certificate web service, and a certificate authority, and wherein the status information comprises at least a portion of the received events. Other embodiments are disclosed. | 2011-04-14 |
20110087882 | APPARATUS AND METHODS FOR PROTECTING NETWORK RESOURCES - Apparatus and methods are provided for protecting network resources, particularly in association with automatic provisioning of new client devices. A global PKI (Public Key Infrastructure) scheme is rooted at a globally available server. Roots of PKIs for individual organizations also reside at this server or another globally available resource. To enable access to an organization's network, one or more authenticators are deployed, which may be co-located with access points or other network components. After a client device enabler (CDE) and an authenticator perform mutual authentication with certificates issued within the global PKI, the CDE is used to provision a new client device for the organization. After the client is provisioned, it and an authenticator use certificates issued within the per-organization PKI to allow the client access to the network. | 2011-04-14 |
20110087883 | SELF-SIGNED IMPLICIT CERTIFICATES - There are disclosed systems and methods for creating a self-signed implicit certificate. In one embodiment, the self-signed implicit certificate is generated and operated upon using transformations of a nature similar to the transformations used in the ECQV protocol. In such a system, a root CA or other computing device avoids having to generate an explicit self-signed certificate by instead generating a self-signed implicit certificate. | 2011-04-14 |
20110087884 | Methods and Systems for Improving the Security of Password-Based Authentication Protocols for IEEE 802.11 Networks - A password element is generated for a station running an Elliptic Curve Cryptography (ECC) or a Finite Field Cryptography (FFC) group based password authenticated protocol. A password element is multiplied by a cofactor to generate a modified password element for the ECC group. The station verifies that the modified password element is not equal to a point at infinity for the ECC group. A password element is generated by exponentiating a password value to a power t, where t=(p−1)/r, p and r are primes, and r has a bit length of at least 160 bits for the FFC group. A commit-element parameter is generated using a temporary secret value and the ECC modified password element or the FFC password element, and is then transmitted to another station in a commit message. The receiving station checks if the received commit-element parameter has desired properties before continuing with the protocol. | 2011-04-14 |
20110087885 | METHOD AND APPARATUS FOR EFFICIENT AND SECURE CREATING, TRANSFERRING, AND REVEALING OF MESSAGES OVER A NETWORK - An encryption based method of enabling a plurality of parties to share, create, hide, or reveal message or token information over a network includes a commutative group cipher (CGC), where the underlying CGC is secure against ciphertext-only attack (COA) and plaintext attacks (KPA), and is deterministic. The protocols doe not require a trusted third party (TTP), and execute rapidly enough on ordinary consumer computers as to be effective for realtime play among more than two players. Protocols are defined which include VSM-L-OL, VSM-VL, VSM-VPUM, and VSM-VL-VUM, wherein the letters V, O, SM, P, and UM represent, respectively, Verified, Locking Round, Open, Shuffle-Masking Round, Partial, and Unmasking Round. | 2011-04-14 |
20110087886 | SYSTEM AND METHOD FOR OPEN DISTRIBUTION OF DIGITAL MEDIA - Various embodiments of the present invention provide a system and method for open digital media distribution. According to one embodiment, a system is provided which performs the operations of: creating a profile (e.g., artist or label profile) based on an input from a first party; receiving a digital media upload from the first party, wherein the digital media upload contains media content and the first party has a property interest in the media content; receiving from the first party an assignment of a payment account to the digital media upload, such that money from sales relating to the digital media upload is deposited into the payment account; receiving from the first party a sales parameters associated with the digital media upload; presenting through a computing device the digital media upload for sale to a second party; and selling the digital media upload to the second party through a computing device. | 2011-04-14 |
20110087887 | METHODS AND APPARATUS FOR DIGITAL ATTESTATION - Methods and apparatus for providing proof of multiple entities being co-located at a specific time and location. An attestor transmits an attestation message via short range communication; the attestation message includes a time stamp, a location stamp, and a verifiable digital signature. An attestee that stores the attestation message can produce the attestation message at a later time to any interested party, as proof of co-location with the attestor at the specified time and location. In one exemplary embodiment, the methods and apparatus are substantially “open” for public implementation. Such public implementation enables attestors and attestees without prior affiliation, to provide attestation. Furthermore, the device-agnostic methods and apparatus can provide attestation capabilities even in previously deployed systems and devices. | 2011-04-14 |
20110087888 | AUTHENTICATION USING A WEAK HASH OF USER CREDENTIALS - Methods and apparatus for logging into a computer. The computer receives a username and password. The computer determines whether a user with the username is authorized to access the computer. If so, the computer retrieves a weak cryptographic hash of the user's password and compares it to a weak cryptographic hash of the received password. The computer grants access if the weak cryptographic hashes are identical, and sends the username and password to a server. The server determines whether a user with the username has a server account. If so, the server retrieves a strong cryptographic hash of the user's password and compares it to a strong cryptographic hash of the received password. The server grants the user access to an account or service if the strong cryptographic hashes are identical. | 2011-04-14 |
20110087889 | System and Method of Providing Security to an External Attachment Device - Systems and methods of providing security to an external Serial Advanced Technology Attachment (SATA) device are described herein. A controller is connected between the eSATA device and the computing device. On startup, the controller presents a first partition of eSata device as a Read Only Memory, e.g., CD-ROM, but at the same time it restricts access of the computing device to a second partition of the eSata device until receiving a valid identity authentication. The second partition is preferably encrypted with a key stored on a first partition. Decryption is performed in the controller as part of presenting the eSata device. The authentication process is preferably stored in the first partition and downloaded to the computing device on startup. | 2011-04-14 |
20110087890 | INTERLOCKING PLAIN TEXT PASSWORDS TO DATA ENCRYPTION KEYS - Described embodiments provide for authenticating a user request for access to at least a portion of an encrypted storage device. First, the request for access to at least a portion of the encrypted storage device is received. The request includes a plaintext password. A hash module generates a hashed version of the received plaintext password based on an authentication hash key. A hashed value of the generated plaintext password is retrieved from a key storage. A hash comparator compares the hashed version of the received plaintext password with the retrieved hashed value of the generated plaintext password. If the hashed version of the received plaintext password and the retrieved hashed value of the generated plaintext password are equal, the user is authenticated for access to at least a portion of the encrypted storage device. Otherwise, the user is denied access to the encrypted storage device. | 2011-04-14 |
20110087891 | METHOD FOR PRODUCING, ALLOCATING AND CHECKING AUTHORIZATION APPROVALS - In a method for producing, allocating and checking authorization approvals that are required in order to fulfill tasks specified by an action plan through performance, by a service technician, of actions defined by the tasks on a device or component of a distributed structure on-the-fly generation and distribution of authorization approvals for service technicians is enabled as a function of necessary actions or measures which are to be performed in the form of tasks and are defined as part of an action plan which is contained or recorded in a work schedule. | 2011-04-14 |
20110087892 | Eliminating False Reports of Security Vulnerabilities when Testing Computer Software - A system for eliminating false reports of security vulnerabilities when testing computer software, including a taint analysis engine configured to identify a tainted variable v in a computer application, a data mapping identification engine configured to identify a variable x within the application that holds data derived from v, where x is in a different format than v, an AddData identification engine configured to identify an AddData operation within the application that is performed on x, a signature identification engine configured to identify a Sign operation within the application that is performed on the results of the AddData operation on x, a signature comparison identification engine configured to identify an operation within the application that compares the results of the Sign operation with another value | 2011-04-14 |
20110087893 | APPARATUS AND METHOD FOR PREVENTING FALSIFICATION OF BLACK BOX DATA - Provided are an apparatus and method for preventing falsification of black box data. The apparatus for preventing falsification of black box data includes a driving information storage module and a falsification prevention module. The driving information storage module stores a driving information data which is collected by a black box. The falsification prevention module encrypts the driving information data to generate a falsification determination data through a predetermined encryption mechanism, and stores the falsification determination data. | 2011-04-14 |
20110087894 | METHOD OF MANAGING MULTIMEDIA DATA AND MOBILE COMMUNICATION TERMINAL EQUIPPED WITH FUNCTION OF MANAGING MULTIMEDIA DATA - A mobile communication terminal having a function of managing multimedia data is provided, including: a main memory including a multimedia database storing the multimedia data; a signal processor converting the multimedia data stored in the main memory into data of a format suitable to be output to a display of the mobile communication terminal; a back_end chip which processes the multimedia data outputted from the signal processor, stores digest information of multimedia data upon occurrence of an update event of the multimedia data, and provides the stored digest information upon receiving a signal of requesting the digest information to be synchronized; and a front_end chip including a controller which requests the digest information stored in the back_end chip, compares and synchronizes the digest information offered from the back_end chip and digest information stored in advance in the front_end chip. | 2011-04-14 |
20110087895 | APPARATUS AND METHOD FOR LOCAL OPERAND BYPASSING FOR CRYPTOGRAPHIC INSTRUCTIONS - A processor may include a hardware instruction fetch unit configured to issue instructions for execution, and a hardware functional unit configured to receive instructions for execution, where the instructions include cryptographic instruction(s) and non-cryptographic instruction(s). The functional unit may include a cryptographic execution pipeline configured to execute the cryptographic instructions with a corresponding cryptographic execution latency, and a non-cryptographic execution pipeline configured to execute the non-cryptographic instructions with a corresponding non-cryptographic execution latency that is longer than the cryptographic execution latency. The functional unit may further include a local bypass network configured to bypass results produced by the cryptographic execution pipeline to dependent cryptographic instructions executing within the cryptographic execution pipeline, such that each instruction within a sequence of dependent cryptographic instructions is executable with the cryptographic execution latency, and where the results of the cryptographic execution pipeline are not bypassed to any other functional unit within the processor. | 2011-04-14 |
20110087896 | SECURE STORAGE OF TEMPORARY SECRETS - Temporarily sensitive information can be stored in the non-volatile storage of a TPM, from which it can be securely, and irretrievably, deleted. Additionally, information stored in a TPM can secure information stored on communicationally disconnectable storage media such that, when communicationally disconnected, the information stored on such media is inaccessible. A whole volume encryption service key can be protected by a key stored in a TPM and, even if the protector remains accessible, the secure deletion of the key from the TPM prevents unauthorized disclosure of the whole volume encryption service key. Additionally, TPM stored data can be released only when a computing device is in a particular state, as determined by the PCRs. A hibernation image can be encrypted and the key stored with the TPM such that it is released to decrypt the image and restore active computing only if the state has not materially changed during hibernation. | 2011-04-14 |
20110087897 | Hardware-Based Key Generation and Recovery - A system and method of recovering encoded information contained in a device by storing and retrieving at least part of the necessary decoding data by setting and measuring the physical characteristics of the device. Storage and recovery options include, but are not limited to, measurement of electronic or optical characteristics of electrically or optically conductive portions of the device using a range of measurement techniques that include, but are not limited to, time-domain reflectometry. | 2011-04-14 |
20110087898 | SAVING ENCRYPTION KEYS IN ONE-TIME PROGRAMMABLE MEMORY - Described embodiments provide encryption/decryption of data transferred between a media controller and a storage device. The media controller provides encryption/decryption based on a root key (RK). Storage in a one-time programmable (OTP) memory is provided as a plurality of un-burned slots. The OTP memory is initially provided without the RK, which is generated with a random number generator. A control module performs the steps of i) burning the RK to an initial slot of the OTP memory, and ii) validating the burned RK (bRK) stored at the initial slot based on a comparison of the RK and the burned RK. If the control module validates the burned RK, the burned RK is employed by the media controller. Otherwise, one or more subsequent slots of the OTP memory are burned with the RK until the control module validates the corresponding burned RK. | 2011-04-14 |
20110087899 | FIREWALL PLUS STORAGE APPARATUS, METHOD AND SYSTEM - A storage firewall architecture, method and system that works in parallel with existing security technologies and, inter alia, provides application software authentication, user authentication & authorization in the execution of an application, examination, verification, and authentication of all storage access requests, monitoring of protected storage to detect & repair anomalous changes, encryption of protected storage, both data and software, provisioning (deployment) of patches, configuration changes, and software through a secure synchronization link to a configuration and patch management server, and server-based system administration & configuration to prevent malware from penetrating local configuration mechanisms. | 2011-04-14 |
20110087900 | DYNAMIC TABLE LOOK-UP BASED VOLTAGE REGULATOR CONTROL - A technique for dynamically controlling microprocessor power plane voltage levels includes storing in a memory on a voltage regulator voltage control identifiers in a table accessible according to performance state. In at least one embodiment of the invention, a method includes transitioning a voltage output of a voltage regulator to a next voltage level associated with a next performance state of a processor coupled to the voltage regulator based on a performance state indicator received from the processor and a corresponding entry of a performance state table. In at least one embodiment, the method includes loading performance state table entries into a storage device on the voltage regulator circuit. | 2011-04-14 |
20110087901 | FAST SPEED COMPUTER SYSTEM POWER-ON & POWER-OFF METHOD - A fast speed computer system power-on & power-off method, that is used to reduce an amount of main memory transferred and stored from a main memory into a second storage device, thus speeding up a speed of re-activation of a computer system from a hibernation state into a full speed operation state. Said fast speed computer system power-on & power-off method is applicable to various types of computer systems, and can be used to write in and load back data in cooperation with a random access processing technology. In addition, said method can be used to reduce extent of data loss and damage of said computer system due to a sudden power outage of said computer system. | 2011-04-14 |