14th week of 2010 patent applcation highlights part 51 |
Patent application number | Title | Published |
20100088423 | ESTABLISHING AND MAINTAINING A CONNECTION BY A CLIENT TO A SERVER WITHIN A NETWORK - A method for establishing and maintaining a connection by a client to a server within a network includes creating a socket for connecting to the server, based on authentication information associated with the client, and connecting to the server using the socket. In addition, the method includes saving the authentication information associated the client. The method further includes in a case where subsequent connection to the server is requested by the client, reconnecting to the server via the socket, based on the saved authentication information. An apparatus for establishing and maintaining a connection by a client to a server within a network is also provided. | 2010-04-08 |
20100088424 | Efficient Buffer Utilization in a Computer Network-Based Messaging System - Buffering messages by receiving a message from a messaging client, writing the message to a logically-contiguous write-available region of a message buffer starting at a logically next write-available location within the write-available region, updating a head index to indicate a head boundary between a logically last message in the message buffer and a logically next write-available location in the message buffer, defining a packet including the message within the message buffer, transmitting a packet that includes a logically first message in the message buffer, and updating a tail index to indicate a tail boundary between a new logically last write-available location in the message buffer and a new logically first message in the message buffer. | 2010-04-08 |
20100088425 | LOCATION BASED MULTICAST POLICIES - Disclosed herein in an example embodiment is a multicast policy infrastructure that allows administrators to integrate location awareness for a particular multicast stream when it is being forwarded to an intended user. The infrastructure provides more flexibility by allowing multicast call admission control, access control, and other multicast policies to be based on the location or conditions where the host/user is receiving the multicast stream. A multicast policy can also provide additional mechanisms such as transcoding services, compression services, etc. based on the host/user location. As will be demonstrated in example embodiments herein, location awareness can include connectivity media (wired or wireless), physical location of user, and/or signal strength (and/or effective bandwidth). | 2010-04-08 |
20100088426 | RECEPTION APPARATUS RECEPTION METHOD, AND COMPUTER PROGRAM - A reception apparatus receiving a stream delivered by multicast through a network includes: a stream reception section receiving a stream of a first channel as a viewing stream and one or more streams of second channels as viewing candidate streams; a buffer section storing the streams of the channels received by the stream reception section; a reproduction processing section performing processing for viewing the stream stored as the viewing stream in the buffer section; and a channel processing section causing, when an instruction to switch over, as a viewing target, from the first channel to any one of the second channels of the streams being received as the viewing candidate streams is input, the reproduction processing section to process as the viewing stream the stream corresponding to the second channel and stored in the buffer section, and the stream reception section to receive the stream as the viewing stream. | 2010-04-08 |
20100088427 | Selective Routing of Data Transmission Between Clients - A method for selective routing of data transmission between clients is provided to select a better communication channel from a direct P2P channel and a relay channel according to routing hop counts of the pats. The method obtains a first routing hop count from a first client to a second client assuming a direct P2P channel therebetween, a second routing hop count from the first client to a relay server assuming a relay channel through the relay server, and a third routing hop count from the relay server two the second client assuming the relay channel through the relay server, and compares the sum of the second routing hop count and the third routing hop count with the first routing hop count. The method then selects a better data transmission channel from the direct P2P channel and the relay channel between the first client and the second client based on a comparison result. Also disclosed is a system using the method for selective routing. | 2010-04-08 |
20100088428 | INDEX RANK OPTIMIZATION SYSTEM AND METHOD - An index ranking optimization system and method are provided herein. | 2010-04-08 |
20100088429 | METHOD FOR CONSTRUCTING A DECOMPOSITION DATA STRUCTURE OF MULTIPLE LEVELS OF DETAIL DESIGN FEATURE OF 3D CAD MODEL AND STREAMING THEREOF - A method for streaming multi-LOD design feature of a 3D-CAD model comprises defining a LOD of a 3D-CAD model with each design feature of the 3D-CAD model, wherein the design feature is the smallest 3D-CAD model constructing unit; constructing the LOD of the 3D-CAD model into a decomposition data structure of LOD design feature recording each design feature of the 3D-CAD model in different LODs, wherein the LOD comprises all unit assembly faces of the design features; constructing a switch face display mechanism controlling whether each design feature of the 3D-CAD model is displayed; and encapsulating a designated design feature into a packet based on users' configuration and transmitting the packet. The invention achieves multi-tier real-time incremental streaming transmission and implements streaming transmission into point-to-point information sharing for collaborative participants to receive information from others to obtain higher level information and share information to others for integrated information sharing efficiency. | 2010-04-08 |
20100088430 | SYSTEM AND METHOD FOR PROPAGATING PERSONAL IDENTIFICATION INFORMATION TO COMMUNICATION DEVICES - A system and method for propagating identification information among a communication device and a server, through an agent installed on the device. Such process optionally and preferably comprises synchronization between the server and the device, through the agent, such that one or both of the agent and the server may optionally “push” or “pull” information. | 2010-04-08 |
20100088431 | CONFIGURATION SPACE VIRTUALIZATION - Various aspects are disclosed herein for bounding the behavior of a non-privileged virtual machine that interacts with a device by creating a description of the device which indicates to a privileged authority (1) which operations on the device may have system-wide effects and (2) which operations have effects local to the device. The privileged authority may then permit or deny these actions. The privileged authority may also translate these actions into other actions with benign consequences. | 2010-04-08 |
20100088432 | APPARATUS FOR MANAGING HOST BUS ADAPTER - A server is installed with host bus adapters (HBAs). The HBA causes light-emitting components thereon to emit light in abnormal light emission patterns upon falling into an abnormal condition, and in predetermined light emission patterns upon receiving a predetermined command. A method for managing the HBA includes storing abnormal light emission patterns of the HBA, detecting an abnormality as to whether a predetermined HBA is in an abnormal condition, obtaining current light emission patterns of a light-emitting component of an abnormal HBA which is detected to be in the abnormal condition in the detecting, and controlling light emission by sending the predetermined command to all of the HBAs except the abnormal one to cause the light-emitting components thereof to emit light in the predetermined light emission patterns, when the current light emission patterns, obtained in the obtaining, do not match the abnormal light emission patterns stored in the storing. | 2010-04-08 |
20100088433 | Direct memory access (DMA) system - A direct memory access (DMA) system includes a memory unit, a memory control unit electrically connected to the memory unit to control the memory unit for data import or data export, a memory bus is electrically connected to the memory unit, an intermediate control unit electrically connected to the memory bus to receive data of the memory unit through the memory bus, and a plurality of DMA units, each of which includes a DMA controller electrically connected to the intermediate control unit and the memory control unit and a data in/out unit electrically connected to the DMA controller and the intermediate control unit. The DMA controllers control the data in/out units to receive data from the intermediate control unit. The present invention may reduce the load on bandwidth of the memory bus | 2010-04-08 |
20100088434 | FCP COMMAND-DATA MATCHING FOR WRITE OPERATIONS - A method for performing a data exchange between an initiator and a receiver in a fibre channel protocol (FCP) is provided. A control flag is set in a write command to indicate the presence of an identifier. The identifier is copied into a command descriptor block (CDB) of the write command and appended to a data frame. The write command and data frame, including the identifier, is sent from the initiator to the receiver. | 2010-04-08 |
20100088435 | Serial Data Transfer Apparatus - A serial data transfer apparatus includes a transport controller that performs a process of a transport layer, a link controller that performs a process of a link layer, and a physical layer circuit that performs a process of a physical layer. The serial data transfer apparatus transmits and receives data with a destination apparatus via a serial bus. The link controller outputs idle data, which is received from the destination apparatus, to the physical layer circuit, and stops to operate of a unit responsible for generating data to transmit to the destination apparatus while outputting the idle data to the physical layer circuit. This enables to output idle data defined in the standard in an idle period of the serial data transfer apparatus and also reduce the power consumption. | 2010-04-08 |
20100088436 | COMMUNICATION METHOD AND INTERFACE BETWEEN A COMPANION CHIP AND A MICROCONTROLLER - The invention relates to a communication method and interface between a companion chip (CC) and a microcontroller (MC), a communication protocol being transmitted, having a first group of data ( | 2010-04-08 |
20100088437 | INFINIBAND ADAPTIVE CONGESTION CONTROL ADAPTIVE MARKING RATE - A device and a method for optimizing data transfer rate in an InfiniBand fabric is provided where a various number of transmitting devices aim data packets to a single receiving device or through a common link. The method which is implemented in an InfiniBand switch includes marking of packets in a rate corresponding to centrally configured marking rate, determination of the current number of data flows between the input ports and the output port of the switch and marking the data packet with Forward Explicit Congestion Notification according to an adaptive value of marking rate which depends on the initial value of the marking rate and is inversely proportional to the number of data flows. | 2010-04-08 |
20100088438 | APPARATUS AND METHODS FOR TRANSLATION OF DATA FORMATS BETWEEN MULTIPLE INTERFACE TYPES - Apparatus and methods for translation of data formats between multiple interface types. Translation logic is interposed between a producer circuit and a consumer circuit to translate data formats of data signals generated by the producer for application to the consumer. The translation logic may include multiple translators to provide translations between any of multiple producer data formats and any of multiple consumer data formats. One or more producer circuits may thus be selectively coupled with one or more consumer circuits through the translation logic circuit. | 2010-04-08 |
20100088439 | INTELLIGENT CASE FOR HANDHELD COMPUTER - An intelligent case for a handheld computer, the case including a compartment for removably housing the handheld computer; a microcontroller; a first communication device to enable communication between the handheld computer and the microcontroller; one or more recesses for housing one or more data-capture modules; and a second communication device to enable communication between the data-capture modules and the microcontroller; wherein the microcontroller includes: a module manager adapted to handle activation of the data-capture modules, collection of data from the data-capture modules, and communication of the collected data to the hand-held computer; and a first set of applications for controlling, in a first mode, at least some operations of the module manager independently of the handheld computer. | 2010-04-08 |
20100088440 | DETECTING AND PREVENTING THE SPLIT-BRAIN CONDITION IN REDUNDANT PROCESSING UNITS - In an example embodiment the occurrence of the split-brain condition in a High-Availability system, having active and standby processing units, is detected, its cause is diagnosed, and the cause is treated to prevent interruption of service. Diagnosis and treatment procedures are performed at the active processing unit prior to being performed at the standby processing unit. | 2010-04-08 |
20100088441 | MULTI-PROCESSOR CONTROLLER FOR AN INVERTER IN AN ELECTRIC TRACTION SYSTEM FOR A VEHICLE - A multi-processor controller is provided. The multi-processor controller can be used to control the operation of an inverter in a vehicle-based electric traction system. The multi-processor controller includes a master processor device having three serial peripheral interfaces (SPIs), and three slave processor devices coupled to the master processor device via the SPIs. The master processor device issues commands to the slave processor devices to control operation of the inverter. | 2010-04-08 |
20100088442 | Communications entity for communications via a bus-oriented communications network - The invention relates to a communications entity for communications via a bus-oriented communications network with a control device ( | 2010-04-08 |
20100088443 | Data processing apparatus and method for arbitrating access to a shared resource - A data processing apparatus and method are provided for arbitrating access to a shared resource. The data processing apparatus includes a plurality of requester elements sharing access to the shared resource, and arbitration circuitry which is responsive to requests asserted by one or more of the requester elements for access to the shared resource, to perform a priority determination operation to select one of the asserted requests as a winning request. Each of the asserted requests has a priority level associated therewith, and the apparatus further comprises relative priority ordering circuitry for attributing relative priorities to the plurality of requester elements. The arbitration circuitry is responsive to the asserted requests to perform the priority determination operation in order to select as the winning request the request asserted by the requester element with the highest relative priority whose asserted request has a priority level not exceeded by any other asserted request. This provides a very flexible mechanism for performing arbitration, whilst allowing priority levels to be set on a request-by-request basis, thereby facilitating use of the arbitration circuitry with various quality of service mechanisms. | 2010-04-08 |
20100088444 | CENTRAL PROCESSING UNIT MEASUREMENT FACILITY - A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss. | 2010-04-08 |
20100088445 | DATA PROCESSING SYSTEM AND SEMICONDUTOR INTEGRATED CIRCUIT - The present invention provides a data processing system having excellent immediacy of interrupting process. Different interrupt request signals are supplied from a circuit module which can be commonly used by a plurality of central processing units to a plurality of interrupt controllers assigned to central processing units, respectively. In response to the input interrupt request signal, each of the interrupt controllers notifies the corresponding central processing unit of an interrupt. The circuit module selects an interrupt controller for supplying an interrupt request signal from the plural interrupt controllers. For example, the circuit module identifies a central processing unit which instructed a start request and supplies an interrupt request signal to an interrupt controller corresponding to the central processing unit. The burden of the interrupting process of the single central processing unit can be lessened. In addition, since the interrupting process in the single central processing unit is not necessary, interruption response of another central processing unit is increased. | 2010-04-08 |
20100088446 | PRIORITIZING INTERRUPT CONTROLLER - A system comprises processing logic. The system also comprises a first interrupt controller coupled to the processing logic and configured to manage interrupts provided to the processing logic. The system further comprises a second interrupt controller coupled to the first interrupt controller. The second interrupt controller is programmable to distribute received interrupts to the first interrupt controller via different output ports. | 2010-04-08 |
20100088447 | SECURE MMC STANDARD SMARTCARD WITH MULTI-APPLICATION OPERATION CAPABILITY, PROCESS OF OPERATION - The invention relates to smartcard under SecureMMC standard, the card being connected to a host through a MMC bus and being compliant to ISO/IEC7816 standard. According to the invention, the card is multi-application operation capable and a determined number N of commands can be processed in the card in parallel, being the number of logical channels the card can support, the card has means for using a command or a response which is encapsulated in an information field of a bloc frame, said bloc frame also having at least a prologue field for at least identifying the source node application and the destination node application in a NAD datum, and the card has means for as long as the number p of active commands in the card is lower than N and none is completed, the card is in Secure_Idle state. | 2010-04-08 |
20100088448 | VIRTUAL COMPUTING ACCELERATOR AND PROGRAM DOWNLOADING METHOD FOR SERVER-BASED VIRTUAL COMPUTING - Provided are a virtual computing accelerator and program downloading method for server-based virtual computing. The virtual computing accelerator divides a program allocated to a virtual memory into groups, such as pages or segments, and downloads the groups of program data in sequence. Here, the groups of program data are downloaded after download sequence is estimated on the basis of statistical data accumulated in a hash table, or only a part that must be first downloaded is downloaded in advance. Thus, a program-execution wait time of a client can be reduced. In addition, only a part of a possibly required program is transferred in advance, and the client can execute the application program using only a small amount of virtual memory. | 2010-04-08 |
20100088449 | DETECTING SYSTEM FOR DETECTING INSERTION OF EXPANSION CARD - A detecting system includes a slot, a controller and a power source terminal. The slot includes a first detecting pin and a second detecting pin. The first detecting pin is electrically connected to a detecting voltage terminal. The second detecting pin is connected to ground. The controller is electrically connected to the first detecting pin. The controller receives a high level voltage signal from the first detecting pin when an expansion card is not detected. The power source terminal is connected to the slot under control of the controller. On the condition that the first detecting pin is electrically connected to the second detecting pin. The controller receives a low level voltage signal from the first detecting pin. The controller is then triggered to connect the power source terminal to the slot to supply power to the expansion card. | 2010-04-08 |
20100088450 | COMPONENT RETENTION MECHANISM - A component retention mechanism facilitates improved installation, retention and removal of hardware components (e.g., PCI cards) on a personal computer. The retention mechanism includes a locking component, support member, and release mechanism coupled to each other. The locking component can be a steel bar or other stiff item positioned proximate to multiple socket connectors on a circuit board. The locking component moves between unlocked and locked positions that mechanically and simultaneously unlock or lock in place multiple add-in cards inserted into the socket connectors. The support member moves and thereby facilitates movement of the locking component between locked and unlocked positions. The release mechanism facilitates movement of the support member and is actuated when a force is exerted by a user thereto. An associated slider housing coupled to the release mechanism and support member includes a fan, support shelves and a door that provides additional support to oversized PCI cards. | 2010-04-08 |
20100088451 | ARCHITECTURE VERIFYING APPARATUS, ARCHITECTURE VERIFYING METHOD, AND MEDIUM STORING ARCHITECTURE VERIFYING PROGRAM - An architecture verifying apparatus includes an inputting unit receiving limitation information, a bus monitor monitoring a bus transaction to obtain bus transaction information, a module monitor monitoring a reception transaction, processing, and a transmission transaction to obtain reception transaction information, processing information, and transmission transaction information, an architecture information generator associating the limitation information and the bus transaction information with the reception transaction information, the processing information, and the transmission transaction information to generate architecture information, and an outputting unit supplying the architecture information. | 2010-04-08 |
20100088452 | Internal BUS Bridge Architecture and Method in Multi-Processor Systems - An internal bus bridge architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus root via a host bus bridge that is internal to at least one bus endpoint. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols. | 2010-04-08 |
20100088453 | Multi-Processor Architecture and Method - Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols. | 2010-04-08 |
20100088454 | Bridging device with power-saving function - A bridging device with power-saving function includes first and second interfaces, first and second physical layer processing devices, and a controller. The first interface is utilized for coupling a first external device complying with the first interface. The first external device receives a device request signal, and accordingly sends back a device response signal through the first physical layer processing device. The second interface is utilized for coupling a second external device complying with the second interface. The controller is coupled between the first and the second physical layer processing device for transmitting the device request signal with the predetermined frequency to the first physical layer processing device in order to receive the device response signal. When the controller does not receive the device response signal, the controller turns the second physical layer processing device off. | 2010-04-08 |
20100088455 | Storage system provided with a plurality of storage modules - For a storage system provided with a plurality of storage modules including a first storage module and a second storage module, the first storage module is provided with a first switch circuit including a plurality of ports and a first circuit connected to any of the plurality of ports included in the first switch circuit via an internal path, and the second storage module is provided with a second circuit. A direct path that is a path for connecting the first switch circuit and the second circuit is connected to any of the plurality of ports included in the first switch circuit. The first circuit issues a packet addressed to the second circuit. The first switch circuit receives the packet addressed from the first circuit to the second circuit, and outputs the packet from a port connected to the direct path to the second circuit. | 2010-04-08 |
20100088456 | STORAGE-SHARING BUS SWITCH - The present invention discloses a storage-sharing bus switch, which comprises a bus exchange device, a controller and a plurality of non-transparent bridge devices. The bus used in the present invention is PCI or a like system bus. The bus exchange device connects with the controller and a plurality of storage devices and links to hosts via the non-transparent bridge devices. The storage-sharing bus switch executes data transmission between hosts and storage devices. The controller starts up and monitors the devices linking to the storage-sharing bus switch. The non-transparent bridge devices implement data transmission between hosts and the storage-sharing bus switch and separate the hosts from the devices linking to the storage-sharing bus switch lest operation errors damage the devices. The present invention enables a plurality of hosts to share data storage simultaneously. | 2010-04-08 |
20100088457 | CACHE MEMORY ARCHITECTURE HAVING REDUCED TAG MEMORY SIZE AND METHOD OF OPERATION THEREOF - A cache memory architecture, a method of operating a cache memory and a memory controller. In one embodiment, the cache memory architecture includes: (1) a segment memory configured to contain at least one most significant bit (MSB) of a main memory address, the at least one MSB being common to addresses in a particular main memory logical segment that includes the main memory address, (2) a tag memory configured to contain tags that include other bits of the main memory address and (3) combinatorial logic associated with the segment memory and the tag memory and configured to indicate a cache hit only when both the at least one most significant bit and the other bits match a requested main memory address. | 2010-04-08 |
20100088458 | OPERATION METHOD OF MEMORY - An operation method of a memory includes the steps of calculating an offset of sequential write commands and the beginning of pages of a block of a non-volatile memory; shifting the block by the offset; and directly writing data from a host to the pages except the first and last pages of the block by the sequential write commands. In an embodiment, the pages are logical pages providing optimal writing efficiency and are determined before calculating the offset. The step of shifting the block by the offset is to increase corresponding logical block addresses (LBA) in the pages by the offset. | 2010-04-08 |
20100088459 | Improved Hybrid Drive - A non-volatile storage system comprises a hard disk drive (HDD) having a first capacity for storing information therein in a plurality of blocks. The storage system also comprises a non-volatile solid state memory (SSD) having a second capacity, less than the first capacity, for storing information therein. Finally, the storage system comprises a controller having a volatile memory and for controlling the read operation of the HDD and the read/write operation of the SSD. The controller stores in the volatile memory the address of read blocks from the HDD in a first period of time and determines a plurality of the most frequently read blocks in the first period of time, The controller then causes the SSD to store information from the most frequently read blocks from the HDD, and thereafter causes information to be read from the SSD when the storage system is requested to access information from the most frequently read blocks. The controller resets the identity of the most frequently read blocks in the volatile memory after a second period of time, where the second period of time is longer than said first period of time. | 2010-04-08 |
20100088460 | MEMORY APPARATUS, SYSTEMS, AND METHODS - Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed. | 2010-04-08 |
20100088461 | SOLID STATE STORAGE SYSTEM USING GLOBAL WEAR LEVELING AND METHOD OF CONTROLLING THE SOLID STATE STORAGE SYSTEM - A solid state storage system is disclosed including a memory area having a plurality of chips. The solid state storage system includes a micro controller unit (MCU) configured to utilize the number of deletions for logical blocks corresponding to logical block addresses when performing wear leveling on the memory area. The allocation of the logical block addresses can be performed using an interleaving process and a multi-plane method. The solid state storage system performs global wear leveling by which the lifespan of the cells of the chips can be uniformly managed. | 2010-04-08 |
20100088462 | METHODS FOR HANDLING DATA UPDATING OF FLASH MEMORY AND RELATED MEMORY CARDS - A method for handling data updating of a flash memory is disclosed, in which the flash memory comprises a mother block with a plurality of pages to be updated, and each page comprises a plurality of sectors. In such method, a first data for updating a target page in the mother block is obtained, and then whether the first data comprises data for updating an ending sector in the target page is determined. The first data is written into a replacing page in a first FAT block when the first data does not comprise data for updating the ending sector in the target page. The first data is written into a corresponding page in a second FAT block when the first data comprises the data for updating the ending sector, in which the corresponding page in the second FAT block and the target page in the mother block have the same page indexes. | 2010-04-08 |
20100088463 | NONVOLATILE MEMORY SYSTEM AND DATA PROCESSING METHOD - A solid-state disk device exchanging data with a host includes a nonvolatile memory device, a buffer memory configured to temporarily store data exchanged between the host and the nonvolatile memory, and a buffer manager configured to control transfer of data to/from the buffer memory, wherein the transfer of data between the nonvolatile memory device and the host during a streaming mode of operation begins immediately when a defined unit data is input to the buffer memory. | 2010-04-08 |
20100088464 | Compression Based Wear Leveling for Non-Volatile Memory - The present disclosure includes systems and techniques relating to non-volatile memory. Systems and techniques can include obtaining information to store in a non-volatile memory, the information including a data segment, compressing data within the data segment, including pad data in one or more portions of the data segment based on a compression result attained by the compression, and writing data of the data segment. | 2010-04-08 |
20100088465 | CONTROL DEVICE OF A STORAGE SYSTEM COMPRISING STORAGE DEVICES OF A PLURALITY OF TYPES - A control device of a storage system including a CPU which receives input information including at least a size and an archive deadline of data which is stored in storage devices; wherein data management information includes a write threshold value regarding one type of storage devices, the write threshold value indicating a write limit number to the one type of storage devices, wherein the CPU: selects a storage device which stores data corresponding to the information which is input to an input device, based on the information which is input to the input device and the data management information which is stored in the memory; CPU stores to the selected storage device, the data corresponding to the information which is input to the input device; and, registers to the data management information in the memory, at least one of the information which is input to the input device. | 2010-04-08 |
20100088466 | STORAGE DEVICE, STORAGE CONTROL DEVICE, AND CONTROL METHOD - According to one embodiment, a storage device includes an actuator to move a head to a position on a disk medium; a module to record or reproduce data to or from the disk medium using the head; a memory controller to write or read to or from a non-volatile memory; a buffer controller to write or read to or from a buffer memory; an interface controller to transmit and receive to or from an upper device; a switching module to switch data transfer paths among the module, the memory controller, and the interface controller; and an access controller to control the switching module to transfer data read from the non-volatile memory to the upper device concurrently with transferring and storing the read data in a cache region of the buffer memory, upon receiving from the upper device a command to read the data from the non-volatile memory. | 2010-04-08 |
20100088467 | MEMORY DEVICE AND OPERATING METHOD OF MEMORY DEVICE - A memory device may include a non-volatile memory and non-volatile RAM. The non-volatile memory may include a data block and a metadata block. Metadata information with respect to the data block may be included in the metadata block. A portion of metadata with respect to the data block or the metadata with respect to the metadata block may be stored in the non-volatile RAM. | 2010-04-08 |
20100088468 | METHOD FOR OPTIMIZING CLEANING OF MAPS IN FLASHCOPY CASCADES CONTAINING INCREMENTAL MAPS - A method implemented in a computer infrastructure having computer executable code having programming instructions tangibly embodied on a computer readable storage medium. The programming instructions are operable to determine whether a target disk of a map contains data unavailable to a downstream disk from an upstream disk in a FlashCopy cascade and detect whether the downstream disk has a copy of the data. Additionally, the programming instructions are operable to copy the data from the target disk to the downstream disk, if the target disk of the map contains data unavailable to the downstream disk from the upstream disk and the downstream disk does not have the copy of the data. Furthermore, the programming instructions are operable to refrain from copying the data from the target disk to the downstream disk, if the target disk of the map does not contain data unavailable to the downstream disk from the upstream disk or the downstream disk does have the copy of the data. Moreover, the programming instructions are operable to remove the map from the FlashCopy cascade. | 2010-04-08 |
20100088469 | Storage system - Disclosed is a storage system that suppress occurrence of a bottleneck in the storage system, efficiently uses a bandwidth of hardware, and achieves high reliability. A storage system includes a storage | 2010-04-08 |
20100088470 | OPTIMIZING INFORMATION LIFECYCLE MANAGEMENT FOR FIXED STORAGE - The method may query the disk drive for a size where size may be a total number of logical blocks on the disk drive. The drive may receive a size response where the size includes a total number of logical blocks on the disk drive. The number of usage blocks necessary to represent the number of logical blocks on the disk drive may then be determined and usage data may be stored in the usage blocks. The data may be stored in the buffer of the disk drive. The data may also be stored in the DDF of a RAID drive. The data may be used to permit incremental backups of disk drives by backing up only the blocks that are indicated as having been changed. In addition, information about the access to the drive may be collected and stored for later analysis. | 2010-04-08 |
20100088471 | FIELD DEVICE - Disclosed is a field device comprising: a storage section to store shared data which is shared between user modules; an interface section to obtain trigger information to access the shared data, and to output access information which includes an access content of the shared data and an access request of the shared data, based on the obtained trigger information; and a control section to access the shared data which is stored in the storage section, based on the access information which has been output by the interface section. | 2010-04-08 |
20100088472 | DATA PROCESSING SYSTEM AND CACHE CONTROL METHOD - A data processing system is provided. The data processing system includes a plurality of processors, a cache memory shared by the plurality of processors, in which memory a cache line is divided into a plurality of partial writable regions. The plurality of processors are given exclusive access rights to the partial writable region waits. | 2010-04-08 |
20100088473 | VECTOR COMPUTER SYSTEM WITH CACHE MEMORY AND OPERATION METHOD THEREOF - A vector computer system includes a vector processor configured to issue a vector store instruction which includes a plurality of store requests; a cache memory of a write back system provided between the vector processor and a main memory; and a write allocate determining section configured to generate an allocation control signal which specifies whether the cache memory operates based on a write allocate system or a non-write allocate system. When the vector processor issues the vector store instruction, the write allocate determining section generates the allocation control signal to each of the plurality of store requests based on a write pattern as a pattern of target addresses of the plurality of store requests. The cache memory executes each store request based on one of the write allocate system and the non-write allocate system which is specified based on the allocation control signal. | 2010-04-08 |
20100088474 | SYSTEM AND METHOD FOR MAINTAINING MEMORY PAGE SHARING IN A VIRTUAL ENVIRONMENT - In a virtualized system using memory page sharing, a method is provided for maintaining sharing when Guest code attempts to write to the shared memory. In one embodiment, virtualization logic uses a pattern matcher to recognize and intercept page zeroing code in the Guest OS. When the page zeroing code is about to run against a page that is already zeroed, i.e., contains all zeros, and is being shared, the memory writes in the page zeroing code have no effect. The virtualization logic skips over the writes, providing an appearance that the Guest OS page zeroing code has run to completion but without performing any of the writes that would have caused a loss of page sharing. The pattern matcher can be part of a binary translator that inspects code before it executes. | 2010-04-08 |
20100088475 | DATA PROCESSING WITH A PLURALITY OF MEMORY BANKS - A data processing circuit comprises an instruction execution circuit ( | 2010-04-08 |
20100088476 | METHOD FOR ALLOWING EXCLUSIVE ACCESS TO SHARED DATA - A method of allowing exclusive access to shared data by a computing device and a computer readable article embodying instructions for executing the method. The method includes: reading from a storage unit into a memory a program including a code for execution in a critical section and an instruction to write a value into or read a value from a shared data area in the memory; acquiring a lock on the critical section before start of a first instruction in the critical section; writing a value into a thread-local area in the memory in response to an instruction to write the value into the shared data area; writing into the shared data area the value written into the thread-local area upon completion of a final instruction in the critical section; and releasing the lock on the critical section, thereby allowing exclusive access to shared data. | 2010-04-08 |
20100088477 | MEMORY SHARE SYSTEM AND MEMORY SHARE APPARATUS - Constructing to include a memory section and a share management section that divides a storage area of a storage apparatus attached to the memory section and allocates the divided areas to each plurality of information processing apparatus, thereby enabling sharing of the storage apparatus by the plurality of information processing apparatuses, carries out a memory access to the storage area on the basis of a memory access request signal from the each information processing apparatus, and generates a response signal from the memory section, thereby allowing the storage apparatus to function as an internal storage apparatus of the information processing apparatus, enables easy modification of the memory size used in an information processing apparatus by sharing memory which is provided external to the information processing apparatus among a plurality of information processing apparatuses, thereby facilitating effective use of the memory. | 2010-04-08 |
20100088478 | System for Internally Monitoring an Integrated Circuit - A system for internally monitoring an integrated circuit, wherein the contents of memory locations in the integrated circuit can be displayed on a dedicated display unit via a graphical interface device provided in the integrated circuit. The system provides a built-in means for observing the internal state of both firmware and hardware (as applicable) on the integrated circuit device. This facilitates the development of, and ongoing health monitoring of, the device in any system into which it may be incorporated. The provision of a graphical interface device provides a relatively high bandwidth for the outgoing data and so allows the internal state of the device to be monitored in real time. | 2010-04-08 |
20100088479 | MEMORY ACCESS CONTROLLER - A memory access controller is disclosed. A packet memory stores a packet and has a clock parallel outputting function of parallel-outputting first data and a clock. A read controller reads the first data. A clock transfer unit performs a clock transfer operation by writing the first data using the clock and reading second data using a system clock. A packet assembly unit receives the second data and reassembles the packet. An information memory stores a read start address where head data of the packet is stored and packet length information indicating a length of the packet. A read controller receives the read start address and the packet length information, generates a read address necessary for reading one packet, and reads the first data from the packet memory. | 2010-04-08 |
20100088480 | SYSTEM AND METHOD FOR STORING DATA IN A MOBILE DEVICE - A method for storing data in a mobile device includes initializing a memory of the mobile device when the mobile device is powered on, allocating a free block of memory from the memory, saving received new data in the free block, and allocating a new free block again from the memory for saving received new data next time. The method further includes prompting for sufficient memory space to be manually freed from the memory if the new free block allocation is a failure, and re-prompting for sufficient memory space to be manually freed from the memory until a preset prompt time has been prompted if sufficient memory space has not been manually freed, or allocating a new free block of memory from the memory if sufficient memory space has been manually freed. | 2010-04-08 |
20100088481 | WRITE CAPTURE FOR FIBRE CHANNEL FABRIC SNAPSHOT SERVICE - The snapshot capability moving into the SAN fabric and being provided as a snapshot service. A well-known address is utilized to receive snapshot commands. Each switch in the fabric connected to a host contains a front end or service interface to receive the snapshot command. Each switch of the fabric connected to a storage device used in the snapshot process contains a write interceptor module which cooperates with hardware in the switch to capture any write operations which would occur to the snapshot data area. The write interceptor then holds these particular write operations until the original blocks are transferred to a snapshot or separate area so that the original read data is maintained. Should a read operation occur to the snapshot device and the original data from requested location has been relocated, a snapshot server captures these commands and redirects the read operation to occur from the snapshot area. If, however, the read operation is directed to the original drive, the read is provided from the original data areas, even if the data had been replaced. The snapshot server determines the existence of particular snapshot devices, allocates their storage locations, provides this information to both the service interfaces and the write interceptors and handles read and write operations to the snapshot device. | 2010-04-08 |
20100088482 | Process and Method for Erase Strategy in Solid State Disks - An embodiment of the invention relates to a nonvolatile mass storage device such as a flash memory device formed with erase blocks partitioned into memory management blocks. An erase block is identified containing at least a minimum number of management blocks marked invalid, from which data is copied, merged, and stored in a new management block. The erase block is then erased. Erase blocks containing at least the minimum number of invalid management blocks may be erased until a minimum amount of management blocks is free. Alternatively, all erase blocks containing at least the minimum number of invalid management blocks may be erased. A management table listing the number of invalid management blocks in erase blocks may be included in the mass storage device. Preferably, the new management block for storage of the merged data is located in an erase block different from the identified erase block. | 2010-04-08 |
20100088483 | DETECTION CIRCUIT FOR MIXED ASYNCHRONOUS AND SYNCHRONOUS MEMORY OPERATION - A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation. | 2010-04-08 |
20100088484 | SYNCHRONOUS FLASH MEMORY WITH STATUS BURST OUTPUT - A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The memory can output data from storage registers on the data communication connections during a series of clock cycles to provide a burst of register data. The memory can also provide the register data in accordance to a defined clock latency value. The register data can include status data, operating setting data, manufacture identification, and memory device identification. | 2010-04-08 |
20100088485 | FAILURE MANAGEMENT METHOD IN THIN PROVISIONING TECHNOLOGY FOR STORAGE - A pool is replicated in the unit of volume providing the pool, and when a physical device is blocked, any volume blocked in the pool is changed to the replicated volume so that the pool and a virtual volume can be recovered. With such a configuration, when any pool or virtual volume is blocked due to blockage of any volume providing the thin provisioning function, volume recovery can be swiftly performed without changing the virtual volume used by a host computer, and consumption of storage resources needed therefor can be suppressed. | 2010-04-08 |
20100088486 | CREATING A SELF-CONTAINED PORTABLE OUTPUT FILE - Various embodiments provide for creating a self-contained portable output file that includes a de-duplicated version of data. According to one embodiment, data, which includes a selected group of files, is partitioned into subblocks. A de-duplicated version of the data is created by eliminating a second subblock from the data and using a first subblock to represent the second subblock, if the second subblock is a duplicate of the first subblock. A self-contained portable output file, which includes the de-duplicated version of the data, is created. | 2010-04-08 |
20100088487 | MEMORY MODULE AND AUXILIARY MODULE FOR MEMORY - In a memory module | 2010-04-08 |
20100088488 | QUANTUM GATE METHOD AND APPARATUS - A method includes causing a common-resonator mode resonating with a transition between |2> | 2010-04-08 |
20100088489 | DATA TRANSFER NETWORK AND CONTROL APPARATUS FOR A SYSTEM WITH AN ARRAY OF PROCESSING ELEMENTS EACH EITHER SELF-OR COMMON CONTROLLED - A processor of SIMD/MIMD dual mode architecture comprises common controlled first processing elements, self-controlled second processing elements and a pipelined (ring) network connecting the first PEs and the second PEs sequentially. An access controller has access control lines, each access control line being connected to each PE of the first and second PEs to control data access timing between each PE and the network. Each PE can be self-controlled or common controlled, such as dual mode SIMD/MIMD architectures, reducing the wiring area requirement. | 2010-04-08 |
20100088490 | METHODS AND SYSTEMS FOR MANAGING COMPUTATIONS ON A HYBRID COMPUTING PLATFORM INCLUDING A PARALLEL ACCELERATOR - In accordance with exemplary implementations, application computation operations and communications between operations on a host processing platform may be adapted to conform to the memory capacity of a parallel accelerator. Computation operations may be split and scheduled such that the computation operations fit within the memory capacity of the accelerator. Further, the operations may be automatically adapted without any modification to the code of an application. In addition, data transfers between a host processing platform and the parallel accelerator may be minimized in accordance with exemplary aspects of the present principles to improve processing performance. | 2010-04-08 |
20100088491 | PROCESSING UNIT - A processing unit includes a plurality of thread execution units each provided with a performance analysis circuit for measuring various types of events resulting from execution of instructions and a commit stack entry unit for controlling the completion of executed instructions and each executing a thread having a plurality of instructions, a commit scope register for storing instructions of completion candidates stored in each commit stack entry unit by execution by each thread execution unit and performing processing for completion of instructions included in the thread, and a thread selecting means for sending commit events of the instructions to a performance analysis circuit provided in each thread execution unit corresponding to the instructions when performing commit processing for instructions stored in the commit scope register. | 2010-04-08 |
20100088492 | SYSTEMS AND METHODS FOR IMPLEMENTING BEST-EFFORT PARALLEL COMPUTING FRAMEWORKS - Implementations of the present principles include Best-effort computing systems and methods. In accordance with various exemplary aspects of the present principles, a application computation requests directed to a processing platform may be intercepted and classified as either guaranteed computations or best-effort computations. Best-effort computations may be dropped to improve processing performance while minimally affecting the end result of application computations. In addition, interdependencies between best-effort computations may be relaxed to improve parallelism and processing speed while maintaining accuracy of computation results. | 2010-04-08 |
20100088493 | IMAGE PROCESSING DEVICE AND DATA PROCESSOR - A restriction is given to the calculation function for image processing achieved by the hard-wired system and the memory access control of a buffer memory, and a range of the restriction is made variable by a program control and others. Data is inputted to the buffer memory from the outside with a restriction of “in units of memory line”, and the number of memory lines and positions of the same to which data is inputted can be programmable by the control circuit. The arithmetic circuit is subjected to the restriction of performing the calculation in units of data of one or plural memory lines supplied from the buffer memory, and a calculation processing content in units of calculation processing for the units of data can be programmably assigned by the control circuit. | 2010-04-08 |
20100088494 | Total cost based checkpoint selection - A method, system, and computer usable program product for total cost based checkpoint selection are provided in the illustrative embodiments. A cost associated with taking a checkpoint is determined. The cost includes an energy cost. An interval between checkpoints is computed so as to minimize the cost. An instruction is sent to schedule the checkpoints at the computed interval. The energy cost may further include a cost of energy consumed in collecting and saving data at a checkpoint, a cost of energy consumed in re-computing a computation lost due to a failure after taking the checkpoint, or a combination thereof. The cost may further include, converted to a cost equivalent, administration time consumed in recovering from a checkpoint, computing resources expended in taking a checkpoint, computing resources expended after a failure in restoring information from a checkpoint, performance degradation of an application while taking a checkpoint, or a combination thereof. | 2010-04-08 |
20100088495 | MODE-SPECIFIC CONTAINER RUNTIME ATTACHMENT - The operation of a multi-mode application. The multi-mode application has a number of mode-specific logical containers of components. Each mode-specific container contains components that assist the multi-mode application in operating in a corresponding mode. If the application transitions to another mode, the component(s) of the other corresponding mode-specific logical container is used to assist in operating in the other mode. The logical containers may be activated and deactivated during execution time as the application transitions from mode to mode. | 2010-04-08 |
20100088496 | METHOD AND SYSTEM FOR EXECUTING AN EXECUTABLE FILE - A method for executing an executable file. The method includes executing instructions in the executable file by a first process, receiving a write request from a second process to write to the executable file, generating an anonymous file from the executable file in response to the write request, executing the anonymous file by the first process, and accessing the executable file by the second process. | 2010-04-08 |
20100088497 | SOFTWARE UPDATING OF A SERVER SUPPORTING ELECTRONIC GAMING MACHINES - An illustrative method imports configuration data used by a server that supports electronic gaming machines (EGMs). Configuration data is used by operational software of the server that supports EGMs in a server-client relationship and is stored in accord with a first data structure template that defines records having fields that contain information of the configuration of each EGM. Configuration data stored in fields of records in accord with the first data structure template is automatically transferred to corresponding fields of records in accord with a second data structure template used by new operational software of the server by migration software. | 2010-04-08 |
20100088498 | SYSTEM AND METHOD FOR MANAGING HARDWARE CONFIGURATION PARAMETERS - A system and method manages configuration data within a hardware component of a device to support hardware component changes during development or manufacture of the device. A Standardized Virtual Part (SVP) file is formed as a binary file and includes a SVP header that comprises metadata of one of at least schema version, revision numbers, part numbers, creator and description. The SVP file also includes hardware configuration data and a SVP trailer that includes error checking data for data authentication. The SVP file is loaded onto the device during development or manufacture for configuring the hardware component. | 2010-04-08 |
20100088499 | SEAMLESS DATA MIGRATION - Provided are techniques for migrating data. Contents are sealed to one or more registers. In response to determining that secure backup is enabled, platform metrics are stored in a private store. An out-of-band request is received. A response to the out-of-band request is provided using the stored platform metrics. | 2010-04-08 |
20100088500 | MULTIPLE GUEST O.S. BOOT FOR SERVER COMPONENT SETUP - A hypervisor boots all guest operating systems needed to setup/update server components as detected by an update utility. The update utility, after detecting server components, is booted into each guest O.S. so that the components are updated in parallel without having to sequentially boot the utility into a guest O.S., update its component, then shut down and re-boot into another guest O.S. | 2010-04-08 |
20100088501 | Post speedup in oprom systems with intervention support - Techniques related to personal computers and devices sharing similar architectures are disclosed. Particularly shown is a system and method for enabling improved computer initialization speed achieved by methods including causing apparently premature timeouts when fruitlessly waiting for human intervention. | 2010-04-08 |
20100088502 | Method for Storing Boot Time - A method for storing boot time is performed by a computer product having a programmable read-only memory with a basic/input output system resident therein. The method includes the steps of:
| 2010-04-08 |
20100088503 | Microcontroller - A microcontroller including: a first voltage detection circuit that generates a first detection signal when a power supply voltage decreases to a voltage lower than a first voltage value; a second voltage detection circuit that generates a second detection signal when the power supply voltage decreases to a voltage lower than a second voltage value that is smaller than the first voltage value; a CPU that has a function of switching between a normal operation mode and a standby mode, performs an interrupt processing operation to shift from the normal operation mode to the standby mode when the first detection signal is generated, and shifts to the standby mode independently of the interrupt processing operation when the second detection signal is generated; and a first memory circuit that stores information indicating that the CPU has shifted to the standby mode before completing the interrupt processing operation. | 2010-04-08 |
20100088504 | System and Method for Implementing an Enhanced Transport Layer Security Protocol - A system and method for implementing an enhanced transport layer security (ETLS) protocol is provided. The system includes a primary server, an ETLS servlet and an ETLS software module. The primary server operates on a computer network and is configured to communicate over the computer network using a non-proprietary security protocol. The ETLS servlet also operates on the computer network and is securely coupled to the primary server. The ETLS servlet is configured to communicate over the computer network using an ETLS security protocol. The ETLS software module operates on a mobile device, and is configured to communicate over the computer network using either the non-proprietary security protocol or the ETLS security protocol. Operationally, the ETLS software module initially contacts the server over the computer network using the non-proprietary security protocol, and subsequently contacts the server through the ETLS servlet using the ETLS security protocol. | 2010-04-08 |
20100088505 | CONTENT DELIVERY NETWORK ENCRYPTION - A system and method for delivering content to end users encrypted within a content delivery network (CDN) for content originators is disclosed. CDNs transport content for content originators to end user systems in a largely opaque manner. Caches and origin servers in the CDN are used to store content. Some or all of the content is encrypted within the CDN. When universal resource indicators (URIs) are received from an end user system, the CDN can determine the key used to decrypt the content object within the CDN before delivery. Where there is a cache miss, an origin server can be queried for the content object, which is encrypted in the CDN. | 2010-04-08 |
20100088506 | METHOD AND SYSTEM FOR PROVIDING A REL TOKEN - The embodiments relate to a method for providing at least one REL (Rights Expression Language) token, the REL-token or tokens being provided in a message by a MIME (Multipurpose Internet Mail Extension) protocol. | 2010-04-08 |
20100088507 | SYSTEM AND METHOD FOR ISSUING DIGITAL CERTIFICATE USING ENCRYPTED IMAGE - The present invention relates to a system and method for issuing a digital certificate using an encrypted image, in which a digital certificate is sealed in a digital envelope image so as to protect a digital certificate user from damages caused by hacking, phishing attacks and the like in the course of issuance, update and re-issuance of the digital certificate, and the method for issuing a digital certificate comprises the steps of: storing a user select image for issuing the digital certificate, by a proxy server or a certificate server; and requesting the certificate server to issue the digital certificate and, if the digital certificate is issued, creating a sealed digital envelope image by combining the digital certificate with the user select image and transmitting the digital envelope image to a user terminal. | 2010-04-08 |
20100088508 | METHOD FOR PROTECTING CONTENT - Disclosed are a method of protecting content and a method of processing information. The method of protecting content can include service related information including revocation application information of content from the outside by employing a content management and protection system, and apply or not apply a content revocation process on the content according to the re- vocation application information. Accordingly, whether to apply a content revocation process can be controlled according to revocation application information. | 2010-04-08 |
20100088509 | SYSTEM AND METHOD FOR SEQUENTIALLY PROCESSING A BIOMETRIC SAMPLE - This invention provides for progressive processing of biometric samples to facilitate verification of an authorized user. The initial processing is performed by a security token. Due to storage space and processing power limitations, excessive false rejections may occur. To overcome this shortfall, the biometric sample is routed to a stateless server, which has significantly greater processing power and data enhancement capabilities. The stateless server receives, processes and returns the biometric sample to the security token for another attempt at verification using the enhanced biometric sample. In a second embodiment of the invention, a second failure of the security token to verify the enhanced biometric sample sends either the enhanced or raw biometric sample to a stateful server. The stateful server again processes the biometric sample and performs a one to many search of a biometric database. The biometric database contains the master set of enrolled biometric templates associated with all authorized users. Signals generated by the stateful server are used by the security token to allow or deny access to a resource or function. In both embodiments of the invention, the heuristics remain with the security token. | 2010-04-08 |
20100088510 | APPARATUS AND METHOD FOR DATA PACKET SECURITY IN A WIRELESS SENSOR NETWORK - An apparatus and method for providing data packet security in a wireless sensor network including a plurality of sensor nodes. The apparatus includes a memory unit for storing a plurality of node characteristic information and a plurality of settable security status information, each of the node characteristic information corresponding to at least one of the settable security status information; and a control unit for examining the node characteristic information of the control unit, if a data packet generation request is made, detecting the security status information corresponding to the examined node characteristic information from the memory unit, and generating data packets including the detected security status information. | 2010-04-08 |
20100088511 | INFORMATION TRANSMISSION SECURITY METHOD - A method for securing the transmission of information in a communication network comprising a plurality of nodes, characterized in that it includes the steps of: an information transmitting node encodes the information with a given code; an error of given weight is added to the encrypted information; the encrypted information and the error are divided into a number of portions that is substantially equal to a chosen number r of possible routes for transmitting the information in the network; the destination address is encrypted; and for each portion, a control information item is associated, making it possible to reconstruct the message at the destination and the encrypted address of the destination node. For the various sets, each including a portion of encrypted information, a control information item and the encrypted address of the recipient node are sent in parallel over the r chosen routes. | 2010-04-08 |
20100088512 | Method and Apparatus for Automatically Publishing Content Based Identifiers - A method and apparatus for automatically publishing content based identifiers are described. In one embodiment, the method comprises accessing an electronic communication to obtain a content based identifier (CBI) contained in the electronic communication. In one embodiment, the method may also comprise using the CBI to validate integrity of a hash chained log. | 2010-04-08 |
20100088513 | NETWORK SECURITY METHOD - This invention provides a method for allowing the recipient of a message | 2010-04-08 |
20100088514 | Method and device for authorising access to data - The present invention is related to a device for authorising access to data content protected by a control signal (CW) and delivered to a terminal over a network comprising an access network. The device is arranged for receiving a version of the control signal and further comprises processing means for processing the received version of the control signal and arranged for sending to the terminal an output signal derived from that processed version of the control signal. Said output signal enables the terminal to get access to the delivered data content protected by the control signal. The device is characterised in that it is operable in the access network. | 2010-04-08 |
20100088515 | SCRAMBLE KEY MANAGEMENT UNIT, SCRAMBLE KEY MANAGEMENT INFORMATION TRANSMITTING UNIT, METHOD FOR SCRAMBLE KEY OUTPUT MANAGEMENT, SCRAMBLE KEY MANAGEMENT PROGRAM, LICENSE INFORMATION MANAGEMENT UNIT, LICENSE MANAGEMENT INFORMATION TRANSMITTING UNIT, METHOD FOR LICENSE INFORMATION OUTPUT MANAGEMENT, AND LICENSE INFORMATION MANAGEMENT PROGRAM - A low cost scramble key management apparatus which enables to manage a scramble key based on individual contract information and to ensure security in narrow band broadcasting. The scramble key management apparatus | 2010-04-08 |
20100088516 | Systems and Methods For Providing Security to Different Functions - Methods and systems are provided that use smartcards, such as subscriber identity module (SIM) cards to provide secure functions for a mobile client. One embodiment of the invention provides a mobile communication network system that includes a mobile network, a mobile terminal, a server coupled to the mobile terminal via the mobile network, and a subscriber identity module (SIM) card coupled to the mobile terminal. The SIM card includes a first key and a second key. The first key is used to authenticate an intended user of the mobile terminal to the mobile network. Upon successful authentication of the intended user to the mobile network, the mobile terminal downloads a function offered from the server through the mobile network. The second key is then used by the mobile terminal to authenticate the intended user to the downloaded function so that the intended user can utilize the function. | 2010-04-08 |
20100088517 | Method and Apparatus for Logging Based Identification - A method and apparatus for logging based identification are described. In one embodiment, the method comprises extracting entries of a hash chained log that represents a series of previous transactions. The method may also comprise ordering hash values of the entries extracted from the hash chained log into an ordered list. In one embodiment, the method may further comprise producing a cryptographic hash of the ordered list. | 2010-04-08 |
20100088518 | Method of exchanging data such as cryptographic keys between a data processing system and an electronic entity such as a microcircuit card - A method of exchanging data between a data processing system and an electronic entity, characterized by the following steps:
| 2010-04-08 |
20100088519 | CLIENT DEVICE, KEY DEVICE, SERVICE PROVIDING APPARATUS, USER AUTHENTICATION SYSTEM, USER AUTHENTICATION METHOD, PROGRAM, AND RECORDING MEDIUM - In a user authentication system according to the present invention, at user registration, a client device obtains a signature for a user ID, a password, and a public key by using a private key corresponding to the public key, and sends user information that includes the signature and the above-described information items to a service providing apparatus. The service providing apparatus verifies the signature by using the public key and stores the user information by which the password and the public key are associated with each other. When a request for a service is made, the client device allows authentication processing by sending to the service providing apparatus an authentication response that includes the user ID together with password authentication information, a signature for a challenge sent from the service providing apparatus, or a signature for the password and the challenge, irrespective of whether the authentication method for the service is password authentication, public key authentication, or public-key-and-password combination authentication. | 2010-04-08 |
20100088520 | PROTOCOL FOR DETERMINING AVAILABILITY OF PEERS IN A PEER-TO-PEER STORAGE SYSTEM - A method and system is provided for monitoring the availability of a peer in a P2P system that is used to provide remote storage or remote processing power. In one illustrative example, a recipient peer requests access to a service provisioned by another peer in a peer-to-peer network. The request may be a request to access a file or a file fragment that is being stored on the other peer. In order to make use of the accessed service, after receiving access to the service provisioned by the peer, the recipient peer needs to report to a central server that the service has been rendered. For instance, in some cases the file fragment accessed by the recipient peer may be encrypted, in which case the central server will send the recipient peer a decryption key after receiving the report that the service has been rendered. | 2010-04-08 |
20100088521 | PUBLIC ENCRYPTED DISCLOSURE - Public encrypted disclosure provides a creation date verification system by making confidential information available in a secure encrypted form that can be decrypted at a later time to verify the existence of the content at the date of the encrypted disclosure. Options provide for various levels of security, verification, and distribution of encrypted content and for automated encryption, submission, and public disclosure of encrypted content. | 2010-04-08 |
20100088522 | Method and Apparatus for Tamper Proof Camera Logs - A method and apparatus for maintaining a tamper proof device log are described. In one embodiment, the method comprises maintaining an embedded log in the device, the embedded log being a chain of log entries. In one embodiment, the method may also comprise publishing at least one log entry to a location external to the device. | 2010-04-08 |