| 14th week of 2012 patent applcation highlights part 35 |
| Patent application number | Title | Published |
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| 20120083039 | METHOD FOR QUANTITATIVELY DETERMINING IMPURITIES - The invention relates to a method for quantitatively determining impurities in the form of aldehydes and ketones in glycerin serving for preparing pharmaceuticals, in which the glycerin containing impurities is reacted with a derivatization reagent in a sample solution and the quantity of derivatized impurities is determined. Said method is characterized in that PFBHA, O-(2,3,4,5,6-pentafluorobenzyl)-hydroxylamine hydrochloride, is used as the derivatization reagent, the derivatizing is conducted in the presence of a solubilizer in the form of a polar organic solvent, and liquid chromatographic separation and UV detection are performed. A subject matter of the invention is also the use of glycerin, in which the content of impurities of 9 ppm or less has been determined by means of the described method in a pharmaceutical preparation. According to the invention, impurities in glycerin can be better determined. | 2012-04-05 |
| 20120083040 | OXYGEN INDICATOR FOR PARENTERAL AND ENTERAL DOSAGE FORMS - The present invention relates to an oxygen indicator in which the presence or absence of oxygen is made visible by a color change, and to the use of such oxygen indicator for monitoring parenteral and enteral dosage forms. | 2012-04-05 |
| 20120083041 | MASS SPECTROMETRY METHOD - The invention provides a mechanism for semi-quantitatively measuring individual isotopomer species of a molecule using gas chromatograph mass spectrometry. The method allows for semi-quantitatively tracking the movement of ions by measuring the individual isotopomer species of a molecule. | 2012-04-05 |
| 20120083042 | INDUCTION FURNACE OPERATING IN A RANGE FROM 2-9 MHZ FOR PROVIDING ANALYTICAL SAMPLES AND METHOD OF SAME - An analytical induction furnace and method for combusting conductive sample materials ( | 2012-04-05 |
| 20120083043 | TEMPERATURE-TIME INDICATOR SYSTEM BASED ON IRREVERSIBLE COLOR CHANGES, AND CORRESPONDING METHOD - The present invention relates to a temperature-time indicator system which allows monitoring the maintenance of the cold chain in frozen or refrigerated substances based on irreversible color changes, comprising a layer with a solution of ascorbic acid and a layer with a solution of at least one base, wherein the solution of ascorbic acid does not mix with the solution of at least one base unless the temperature reaches a pre-determined threshold. The invention also relates to a method using said system. | 2012-04-05 |
| 20120083044 | ELECTRONIC ANALYTE ASSAYING DEVICE - An improved electronic diagnostic device for detecting the presence of an analyte in a fluid sample comprises a casing having a display, a test strip mounted in the casing, a processor mounted in the casing, and a first sensor mounted in the casing and operatively coupled to the processor. The processor is configured to receive a signal from the first sensor when the device is exposed to ambient light thereby causing the device to become activated. The device includes a light shield that exerts pressure across a width of the test strip to prevent fluid channeling along the length of the test strip. The processor is configured to present an early positive test result reading when a measured value exceeds a predetermined early reading threshold value at any time after a predetermined early testing time period. | 2012-04-05 |
| 20120083045 | SURFACE SAMPLING CONCENTRATION AND REACTION PROBE - A method of analyzing a chemical composition of a specimen is described. The method can include providing a probe comprising an outer capillary tube and an inner capillary tube disposed co-axially within the outer capillary tube, where the inner and outer capillary tubes define a solvent capillary and a sampling capillary in fluid communication with one another at a distal end of the probe; contacting a target site on a surface of a specimen with a solvent in fluid communication with the probe; maintaining a plug volume proximate a solvent-specimen interface, wherein the plug volume is in fluid communication with the probe; draining plug sampling fluid from the plug volume through the sampling capillary; and analyzing a chemical composition of the plug sampling fluid with an analytical instrument. A system for performing the method is also described. | 2012-04-05 |
| 20120083046 | HYBRID DIGITAL AND CHANNEL MICROFLUIDIC DEVICES AND METHODS OF USE THEREOF - The present invention provides a hybrid digital and channel microfluidic device in the form of an integrated structure in which a droplet may be transported by a digital microfluidic array and transferred to a microfluidic channel. In one aspect of the invention, a hybrid device comprises a first substrate having a digital microfluidic array capable of transporting a droplet to a transfer location, and a second substrate having a microfluidic channel. The first and second substrates are affixed to form a hybrid device in which an opening in the microfluidic channel is positioned adjacent to the transfer location, so that a droplet transported to the transfer location contacts the channel opening and may enter the channel. The invention also provides methods of performing separations using a hybrid digital and channel microfluidic device and methods of assembling a hybrid digital microfluidic device. | 2012-04-05 |
| 20120083047 | OVULATION PREDICTOR TEST - The present invention is related to a diagnostic test kit for detecting luteinizing hormone (LH) in a biological sample at a concentration relative to a threshold concentration of LH. The device can include a release medium formed of a first material and including a labeled conjugate with a detectable label and a first binding member reactive with a first epitope of LH and a capture medium formed of a second, different material, in fluid communication with the release medium. The capture medium includes a result site having immobilized thereon a capture component capable of directly or indirectly binding LH that is bound to the labeled conjugate. The device is calibrated such that color development at the result site occurs only when the LH concentration of the liquid sample is greater than the threshold concentration. | 2012-04-05 |
| 20120083048 | METHOD FOR DETECTING LIGAND USING FRET BIOSENSOR - The present application relates to a method for detecting ligand using a biosensor applied the FRET(fluorescence resonance energy transfer) phenomenon. More particularly, the method may be used for simply detecting a ligand in a sample by measuring the FRET of a biosensor under the conditions in which a specific critical temperature is maintained. The method may use a phenomenon in which a ligand-binding protein in a biosensor shows reversible unfolding at a temperature higher than the specific critical temperature and the level of the unfolding changes depending on the concentration of a ligand. The method can be widely applied to a variety of kinds of FRET biosensors using the ligand-binding protein. | 2012-04-05 |
| 20120083049 | SYSTEM AND METHOD FOR LASER PROCESSING AT NON-CONSTANT VELOCITIES - A method is disclosed for on-the-fly processing at least one structure of a group of structures with a pulsed laser output, The method includes the steps of relatively positioning the group of structures and the pulsed laser output axis with non-constant velocity, and applying the pulsed laser output to the at least one structure of the group of structures during the step of relatively positioning the group of structures and the pulsed laser output axis with non-constant velocity. | 2012-04-05 |
| 20120083050 | DETECTING A DEPOSITION CONDITION - Apparatus and methods for detecting evaporation conditions in an evaporator for evaporating metal onto semiconductor wafers, such as GaAs wafers, are disclosed. One such apparatus can include a crystal monitor sensor configured to detect metal vapor associated with a metal source prior to metal deposition onto a semiconductor wafer. This apparatus can also include a shutter configured to remain in a closed position when the crystal monitor sensor detects an undesired condition, so as to prevent metal deposition onto the semiconductor wafer. In some implementations, the undesired condition can be indicative of a composition of a metal source, a deposition rate of a metal source, impurities of a metal source, position of a metal source, position of an electron beam, and/or intensity of an electron beam. | 2012-04-05 |
| 20120083051 | APPARATUS AND METHODS FOR ELECTRICAL MEASUREMENTS IN A PLASMA ETCHER - Apparatus and methods for plasma etching are disclosed. In one embodiment, an apparatus for etching a plurality of features on a wafer comprises a chamber, a feature plate disposed in the chamber for holding the wafer, a gas channel configured to receive a plasma source gas, an anode disposed above the feature plate, a cathode disposed below the feature plate, a radio frequency power source configured to provide a radio frequency voltage between the anode and the cathode so as to generate plasma ions from the plasma source gas, a pump configured to remove gases and etch particulates from the chamber, and a clamp configured to clamp the wafer against the feature plate. The clamp includes at least one measurement hole for passing a portion of the plasma ions to measure a DC bias of the feature plate. | 2012-04-05 |
| 20120083052 | Flexible Packaging for Chip-on-Chip and Package-on-Package Technologies - In one embodiment, a packaging solution for an application integrated circuit (IC) and one or more other ICs is provided. The packaging solution may support both chip-on-chip packaging of the application IC (in flip-chip connection to a package substrate) and other ICs (in non-flip chip orientation), and package-on-package packaging of the application IC and the other ICs. The package substrate may include a first set of pads proximate to the application IC to support chip-on-chip connection to the other ICs. The pads may be connected to conductors that extend underneath the application IC, to connect to the application IC. A second set of pads may be connected to package pins for package-on-package solutions. If the chip-on-chip solution proves reliable, support for the package-on-package solution may be eliminated and the package substrate may be reduced in size. | 2012-04-05 |
| 20120083053 | METHOD FOR ALIGNING WAFER STACK - A method for aligning a wafer stack includes providing a wafer stack including a top wafer with a top mark and a bottom wafer with a bottom mark in particular the top mark and the bottom mark capable of corresponding to each other; adjusting a relative position between the top wafer and the bottom wafer so that the top mark and the bottom mark are in contact with each other; applying an electrical signal on the top mark to obtain an electrical reading and optimizing the electrical reading to substantially align the wafer stack. | 2012-04-05 |
| 20120083054 | METHODS AND APPARATUS FOR ALIGNING A SET OF PATTERNS ON A SILICON SUBSTRATE - The disclosure relates to a method of aligning a set of patterns on a substrate, which includes depositing on the substrate's surface a set of silicon nanoparticles, which includes a set of ligand molecules including a set of carbon atoms. The method involves forming a first set of regions where the nanoparticles are deposited, while the remaining portions of the substrate surface define a second set of regions. The method also includes densifying the set of nanoparticles into a thin film to form a set of silicon-organic zones on the substrate's surface, wherein the first and the second set of regions have respectively first and second reflectivity values, such that the ratio of the second reflectivity value to the first reflectivity value is greater than about 1.1. | 2012-04-05 |
| 20120083055 | STRUCTURE AND METHOD FOR DETERMINING A DEFECT IN INTEGRATED CIRCUIT MANUFACTURING PROCESS - The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas. | 2012-04-05 |
| 20120083056 | LIGHT EMITTING DIODE SEALING MEMBER AND METHOD FOR PRODUCING LIGHT EMITTING DIODE DEVICE - A light emitting diode sealing member includes a light emitting diode sealing layer, and a lens mold layer laminated on the light emitting diode sealing layer. | 2012-04-05 |
| 20120083057 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE PACKAGE - A method for manufacturing a light emitting diode package, includes: providing a light emitting chip structure comprising a substrate and a light emitting layer; treating the light emitting layer to form at least two spaced light emitting chips on the substrate, the light emitting chips each comprising a first surface away from the substrate and a second surface; forming a first carbon nanotube layer covering the first surfaces of the at least two spaced light emitting chips; removing the substrate; forming a second carbon nanotube layer on the second surfaces of the light emitting chips, thus obtaining a first carbon nanotube layer and a second carbon nanotube layer on opposite sides of the at least two spaced light emitting chips; and packaging the light emitting chip structure to obtain the light emitting diode package. | 2012-04-05 |
| 20120083058 | Optical semiconductor device and method for manufacturing the same - There is provided an optical semiconductor device having a first optical semiconductor element including an InP substrate, a lower cladding layer formed on the InP substrate, a lower optical guide layer which is formed on the lower cladding layer and is composed of AlGaInAs, an active layer which is formed on the lower optical guide layer and has a multiple quantum well structure where a well layer and a barrier layer that is formed of AlGaInAs are alternately stacked, an upper optical guide layer which is formed on the active layer and is composed of InGaAsP, and an upper cladding layer formed on the upper optical guide layer. | 2012-04-05 |
| 20120083059 | SAPPHIRE WAFER DIVIDING METHOD - A sapphire wafer dividing method including a cut groove forming step of forming a plurality of cut grooves on the back side of a sapphire wafer along a plurality of crossing division lines formed on the front side where a light emitting layer is formed, a modified layer forming step of forming a plurality of modified layers inside the sapphire wafer along the division lines, and a dividing step of dividing the sapphire wafer into individual light emitting devices along the modified layers as a division start point, thereby chamfering the corners of the back side of each light emitting device owing to the formation of the cut grooves in the cut groove forming step. | 2012-04-05 |
| 20120083060 | INTEGRATION OF CLUSTER MOCVD AND HVPE REACTORS WITH OTHER PROCESS CHAMBERS - The integration of cluster metal-organic chemical vapor deposition (MOCVD) and hydride vapor phase epitaxy (HVPE) reactors with other process chambers is described. For example, a method of fabricating a light-emitting diode (LED) structure described herein includes forming, in a first chamber of a cluster tool, a P-type group III-V material layer above a substrate. Without removing the substrate from the cluster tool a metal contact layer is formed directly on the P-type group III-V material layer in a second chamber of the cluster tool. | 2012-04-05 |
| 20120083061 | THIN FILM DEPOSITION APPARATUS AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY DEVICE BY USING THE SAME - A thin film deposition apparatus and an organic light-emitting display device by using the same. The thin film deposition apparatus includes an electrostatic chuck, a plurality of chambers; at least one thin film deposition assembly; a carrier; a first power source plug; and a second power source plug. The electrostatic chuck includes a body having a supporting surface that contacts a substrate to support the substrate, wherein the substrate is a deposition target; an electrode embedded into the body and applying an electrostatic force to the supporting surface; and a plurality of power source holes formed to expose the electrode and formed at different locations on the body. | 2012-04-05 |
| 20120083062 | METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DEVICE - Provided is a method of manufacturing an organic light emitting device including the step of forming an electron injection layer. The step of forming the electron injection layer includes the steps of: vaporizing in a container a dopant material as a raw material of a dopant; causing the vaporized dopant material to pass a heated medium between the container and the substrate; and forming the organic compound into the electron injection layer. According to the method the organic light emitting device which has high electron injection efficiency and can be driven at a low voltage can be obtained. | 2012-04-05 |
| 20120083063 | Method for producing group III nitride semiconductor light-emitting device - A method for producing a Group III nitride semiconductor light-emitting device includes an n-type layer, a light-emitting layer, and a p-type layer, each of the layers being formed of Group III nitride semiconductor, being sequentially deposited via a buffer layer on a textured sapphire substrate. A buried layer is formed of Group III nitride semiconductor on the buffer layer, at a temperature lower by 20° C. to 80° C. than the temperature of 1000° C. to 1200° C. when the n-type layer is deposited on the buried layer. The texture provided on the sapphire substrate may have a depth of 1 μm to 2 μm and a side surface inclined by 40° to 80°. A preventing layer may be formed of GaN at 600° C. to 1050° C. so as to cover the entire top surface of the buffer layer. | 2012-04-05 |
| 20120083064 | Process for solar cell module edge sealing - A new process of edge sealing for solar cell modules is described. The process comprises coating a waterproof material on the edge of the solar cell module to form a U-like shaped edge sealing which can achieve the function of shock absorber. | 2012-04-05 |
| 20120083065 | ARTICLES SUCH AS SAFETY LAMINATES AND SOLAR CELL MODULES CONTAINING HIGH MELT FLOW ACID COPOLYMER COMPOSITIONS - A process of manufacturing a solar cell module, the process comprising:
| 2012-04-05 |
| 20120083066 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - A complementary metal oxide semiconductor (CMOS) device and a method for fabricating the same are provided. The CMOS image sensor includes: a first conductive type substrate including a trench; a channel stop layer formed by using a first conductive type epitaxial layer over an inner surface of the trench; a device isolation layer formed on the channel stop layer to fill the trench; a second conductive type. photodiode formed in a portion of the substrate in one side of the channel stop layer; and a transfer gate structure formed on the substrate adjacent to the photodiode to transfer photo-electrons generated from the photodiode. | 2012-04-05 |
| 20120083067 | METHOD FOR FORMING PHOTODETECTOR ISOLATION IN IMAGERS - A first shallow trench isolation region is disposed in the silicon semiconductor layer laterally adjacent to a photodetector while a second shallow trench isolation region is disposed in the silicon semiconductor layer laterally adjacent to other electrical components in a pixel. The first and second shallow trench isolation regions each include a trench disposed in the silicon semiconductor layer that is filled with a dielectric material. An isolation layer having the second conductivity is disposed only along a portion of a bottom and only along a sidewall of the trench immediately adjacent to the photodetector. The isolation layer is not disposed along the other portion of the bottom and along the other sidewall of the trench adjacent the photodetector. The isolation layer is not disposed along the bottom and sidewalls of the trench adjacent to the other electrical components. | 2012-04-05 |
| 20120083068 | PHOTOVOLTAIC DEVICE AND METHOD FOR MAKING - One aspect of the present invention provides a device that includes a substrate; a first semiconducting layer; a transparent conductive layer; a transparent window layer. The transparent window layer includes cadmium sulfide and oxygen. The device has a fill factor of greater than about 0.65. Another aspect of the present invention provides a method of making the device. | 2012-04-05 |
| 20120083069 | ORGANIC THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - Disclosed are an organic thin film transistor and a method of manufacturing the same, in which a crystalline organic binder layer is on the surface of an organic insulating layer and source/drain electrodes or on the surface of the source/drain electrodes. The organic thin film transistor may be improved in two-dimensional geometric lattice matching and interface stability at the interface between the organic semiconductor and the insulating layer or at the interface between the organic semiconductor layer and the electrode, thereby improving the electrical properties of the device. | 2012-04-05 |
| 20120083070 | CHARGE INJECTION AND TRANSPORT LAYERS - Compositions for use in hole transporting layers (HTLs) or hole injection layers (HILs) are provided, as well as methods of making the compositions and devices fabricated from the compositions. OLED devices can be made. The compositions comprise at least one conductive conjugated polymer, at least one semiconducting matrix component that is different from the conductive conjugated polymer, and an optional dopant, and are substantially free of an insulating matrix component. | 2012-04-05 |
| 20120083071 | SEMICONDUCTOR DIE PACKAGE INCLUDING LOW STRESS CONFIGURATION - A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure. | 2012-04-05 |
| 20120083072 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Performing electrolysis plating to a wiring is made possible, aiming at the increasing of pin count of a semiconductor device. Package substrate | 2012-04-05 |
| 20120083073 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - It is aimed at improving the reliability of a semiconductor device. | 2012-04-05 |
| 20120083074 | FLEXIBLE SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME - A flexible semiconductor package includes a flexible substrate. A data chip is disposed over the flexible substrate. The data chip includes a data storage unit for storing data and first bonding pads that are electrically connected to the data storage unit. A control chip is disposed over the flexible substrate. The control chip includes a data processing unit for processing the data in the data chip and second bonding pads that are electrically connected to the data processing unit. Wirings are formed in order to electrically connect the first bonding pads to the second bonding pads. | 2012-04-05 |
| 20120083075 | METHOD OF FORMING A BI-DIRECTIONAL TRANSISTOR WITH BY-PASS PATH - In one embodiment, a transistor is formed to have a first current flow path to selectively conduct current in both directions through the transistor and to have a second current flow path to selectively conduct current in one direction. | 2012-04-05 |
| 20120083076 | Ultra-Shallow Junction MOSFET Having a High-k Gate Dielectric and In-Situ Doped Selective Epitaxy Source/Drain Extensions and a Method of Making Same - A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described. | 2012-04-05 |
| 20120083077 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer. | 2012-04-05 |
| 20120083078 | METHOD FOR MANUFACTURING TRANSISTOR - To provide a method for manufacturing a transistor which has little variation in characteristics and favorable electric characteristics. A gate insulating film is formed over a gate electrode; a semiconductor layer including a microcrystalline semiconductor is formed over the gate insulating film; an impurity semiconductor layer is formed over the semiconductor layer; a mask is formed over the impurity semiconductor layer, and then the semiconductor layer and the impurity semiconductor layer are etched with use of the mask to form a semiconductor stacked body; the mask is removed and then the semiconductor stacked body is exposed to plasma generated in an atmosphere containing a rare gas to form a barrier region on a side surface of the semiconductor stacked body; and a wiring over the impurity semiconductor layer of the semiconductor stacked body is formed. | 2012-04-05 |
| 20120083079 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing the semiconductor device includes amorphizing a first region and a second region of a semiconductor substrate by an ion implantation, implanting a first impurity and a second impurity respectively in the first region and the second region, activating the implanted impurities to form a first impurity layer and a second impurity layer, epitaxially growing a semiconductor layer above the semiconductor substrate with the impurity layers formed on, growing a gate insulating film above the first region and the second region, and forming a first gate electrode above the gate insulating film in the first region and the second gate electrode above the gate insulating film in the second region. | 2012-04-05 |
| 20120083080 | METHOD FOR REDUCING PUNCH-THROUGH IN A TRANSISTOR DEVICE - Punch-through in a transistor device is reduced by forming a well layer in an implant region, forming a stop layer in the well layer of lesser depth than the well layer, and forming a doped layer in the stop layer of lesser depth than the stop layer. The stop layer has a lower concentration of impurities than the doped layer in order to prevent punch-through without increasing junction leakage. | 2012-04-05 |
| 20120083081 | METHOD FOR PRODUCING A GATE ELECTRODE STRUCTURE - A transistor with a gate electrode structure is produced by providing a semiconductor body with a first surface, and with a first sacrificial layer extending in a vertical direction of the semiconductor body from the first surface. A first trench extending from the first surface into the semiconductor body is formed by removing the sacrificial layer in a section adjacent the first surface. A second trench is formed by isotropically etching the semiconductor body in the first trench. A third trench is formed below the second trench by removing at least a part of the first sacrificial layer below the second trench. A dielectric layer is formed which at least covers sidewalls of the third trench and which only covers sidewalls of the second trench. A gate electrode is formed on the dielectric layer in the second trench. The gate electrode and dielectric layer in the second trench form the gate electrode structure. | 2012-04-05 |
| 20120083082 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The method of manufacturing the semiconductor device includes forming a trench to be an alignment mark in a semiconductor substrate, forming a mask film exposing a region to be a device isolation region and covering a region to be a device region by aligning with the alignment mark above the semiconductor substrate with the trench formed in, anisotropically etching the semiconductor substrate with the mask film as a mask to form a device isolation trench in the region to be the device isolation region of the semiconductor substrate, and burying the device isolation trench by an insulating film to form a device isolation insulating film. In forming the trench, the trench is formed in a depth which is smaller than a depth equivalent to a thickness of the mask film. | 2012-04-05 |
| 20120083083 | Trench metal oxide semiconductor field effect transistor (MOSFET) with low gate to drain coupled charges (Qgd) structures - A trenched semiconductor power device includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The trenched semiconductor power device further comprises tilt-angle implanted body dopant regions surrounding a lower portion of trench sidewalls for reducing a gate-to-drain coupling charges Qgd between the trenched gates and a drain disposed at a bottom of the semiconductor substrate. The trenched semiconductor power device further includes a source dopant region disposed below a bottom surface of the trenched gates for functioning as a current path between the drain to the source for preventing a resistance increase caused by the body dopant regions surrounding the lower portions of the trench sidewalls. | 2012-04-05 |
| 20120083084 | Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier source - A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source and that may include a PtSi, ErSi layer and may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer. | 2012-04-05 |
| 20120083085 | METHOD FOR PRODUCING AN ELECTRODE STRUCTURE - A method for producing a semiconductor device with an electrode structure includes providing a semiconductor body with a first surface, and with a first sacrificial layer extending in a vertical direction of the semiconductor body from the first surface, and forming a first trench extending from the first surface into the semiconductor body. The first trench is formed at least by removing the sacrificial layer in a section adjacent to the first surface. The method further includes forming a second trench by isotropically etching the semiconductor body in the first trench, forming a dielectric layer which covers sidewalls of the second trench, and forming an electrode on the dielectric layer in the second trench, the electrode and the dielectric layer in the second trench forming the electrode structure. | 2012-04-05 |
| 20120083086 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - There is provided a semiconductor device including a semiconductor substrate ( | 2012-04-05 |
| 20120083087 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A protection film is formed on a semiconductor substrate. Impurity ions are implanted into the semiconductor substrate through the protection film. The impurity is activated to form an impurity layer. The protection film is removed after forming the impurity layer. The semiconductor substrate of a surface portion of the impurity layer is removed after removing the protection film. A semiconductor layer is epitaxially grown above the semiconductor substrate after removing the semiconductor substrate of the surface portion of the impurity layer. | 2012-04-05 |
| 20120083088 | INTEGRATED CIRCUIT DEVICE WITH WELL CONTROLLED SURFACE PROXIMITY AND METHOD OF MANUFACTURING SAME - An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region. | 2012-04-05 |
| 20120083089 | FABRICATING METHOD OF METAL SILICIDE LAYER, FABRICATING METHOD OF SEMICONDUCTOR DEVICE USING THE SAME AND SEMICONDUCTOR DEVICE FABRICATED USING THE METHOD - A method of fabricating a metal silicide layer includes forming a metal layer on a substrate, and forming a pre-metal silicide layer by reacting the substrate with the metal layer by performing a first annealing process on the substrate. The method also includes implanting silicon into the substrate using a gas cluster ion beam (GCIB) process, and changing the pre-metal silicide layer into a metal silicide layer by performing a second annealing process on the substrate. | 2012-04-05 |
| 20120083090 | Method of fabricating an NMOS transistor - A SiC region and a source/drain region are formed such that the SiC region includes a first portion overlapping the source/drain region and a second portion protruding from the source/drain region to a position beneath the LDD region. The concentration of crystalline SiC in the second portion is higher than the concentration of crystalline SiC in the first portion. The SiC region may be formed through a normal implantation before the second spacer is formed, or the SiC region may be formed through a tilt implantation or deposition epitaxially in a recess having a sigma-shape like sidewall after the second spacer is formed. | 2012-04-05 |
| 20120083091 | DEEP TRENCH ELECTROSTATIC DISCHARGE (ESD) PROTECT DIODE FOR SILICON-ON-INSULATOR (SOI) DEVICES - A semiconductor includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region. | 2012-04-05 |
| 20120083092 | STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM - A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures. | 2012-04-05 |
| 20120083093 | ISOLATION STRUCTURE FOR A MEMORY CELL USING AL2O3 DIELECTRIC - The invention provides, in one exemplary embodiment, an isolation gate formed over a substrate for biasing the substrate and providing isolation between adjacent active areas of an integrated circuit structure, for example a DRAM memory cell. An aluminum oxide (Al2O3) is used as a gate dielectric, rather than a conventional gate oxide layer, to create a hole-rich accumulation region under and near the trench isolation region. Another exemplary embodiment of the invention provides an aluminum oxide layer utilized as a liner in a shallow trench isolation (STI) region to increase the effectiveness of the isolation region. The embodiments may also be used together at an isolation region. | 2012-04-05 |
| 20120083094 | INTEGRATED CIRCUIT GUARD RINGS - Integrated circuits with guard rings are provided. Integrated circuits may include internal circuitry that is sensitive to external noise sources. A guard ring may surround the functional circuitry to isolate the circuitry from the noise sources. The guard ring may include first, second, and third regions. The first and third regions may include p-wells. The second region may include an n-well. Stripes of diffusion regions may be formed at the surface of a substrate in the three regions. Areas in the guard ring that are not occupied by the diffusion regions are occupied by shallow trench isolation (STI) structures. Stripes of dummy structures may be formed over respective STI structures and may not overlap the diffusion regions. The diffusion regions in the first and third regions may be biased to a ground voltage. The diffusion regions in the second section may be biased to a positive power supply voltage. | 2012-04-05 |
| 20120083095 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE BY THINNING HARDMASK LAYERS ON FRONTSIDE AND BACKSIDE OF SUBSTRATE - The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate. | 2012-04-05 |
| 20120083096 | SEMICONDUCTOR DEVICE HAVING A SIMPLIFIED STACK AND METHOD FOR MANUFACTURING TEHREOF - Embodiments of the present invention are directed to provide a semiconductor device including a semiconductor chip formed of a conductive material, a connector terminal around the semiconductor chip, which is formed of a same material for forming the semiconductor chip, an insulating member for electrically insulating the semiconductor chip from the connector terminal, and a first connection member for electrically coupling the semiconductor chip with the connector terminal Simplified step of manufacturing the connector terminal may further simplify the steps of manufacturing the semiconductor device. | 2012-04-05 |
| 20120083097 | Methods of Forming a Semiconductor Package Using a Seed Layer and Semiconductor Packages Formed Using the Same - Provided is a method of forming a semiconductor package including providing a substrate having a first side and an opposite second side and providing a wafer having a plurality of semiconductor chips, each of the semiconductor chips having a conductive pad, wherein at least one of the substrate and the wafer includes a seed pattern. The first side of the substrate is bonded to the wafer with the conductive pad positioned adjacent to the first side of the substrate and the seed pattern positioned between the conductive pad and the first side of the substrate. A through hole is then formed penetrating the substrate from the second side of the substrate to expose the seed pattern. A through electrode is formed in the through hole using the seed pattern as a seed. Corresponding devices are also provided. | 2012-04-05 |
| 20120083098 | Method for Manufacturing a Composite Wafer Having a Graphite Core, and Composite Wafer Having a Graphite Core - According to an embodiment, a composite wafer includes a carrier substrate having a graphite layer and a monocrystalline semiconductor layer attached to the carrier substrate. | 2012-04-05 |
| 20120083099 | Printable Semiconductor Structures and Related Methods of Making and Assembling - The present invention provides a high yield pathway for the fabrication, transfer and assembly of high quality printable semiconductor elements having selected physical dimensions, shapes, compositions and spatial orientations. The compositions and methods of the present invention provide high precision registered transfer and integration of arrays of microsized and/or nanosized semiconductor structures onto substrates, including large area substrates and/or flexible substrates. In addition, the present invention provides methods of making printable semiconductor elements from low cost bulk materials, such as bulk silicon wafers, and smart-materials processing strategies that enable a versatile and commercially attractive printing-based fabrication platform for making a broad range of functional semiconductor devices. | 2012-04-05 |
| 20120083100 | THERMALIZING GAS INJECTORS FOR GENERATING INCREASED PRECURSOR GAS, MATERIAL DEPOSITION SYSTEMS INCLUDING SUCH INJECTORS, AND RELATED METHODS - Methods of depositing material on a substrate include forming a precursor gas and a byproduct from a source gas within a thermalizing gas injector. The byproduct may be reacted with a liquid reagent to form additional precursor gas, which may be injected from the thermalizing gas injector into a reaction chamber. Thermalizing gas injectors for injecting gas into a reaction chamber of a deposition system may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. A pathway may extend from the inlet, through the thermalizing conduit to an interior space within the liquid container, and from the interior space within the liquid container to the outlet. The thermalizing conduit may have a length that is greater than a shortest distance between the inlet and the liquid container. Deposition systems may include one or more such thermalizing gas injectors. | 2012-04-05 |
| 20120083101 | SYSTEMS AND METHODS FOR FORMING SEMICONDUCTOR MATERIALS BY ATOMIC LAYER DEPOSITION - Methods of depositing a III-V semiconductor material on a substrate include sequentially introducing a gaseous precursor of a group III element and a gaseous precursor of a group V element to the substrate by altering spatial positioning of the substrate with respect to a plurality of gas columns. For example, the substrate may be moved relative to a plurality of substantially aligned gas columns, each disposing a different precursor. Thermalizing gas injectors for generating the precursors may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. Deposition systems for forming one or more III-V semiconductor materials on a surface of the substrate may include one or more such thermalizing gas injectors configured to direct the precursor to the substrate via the plurality of gas columns. | 2012-04-05 |
| 20120083102 | Integrated Shadow Mask/Carrier for Pattern Ion Implantation - An improved, lower cost method of processing substrates, such as to create solar cells is disclosed. In addition, a modified substrate carrier is disclosed. The carriers typically used to carry the substrates are modified so as to serve as shadow masks for a patterned implant. In some embodiments, various patterns can be created using the carriers such that different process steps can be performed on the substrate by changing the carrier or the position with the carrier. In addition, since the alignment of the substrate to the carrier is critical, the carrier may contain alignment features to insure that the substrate is positioned properly on the carrier. In some embodiments, gravity is used to hold the substrate on the carrier, and therefore, the ions are directed so that the ion beam travels upward toward the bottom side of the carrier. | 2012-04-05 |
| 20120083103 | METHOD FOR MINIMIZING DEFECTS IN A SEMICONDUCTOR SUBSTRATE DUE TO ION IMPLANTATION - Defects in a semiconductor substrate due to ion implantation are minimized by forming an implant region in the semiconductor substrate and subjecting the semiconductor substrate to a first anneal to recrystallize the semiconductor substrate. The semiconductor substrate is subjected to a second anneal to suppress diffusion of implanted ions in the semiconductor substrate. The first anneal being at a lower temperature and longer duration than the second anneal. | 2012-04-05 |
| 20120083104 | METHODS OF FORMING A FLOATING JUNCTION ON A SOLAR CELL WITH A PARTICLE MASKING LAYER - A method of forming a floating junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front surface and a rear surface. The method also includes depositing a set of masking particles on the rear surface in a set of patterns; and heating the substrate in a baking ambient to a first temperature and for a first time period in order to create a particle masking layer. The method further includes exposing the substrate to a phosphorous deposition ambient at a second temperature and for a second time period, wherein a front surface PSG layer, a front surface phosphorous diffusion, a rear surface PSG layer, and a rear surface phosphorous diffusion are formed, and wherein a first phosphorous dopant surface concentration in the substrate proximate to the set of patterns is less than a second dopant surface concentration in the substrate not proximate to the set of patterns. The method also includes exposing the substrate to a set of etchants for a third time period, wherein the front surface PSG layer and the rear surface PSG layer are substantially removed; depositing a front surface SiN | 2012-04-05 |
| 20120083105 | METHOD FOR BORON DOPING SILICON WAFERS - A process for P-type boron doping of silicon wafers placed on a support in the chamber of a furnace of whose one end includes a wall in which element for introducing reactive gases and a carrier gas carrying a boron precursor in gaseous form are located, whereby the process includes the following stages: a) reacting in the chamber, the reactive gases with boron trichloride BCl | 2012-04-05 |
| 20120083106 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - The present application discloses a method for manufacturing a semiconductor structure, comprising the steps of: a) providing a p-type field effect transistor; b) forming a tensile-stressed layer on the p-type field effect transistor; c) removing a portion of the tensile-stressed layer, so that the remaining portion of the tensile-stressed layer generates compressive stress in the channel of the p-type field effect transistor; and d) performing annealing, so as to achieve the object of memorizing compressive stress in a channel of a transistor and improving the performance of the transistor. The method according to the present invention memorizes the compressive stress in the channel of the transistor by a stress memorization technique, increases mobility of holes, and improves overall performance of the semiconductor structure. | 2012-04-05 |
| 20120083107 | FinFETs Having Dielectric Punch-Through Stoppers - A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator. | 2012-04-05 |
| 20120083108 | Transistor Level Routing - A system and a method for transistor level routing are disclosed. The method comprises forming a high-k dielectric layer over a substrate, forming a metal layer directly over the high-k dielectric layer, and selectively disposing a semiconductive layer over the metal layer. The method further comprises forming a first transistor in a first region and a second transistor in a second region spaced from the first region, the first and second transistor having gate stacks comprising a high-k dielectric layer, a metal layer and a semiconductive layer, and forming an electrical connection between the first transistor and the second transistor comprising the high-k dielectric layer and the metal layer but not the semiconductive layer. | 2012-04-05 |
| 20120083109 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a bit line that is provided in a semiconductor substrate, a silicide layer that has side faces and a bottom face surrounded by the bit line and is provided within the bit line, an ONO film that is provided on the semiconductor substrate, and sidewalls that are in contact with the side faces of a trapping layer in the ONO film over the portions of the bit line located on both sides of the silicide layer, the sidewalls being formed with silicon oxide films including phosphorus. | 2012-04-05 |
| 20120083110 | METHOD FOR MANUFACTURING MOS TRANSISTORS WITH DIFFERENT TYPES OF GATE STACKS - A method for manufacturing three types of MOS transistors in three regions of a same substrate, including the steps of: forming a first insulating layer, removing the first insulating layer from the first and second regions, forming a silicon oxide layer, depositing an insulating layer having a dielectric constant which is at least twice greater than that of silicon oxide, depositing a first conductive oxygen scavenging layer, removing the first conductive layer from the second and third regions, and annealing. | 2012-04-05 |
| 20120083111 | Methods of Manufacturing a Semiconductor Device - There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern. | 2012-04-05 |
| 20120083112 | METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY WITH BACKING WIRINGS - A nonvolatile semiconductor memory comprises a first memory cell transistor, a second memory cell transistor, a connection layer, protrusion portions and a contact portion. The first memory cell transistor comprises a first gate electrode formed above a first channel region, and a second gate electrode formed on a side of the first gate electrode through an insulating film. The second memory cell transistor comprises a third gate electrode formed above a second channel region, and a fourth gate electrode formed on a side of the third gate electrode through an insulating film and facing the second gate electrode. The connection layer connects the second gate electrode and the fourth gate electrode. The protrusion portions are formed of a material different than that of the second and fourth gate electrodes, and are formed on both ends of the connection layer. The contact portion is formed on the connection layer. | 2012-04-05 |
| 20120083113 | CREATION OF LEAD-FREE SOLDER JOINT WITH INTERMETALLICS - A method of coupling an integrated circuit to a substrate includes providing the substrate, forming a contact pad in the substrate, contacting the contact pad with a solder ball, and repeatedly exposing the solder ball to a thermal process to cause intermetallics based on a metal in the contact pad to be formed in the thermal ball. | 2012-04-05 |
| 20120083114 | DIMENSIONALLY DECOUPLED BALL LIMITING METALURGY - A method for reducing stress on under ball metallurgy (UBM) is disclosed. A collar is disposed around the ball to provide support, and prevent solder interaction in the undercut areas of the UBM. In one embodiment, the collar is comprised of photosensitive polyimide. | 2012-04-05 |
| 20120083115 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT STRUCTURE AND A REINFORCING INSULATING FILM - A semiconductor device includes in an interconnect structure which includes a first interconnect made of a copper-containing metal, a first Cu silicide layer covering the upper portion of the first interconnect, a conductive first plug provided on the upper portion of the Cu silicide layer and connected to the first interconnect, a Cu silicide layer covering the upper portion of the first plug, a first porous MSQ film provided over the side wall from the first interconnect through the first plug and formed to cover the side wall of the first interconnect, the upper portion of the first interconnect, and the side wall of the first plug, and a first SiCN film disposed under the first porous MSQ film to contact with the lower portion of the side wall of the first interconnect and having the greater film density than the first porous MSQ film. | 2012-04-05 |
| 20120083116 | Cost-Effective TSV Formation - A device includes a substrate having a first surface, and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the substrate. A dielectric layer is disposed over the substrate. A metal pad is disposed in the dielectric layer and physically contacting the TSV, wherein the metal pad and the TSV are formed of a same material, and wherein no layer formed of a material different from the same material is between and spacing the TSV and the metal pad apart from each other. | 2012-04-05 |
| 20120083117 | Method Of Forming Hardened Porous Dielectric Layer And Method Of Fabricating Semiconductor Device Having Hardened Porous Dielectric Layer - Example embodiments relate to a method of forming a hardened porous dielectric layer. The method may include forming a dielectric layer containing porogens on a substrate, transforming the dielectric layer into a porous dielectric layer using a first UV curing process to remove the porogens from the dielectric layer, and transforming the porous dielectric layer into a crosslinked porous dielectric layer using a second UV curing process to generate crosslinks in the porous dielectric layer. | 2012-04-05 |
| 20120083118 | METHODS OF EVAPORATING METAL ONTO A SEMICONDUCTOR WAFER IN A TEST WAFER HOLDER - Apparatus and methods for evaporating metal onto semiconductor wafers are disclosed. One such apparatus can include an evaporation chamber that includes a wafer holder, such as a dome, and a test wafer holder that is separate and spaced apart from the wafer holder. In certain implementations, the test wafer can be coupled to a cross beam supporting at least one shaper. A metal can be evaporated onto production wafers positioned in the wafer holder while metal is evaporated on a test wafer positioned in a test wafer holder. In some instances, the production wafers can be GaAs wafers. The test wafer can be used to make a quality assessment about the production wafers. | 2012-04-05 |
| 20120083119 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming a first insulating interlayer positioned above one surface of a substrate, forming a first hole extended from the surface of the first insulating interlayer to midway of the substrate, forming a through-electrode in the first hole, forming an electro-conductive pattern positioned on the surface of the first insulating interlayer, and connected to one end of the through-electrode, making the other end of the through-electrode expose, by removing the other surface of the substrate, and forming a connection terminal connected to the other end of the through-electrode, on the other surface of the substrate. | 2012-04-05 |
| 20120083120 | SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A substrate processing apparatus includes a processing chamber in which a substrate is processed, a substrate holder configured to be loaded into and unloaded from the processing chamber while holding the substrate, a transfer chamber in which a charging operation for causing the substrate holder to hold an unprocessed substrate and a discharging operation for taking out a processed substrate from the substrate holder are performed, and a cleaning unit configured to blow clean air into the transfer chamber. The transfer chamber has a polygonal plan-view shape and includes corner areas. The cleaning unit is arranged in one of the corner areas of the transfer chamber. | 2012-04-05 |
| 20120083121 | Fabrication of Replacement Metal Gate Devices - Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor. | 2012-04-05 |
| 20120083122 | Shallow Trench Isolation Chemical Mechanical Planarization - A polishing method includes polishing, in a first polish, a wafer to remove overburden and planarize a top layer leaving a portion remaining on an underlying layer. A second polishing step includes two phases. In a first phase, the top layer is removed and the underlying layer is exposed, with a top layer to underlying layer selectivity of between about 1:1 to about 2:1 to provide a planar topography. In a second phase, residual portions of the top layer are removed from a top of the underlying layer to ensure complete exposure of an underlying layer surface. | 2012-04-05 |
| 20120083123 | Chemical Mechanical Planarization Processes For Fabrication of FINFET Devices - A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography. | 2012-04-05 |
| 20120083124 | Method of Patterning NAND Strings Using Perpendicular SRAF - A lithography mask includes a plurality of patterning features formed on a mask substrate and a first plurality of sub-resolution assist features (SRAFs) formed substantially perpendicular to the patterning features on the mask substrate. | 2012-04-05 |
| 20120083125 | Chemical Mechanical Planarization With Overburden Mask - Planarization methods include depositing a mask material on top of an overburden layer on a semiconductor wafer. The mask material is planarized to remove the mask material from up areas of the overburden layer to expose the overburden layer without removing the mask material from down areas. The exposed overburden layer is wet etched and leaves a thickness remaining over an underlying layer. Remaining portions of the mask layer and the exposed portions of the overburden layer are planarized to expose the underlying layer. | 2012-04-05 |
| 20120083126 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method for forming a semiconductor device includes forming a partition line pattern and a partition pad pattern connected to an end part of the partition line pattern over the semiconductor substrate. Spacer insulation layers are formed at sidewalls of the partition line pattern and the partition pad pattern. A gap-filling layer is formed between the spacer insulation layers. A first cutting mask pattern is formed to expose a connecting part between the partition line pattern and the partition pad pattern. The partition line pattern and the gap-filling layer adjacent to the spacer insulation layer are removed using the first cutting mask pattern as a mask. A second cutting mask pattern including a first pattern and a second pattern are formed. The spacer insulation layer is removed using the second cutting mask pattern as a mask to form a gate trench in the substrate. | 2012-04-05 |
| 20120083127 | METHOD FOR FORMING A PATTERN AND A SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A method for forming a fine pattern on a substrate includes providing a substrate including a material with an initial pattern formed thereon and having a first line width, performing a self-limiting oxidation and/or nitridation process on a surface of the material and thereby forming an oxide, a nitride, or an oxynitride film on a surface of the initial pattern, and removing the oxide, nitride, or oxynitride film. The method further includes repeating the formation and removal of the oxide, nitride, or oxynitride film to form a second pattern having a second line width that is smaller than the first line width of the initial pattern. The patterned material can contain silicon, a silicon-containing material, a metal, or a metal-nitride, and the self-limiting oxidation process can include exposure to vapor phase ozone, atomic oxygen generated by non-ionizing electromagnetic (EM) radiation, atomic nitrogen generated by ionizing or non-ionizing EM radiation, or a combination thereof. | 2012-04-05 |
| 20120083128 | METHOD FOR ETCHING HIGH-ASPECT-RATIO FEATURES - A method for etching high-aspect-ratio features is disclosed. The method is applicable in forming a nanoscale deep trench having a smooth and angle-adjustable sidewall. The method includes: forming a patterned photoresist layer on a surface of a silicon substrate for exposing a part of the silicon substrate; and supplying a process gas simultaneously containing sulfur hexafluoride (SF | 2012-04-05 |
| 20120083129 | APPARATUS AND METHODS FOR FOCUSING PLASMA - Apparatus and methods for plasma etching are disclosed. In one embodiment, a method for etching a plurality of features on a wafer includes positioning the wafer within a chamber of a plasma etcher, generating plasma ions using a radio frequency power source and a plasma source gas, directing the plasma ions toward the wafer using an electric field, and focusing the plasma ions using a plasma focusing ring. The plasma focusing ring is configured to increase a flux of plasma ions arriving at a surface of the wafer to control the formation of the plurality of features and structures associated therewith. | 2012-04-05 |
| 20120083130 | APPARATUS AND METHODS FOR SHIELDING A PLASMA ETCHER ELECTRODE - Apparatus and methods for plasma etching are disclosed. In one embodiment, a method of etching a plurality of features on a wafer includes positioning a wafer on a feature plate within a chamber of a plasma etcher, providing a plasma source gas within the chamber, providing an anode above the feature plate and a cathode below the feature plate, connecting a portion of the cathode to the feature plate, generating plasma ions using a radio frequency power source and the plasma source gas, directing the plasma ions toward the wafer using an electric field, and providing an electrode shield around the cathode. The electrode shield is configured to protect the cathode from ions directed toward the cathode including the portion of the cathode connected to the feature plate. | 2012-04-05 |
| 20120083131 | METHOD AND APPARATUS FOR TREATING SILICON SUBSTRATE - A method and an apparatus for treating a silicon substrate for effectively removing a silicon oxide film formed on a surface of a silicon film and improving surface uniformity of the silicon film. The method comprises providing a substrate including a silicon film; providing a first fluid, which is capable of etching a silicon oxide film, to a surface of the substrate in a first time band; providing a second fluid containing water to the surface of the substrate in a second time band, which is different from the first time band; and providing a third fluid, which is capable of etching the silicon oxide film, has different ingredients as compared to the first fluid, and has high etching ratio with respect to the silicon oxide film, to a surface of the substrate in a third time band, which is different from the first time band and the second time band. | 2012-04-05 |
| 20120083132 | METHOD FOR MINIMIZING DEFECTS IN A SEMICONDUCTOR SUBSTRATE DUE TO ION IMPLANTATION - The effects of knock-on oxide in a semiconductor substrate are reduced by providing a semiconductor substrate and forming a thin layer of native oxide on the semiconductor substrate. Ion implantation is performed through the native oxide layer. The native oxide layer reduces the phenomenon of knock-on oxide and oxygen concentration within the semiconductor substrate. Further reduction may be achieved by etching the surface of the semiconductor substrate in order to eliminate a concentration of oxygen at a surface of the semiconductor substrate. | 2012-04-05 |
| 20120083133 | AMINE CURING SILICON-NITRIDE-HYDRIDE FILMS - Methods of forming dielectric layers are described. The methods may include forming a silicon-nitrogen-and-hydrogen-containing layer on a substrate. The methods include ozone curing the silicon-nitrogen-and-hydrogen-containing layer to turn the silicon-nitrogen-and-hydrogen-containing layer into a silicon-and-oxygen-containing layer. Following ozone curing, the layer is exposed to an amine-water combination at low temperature before an anneal. The presence of the amine cure allows the conversion to silicon-and-oxygen-containing layer to occur more rapidly and completely at a lower temperature during the anneal. The amine cure also enables the anneal to use a less oxidative environment to effect the conversion to the silicon-and-oxygen-containing layer. | 2012-04-05 |
| 20120083134 | METHOD OF MITIGATING SUBSTRATE DAMAGE DURING DEPOSITION PROCESSES - Systems, methods, and apparatus for depositing a protective layer on a wafer substrate are disclosed. In one aspect, a protective layer is deposited over a surface of a wafer substrate using a process configured to produce substantially less damage in the wafer substrate than a first plasma-assisted deposition process. The protective layer is less than about 100 Angstroms thick. A barrier layer is deposited over the protective layer using the first plasma-assisted deposition process. | 2012-04-05 |
| 20120083135 | ASYMMETRIC RAPID THERMAL ANNEALING TO REDUCE PATTERN EFFECT - Rapid thermal annealing methods and systems for annealing patterned substrates with minimal pattern effect on substrate temperature non-uniformity are provided. The rapid thermal annealing system includes a front-side heating source and a backside heating source. The backside heating source of the rapid thermal annealing system supplies a dominant amount of heat to bring the substrate temperature to the peak annealing temperature. The front-side heating source contributes to heat up the environment near the front-side of the substrate to a temperature lower than about 100° C. to about 200° C. less than the peak annealing temperature. The asymmetric front-side and backside heating for rapid thermal annealing reduce or eliminate pattern effect and improve WIW and WID device performance uniformity. | 2012-04-05 |
| 20120083136 | METHOD AND SYSTEM FOR MODIFYING PATTERNED PHOTORESIST USING MULTI-STEP ION IMPLANTATION - A method of reducing the roughness profile in a plurality of patterned resist features. Each patterned resist feature includes a first sidewall and a second sidewall opposite the first sidewall, wherein each patterned resist feature comprises a mid frequency line width roughness and a low frequency linewidth roughness. A plurality of ion exposure cycles are performed, wherein each ion exposure cycle comprises providing ions at a tilt angle of about five degrees or larger upon the first sidewall, and providing ions at a tilt angle of about five degrees or larger upon the second sidewall. Upon the performing of the plurality of ion exposure cycles the mid frequency and low frequency linewidth roughness are reduced. | 2012-04-05 |
| 20120083137 | MAGNETIC CONNECTOR FOR ELECTRONIC DEVICE - An electrical plug and receptacle relying on magnetic force from an electromagnet to maintain contact are disclosed. The plug and receptacle can be used as part of a power adapter for connecting an electronic device, such as a laptop computer, to a power supply. The plug includes electrical contacts, which are preferably biased toward corresponding contacts on the receptacle. The plug and receptacle each have a magnetic element. The magnetic element on one of the plug or receptacle can be a magnet or ferromagnetic material. The magnetic element on the other of the plug or receptacle is an electromagnet. When the plug and receptacle are brought into proximity, the magnetic attraction between the electromagnet magnet and its complement, whether another magnet or a ferromagnetic material, maintains the contacts in an electrically conductive relationship. | 2012-04-05 |
| 20120083138 | Electronic Device - An electronic device is provided. The electronic device includes a substrate and a joint. The substrate includes a first surface and a second surface, wherein a substrate signal contact, two ground contacts and two positioning openings are formed on the substrate, and the positioning openings are respectively formed on the ground contact and pass through the substrate. The joint includes a connection port, a joint signal contact and two ground structure, wherein the connection port is electrically connected to the joint signal contact, the joint signal contact is connected to the substrate signal contact, and the joint signal contact is located between the two ground structures, and the ground structures are respectively inserted into the positioning openings to be electrically connected to the ground contacts. | 2012-04-05 |
