14th week of 2014 patent applcation highlights part 57 |
Patent application number | Title | Published |
20140095748 | RECONFIGURABLE HARDWARE STRUCTURES FOR FUNCTIONAL PIPELINING OF ON-CHIP SPECIAL PURPOSE FUNCTIONS - A method and apparatus for reconfiguring hardware structures to pipeline the execution of multiple special purpose hardware implemented functions, without saving intermediate results to memory, is provided. Pipelining functions in a program is typically performed by a first function saving its results (the “intermediate results”) to memory, and a second function subsequently accessing the memory to use the intermediate results as input. Saving and accessing intermediate results stored in memory incurs a heavy performance penalty, requires more power, consumes more memory bandwidth, and increases the memory footprint. Due to the ability to redirect the input and output of the hardware structures, intermediate results are passed directly from one special purpose hardware implemented function to another without storing the intermediate results in memory. Consequently, a program that utilizes the method or apparatus, reduces power consumption, consumes less memory bandwidth, and reduces the program's memory footprint. | 2014-04-03 |
20140095749 | METHOD FOR ADDRESSING THE PARTICIPANTS OF A BUS SYSTEM - A robust method for addressing each of the participants of a bus system comprising a control unit, and a bus and a plurality of addressable participants connected to the bus, comprising the steps of a) pre-selecting a first number of participants, b) selecting from the pre-selected participants a second number of participants, and c) assigning one or more addresses to them, and repeating the steps a) to c). The selection and pre-selection is based on current sources, specific threshold values, and measurement error. The bus system and addressable device (are also claimed. | 2014-04-03 |
20140095750 | Method for Managing the Operation of a Circuit Connected to a Two-Wire Bus - A method is provided for managing the operation of a circuit operating in a slave mode. The circuit is connected to a bus having at least two of wires and a priority logic level. The slave circuit imposes the priority logic level on a first wire of the bus. While imposing, the slave circuit detects a possible conflict on the first wire resulting from a forcing, external to the slave circuit, of the first wire to another logic level. Upon detecting a conflict, the slave circuit is placed in a state stopping the sending by the circuit of any data over the bus while leaving the circuit listening to the bus. | 2014-04-03 |
20140095751 | FAST DESKEW WHEN EXITING LOW-POWER PARTIAL-WIDTH HIGH SPEED LINK STATE - Methods and apparatus relating to fast deskew when exiting a low-power partial-width high speed link state are described. In one embodiment, an exit flit on active lanes and/or a wake signal/sequence on idle lanes may be transmitted at a first point in time to cause one or more idle lanes of a link to enter an active state. At a second point in time (following or otherwise subsequent to the first point in time), training sequences are transmitted over the one or more idle lanes of the link. And, the one or more idle lanes are deskewed in response to the training sequences and prior to a third point in time (following or otherwise subsequent to the second point in time). Other embodiments are also disclosed and claimed. | 2014-04-03 |
20140095752 | INTERRUPT SUPPRESSION STRATEGY - The disclosed embodiments provide a system that suppresses interrupts to facilitate efficient use of a processor in a computer system. The system includes a node that transmits a first interrupt to the processor upon receiving a first packet for processing at the processor and disables subsequent interrupts to the processor during an interrupt-suppression state in the processor. The system also includes the processor, which processes the first packet upon receiving the first interrupt and transmits a first acknowledgment of the first packet to the node to enable the interrupt-suppression state. | 2014-04-03 |
20140095753 | Network interface controller with direct connection to host memory - A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration. | 2014-04-03 |
20140095754 | Back-Off Retry with Priority Routing - A method for back-off retry with priority routing includes routing a data transfer between an input of a single, cohesive SAS expander and an output of the SAS expander via at least one inter-expander link (IEL), the expander including a first SAS expander and at least one additional SAS expander. The method includes routing a first OPEN request on a direct path through the first SAS expander to a port of a device and routing a second OPEN request on an alternate path from the first SAS expander and through a second SAS expander to the port of the device. The method further includes, upon determination of a failed link or a busy link, re-routing the data transfer from the second SAS expander to the first SAS expander or a third SAS expander, or retrying the data transfer through the second SAS expander. | 2014-04-03 |
20140095755 | USING ADAPTIVE CHANNEL SELECTION TO ENHANCE THE PERFORMANCE OF WIRELESS DOCKING - An Adaptive Channel Selection (ACS) system is disclosed. A computing device uses wireless docking to provide a separate monitor and full-size input devices. The computing device requests docking, receives data wirelessly from the full-size input devices, and provides compressed video display data wirelessly for display on the separate monitor. An adaptive docking adapter receives and decodes compressed video display data and provides the decoded compressed video display data to a separate monitor for display. A wireless connection is disposed between the computing device and the adaptive docking adapter to provide wireless transmission of signals between the computing device and the adaptive docking adapter. | 2014-04-03 |
20140095756 | HIGH-SPEED DATA TRANSMISSION INTERFACE CIRCUIT AND DESIGN METHOD OF THE SAME - A high-speed data transmission interface circuit used in a network switch device is provided. The high-speed data transmission interface circuit comprises a main circuit hoard, a connector and a daughter circuit board. The main circuit board comprises a transmission port interface module and a first wire. The transmission port interface module comprises a reduced pin extended attachment unit interface (RXAUI). The first wire connects the connector and the main circuit board. The daughter circuit board comprises a high definition multimedia interface (HDMI) module and a second wire. The HDMI module is connected to an external network device through a HDMI signal wire. The second wire connects the connector and the HDMI module. The transmission port interface module communicates with the external network device through the connector and the daughter board. | 2014-04-03 |
20140095757 | MICROCONTROLLER PROGRAMMABLE SYSTEM ON A CHIP WITH PROGRAMMABLE INTERCONNECT - Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks. | 2014-04-03 |
20140095758 | STORAGE ARCHITECTURE FOR SERVER FLASH AND STORAGE ARRAY OPERATION - A storage architecture of a storage system environment has a storage connector interface configured to exchange data directly between flash storage devices on a server and a storage array of the environment so as to bypass main memory and a system bus of the server. According to one or more embodiments, the storage connnector interface includes control logic configured to implement the data exchange in accordance with one of a plurality of operational modes that deploy and synchronize the data on the flash storage devices and the storage array. Advantageously, the storage connector interface obviates latencies and bandwidth consumption associated with prior data exchanges over the main memory and bus, thereby enhancing storage architecture performance. | 2014-04-03 |
20140095759 | REPLICATED STATELESS COPY ENGINE - Techniques are disclosed for performing an auxiliary operation via a compute engine associated with a host computing device. The method includes determining that the auxiliary operation is directed to the compute engine, and determining that the auxiliary operation is associated with a first context comprising a first set of state parameters. The method further includes determining a first subset of state parameters related to the auxiliary operation based on the first set of state parameters. The method further includes transmitting the first subset of state parameters to the compute engine, and transmitting the auxiliary operation to the compute engine. One advantage of the disclosed technique is that surface area and power consumption are reduced within the processor by utilizing copy engines that have no context switching capability. | 2014-04-03 |
20140095760 | Generic and multi-role controller structure for data and communication exchanges - This generic and multi-role data and communication exchange controller structure is characterized in that it assumes the form of a single component further including means forming a generic data and communication exchange controller, associated with at least a means forming a data storage/exchange buffer; a means forming multiple connection interfaces to several data production/consumption units, one connection interface being associated with one data production/consumption unit; and a means forming multiple connection interfaces with several external data communication buses, one connection interface being associated with one external data communication bus. | 2014-04-03 |
20140095761 | REPRODUCTION DEVICE AND REPRODUCTION SYSTEM - A reproduction device includes a reproduction unit, communication paths, and a communication-path control unit. The reproduction unit is configured to be able to alternatively reproduce content items supplied from sources. The communication paths respectively correspond to the sources. The reproduction unit is connected to the sources via the respective communication paths. The communication-path control unit invalidates, when receiving an instruction to switch to the source having content to be reproduced by the reproduction unit, communication via the communication path corresponding to the source before the switching among the communication paths. | 2014-04-03 |
20140095762 | FUZZY COUNTERS FOR NVS TO REDUCE LOCK CONTENTION - A system for data management in a computing storage environment includes a processor device, operable in the computing storage environment, that divides a plurality of counters tracking write and discard storage operations through Non Volatile Storage (NVS) space into first, accurate, and second, fuzzy, groups where the first, accurate, group is one of incremented and decremented per each write and discard storage operation, while the second, fuzzy, group is one of incremented and decremented on a more infrequent basis as compared to the first, accurate group. | 2014-04-03 |
20140095763 | NVS THRESHOLDING FOR EFFICIENT DATA MANAGEMENT - For data management by a processor device in a computing storage environment, a threshold for an amount of Non Volatile Storage (NVS) space to be consumed by any particular logically contiguous storage space in the computing storage environment is established based on at least one of a Redundant Array of Independent Disks (RAID) type, a number of point-in-time copy source data segments in the logically contiguous storage space, and a storage classification. | 2014-04-03 |
20140095764 | MICROCONTROLLER WITH INTEGRATED INTERFACE ENABLING READING DATA RANDOMLY FROM SERIAL FLASH MEMORY - A microcontroller includes a microprocessor, a serial flash memory interface, and input/output (I/O) terminals for coupling the serial flash memory interface to external serial flash memory. The microprocessor is operable to generate instruction frames that trigger respective commands to read data from specified addresses in the external serial flash memory. The serial flash memory interface receives and processes the instruction frames, obtains the data contained in the specified addresses in the external serial flash memory regardless of whether the specified addresses are sequential or non-sequential, and provides the data for use by the microprocessor. | 2014-04-03 |
20140095765 | FLASH TRANSLATION LAYER (FTL) DATABASE JOURNALING SCHEMES - A method includes, in a storage device that includes a non-volatile memory and a volatile memory, maintaining at least one data structure that stores management information used for managing data storage in the non-volatile memory, such that at least a portion of the data structure is stored in the volatile memory. A sequence of journaling chunks is created during operation of the storage device, each journaling chunk including a respective slice of the data structure and one or more changes that occurred in the data structure since a previous journaling chunk in the sequence. The sequence of the journaling chunks is stored in the non-volatile memory. Upon recovering from an electrical power interruption in the storage device, the data structure is reconstructed using the stored journaling chunks. | 2014-04-03 |
20140095766 | PERSISTENT LOG OPERATIONS FOR NON-VOLATILE MEMORY - In an embodiment, a first delayed persistence operation to store information in a log contained in a non-volatile memory (NVM) may be performed. The information may include, for example, a current value of a variable contained in the NVM. A second delayed persistence operation to store information in the variable may be performed. A third delayed persistence operation to store information in the NVM that indicates the log is cleared may be performed. A flush operation may be performed, for example after the first, second, and third delayed persistence operations. The flush operation may commit information associated with at least one of the first, second, or third delayed persistence operations to the NVM. | 2014-04-03 |
20140095767 | STORAGE DEVICE TRIMMING - In an embodiment, a command that specifies a logical block to trim in a storage device is acquired. An entry in a logical-to-physical address (L2P) table that contains a physical address that corresponds to the logical block may be set to point to an invalid address. A trim token that specifies the logical block may be generated. The trim token may be stored in a non-volatile storage contained in the storage device. | 2014-04-03 |
20140095768 | ENCODING DATA FOR STORAGE IN A DATA STORAGE DEVICE - A data storage device includes a memory and a controller. A method performed in the data storage device includes performing a first transformation of a unit of data to generate a first transformed unit of data. Performing the first transformation includes sorting permutations of the unit of data. The method includes performing a move-to-front transformation of the first transformed unit of data to generate a second transformed unit of data. The method includes performing a weight-based encoding of the second transformed unit of data to generate an encoded unit of data. The encoded unit of data has a same number of bits as the unit of data. | 2014-04-03 |
20140095769 | FLASH MEMORY DUAL IN-LINE MEMORY MODULE MANAGEMENT - Systems and methods to manage memory on a dual in-line memory module (DIMM) are provided. A particular method may include receiving at a flash application-specific integrated circuit (ASIC) a request from a processor to access data stored in a flash memory of a DIMM. The data may be transferred from the flash memory to a switch of the DIMM. The data may be routed to a dynamic random-access memory (DRAM) of the DIMM. The data may be stored in the DRAM and may be provided from the DRAM to the processor. | 2014-04-03 |
20140095770 | Selective Protection of Lower Page Data During Upper Page Write - Lower page data that may be endangered by programming upper page data in the same memory cells is protected during upper programming using protective upper page programming schemes. High overall programming speeds are maintained by selectively using protective upper programming schemes only where endangered data is committed and may not be recoverable from another location. | 2014-04-03 |
20140095771 | HOST DEVICE, COMPUTING SYSTEM AND METHOD FOR FLUSHING A CACHE - A computing system includes a storage device, and a host device configured to flush a plurality of pages to the storage device. The host device includes a write-back (WB) cache configured to store the pages, and a file system module configured to flush pages having first characteristics to the storage device from among the pages stored in the WB cache, and then flush pages having second characteristics which are different from the first characteristics to the storage device from among the pages stored in the WB cache. | 2014-04-03 |
20140095772 | COMPUTING SYSTEM AND METHOD OF MANAGING DATA IN THE COMPUTING SYSTEM - A computing system a storage device and a file system. The storage device includes a storage area having flash memory. The file system is configured to divide the storage area into multiple zones, multiple sections and multiple blocks, and to write a log in each block. The file system includes a block allocation module. The block allocation module is configured to allocate a target block, in which a log is to be written, by a continuous block allocation method according to which a block having a continuous address with a most recently selected block is set as the target block. The block allocation module is further configured to find a free section from the multiple sections when it is not possible to allocate the target block by the continuous block allocation method, and to set a block in the found free section as the target block. | 2014-04-03 |
20140095773 | SOLID STATE MEMORY DEVICE LOGICAL AND PHYSICAL PARTITIONING - Embodiments relate to solid state memory device including a storage array having a plurality of physical storage devices and the storage array includes a plurality of partitions. The solid state memory device also includes a controller comprising a plurality of mapping tables, wherein each of the plurality of mapping tables corresponds to one of the plurality of partitions. Each of the plurality of mapping tables is configured to store a physical location and a logical location of data stored in its corresponding partition. | 2014-04-03 |
20140095774 | CODE PATCHING FOR NON-VOLATILE MEMORY - Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored in a trap address register. | 2014-04-03 |
20140095775 | SYSTEMS AND METHODS FOR CACHE ENDURANCE - A cache and/or storage module may be configured to reduce write amplification in a cache storage. Cache layer write amplification (CLWA) may occur due to an over-permissive admission policy. The cache module may be configured to reduce CLWA by configuring admission policies to avoid unnecessary writes. Admission policies may be predicated on access and/or sequentiality metrics. Flash layer write amplification (FLWA) may arise due to the write-once properties of the storage medium. FLWA may be reduced by delegating cache eviction functionality to the underlying storage layer. The cache and storage layers may be configured to communicate coordination information, which may be leveraged to improve the performance of cache and/or storage operations. | 2014-04-03 |
20140095776 | STORAGE SYSTEM INCLUDING A PLURALITY OF FLASH MEMORY DEVICES - A storage system including a storage device which includes media for storing data from a host computer, a medium controller for controlling the media, a plurality of channel controllers for connecting to the host computer through a channel and a cache memory for temporarily storing data from the host computer, wherein the media have a restriction on a number of writing times. The storage device includes a bus for directly transferring data from the medium controller to the channel controller. | 2014-04-03 |
20140095777 | SYSTEM CACHE WITH FINE GRAIN POWER MANAGEMENT - Methods and apparatuses for reducing leakage power in a system cache within a memory controller. The system cache is divided into multiple small sections, and each section is supplied with power from a separately controllable power supply. When a section is not being accessed, the voltage supplied to the section is reduced to a voltage sufficient for retention of data but not for access. Incoming requests are grouped together based on which section of the system cache they target. When enough requests that target a given section have accumulated, the voltage supplied to the given section is increased to a voltage sufficient for access. Then, once the given section has enough time to ramp-up and stabilize at the higher voltage, the waiting requests may access the given section in a burst of operations. | 2014-04-03 |
20140095778 | METHODS, SYSTEMS AND APPARATUS TO CACHE CODE IN NON-VOLATILE MEMORY - Methods and apparatus are disclosed to cache code in non-volatile memory. A disclosed example method includes identifying an instance of a code request for first code, identifying whether the first code is stored on non-volatile (NV) random access memory (RAM) cache, and when the first code is absent from the NV RAM cache, adding the first code to the NV RAM cache when a first condition associated with the first code is met and preventing storage of the first code to the NV RAM cache when the first condition is not met. | 2014-04-03 |
20140095779 | PROCESSING MEMORY ACCESS INSTRUCTIONS THAT HAVE DUPLICATE MEMORY INDICES - A method of an aspect includes receiving an instruction indicating a first source packed memory indices, a second source packed data operation mask, and a destination storage location. Memory indices of the packed memory indices are compared with one another. One or more sets of duplicate memory indices are identified. Data corresponding to each set of duplicate memory indices is loaded only once. The loaded data corresponding to each set of duplicate memory indices is replicated for each of the duplicate memory indices in the set. A packed data result in the destination storage location in response to the instruction. The packed data result includes data elements from memory locations that are indicated by corresponding memory indices of the packed memory indices when not blocked by corresponding elements of the packed data operation mask. | 2014-04-03 |
20140095780 | DISTRIBUTED ROW HAMMER TRACKING - A memory controller issues a targeted refresh command in response to detection by a distributed detector. A memory device includes detection logic that monitors for a row hammer event, which is a threshold number of accesses to a row within a time threshold that can cause data corruption to a physically adjacent row (a “victim” row). The memory device sends an indication of the row hammer event to the memory controller. In response to the row hammer event indication, the memory controller sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row. | 2014-04-03 |
20140095781 | PHASE CHANGE MEMORY IN A DUAL INLINE MEMORY MODULE - Subject matter disclosed herein relates to management of a memory device. | 2014-04-03 |
20140095782 | METHOD AND SYSTEM FOR USING RANGE BITMAPS IN TCAM ACCESS - Various exemplary embodiments relate to a method and related network node including one or more of the following: determining that a first search value is associated with a first range field; determining a first bitmap associated with the first search value, wherein the first bitmap indicates at least one range encompassing the first search value; generating a search key based on the first bitmap; and accessing the ternary content addressable memory based on the search key. | 2014-04-03 |
20140095783 | PHYSICAL AND LOGICAL COUNTERS - Techniques for reducing a number of physical counters are provided. Logical counters may be associated with physical counters. The number of logical counters may be less than the number of physical counters. It may be determined if an association of a logical counter to a physical counter exists already. If not, a new association may be created. The physical counter associated with the logical counter may then be updated. | 2014-04-03 |
20140095784 | Techniques for Utilizing Transaction Lookaside Buffer Entry Numbers to Improve Processor Performance - A technique for operating a processor includes translating, using an associated transaction lookaside buffer, a first virtual address into a first physical address through a first entry number in the transaction lookaside buffer. The technique also includes translating, using the transaction lookaside buffer, a second virtual address into a second physical address through a second entry number in the translation lookaside buffer. The technique further includes, in response to the first entry number being the same as the second entry number, determining that the first and second virtual addresses point to the same physical address in memory and reference the same data. | 2014-04-03 |
20140095785 | Content Aware Block Power Savings - A memory architecture power savings system includes a first memory module configured to provide data corresponding to a stored address from among a plurality of stored addresses by comparing the plurality of stored addresses to a search key in response to a control signal. A second memory module is configured to store a plurality of data entries corresponding to truncated portions of the plurality of stored addresses, and to generate the control signal by comparing the plurality of data entries to a truncated portion of the search key. | 2014-04-03 |
20140095786 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device includes a first stage register for storing events occurring for a first period, a second stage register for storing events occurring for a second period shorter than the first period and a controller for controlling the second stage register to select events from the second stage register each having a reference value larger than a second threshold value to the first stage register and for controlling the first stage register to store events which are selected from the second stage register. | 2014-04-03 |
20140095787 | NVS THRESHOLDING FOR EFFICIENT DATA MANAGEMENT - For data management by a processor device in a computing storage environment, a threshold for an amount of Non Volatile Storage (NVS) space to be consumed by any particular logically contiguous storage space in the computing storage environment is established based on at least one of a Redundant Array of Independent Disks (RAID) type, a number of point-in-time copy source data segments in the logically contiguous storage space, and a storage classification. | 2014-04-03 |
20140095788 | METHOD FOR VIRTUALIZING RAID OF COMPUTER SYSTEM - A method for virtualizing a redundant array of independent disks (RAID) of a computer system is provided. The computer system includes a plurality of storage devices and a central processing unit (CPU). The method includes following steps: establishing a storage device interface via the CPU after the computer system is powered on and a power-on self-test (POST) is executed, wherein the storage device interface integrates the storage devices into at least one RAID according to an array configuration; accessing the storage devices by the CPU via the storage device interface after the RAID is established; determining an access mode of the storage devices by the CPU according to a level of the RAID when the CPU receives an access instruction; and establishing a user interface by the CPU according to a system program of the RAID. | 2014-04-03 |
20140095789 | MANAGEMENT OF DATA USING INHERITABLE ATTRIBUTES - Embodiments relate to a system and computer program product for data management. An aspect includes a method for assigning storage types to data based on access frequency. Past or historical data associated with current data usage is also considered prior to assignment. Once data frequency access is determined, the current data is assigned to a first tier of a plurality of hierarchical ordered tiers, each tier corresponding to at least one class of storage. In one embodiment, there may be a condition that overrides the assignment with option to override it. The tier assignment may also be preserved so that the current data can be appropriately assigned in the future. | 2014-04-03 |
20140095790 | MANAGEMENT OF DATA USING INHERITABLE ATTRIBUTES - Embodiments relate to a method for data management. An aspect includes a method for assigning storage types to data based on access frequency. Past or historical data associated with current data usage is also considered prior to assignment. Once data frequency access is determined, the current data is assigned to a first tier of a plurality of hierarchical ordered tiers, each tier corresponding to at least one class of storage. In one embodiment, there may be a condition that overrides the assignment with option to override it. The tier assignment may also be preserved the tier so that the current data can be appropriately assigned in the future. | 2014-04-03 |
20140095791 | PERFORMANCE-DRIVEN CACHE LINE MEMORY ACCESS - According to one aspect of the present disclosure a system and technique for performance-driven cache line memory access is disclosed. The system includes: a processor, a cache hierarchy coupled to the processor, and a memory coupled to the cache hierarchy. The system also includes logic executable to, responsive to receiving a request for a cache line: divide the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; service the high priority data request; and delay servicing of the low priority data request until a low priority condition has been satisfied. | 2014-04-03 |
20140095792 | CACHE CONTROL DEVICE AND PIPELINE CONTROL METHOD - A cache control device includes an entering unit, a first searching unit, a reading unit, a second searching unit, and a rewriting unit. The entering unit alternately enters, into a pipeline, a load request for reading a directory received from a processor and a store request for rewriting a directory received from the processor. When the first searching unit determines that the directory targeted by the load request is present in the first cache memory or the second cache memory, the reading unit reads the directory from the cache memory in which the directory is present. When the second searching unit determines that the directory targeted by the store request is present in the first cache memory, the rewriting unit rewrites the directory that is stored in the first cache memory. | 2014-04-03 |
20140095793 | STORAGE SYSTEM - An object of the present invention is to provide a storage system which is shared by a plurality of application programs, wherein optimum performance tuning for a cache memory can be performed for each of the individual application programs. The storage system of the present invention comprises a storage device which provides a plurality of logical volumes which can be accessed from a plurality of application programs, a controller for controlling input and output of data to and from the logical volumes in response to input/output requests from the plurality of application programs, and a cache memory for temporarily storing data input to and output from the logical volume, wherein the cache memory is logically divided into a plurality of partitions which are exclusively assigned to the plurality of logical volumes respectively. | 2014-04-03 |
20140095794 | Apparatus and Method For Reducing The Flushing Time Of A Cache - A processor is described having cache circuitry and logic circuitry. The logic circuitry is to manage the entry and removal of cache lines from the cache circuitry. The logic circuitry includes storage circuitry and control circuitry. The storage circuitry is to store information identifying a set of cache lines within the cache that are in a modified state. The control circuitry is coupled to the storage circuitry to receive the information from the storage circuitry, responsive to a signal to flush the cache, and determine addresses of the cache therefrom so that the set of cache lines are read from the cache so as to avoid reading cache lines from the cache that are in an invalid or a clean state. | 2014-04-03 |
20140095795 | REDUCING PENALTIES FOR CACHE ACCESSING OPERATIONS - A computer program product for reducing penalties for cache accessing operations is provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes respectively associating platform registers with cache arrays, loading control information and data of a store operation to be executed with respect to one or more of the cache arrays into the one or more of the platform registers respectively associated with the one or more of the cache arrays, and, based on the one or more of the cache arrays becoming available, committing the data from the one or more of the platform registers using the control information from the same platform registers to the one or more of the cache arrays. | 2014-04-03 |
20140095796 | PERFORMANCE-DRIVEN CACHE LINE MEMORY ACCESS - According to one aspect of the present disclosure, a method and technique for performance-driven cache line memory access is disclosed. The method includes: receiving, by a memory controller of a data processing system, a request for a cache line; dividing the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; servicing the high priority data request; and delaying servicing of the low priority data request until a low priority condition has been satisfied. | 2014-04-03 |
20140095797 | Cache Memory Having Enhanced Performance And Security Features - Methods for accessing, storing and replacing data in a cache memory are provided, wherein a plurality of index bits and a plurality of tag bits at the cache memory are received. The plurality of index bits are processed to determine whether a matching index exists in the cache memory and the plurality of tag bits are processed to determine whether a matching tag exists in the cache memory, and a data line is retrieved from the cache memory if both a matching tag and a matching index exist in the cache memory. A random line in the cache memory can be replaced with a data line from a main memory, or evicted without replacement, based on the combination of index and tag misses, security contexts and protection bits. User-defined and/or vendor-defined replacement procedures can be utilized to replace data lines in the cache memory. | 2014-04-03 |
20140095798 | Protecting Data During Different Connectivity States - Aspects of the subject matter described herein relate to data protection. In aspects, during a backup cycle, backup copies may be created for files that are new or that have changed since the last backup. If external backup storage is not available, the backup copies may be stored in a cache located on the primary storage. If backup storage is available, the backup copies may be stored in the backup storage device and backup copies that were previously stored in the primary storage may be copied to the backup storage. The availability of the backup storage may be detected and used to seamlessly switch between backing up files locally and remotely as availability of the backup storage changes. | 2014-04-03 |
20140095799 | DIFFERENTIATING CACHE RELIABILITY TO REDUCE MINIMUM ON-DIE VOLTAGE - Systems and methods may provide for determining whether a memory access request is error-tolerant, and routing the memory access request to a reliable memory region if the memory access request is error-tolerant. Moreover, the memory access request may be routed to an unreliable memory region if the memory access request is error-tolerant. In one example, use of the unreliable memory region enables a reduction in the minimum operating voltage level for a die containing the reliable and unreliable memory regions. | 2014-04-03 |
20140095800 | SYSTEM CACHE WITH STICKY REMOVAL ENGINE - Methods and apparatuses for releasing the sticky state of cache lines for one or more group IDs. A sticky removal engine walks through the tag memory of a system cache looking for matches with a first group ID which is clearing its cache lines from the system cache. The engine clears the sticky state of each cache line belonging to the first group ID. If the engine receives a release request for a second group ID, the engine records the current index to log its progress through the tag memory. Then, the engine continues its walk through the tag memory looking for matches with either the first or second group ID. The engine wraps around to the start of the tag memory and continues its walk until reaching the recorded index for the second group ID. | 2014-04-03 |
20140095801 | SYSTEM AND METHOD FOR RETAINING COHERENT CACHE CONTENTS DURING DEEP POWER-DOWN OPERATIONS - A system, method, and computer program product for retaining coherent cache contents during deep power-down operations, and reducing the low-power state entry and exit overhead to improve processor energy efficiency and performance. The embodiments flush or clean the Modified-state lines from the cache before entering a deep low-power state, and then implement a deferred snoop strategy while in the powered-down state. Upon existing the powered-down state, the embodiments process the deferred snoops. A small additional cache and a snoop filter (or other cache-tracking structure) may be used along with additional logic to retain cache contents coherently through deep power-down operations, which may span multiple low-power states. | 2014-04-03 |
20140095802 | Caching Large Objects In A Computer System With Mixed Data Warehousing And Online Transaction Processing Workload - Techniques are provided for managing cached data objects in a mixed workload environment. In an embodiment, a database system receives request to access a target data object. The database system determines whether the request to access the target data object is associated with a first type of workload or a second type of workload. In response to determining that the request is associated with the first type of workload, the target data object replaces a least recently used data object in a cache. In response to determining that the request is associated with the second type of workload, the target data object is cached based on an associated access-level value. | 2014-04-03 |
20140095803 | MEMORY SYSTEM CONFIGURED TO PERFORM SEGMENT CLEANING AND RELATED METHOD OF OPERATION - A host configured to interact with a storage device comprises a write-back (WB) cache configured to write data to the storage device, a cache managing module configured to manage the WB cache, and a file system module configured to determine whether live blocks in victim segments among a plurality of segments stored in the storage device are stored in the WB cache, to read the live blocks from the storage device as a consequence of determining that the live blocks are not stored in the WB cache, to load the read live blocks to the WB cache, and to request the cache managing module to set dirty flags for the stored live blocks. | 2014-04-03 |
20140095804 | Efficient Cache Validation and Content Retrieval in a Content Delivery Network - Some embodiments provide systems and methods for validating cached content based on changes in the content instead of an expiration interval. One method involves caching content and a first checksum in response to a first request for that content. The caching produces a cached instance of the content representative of a form of the content at the time of caching. The first checksum identifies the cached instance. In response to receiving a second request for the content, the method submits a request for a second checksum representing a current instance of the content and a request for the current instance. Upon receiving the second checksum, the method serves the cached instance of the content when the first checksum matches the second checksum and serves the current instance of the content upon completion of the transfer of the current instance when the first checksum does not match the second checksum. | 2014-04-03 |
20140095805 | REMOTE-KEY BASED MEMORY BUFFER ACCESS CONTROL MECHANISM - A system and method implementing revocable secure remote keys is disclosed. A plurality of indexed base secrets is stored in a register of a coprocessor of a local node coupled with a local memory. When it is determined that a selected base secret expired, the base secret stored in the register based on the base secret index is changed, thereby invalidating remote keys generated based on the expired base secret. A remote key with validation data and a base secret index is received from a node requesting access to the local memory. A validation base secret is obtained from the register based on the base secret index. The coprocessor performs hardware validation on the validation data based on the validation base secret. Hardware validation fails if the base secret associated with the base secret index has been changed in the register of the selected coprocessor. | 2014-04-03 |
20140095806 | CONFIGURABLE SNOOP FILTER ARCHITECTURE - Configurable snoop filters. A memory system is coupled with one or more processing cores. A coherent system fabric couples the memory system with the one or more processing cores. The coherent system fabric comprising at least a configurable snoop filter that is configured based on workload. The configurable snoop filter having a configurable snoop filter directory and a bloom filter. The configurable snoop filter and the bloom filter include runtime configuration parameters that are used to selectively limit snoop traffic. | 2014-04-03 |
20140095807 | ADAPTIVE TUNING OF SNOOPS - A coherency controller, such as one used within a system-on-chip, is capable of issuing different types of snoops to coherent caches. The coherency controller chooses the type of snoop based on the type of request that caused the snoops or the state of the system or both. By so doing, coherent caches provide data when they have sufficient throughput, and are not required to provide data when they do not have insufficient throughput. | 2014-04-03 |
20140095808 | ADAPTIVE TUNING OF SNOOPS - A coherency controller, such as one used within a system-on-chip, is capable of issuing different types of snoops to coherent caches. The coherency controller chooses the type of snoop based on the type of request that caused the snoops or the state of the system or both. By so doing, coherent caches provide data when they have sufficient throughput, and are not required to provide data when they do not have insufficient throughput. | 2014-04-03 |
20140095809 | COHERENCY CONTROLLER WITH REDUCED DATA BUFFER - A coherency controller with a data buffer store that is smaller than the volume of pending read data requests. Data buffers are allocated only for requests that match the ID of another pending request. Buffers are deallocated if all snoops receive responses, none of which contain data. Buffers containing clean data have their data discarded and are reallocated to later requests. The discarded data is later read from the target. When all buffers are full of dirty data requests with a pending order ID are shunted into request queues for later service. Dirty data may be foisted onto coherent agents to make buffers available for reallocation. Accordingly, the coherency controller can issue snoops and target requests for a volume of data that exceeds the number of buffers in the data store. | 2014-04-03 |
20140095810 | MEMORY SHARING ACROSS DISTRIBUTED NODES - A method and apparatus are disclosed for enabling nodes in a distributed system to share one or more memory portions. A home node makes a portion of its main memory available for sharing, and one or more sharer nodes mirrors that shared portion of the home node's main memory in its own main memory. To maintain memory coherency, a memory coherence protocol is implemented. Under this protocol, load and store instructions that target the mirrored memory portion of a sharer node are trapped, and store instructions that target the shared memory portion of a home node are trapped. With this protocol, valid data is obtained from the home node and updates are propagated to the home node. Thus, no “dirty” data is transferred between sharer nodes. As a result, the failure of one node will not cause the failure of another node or the failure of the entire system. | 2014-04-03 |
20140095811 | FUZZY COUNTERS FOR NVS TO REDUCE LOCK CONTENTION - A system for data management in a computing storage environment includes a processor device, operable in the computing storage environment, that divides a plurality of counters tracking write and discard storage operations through Non Volatile Storage (NVS) space into first, accurate, and second, fuzzy, groups where the first, accurate, group is one of incremented and decremented per each write and discard storage operation, while the second, fuzzy, group is one of incremented and decremented on a more infrequent basis as compared to the first, accurate group. | 2014-04-03 |
20140095812 | OBFUSCATING FUNCTION RESOURCES WHILE REDUCING STACK CONSUMPTION - In one embodiment, a system wide static global stack pool in a contiguous range of random access memory is generated, a block of memory in the system global pool is assigned to a thread of a running process, and the thread stores local variable information in static global stack pool, such that the local variable is hidden from a stack frame back-trace. In one embodiment, a dynamically allocated data structure in system heap memory is generated, the data structure is locked to ensure atomic access, a block of memory in the data structure is assigned to a thread of a process, the data structure is unlocked, and the thread stores local variable information in static global stack pool, such that the local variable is hidden from a stack frame back-trace. | 2014-04-03 |
20140095813 | CONFIGURABLE AND TUNABLE DATA STORE TRADEOFFS - A data store is configurable in terms of various tradeoffs including consistency and availability, among others. Consistency can be specified in terms of one of a myriad of configuration levels. Availability can be specified with respect to a maximum and minimum number of replicas or failure tolerance. In operation, one or more of write or read quorums can be automatically adjusted to ensure satisfaction of a specified configuration level in light of changes in the number of replicas. | 2014-04-03 |
20140095814 | Memory Renaming Mechanism in Microarchitecture - A processor includes a processing unit including a storage module having stored thereon a table for tracking physical registers in which each store operation stores source data and a memory renaming module for register renaming load operations based on the table. | 2014-04-03 |
20140095815 | MEDIA LIBRARY MONITORING SYSTEM AND METHOD - Embodiments of methods and systems comprise collecting data associated with a library or library components and storing the collected data in repository. By collecting data associated with a library or library components and storing the collected data in a repository, the degradation of library components can be monitored and the reliability of library components determined, allowing unreliable components to be bypassed or replaced, enhancing the reliability of the library and preventing data loss. | 2014-04-03 |
20140095816 | SYSTEM AND METHOD FOR FULL VIRTUAL MACHINE BACKUP USING STORAGE SYSTEM FUNCTIONALITY - Techniques for virtual machine full backup are described herein. According to one embodiment, in response to a request to back up a virtual machine (VM) of a client, a request of VM backup is sent out. A consistent state of the VM is then identified via a VM application program interface (VM API). Subsequently a request is sent to a storage system associated with the client to ask for VM disk image associated with the consistent state of the VM to a target backup storage system. | 2014-04-03 |
20140095817 | SYSTEM AND METHOD FOR INCREMENTAL VIRTUAL MACHINE BACKUP USING STORAGE SYSTEM FUNCTIONALITY - Techniques for virtual machine incremental backup are described herein. According to one embodiment, a request for an incremental backing up a virtual machine (VM) is received at a storage system, the request identifying a requested VM disk image associated with a consistent state of the VM. The storage system determines a difference between the requested VM disk image and a previous VM disk image representing a previous VM backup. The changes between the requested VM disk image and a previous VM disk image are then transmitted to a target backup storage system. | 2014-04-03 |
20140095818 | UPDATING SYSTEM AND METHOD - An updating system includes an input unit, a recording unit, and a processor. The input unit generates updating data for updating a to-be-updated file in response to users operations. The processor updates the to-be-updated file using the updating data generated in response to users operations. The recording unit creates a duplicate record for recording the updating data during the procedure of updating the to-be-updated file. If the updating system is powered off before the to-be-updated file has been updated, the processor can obtain the duplicate record to update the to-be-updated file when the updating system is again powered on. An updating method applied in the updating system is also provided. | 2014-04-03 |
20140095819 | INFORMATION PROCESSING DEVICE, METHOD FOR CONTROLLING INFORMATION PROCESSING DEVICE - An information processing device includes a plurality of arithmetic processing devices, a plurality of storage devices, a connection section that connects a first arithmetic processing device to a first storage device and a second storage device which are duplexed and a control section that causes, when the performance of the second storage device is reduced, the connection section to cut out the second storage device whose performance has been reduced from the first arithmetic processing device and the first storage device, causes to duplex a third storage device with the first storage device, causes the connection section to connect the first storage device and the third storage device which have been duplexed to the first arithmetic processing device and to connect a second arithmetic processing device to the second storage device that has been cut out, and causes the second arithmetic processing device to initialize the second storage device. | 2014-04-03 |
20140095820 | STORAGE CONTROL APPARATUS AND COPYING METHOD - A storage control apparatus includes: a copy processing unit to perform a first copy process of copying, when receiving a write request targeting on a write destination address with a copy of a copy source volume to a copy destination volume being not yet completed, write data of the write destination address to the copy destination volume, and to perform a second copy process, when executing a copy process of an overall storage area of the copy source volume, according to a copy sequence on a management area unit basis of management areas into which the overall storage area is segmented; and a copy sequence resetting unit to reset the copy sequences on the basis of a reception timing of the write request received during the second copy process by the copy processing unit and a write destination address. | 2014-04-03 |
20140095821 | SYSTEM AND METHOD FOR SECURITY AND PRIVACY AWARE VIRTUAL MACHINE CHECKPOINTING - A checkpointing method for creating a file representing a restorable state of a virtual machine in a computing system, comprising identifying processes executing within the virtual machine that may store confidential data, and marking memory pages and files that potentially contain data stored by the identified processes; or providing an application programming interface for marking memory regions and files within the virtual machine that contain confidential data stored by processes; and creating a checkpoint file, by capturing memory pages and files representing a current state of the computing system, which excludes information from all of the marked memory pages and files. | 2014-04-03 |
20140095822 | SECURE REMOVABLE MASS STORAGE DEVICES - A removable mass storage device includes a controller and a memory storage area. A secured portion of the memory storage area may be a permanently write-protected portion. Programs provided by the operating system, e.g., application programming interface (API), for accessing the memory storage area cannot disable the write-protection of the permanently write-protected portion, preventing them from writing to the permanently write-protected portion. The controller does not enforce the write-protection against a security command of a secure library, allowing writing to the permanently write-protected portion using the security command. The security command may be issued by an API of the secure library. The secured portion of the memory storage area may also be a hidden portion that is not visible to the operating system, but is accessible by way of the secure library. | 2014-04-03 |
20140095823 | Virtual Disk Snapshot Consolidation Using Block Merge - A virtualized computer system employs a virtual disk. Multiple snapshots of the virtual disk can be created. After a snapshot is created, writes to the virtual disk are captured in delta disks. Two snapshots are consolidated by updating block references in snapshot meta data. Block reference update takes advantage of the fact that blocks for the two snapshot are managed within the same storage container and, therefore, can be moved in the snapshot logical space without incurring data copy operations. Consolidation of delta disks also gracefully handles failures during the consolidation operation and can be restarted anew after the system has recovered from failure. | 2014-04-03 |
20140095824 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device comprises: a read queue configured to store one or more read requests to a semiconductor memory device; a write queue configured to store one or more write requests to the semiconductor memory device; and a dispatch block configured to determine a scheduling order of the one or more read requests and the one or more write requests and switch to the read queue or to the write queue if a request exists in a Row Hit state in the read queue or in the write queue. | 2014-04-03 |
20140095825 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - An operating method of a semiconductor device may comprise determining whether a read request is pending, setting a delay interval in accordance with a density of requests if there is no read request pending; and processing a write request after the delay interval. | 2014-04-03 |
20140095826 | SYSTEM AND METHOD FOR ALLOCATING DATASTORES FOR VIRTUAL MACHINES - A datastore for a virtual machine that can be executed on a host computer networked to a physical storage system is allocated by a server. The server generates a unique identifier to associate with the datastore, wherein the unique identifier mimics a form of identifier that is generated by the physical storage system to identify volumes of physical storage in the physical storage system that are accessible to the host computer. At least one volume of physical storage in the physical storage system having physical storage available to satisfy the request to allocate the datastore is identified and the server maintains a mapping of the unique identifier to the at least one volume of physical storage and provides the mapping to the host computer upon running the virtual machine, thereby enabling the host computer to store data for the datastore in the at least one volume of physical storage. | 2014-04-03 |
20140095827 | MEMORY STORAGE DEVICE, AND A RELATED ZONE-BASED BLOCK MANAGEMENT AND MAPPING METHOD - A storage device is disclosed, in which the device comprises memory ( | 2014-04-03 |
20140095828 | VECTOR MOVE INSTRUCTION CONTROLLED BY READ AND WRITE MASKS - A processor executes a vector move instruction to move data elements from a second vector register to a first vector register under the control of a first mask register and a second mask register. A register file within the processor includes the first vector register, the second vector register, the first mask register and the second mask register. In response to the vector move instruction, execution circuitry in the processor is to replace a given number of target data elements in the first vector register with the given number of source data elements in the second vector register. Each source data element corresponds to a mask bit in the second mask register having a second bit value, and wherein each target data element corresponds to a mask bit in the first mask register having a first bit value. | 2014-04-03 |
20140095829 | Method and device for passing parameters between processors - The disclosure provides a method for passing a parameter between processors. The method comprises the following steps: in a source program of a slave processor, directly introducing a static configuration parameter to be passed; obtaining a relative address of the static configuration parameter when converting the source program of the slave processor into a target program of the slave processor; and configuring directly, by a master processor, a parameter value of the static configuration parameter in the target program of the slave processor according to the obtained relative address of the static configuration parameter. The disclosure also provides a system for passing a parameter between processors. The system has no need to use external hardware such as a dual-port Random Access Memory (RAM) and a register, thus, the requirement of parameter transmission on the external hardware is reduced, and further the area and static power consumption of a chip are reduced. The disclosure reduces the cycle delay of the slave processor in accessing the dual-port RAM and the register, thereby effectively reducing the dynamic power consumption of the chip, improving the processing capability of the slave processor and enhancing the effective performance of the slave processor. | 2014-04-03 |
20140095830 | INSTRUCTION FOR SHIFTING BITS LEFT WITH PULLING ONES INTO LESS SIGNIFICANT BITS - A mask generating instruction is executed by a processor to improve efficiency of vector operations on an array of data elements. The processor includes vector registers, one of which stores data elements of an array. The processor further includes execution circuitry to receive a mask generating instruction that specifies at least a first operand and a second operand. Responsive to the mask generating instruction, the execution circuitry is to shift bits of the first operand to the left by a number of times defined in the second operand, and pull in a bit of one from the right each time a most significant bit of the first operand is shifted out from the left to generate a result. Each bit in the result corresponds to one of the data elements of the array. | 2014-04-03 |
20140095831 | APPARATUS AND METHOD FOR EFFICIENT GATHER AND SCATTER OPERATIONS - An apparatus and method are described for performing efficient gather operations in a pipelined processor. For example, a processor according to one embodiment of the invention comprises: gather setup logic to execute one or more gather setup operations in anticipation of one or more gather operations, the gather setup operations to determine one or more addresses of vector data elements to be gathered by the gather operations; and gather logic to execute the one or more gather operations to gather the vector data elements using the one or more addresses determined by the gather setup operations. | 2014-04-03 |
20140095832 | METHOD AND APPARATUS FOR PERFORMANCE EFFICIENT ISA VIRTUALIZATION USING DYNAMIC PARTIAL BINARY TRANSLATION - Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory. | 2014-04-03 |
20140095833 | Prefix Computer Instruction for Compatibly Extending Instruction Functionality - A prefix instruction is executed and passes operands to a next instruction without storing the operands in an architected resource such that the execution of the next instruction uses the operands provided by the prefix instruction to perform an operation, the operands may be prefix instruction immediate field or a target register of the prefix instruction execution. | 2014-04-03 |
20140095834 | INSTRUCTION AND LOGIC FOR BOYER-MOORE SEARCH OF TEXT STRINGS - Instructions and logic provide extended vector suffix comparisons for Boyer-Moore searches. Some embodiments, responsive to an instruction specifying: a pattern source operand and a target source operand, compare each of m data elements of the pattern operand with each data element of the target operand. A first and second equal ordered aggregation operation are performed from the comparisons according to the m data elements of the pattern source operand. A result of the first and second aggregation operations indicating whether or not a possible match exists between the m data elements of the pattern source operand and d data element positions relative to data elements of the target source operand is stored. Ordering of the data elements of the pattern and the target operands may be reversed for the second aggregation operation, and d may be a sum of m−1 and the quantity of target operand elements in some embodiments. | 2014-04-03 |
20140095835 | PERFORMING PREDECODE-TIME OPTIMIZED INSTRUCTIONS IN CONJUNCTION WITH PREDECODE TIME OPTIMIZED INSTRUCTION SEQUENCE CACHING - A method for performing predecode-time optimized instructions in conjunction with predecode time optimized instruction sequence caching. The method includes receiving a first instruction of an instruction sequence and a second instruction of the instruction sequence and determining if the first instruction and the second instruction can be optimized. In response to the determining that the first instruction and second instruction can be optimized, the method includes, preforming a pre-decode optimization on the instruction sequence and generating a new second instruction, wherein the new second instruction is not dependent on a target operand of the first instruction and storing a pre-decoded first instruction and a pre-decoded new second instruction in an instruction cache. In response to determining that the first instruction and second instruction can not be optimized, the method includes, storing the pre-decoded first instruction and a pre-decoded second instruction in the instruction cache. | 2014-04-03 |
20140095836 | CROSS-PIPE SERIALIZATION FOR MULTI-PIPELINE PROCESSOR - Embodiments relate to cross-pipe serialization for a multi-pipeline computer processor. An aspect includes receiving, by a processor, the processor comprising a first pipeline, the first pipeline comprising a serialization pipeline, and a second pipeline, the second pipeline comprising a non-serialization pipeline, a request comprising a first subrequest for the first pipeline and a second subrequest for the second pipeline. Another aspect includes completing the first subrequest by the first pipeline. Another aspect includes, based on completing the first subrequest by the first pipeline, sending cross-pipe unlock signal from the first pipeline to the second pipeline. Yet another aspect includes, based on receiving the cross-pipe unlock signal by the second pipeline, completing the second subrequest by the second pipeline. | 2014-04-03 |
20140095837 | READ AND WRITE MASKS UPDATE INSTRUCTION FOR VECTORIZATION OF RECURSIVE COMPUTATIONS OVER INTERDEPENDENT DATA - A processor executes a mask update instruction to perform updates to a first mask register and a second mask register. A register file within the processor includes the first mask register and the second mask register. The processor includes execution circuitry to execute the mask update instruction. In response to the mask update instruction, the execution circuitry is to invert a given number of mask bits in the first mask register, and also to invert the given number of mask bits in the second mask register. | 2014-04-03 |
20140095838 | Physical Reference List for Tracking Physical Register Sharing - A processor includes a processing unit including a storage module having stored thereon a physical reference list for storing identifications of physical registers that have been referenced by multiple logical registers, and a reclamation module for reclaiming physical registers to a free list based on a count of each of the physical registers on the physical reference list. | 2014-04-03 |
20140095839 | MONITORING PROCESSING TIME IN A SHARED PIPELINE - A pipelined processing device includes: a pipeline controller configured to receive at least one instruction associated with an operation from each of a plurality of subcontrollers, and input the at least one instruction into a pipeline; and a pipeline counter configured to receive an active time value from each of the plurality of subcontrollers, the active time value indicating at least a portion of a time taken to process the at least one instruction, the pipeline controller configured to route the active time value to a shared pipeline storage for performance analysis. | 2014-04-03 |
20140095840 | DIAGNOSE INSTRUCTION FOR SERIALIZING PROCESSING - A system serialization capability is provided to facilitate processing in those environments that allow multiple processors to update the same resources. The system serialization capability is used to facilitate processing in a multi-processing environment in which guests and hosts use locks to provide serialization. The system serialization capability includes a diagnose instruction which is issued after the host acquires a lock, eliminating the need for the guest to acquire the lock. | 2014-04-03 |
20140095841 | PROCESSOR AND CONTROL METHOD OF PROCESSOR - A processor including a circuit unit includes a state information holding unit, a direction controller, a direction generator, and a direction execution unit. The state information holding unit holds state information indicating a state of the circuit unit. The direction controller decodes a first direction for generating a control direction that is contained in a program. The direction generator generates a second direction when the first direction decoded by the direction controller is a direction for generating the second direction for reading the state information from the state information holding unit. The direction execution unit reads the state information from the state information holding unit based on the second direction generated by the direction generator so as to store the state information in a register unit that is capable of being read from a program. | 2014-04-03 |
20140095842 | ACCELERATED INTERLANE VECTOR REDUCTION INSTRUCTIONS - A vector reduction instruction is executed by a processor to provide efficient reduction operations on an array of data elements. The processor includes vector registers. Each vector register is divided into a plurality of lanes, and each lane stores the same number of data elements. The processor also includes execution circuitry that receives the vector reduction instruction to reduce the array of data elements stored in a source operand into a result in a destination operand using a reduction operator. Each of the source operand and the destination operand is one of the vector registers. Responsive to the vector reduction instruction, the execution circuitry applies the reduction operator to two of the data elements in each lane, and shifts one or more remaining data elements when there is at least one of the data elements remaining in each lane. | 2014-04-03 |
20140095843 | Systems, Apparatuses, and Methods for Performing Conflict Detection and Broadcasting Contents of a Register to Data Element Positions of Another Register - Systems, apparatuses, and methods of performing in a computer processor broadcasting data in response to a single vector packed broadcasting instruction that includes a source writemask register operand, a destination vector register operand, and an opcode. In some embodiments, the data of the source writemask register is zero extended prior to broadcasting. | 2014-04-03 |
20140095844 | Systems, Apparatuses, and Methods for Performing Rotate and XOR in Response to a Single Instruction - Disclosed herein are systems, apparatuses, and methods performing in a computer processor of performing a rotate and XOR in response to a single XOR and rotate instruction, wherein the rotate and XOR instruction includes a first and second source operand, a destination operand, and an immediate value. | 2014-04-03 |
20140095845 | APPARATUS AND METHOD FOR EFFICIENTLY EXECUTING BOOLEAN FUNCTIONS - An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, a processor according to one embodiment of the invention comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register. | 2014-04-03 |
20140095846 | TRACE BASED MEASUREMENT ARCHITECTURE - A method for performing trace based measurement for a plurality of CPUs in parallel includes receiving a signal to perform a CPU parallel trace mode and enabling a parallel trace mode multiplexer to output all trace data, representing all data writes to the local memory, to a single observation unit. In one embodiment, the single observation unit is a processor observation block (POB), and in another embodiment, a bus observation block (BOB). If the single observation unit is a BOB, then the parallel trace mode multiplexer first routes the local memory data trace through a BOB adaptation layer to convert the CPU trace output data to data which is understood by the BOB. | 2014-04-03 |
20140095847 | INSTRUCTION AND HIGHLY EFFICIENT MICRO-ARCHITECTURE TO ENABLE INSTANT CONTEXT SWITCH FOR USER-LEVEL THREADING - A processor uses multiple banks of an extended register set to store the contexts of multiple user-level threads. A current bank register provides a pointer to the bank that is currently active. A first thread saves its context (first context) in a first bank of the extended register set and a second thread saves its context (second context) in a second bank of the extended register set. When the processor receives an instruction for exchanging contexts between the first thread and the second thread, the processor changes the pointer from the first bank to the second bank, and executes the second thread using the second context stored in the second bank. | 2014-04-03 |