14th week of 2014 patent applcation highlights part 13 |
Patent application number | Title | Published |
20140091343 | COLOR FILTER SUBSTRATE MANUFACTURING METHOD, DISPLAY DEVICE MANUFACTURING METHOD, COLOR FILTER SUBSTRATE, AND DISPLAY DEVICE - The present invention provides a color filter substrate manufacturing method which can prevent the occurrence of color mixing between adjacent pixels despite of the use of an inkjet method, and which are unlikely to cause flicker when used for displays such as televisions. The prevent invention is a color filter substrate manufacturing method including: a first inkjet step of applying inks simultaneously to at least two of a plurality of regions separated by a grid-shaped partition; and a second inkjet step of applying an ink to at least one of regions to which the inks are not applied in the first inkjet step, wherein at least one of inks applied in the first inkjet step is a first ink that is applied to a first target region without applying inks to regions vertically and horizontally adjacent to the first target region, and at least one of the other inks applied in the first inkjet step is a second ink that is applied to a second target region while another ink is applied to one of regions vertically and horizontally adjacent to the second target region. | 2014-04-03 |
20140091344 | ILLUMINATION COMPONENT PACKAGE - An illumination component package includes a substrate, at least one illumination component, a dam and an encapsulating glue. The illumination component is mounted on the substrate. The dam surrounds the illumination component to form a accommodating space. The inner wall of the dam includes a plurality of glue adhering microstructures. The encapsulating glue is filled in the accommodating space. | 2014-04-03 |
20140091345 | LUMINESCENCE DEVICE - A luminescence device used in a backlight unit for lighting or displaying may include a substrate having a first electrode and a second electrode, and an LED chip disposed on the first electrode. A dam is disposed on the substrate. The dam is disposed spaced from the LED chip, and the substrate comprises a direct copper bonding (DCB) substrate including a first copper layer and a second copper layer. The first electrode and the second electrode include respectively a metal film which fills a void of the surfaces thereof. | 2014-04-03 |
20140091346 | PHOSPHOR ADHESIVE SHEET, OPTICAL SEMICONDUCTOR ELEMENT-PHOSPHOR LAYER PRESSURE-SENSITIVE ADHESIVE BODY, AND OPTICAL SEMICONDUCTOR DEVICE - A phosphor adhesive sheet includes a phosphor layer containing a phosphor and an adhesive layer laminated on one surface in a thickness direction of the phosphor layer. The adhesive layer is formed from a silicone pressure-sensitive adhesive composition. A percentage of the peel strength of the phosphor adhesive sheet is 30% or more. | 2014-04-03 |
20140091347 | PHOSPHOR LAYER ATTACHING KIT, OPTICAL SEMICONDUCTOR ELEMENT-PHOSPHOR LAYER ATTACHING BODY, AND OPTICAL SEMICONDUCTOR DEVICE - A phosphor layer attaching kit includes a phosphor layer and a silicone pressure-sensitive adhesion composition for attaching the phosphor layer to an optical semiconductor element or an optical semiconductor element package. A percentage of the peel strength of the silicone pressure-sensitive adhesion composition is 30% or more. | 2014-04-03 |
20140091348 | ENCAPSULATING SHEET-COVERED SEMICONDUCTOR ELEMENT, PRODUCING METHOD THEREOF, SEMICONDUCTOR DEVICE, AND PRODUCING METHOD THEREOF - An encapsulating sheet-covered semiconductor element includes a semiconductor element having one surface in contact with a board and the other surface disposed at the other side of the one surface and an encapsulating sheet covering at least the other surface of the semiconductor element. The encapsulating sheet includes an exposed surface that is, when projected from one side toward the other side, not included in the one surface of the semiconductor element and exposed from the one surface and the exposed surface has the other side portion that is positioned toward the other side with respect to the one surface of the semiconductor element. | 2014-04-03 |
20140091349 | OPTICAL DESIGNS FOR HIGH-EFFICACY WHITE-LIGHT EMITTING DIODES - A method for increasing the luminous efficacy of a white light emitting diode (WLED), comprising introducing optically functional interfaces between an LED die and a phosphor, and between the phosphor and an outer medium, wherein at least one of the interfaces between the phosphor and the LED die provides a reflectance for light emitted by the phosphor away from the outer medium and a transmittance for light emitted by the LED die. Thus, a WLED may comprise a first material which surrounds an LED die, a phosphor layer, and at least one additional layer or material which is transparent for direct LED emission and reflective for the phosphor emission, placed between the phosphor layer and the first material which surrounds the LED die. | 2014-04-03 |
20140091350 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor light emitting device, includes: a stacked structural unit including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer provided therebetween; and an electrode including a first and second metal layers, the first metal layer including silver or silver alloy and being provided on a side of the second semiconductor layer opposite to the light emitting layer, the second metal layer including at least one element selected from gold, platinum, palladium, rhodium, iridium, ruthenium, and osmium and being provided on a side of the first metal layer opposite to the second semiconductor layer. A concentration of the element in a region including an interface between the first and second semiconductor layers is higher than that of the element in a region of the first metal layer distal to the interface. | 2014-04-03 |
20140091351 | LIGHT EMITTING DIODE CHIP - A Light emitting diode (LED) chip includes a substrate, an N-type semiconductor layer, a luminous layer, a P-type semiconductor layer, an N-type electrode layer and a P-type electrode layer. The N-type semiconductor layer is mounted on the substrate. The luminous layer is mounted on the N-type semiconductor layer. The P-type semiconductor layer is mounted on the luminous layer. The N-type electrode layer is mounted on the N-type semiconductor layer. The P-type electrode layer is mounted on the P-type semiconductor layer, and includes a plurality of enclosed circuit patterns. These enclosed circuit patterns respectively encompass different parts of the N-type electrode layer. | 2014-04-03 |
20140091352 | LIGHT EMITTING DIODE - A light emitting diode includes a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode, a second electrode. The second electrode includes a treated patterned carbon nanotube film. The treated patterned carbon nanotube film includes at least two carbon nanotube linear units spaced from each other; and carbon nanotube groups spaced from each other. The carbon nanotube groups are located between the at least two carbon nanotube linear units, and combined with the at least two carbon nanotube linear units. | 2014-04-03 |
20140091353 | VERTICAL STRUCTURE LEDS - A vertical structure light-emitting device includes a conductive support, a light-emitting semiconductor structure disposed on the conductive support structure, the semiconductor structure having a first semiconductor surface, a side semiconductor surface and a second semiconductor surface, a first electrode electrically connected to the first-type semiconductor layer, a second electrode electrically connected to the second-type semiconductor layer, wherein the second electrode has a first electrode surface, a side electrode surface and a second electrode surface, wherein the first electrode surface, relative to the second electrode surface, is proximate to the semiconductor structure; and wherein the second electrode surface is opposite to the first electrode surface, and a passivation layer disposed on the side semiconductor surface and the second semiconductor surface. | 2014-04-03 |
20140091354 | LIGHT EMITTING DIODE HAVING TWO SEPARATED SUBSTRATE PARTS CONNECTED TOGETHER BY ENCAPSULATION - A light emitting diode includes a substrate consisting two separated parts with a gap therebetween. A first electrical connecting portion is fixed to one of the two separated parts of the substrate and adjacent to the gap. A second electrical connecting portion is fixed to the other one of the two separated parts of the substrate and adjacent to the gap. An LED chip is mounted on the substrate and electrically connected to the first and second electrical connecting portions. An encapsulation covers the LED chip and fills in at least a part of the gap to connect the two separated parts of the substrate together. | 2014-04-03 |
20140091355 | METHOD FOR FORMING CURRENT DIFFUSION LAYER IN LIGHT EMITTING DIODE DEVICE AND METHOD FOR FABRICATING THE SAME - A method of forming a current diffusion layer is provided that comprises providing an epitaxial wafer. The method further comprises depositing ITO source material on the epitaxial wafer to form a base ITO layer by a direct current electron gun and depositing ZnO source material, during simultaneous deposition of the ITO source material, on the base ITO layer to form a ZnO doped ITO layer by a pulse current electron gun. The ZnO source material is deposited at a deposition rate higher than the rate at which the ITO source material is deposited. Generation and termination of current may be controlled by adjusting a duty cycle of pulse current provided by the pulse current electron gun and result in discontinuous deposition of the ZnO source material. The method further comprises depositing the ITO source material on the ZnO doped ITO layer to cover the ZnO doped ITO layer and form a finished ITO layer. | 2014-04-03 |
20140091356 | LIGHT EMITTING DEVICE - A light emitting device includes a package constituted by a molded article having a light emitting face, a bottom face, and a rear face, and a pair of leads partially embedded in the molded article, protrude from the bottom face, and have ends that bend toward either the light emitting face or the rear face. The molded article has a front protruding part that protrudes from the bottom face and includes a surface continuous with the light emitting face, the front protruding part being spaced apart from the rear face, and a rear protruding part that protrudes from the bottom face and includes a surface continuous with the rear face, the rear protruding part being spaced apart from the light emitting face, between the leads on the bottom face, the front protruding part being spaced apart from the rear protruding part. | 2014-04-03 |
20140091357 | ENCAPSULATED STRUCTURE OF LIGHT-EMITTING DEVICE, ENCAPSULATING PROCESS THEREOF AND DISPLAY DEVICE COMPRISING ENCAPSULATED STRUCTURE - An encapsulated structure of a light-emitting device, an encapsulating process thereof, and a display device comprising said encapsulated structure. The encapsulated structure of the light-emitting device comprises: a light-emitting device; and a protective layer of a sulfonate salt formed on a top electrode of the light-emitting device, the sulfonate salt having the following structure: | 2014-04-03 |
20140091358 | MCT Device with Base-Width-Determined Latching and Non-Latching States - Methods and systems for a gate-controlled thyristor which switches between narrow-base operation in the ON state and wide-base operation in the OFF state, and which can only sustain latch-up in the narrow-base ON state. | 2014-04-03 |
20140091359 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having one main surface in which an anode of a diode is formed. At a distance from the outer periphery of the anode, a guard ring is formed to surround the anode. The anode includes a p | 2014-04-03 |
20140091360 | TRENCH CONFINED EPITAXIALLY GROWN DEVICE LAYER(S) - Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer. | 2014-04-03 |
20140091361 | METHODS OF CONTAINING DEFECTS FOR NON-SILICON DEVICE ENGINEERING - An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor. | 2014-04-03 |
20140091362 | INTEGRATED CIRCUIT TRANSISTOR STRUCTURE WITH HIGH GERMANIUM CONCENTRATION SiGe STRESSOR - An integrated circuit transistor structure includes a semiconductor substrate, a first SiGe layer in at least one of a source area or a drain area on the semiconductor substrate, and a channel between the source area and the drain area. The first SiGe layer has a Ge concentration of 50 percent or more. | 2014-04-03 |
20140091363 | NORMALLY-OFF HIGH ELECTRON MOBILITY TRANSISTOR - According to example embodiments, a normally-off high electron mobility transistor (HEMT) includes: a channel layer having a first nitride semiconductor, a channel supply layer on the channel layer, a source electrode and a drain electrode at sides of the channel supply layer, a depletion-forming layer on the channel supply layer, a gate insulating layer on the depletion-forming layer, and a gate electrode on the gate insulation layer. The channel supply layer includes a second nitride semiconductor and is configured to induce a two-dimensional electron gas (2DEG) in the channel layer. The depletion-forming layer is configured has at least two thicknesses and is configured to form a depletion region in at least a partial region of the 2DEG. The gate electrode contacts the depletion-forming layer. | 2014-04-03 |
20140091364 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An AlGaN/GaN HEMT includes: an electron transit layer; an electron supply layer formed above the electron transit layer; and a gate electrode formed above the electron supply layer, wherein a p-type semiconductor region is formed only at a site of the electron transit layer which is contained in a region below the gate electrode. | 2014-04-03 |
20140091365 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A compound semiconductor device includes: a compound semiconductor layer; and a gate electrode formed above the compound semiconductor layer; and a source electrode and a drain electrode formed on both sides of the gate electrode, on the compound semiconductor layer, wherein the source electrode has a plurality of bottom surfaces along transit electrons out of contact surfaces with the compound semiconductor layer, and the plural bottom surfaces are located at different distances from the transit electrons, with the bottom surface closer to the gate electrode being more apart from the transit electrons. | 2014-04-03 |
20140091366 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - Example embodiments relate to semiconductor devices and/or methods of manufacturing the same. According to example embodiments, a semiconductor device may include a first heterojunction field effect transistor (HFET) on a first surface of a substrate, and a second HFET. A second surface of the substrate may be on the second HFET. The second HFET may have different properties (characteristics) than the first HFET. One of the first and second HFETs may be of an n type, while the other thereof may be of a p type. The first and second HFETs may be high-electron-mobility transistors (HEMTs). One of the first and second HFETs may have normally-on properties, while the other thereof may have normally-off properties. | 2014-04-03 |
20140091367 | Integrated Circuits, Standard Cells, And Methods For Generating A Layout Of An Integrated Circuit - An integrated circuit according to an embodiment of the invention includes a substrate having a first cell and a second cell, the first and the second cells being adapted to perform a substantially same functionality. Corresponding functional structures of the first and the second cell are electrically connected, at different locations inside the standard cells, to information carrying signal interconnection lines, wherein the functional structures are adapted to serve as an information carrying signal input or as an information carrying signal output. | 2014-04-03 |
20140091368 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device including: a semiconductor substrate of a first conductivity type, having a fixed electric potential; a dark-current drain region of a second conductivity type, formed on a portion of the semiconductor substrate; a connection region of the first conductivity type, formed on another portion of the semiconductor substrate where the dark-current drain region is not formed; a well region of the first conductivity type, covering the dark-current drain region and the connection region; and a first region and a second region, formed within the well region and constituting a part of a read transistor that reads signal charge generated by photoelectric conversion. The well region is maintained at a fixed electric potential by being connected to the semiconductor substrate via the connection region. | 2014-04-03 |
20140091369 | HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE - A HV MOS transistor device is provided. The HV MOS transistor device includes a substrate comprising at least an insulating region formed thereon, a gate positioned on the substrate and covering a portion of the insulating region, a drain region and a source region formed at respective sides of the gate in the substrate, and a first implant region formed under the insulating region. The substrate comprises a first conductivity type, the drain, the source, and the first implant region comprise a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. | 2014-04-03 |
20140091370 | TRANSISTOR FORMATION USING COLD WELDING - A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device. | 2014-04-03 |
20140091371 | SEMICONDUCTOR DEVICE - A semiconductor device including: a substrate having a channel region and first and second recesses disposed on opposite sides of the channel region; a gate insulating layer disposed on the channel region; a gate structure disposed on the gate insulating layer; and a source region disposed in the first recess and a drain region disposed in the second recess, wherein the source region includes a first layer disposed on a surface of the first recess and a second layer disposed on the first layer and the drain region includes a third layer disposed on a surface of the second recess and a fourth layer disposed on the third layer; and a distance between the gate structure and the second layer of the source region is greater or less than a distance between the gate structure and the fourth layer of the drain region. | 2014-04-03 |
20140091372 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - In a first step, a planar silicon layer is formed on a silicon substrate and first and second pillar-shaped silicon layers are formed on the planar silicon layer; a second step includes forming an oxide film hard mask on the first and second pillar-shaped silicon layers, and forming a second oxide film on the planar silicon layer, the second oxide film being thicker than a gate insulating film; and a third step includes forming the gate insulating film around each of the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a metal film and a polysilicon film around the gate insulating film, the polysilicon film having a thickness that is smaller than one half a distance between the first pillar-shaped silicon layer and the second pillar-shaped silicon layer, forming a third resist for forming a gate line, and performing anisotropic etching to form the gate line. | 2014-04-03 |
20140091373 | Semiconductor Device with Breakdown Preventing Layer - A semiconductor device with a breakdown preventing layer is provided. The breakdown preventing layer can be located in a high-voltage surface region of the device. The breakdown preventing layer can include an insulating film with conducting elements embedded therein. The conducting elements can be arranged along a lateral length of the insulating film. The conducting elements can be configured to split a high electric field spike otherwise present in the high-voltage surface region during operation of the device into multiple much smaller spikes. | 2014-04-03 |
20140091374 | STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND Si NANOPHOTONICS - A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device. | 2014-04-03 |
20140091375 | Implant Isolated Devices and Method for Forming the Same - A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate and extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and two end cap hardmasks are between the gate dielectric and the gate electrode over the implant isolation region. The two end cap hardmasks include same dopants as those implanted into the active region. | 2014-04-03 |
20140091376 | Monolithically Integrated Antenna and Receiver Circuit - The invention relates to a device for detecting electromagnetic radiation in the THz frequency range, comprising at least one transistor (FET | 2014-04-03 |
20140091377 | Implant Isolated Devices and Method for Forming the Same - A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and an end cap dielectric layer is between the gate dielectric and the gate electrode over the implant isolation region. | 2014-04-03 |
20140091378 | SOLID-STATE IMAGING DEVICE AND IMAGE CAPTURING SYSTEM - A solid-state imaging device includes a photoelectric converting portion including a first semiconductor region capable of accumulating a signal charge, a second semiconductor region of the same conductivity type as the first semiconductor region, a gate electrode provided between the first and second semiconductor regions, and an insulating layer provided on the first semiconductor region, the second semiconductor region, and the gate electrode. The solid-state imaging device further includes a first light-shielding portion including a metal portion provided in an opening or a trench of the insulating layer between the first and second semiconductor regions, and a second light-shielding portion including a metal portion provided on the insulating layer on the second semiconductor region. | 2014-04-03 |
20140091379 | FLUOROCARBON COATING HAVING LOW REFRACTIVE INDEX - A fluorocarbon coating comprises an amorphous structure with CF | 2014-04-03 |
20140091380 | Split Gate Flash Cell - In one aspect, a disclosed method of fabricating a split gate memory device includes forming a gate dielectric layer overlying an channel region of a semiconductor substrate and forming an electrically conductive select gate overlying the gate dielectric layer. The method further includes forming a counter doping region in an upper region of the substrate. A proximal boundary of the counter doping region is laterally displaced from a proximal sidewall of the select gate. The method further includes forming a charge storage layer comprising a vertical portion adjacent to the proximal sidewall of the select gate and a lateral portion overlying the counter doping region and forming an electrically conductive control gate adjacent to the vertical portion of the charge storage layer and overlying the horizontal portion of the charge storage layer. | 2014-04-03 |
20140091381 | SUPPORT LINES TO PREVENT LINE COLLAPSE IN ARRAYS - Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be provided to prevent the collapse of closely spaced device structures during fabrication. In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be set in place prior to performing a high aspect ratio word line etch for forming the NAND strings. The one or more mechanical support structures may comprise one or more fin supports that are arranged in a bit line direction. In another example, the one or more mechanical support structures may be developed during the word line etch for forming the NAND strings. | 2014-04-03 |
20140091382 | Split-Gate Memory Cell With Substrate Stressor Region, And Method Of Making Same - A memory device, and method of make same, having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and a stressor region of embedded silicon carbide formed in the substrate underneath the second gate. | 2014-04-03 |
20140091383 | SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions. | 2014-04-03 |
20140091384 | Reverse Polarity Protection for n-Substrate High-Side Switches - A semiconductor device is disclosed. In accordance with a first aspect of the present invention the device includes a semiconductor chip having a substrate, a first supply terminal electrically coupled to the substrate to provide a first supply potential (V | 2014-04-03 |
20140091385 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first pillar-shaped silicon layer formed on a planar silicon layer, a gate insulating film formed around the first pillar-shaped silicon layer, a first gate electrode formed around the gate insulating film, a gate line connected to the first gate electrode, a first first-conductivity-type diffusion layer formed in an upper portion of the first pillar-shaped silicon layer, a second first-conductivity-type diffusion layer formed in a lower portion of the first pillar-shaped silicon layer and an upper portion of the planar silicon layer, a first sidewall having a laminated structure of an insulating film and polysilicon and being formed on an upper sidewall of the first pillar-shaped silicon layer and an upper portion of the first gate electrode, and a first contact formed on the first first-conductivity-type diffusion layer and the first sidewall. | 2014-04-03 |
20140091386 | MOSFET DEVICE AND FABRICATION - A semiconductor device includes a substrate, an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; and a body region in the substrate. The top surface of the polysilicon electrode is below the bottom of the body region. | 2014-04-03 |
20140091387 | SEMICONDUCTOR DEVICE - In a transistor including a trench gate, a gate contact hole for connecting a gate electrode and a gate wiring to each other is provided on a trench. In a transistor in which the trench gate is formed in a grid pattern and a plurality of source regions are surrounded by the trench gate, the gate contact hole is formed at an intersection portion of the trench gate. | 2014-04-03 |
20140091388 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer. | 2014-04-03 |
20140091389 | HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE - A high voltage metal-oxide-semiconductor transistor device includes a substrate having an insulating region formed therein, a gate covering a portion of the insulating region and formed on the substrate, a source region and a drain region formed at respective sides of the gate in the substrate, a body region formed in the substrate and partially overlapped by the gate, and a first implant region formed in the substrate underneath the gate and adjacent to the body region. The substrate and body region include a first conductivity type. The source region, the drain region, and the first implant region include a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. | 2014-04-03 |
20140091390 | Protection Layer for Halftone Process of Third Metal - A thin-film transistor having a protection layer for a planarization layer. The protection layer prevents reduction of the planarization layer during an ashing process, thereby preventing the formation of a steeply tapered via hole through the planarization layer. In this manner, the via hole may be coated with a conductive element that may serve as a conductive path between a common electrode and the drain of the transistor. | 2014-04-03 |
20140091391 | FIELD-EFFECT-TRANSISTOR WITH SELF-ALIGNED DIFFUSION CONTACT - Embodiments of the present invention provide an array of fin-type transistors formed on top of an oxide layer. At least a first and a second of the fin-type transistors have their respective source and drain contacts being formed inside the oxide layer, with one of the contacts of the first fin-type transistor being conductively connected to one of the contacts of the second fin-type transistor by an epitaxial silicon layer, wherein the epitaxial silicon layer is formed on top of a first and a second fin of the first and second fin-type transistors respectively. | 2014-04-03 |
20140091392 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, METHOD FOR PRODUCING SEMICONDUCTOR WAFER, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - There is provided a semiconductor device including a first channel-type first MISFET formed and a second channel-type second MISFET: a first source and a first drain of the first MISFET and a second source and a second drain of the second MISFET are made of the same conductive substance, and the work function Φ | 2014-04-03 |
20140091393 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, METHOD FOR PRODUCING SEMICONDUCTOR WAFER, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - There is provided a semiconductor device including: a first source and a first drain of a first-channel-type MISFET formed on a first semiconductor crystal layer, which are made of a compound having an atom constituting the first semiconductor crystal layer and a nickel atom, a compound having an atom constituting the first semiconductor crystal layer and a cobalt atom, or a compound having an atom constituting the first semiconductor crystal layer, a nickel atom, and a cobalt atom; and a second source and a second drain of a second-channel-type MISFET formed on a second semiconductor crystal layer, which are made of a compound having an atom constituting the second semiconductor crystal layer and a nickel atom, a compound having an atom constituting the second semiconductor crystal layer and a cobalt atom, or a compound having an atom constituting the second semiconductor crystal layer, a nickel atom, and a cobalt atom. | 2014-04-03 |
20140091394 | MULTI-GATE FIELD EFFECT TRANSISTOR (FET) INCLUDING ISOLATED FIN BODY - Aspects of the disclosure provide a multi-gate field effect transistor (FET) formed on a bulk substrate that includes an isolated fin and methods of forming the same. In one embodiment, the multi-gate FET includes: a plurality of silicon fin structures formed on the bulk substrate, each silicon fin structure including a body region, a source region, and a drain region; wherein a bottom portion the body region of each silicon fin structure includes a tipped shape to isolate the body region from the bulk substrate, and wherein the plurality of silicon fin structures are attached to the bulk substrate via at least a portion of the source region, or at least a portion of the drain region, or both. | 2014-04-03 |
20140091395 | TRANSISTOR - A method for fabricating a transistor device including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.). Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a lower tensile stress than the second tensile stress layer. | 2014-04-03 |
20140091396 | PASS GATE, SEMICONDUCTOR MEMORY, AND SEMICONDUCTOR DEVICE - According to one embodiment, a pass gate provided between a data holding unit of an SRAM cell and a bit line, includes a first tunnel transistor and a first diode connected in series between the data holding unit and the bit line, and a second tunnel transistor and a second diode connected in series between the data holding unit and the bit line and connected in parallel to the first tunnel transistor and the first diode. Gate electrodes of the first tunnel transistor and the second tunnel transistor are connected to a word line. The first diode and the second diode have rectification in mutually opposite directions between the data holding unit and the bit line. | 2014-04-03 |
20140091397 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THEREOF - It is therefore an object of the present invention to provide a method in which, in a semiconductor integrated circuit device, a plurality of transistors having wide-rangingly different I | 2014-04-03 |
20140091398 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, METHOD FOR PRODUCING SEMICONDUCTOR WAFER, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a first source and a first drain of a P-channel-type MISFET formed on a Ge wafer, which are made of a compound having a Ge atom and a nickel atom, a compound having a Ge atom and a cobalt atom, or a compound having a Ge atom, a nickel atom, and a cobalt atom, and a second source and a second drain of an N-channel-type MISFET formed on the Group III-V compound semiconductor, which are made of a compound having a Group III atom, a Group V atom, and a nickel atom, a compound having a Group III atom, a Group V atom, and a cobalt atom, or a compound having a Group III atom, a Group V atom, a nickel atom, and a cobalt atom. | 2014-04-03 |
20140091399 | ELECTRONIC DEVICE INCLUDING A TRANSISTOR AND A VERTICLE CONDUCTIVE STRUCTURE - An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region. | 2014-04-03 |
20140091400 | Gate Dielectric Of Semiconductor Device - A method of fabricating a semiconductor device having a different gate structure in each of a plurality of device regions is described. The method may include a replacement gate process. The method includes forming a hard mask layer on oxide layers formed on one or more regions of the substrate. A high-k gate dielectric layer is formed on each of the first, second and third device regions. The high-k gate dielectric layer may be formed directly on the hard mask layer in a first and second device regions and directly on an interfacial layer formed in a third device region. A semiconductor device including a plurality of devices (e.g., transistors) having different gate dielectrics formed on the same substrate is also described. | 2014-04-03 |
20140091401 | POWER SEMICONDUCTOR HOUSING WITH REDUNDANT FUNCTIONALITY - In various embodiments, a power semiconductor housing having an integrated circuit is provided. The integrated circuit may include: a first gate pad and a second gate pad; and a first gate contact and a second gate contact; wherein the first gate pad is electrically connected to the first gate contact; wherein the second gate pad is electrically connected to the second gate contact. The integrated circuit may further include a drain-contact surface, wherein the drain-contact surface is connected to a drain contact; and a second drain contact, which is electrically connected to the drain-contact surface of the integrated circuit. | 2014-04-03 |
20140091402 | INTEGRATED CIRCUIT METAL GATE STRUCTURE - A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer. | 2014-04-03 |
20140091403 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a step of forming a first insulating film around a fin-shaped silicon layer and forming a pillar-shaped silicon layer in an upper portion of the fin-shaped silicon layer; a step of implanting an impurity into upper portions of the pillar-shaped silicon layer and fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer to form diffusion layers; and a step of forming a polysilicon gate electrode, a polysilicon gate line, and a polysilicon gate pad. The polysilicon gate electrode and the polysilicon gate pad have a larger width than the polysilicon gate line. After these steps follow a step of depositing an interlayer insulating film, exposing and etching the polysilicon gate electrode and the polysilicon gate line, and depositing a metal layer to form a metal gate electrode and a metal gate line, and a step of forming a contact. | 2014-04-03 |
20140091404 | ACCELERATION SENSOR - A first sensor section installed in an acceleration sensor employs a first elastic member which is elastically movable according to acceleration in the first and third directions and is stiff against acceleration in second direction so as to restrict elasticity in second direction. Thereby, the first sensor section is provided as a biaxial acceleration sensor which detects the first and third directional acceleration according to a change of electrostatic capacity between a first weight (i.e. the first movable electrode) made movable according to acceleration and the first fixed electrode. A second sensor section installed in the acceleration sensor is structurally identical with the first sensor section and configured to detect acceleration in second and third directions. Thereby, such combination of the first sensor section and the second sensor section constitutes a three-dimensional acceleration sensor. | 2014-04-03 |
20140091405 | HYBRID INTEGRATED PRESSURE SENSOR COMPONENT - A pressure sensor component includes a MEMS component having at least one pattern element that is able to be deflected perpendicular to the component plane, which is equipped with at least one electrode of a measuring capacitor device, and an ASIC component having integrated circuit elements and at least one back end stack, at least one counter-electrode of the measuring capacitor device being developed in a metallization plane of the back end stack. The MEMS component is mounted on the back end pile of the ASIC component. The MEMS component includes at least one pressure-sensitive diaphragm pattern and is mounted on the ASIC component in such a way that the pressure-sensitive diaphragm pattern spans a cavity between the MEMS component and the back end stack of the ASIC component. | 2014-04-03 |
20140091406 | MEMS Microphone System for Harsh Environments - A MEMS microphone system suited for harsh environments. The system uses an integrated circuit package. A first, solid metal lid covers one face of a ceramic package base that includes a cavity, forming an acoustic chamber. The base includes an aperture through the opposing face of the base for receiving audio signals into the chamber. A MEMS microphone is attached within the chamber about the aperture. A filter covers the aperture opening in the opposing face of the base to prevent contaminants from entering the acoustic chamber. A second metal lid encloses the opposing face of the base and may attach the filter to this face of the base. The lids are electrically connected with vias forming a radio frequency interference shield. The ceramic base material is thermally matched to the silicon microphone material to allow operation over an extended temperature range. | 2014-04-03 |
20140091407 | INTEGRATED SEMICONDUCTOR DEVICES WITH AMORPHOUS SILICON BEAM, METHODS OF MANUFACTURE AND DESIGN STRUCTURE - Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS processes, methods of manufacture and design structures are disclosed. The method includes forming at least one beam comprising amorphous silicon material and providing an insulator material over and adjacent to the amorphous silicon beam. The method further includes forming a via through the insulator material and exposing a material underlying the amorphous silicon beam. The method further includes providing a sacrificial material in the via and over the amorphous silicon beam. The method further includes providing a lid on the sacrificial material and over the insulator material. The method further includes venting, through the lid, the sacrificial material and the underlying material to form an upper cavity above the amorphous silicon beam and a lower cavity below the amorphous silicon beam, respectively. | 2014-04-03 |
20140091408 | SENSOR MODULE AND SEMICONDUCTOR CHIP - A sensor module and semiconductor chip. One embodiment provides a carrier. A semiconductor chip includes a first recess and a second recess and a main surface of the semiconductor chip. The semiconductor chip is mounted to the carrier such that the first recess forms a first cavity with the carrier and the second recess forms a second cavity with the carrier. The first cavity is in fluid connection with the second cavity. | 2014-04-03 |
20140091409 | APPLICATIONS OF CONTACT-TRANSFER PRINTED MEMBRANES - The disclosed embodiments provide sensitive pixel arrays formed using solvent-assisted or unassisted release processes. Exemplary devices include detectors arrays, tunable optical instruments, deflectable mirrors, digital micro-mirrors, digital light processing chips, tunable optical micro-cavity resonators, acoustic sensors, acoustic actuators, acoustic transducer devices and capacitive zipper actuators to name a few. | 2014-04-03 |
20140091410 | Method and Apparatus for Fabricating Piezoresistive Polysilicon by Low-Temperature Metal Induced Crystallization - The present invention provides a method and apparatus for fabricating piezoresistive polysilicon on a substrate by low-temperature metal induced crystallization by: (1) providing the substrate having a passivation layer; (2) performing, at or near room temperature in a chamber without breaking a vacuum or near-vacuum within the chamber, the steps of: (a) creating a metal layer on the passivation layer, and (b) creating an amorphous silicon layer on the metal layer, wherein the metal layer and the amorphous silicon layer have approximately the same thickness; (3) annealing the substrate, the passivation layer, the metal layer and the amorphous silicon layer at a temperature equal to or less than 600° C. and a period of time equal to or less than three hours to form a doped polysilicon layer below a residual metal layer; and (4) removing the residual metal layer to expose the doped polysilicon layer. | 2014-04-03 |
20140091411 | Repeated Spin Current Interconnects - One embodiment includes a metal layer including first and second metal portions; a ferromagnetic layer including a first ferromagnetic portion that directly contacts the first metal portion and a second ferromagnetic portion that directly contacts the second metal portion; and a first metal non-magnetic interconnect coupling the first ferromagnetic portion to the second ferromagnetic portion. The spin interconnect conveys spin polarized current suitable for spin logic circuits. The interconnect may be included in a current repeater such as an inverter or buffer. The interconnect may perform regeneration of spin signals. Some embodiments extend spin interconnects into three dimensions (e.g., vertically across layers of a device) using vertical non-magnetic metal interconnects. Spin interconnects that can communicate spin current without repeated conversion of the current between spin and electrical signals enable spin logic circuits by reducing power requirements, reducing circuit size, and increasing circuit speed. | 2014-04-03 |
20140091412 | Magnetic Sidewalls for Write Lines in Field-Induced MRAM and Methods of Manufacturing Them - In one embodiment, there is provided a non-volatile magnetic memory cell. The non-volatile magnetic memory cell comprises a switchable magnetic element; and a word line and a bit line to energize the switchable magnetic element; wherein at least one of the word line and the bit line comprises a magnetic sidewall that is discontinuous. | 2014-04-03 |
20140091413 | DETECTOR DIODE - The present invention generally relates to a radiation sensor for use particularly in, but by no means exclusively, in measuring radiation dose in photon or electron fields such as for radiation medicine, including radiotherapy and radiation based diagnosis. According to the present invention, there is provided a semiconductor radiation detector comprising a radiation sensitive detector element arranged such that it forms a continuous radiation sensitive portion having surfaces oriented in at least two non-parallel directions. | 2014-04-03 |
20140091414 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a conductive member penetrating through a first semiconductor layer, a first insulator layer, and a third insulator layer, and connecting a first conductor layer with a second conductor layer. The conductive member has a first region containing copper, and a second region containing a material different from the copper is located at least between a first region and the first semiconductor layer, between the first region and the first insulator layer, and between the first region and the third insulator layer. A diffusion coefficient of the copper to a material is lower than a diffusion coefficient of the copper to the first semiconductor layer and a diffusion coefficient of the copper to the first insulator layer. | 2014-04-03 |
20140091415 | SOLID-STATE IMAGING APPARATUS, MANUFACTURING METHOD FOR THE SAME, AND ELECTRONIC APPARATUS - A solid-state imaging apparatus includes a semiconductor substrate, an upper layer film, and on-chip lenses. On the semiconductor substrate, a plurality of pixels are formed. The upper layer film is laminated on the semiconductor substrate. The on-chip lenses are formed on the upper layer film so as to correspond to the respective pixels. A pupil correction amount of one of the on-chip lenses is changed depending on a distance between a center of a pixel area and the on-chip lens, and depending on a film thickness of the upper layer film at a position of the on-chip lens on the upper layer film. | 2014-04-03 |
20140091416 | PHOTOELECTRIC CONVERSION APPARATUS AND MANUFACTURING METHOD FOR A PHOTOELECTRIC CONVERSION APPARATUS - A photoelectric conversion apparatus has multiple photoelectric converting units disposed in a semiconductor substrate, and isolation portions disposed in the semiconductor substrate. Each photoelectric converting unit includes a second semiconductor region, a third semiconductor region, disposed below the second semiconductor region and a fourth semiconductor region disposed below the third semiconductor region. Each isolation portion includes a fifth semiconductor region, placed deeper than the surface of the semiconductor substrate and at least extending laterally to the second semiconductor region, containing a first conductivity type impurity, and a sixth semiconductor region, below the fifth semiconductor region and at least extending laterally to the third semiconductor region, containing the first conductivity type impurity, and the diffusion coefficient of the impurity contained in the fifth semiconductor region is lower than the diffusion coefficient of the impurity contained in the sixth semiconductor region. | 2014-04-03 |
20140091417 | LOW REFRACTIVE INDEX COATING DEPOSITED BY REMOTE PLASMA CVD - A method of depositing a low refractive index coating on a photo-active feature on a substrate comprises forming a substrate having one or more photo-active features thereon and placing the substrate in a process zone. A deposition gas is energized in a remote gas energizer, the deposition gas comprising a fluorocarbon gas and an additive gas. The remotely energized deposition gas is flowed into the process zone to deposit a low refractive index coating on the substrate. | 2014-04-03 |
20140091418 | COLOR FILTER, CCD SENSOR, CMOS SENSOR, ORGANIC CMOS SENSOR, AND SOLID-STATE IMAGE SENSOR - A color filter includes: a red pixel in which a transmittance of a light having a wavelength of 400 nm is 15% or less, and a transmittance of a light having a wavelength of 650 nm is 90% or more; a green pixel in which a transmittance of a light having a wavelength of 450 nm is 5% or less, and a transmittance of a light having a wavelength within a range of from 500 nm to 600 nm is 90% or more; and a blue pixel in which a transmittance of a light having a wavelength of 450 nm is 85% or more, a transmittance of a light having a wavelength of 500 nm is from 10% to 50%, and a transmittance of a light having a wavelength of 700 nm is 10% or less. | 2014-04-03 |
20140091419 | OPTICAL FILTER, SOLID-STATE IMAGING ELEMENT, IMAGING DEVICE LENS AND IMAGING DEVICE - The present invention relates to an optical filter, a solid-state imaging element and an imaging device lens which contain a near infrared ray absorbing layer having a specific near infrared ray absorbing dye dispersed in a transparent resin having a refractive index of 1.54 or more, and also relates to an imaging device containing the solid-state imaging element or the imaging device lens. The near infrared ray absorbing layer has a transmittance of visible light of from 450 to 600 nm of 70% or more, a transmittance of light in a wavelength region of from 695 to 720 nm of not more than 10%, and an amount of change of transmittance of not more than −0.8 | 2014-04-03 |
20140091420 | METHOD OF MONOLITHICALLY INTEGRATED OPTOELECTRICS - A monolithically integrated sensor is disclosed in the form of light detector(s), visible light emitter(s) and associated control circuit(s) monolithically integrated on a single silicon microchip. The detector structures consist of p-i-n photodiode structures, both diffused into and deposited on the surface of the silicon substrate. The emitter structures consist of III-V compound semiconductor hetero-epitaxial layers deposited on the surface of the silicon substrate. The control circuits are fabricated using traditional CMOS high volume manufacturing techniques. The sensor assembly is designed to be processed in a traditional CMOS wafer fab. The sensor assembly is further designed to be packaged at the wafer level. | 2014-04-03 |
20140091421 | SOLID-STATE IMAGE PICKUP ELEMENT AND SOLID-STATE IMAGE PICKUP ELEMENT MOUNTING STRUCTURE - A solid-state image pickup element is provided with a semiconductor substrate having a photosensitive region, a plurality of first electrode pads arrayed on a principal face of the semiconductor substrate, a plurality of second electrode pads arrayed in a direction along a direction in which the plurality of first electrode pads are arrayed, on the principal face of the semiconductor substrate, and a plurality of interconnections connecting the plurality of first electrode pads and the plurality of second electrode pads in one-to-one correspondence. The plurality of interconnections connect the first and second electrode pads so that each interconnection connects the first electrode pad and the second electrode pad in a positional relation of line symmetry with respect to a center line perpendicular to the array directions of the plurality of first and second electrode pads. | 2014-04-03 |
20140091422 | Thin Film with Improved Temperature Range - A device and a method of forming the same are disclosed. The device comprises a substrate and a thin film. The substrate is characterized by a first coefficient of thermal expansion. The thin film is attached to a surface of the substrate, and is characterized by a second coefficient of thermal expansion. The thin film includes first and second layers in states of compression, and a third layer in a state of tension, the third layer being positioned between the first and second layers. The thin film is in a net state of tension within a temperature range. | 2014-04-03 |
20140091423 | Infrared photosensor - A thermal diode for a photosensor of a thermal imaging camera includes a semiconductor substrate having a surface and two doped structures set apart from each other on the surface. Furthermore, a device is provided for influencing a current between the first and the second structure, in order to reduce a current density in an area near to the surface and to increase it in an area far from the surface. In addition, a topology having an even absorption layer is proposed. The measures proposed have the aim of realizing a low-noise diode for thermal applications. | 2014-04-03 |
20140091424 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A compound semiconductor device includes: a compound semiconductor layer; a protective insulating film that covers a top of the compound semiconductor layer and has an opening formed thereon; and an electrode that fills the opening, that is brought into contact with the compound semiconductor layer, and that is formed on the protective insulating film, in which an orientation state of a contact portion between the electrode and the compound semiconductor layer and an orientation state of a contact portion between the electrode and the protective insulating film are the same. | 2014-04-03 |
20140091425 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a semiconductor integrated circuit device including fuse elements for performing laser trimming processing, a dummy fuse formed of a first polycrystalline Si film is formed between the fuse elements formed of a second polycrystalline Si film, and a nitride film is formed on the dummy fuse. In this manner, the step difference of an interlayer film caused by the presence and absence of the fuse element formed of the polycrystalline Si film is eliminated, to thereby prevent SOG films having moisture-absorption characteristics on an inner surface of a fuse opening region and on an internal element side from connecting to each other. | 2014-04-03 |
20140091426 | Capacitor and Method for Making Same - A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth. | 2014-04-03 |
20140091427 | ELECTRICAL FUSE AND METHOD OF FABRICATING THE SAME - An electrical fuse is provided. The electrical fuse includes an anode formed on a substrate, a cathode formed on the substrate, a fuse link connecting the anode and the cathode to each other, a first contact formed on the anode, and a second contact formed on the cathode and arranged closer to the fuse link than the first contact. | 2014-04-03 |
20140091428 | LAND SIDE AND DIE SIDE CAVITIES TO REDUCE PACKAGE Z-HEIGHT - A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB. | 2014-04-03 |
20140091429 | MULTILAYER DIELECTRIC MEMORY DEVICE - A memory device has multiple dielectric barrier regions. A memory device has multiple barrier regions that provide higher or lower current-voltage slope compared to a memory device having a single barrier region. The device also has electrode regions that provide further control over the current-voltage relationship. | 2014-04-03 |
20140091430 | SEMICONDUCTOR DEVICE INCLUDING OPERATIVE CAPACITORS AND DUMMY CAPACITORS - The semiconductor device according to the present invention comprises a plurality of actually operative capacitors formed, arranged in an actually operative capacitor part over a semiconductor substrate and each including a lower electrode, a ferroelectric film and an upper electrode; a plurality of dummy capacitors formed, arranged in a dummy capacitor part provided outside of the actually operative capacitor part over the semiconductor substrate and each including the lower electrode, the ferroelectric film and the upper electrode; a plurality of interconnections respectively formed on said plurality of the actually operative capacitors and respectively connected to the upper electrodes of said plurality of the actually operative capacitors; and the interconnections respectively formed on said plurality of the dummy capacitors. | 2014-04-03 |
20140091431 | SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method includes forming a first capacitance film formed on the lower electrode; forming an intermediate electrode in a first region on the first capacitance film, wherein the first capacitance is interposed between the intermediate electrode and the lower electrode; forming a second capacitance film on the intermediate electrode to be interposed between the first capacitance film and the second capacitance film; and forming an upper electrode, wherein at least a portion of the second capacitance film is interposed between the upper electrode and the intermediate electrode; the upper electrode extending to a second region outside the first region, and having at least the first capacitance film interposed between the upper electrode and the lower electrode in the second region. | 2014-04-03 |
20140091432 | CERAMIC POWDER, SEMICONDUCTOR CERAMIC CAPACITOR, AND METHOD FOR MANUFACTURING SAME - A ceramic powder for use in a grain boundary insulated semiconductor ceramic that has an excellent ESD withstanding voltage, a semiconductor ceramic capacitor using the ceramic powder, and a manufacturing method therefor. The ceramic powder for use in a SrTiO | 2014-04-03 |
20140091433 | METHOD OF PRODUCING SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER - There is provided a method of producing a semiconductor wafer, including: forming a compound semiconductor layer on a base wafer by epitaxial growth; cleansing a surface of the compound semiconductor layer by means of a cleansing agent containing a selenium compound; and forming an insulating layer on the surface of the compound semiconductor layer. Examples of the selenium compound include a selenium oxide. Examples of the selenium oxide include H | 2014-04-03 |
20140091434 | Patterned Bases, and Patterning Methods - Some embodiments include methods of patterning a base. First and second masking features are formed over the base. The first and second masking features include pedestals of carbon-containing material capped with silicon oxynitride. A mask is formed over the second masking features, and the silicon oxynitride caps are removed from the first masking features. Spacers are formed along sidewalls of the first masking features. The mask and the carbon-containing material of the first masking features are removed. Patterns of the spacers and second masking features are transferred into one or more materials of the base to pattern said one or more materials. Some embodiments include patterned bases. | 2014-04-03 |
20140091435 | Etching of Block-Copolymers - The present disclosure relates to a method ( | 2014-04-03 |
20140091436 | EPITAXIAL STRUCTURE - An epitaxial structure is provided. The epitaxial structure includes a substrate, an first epitaxial layer, a second epitaxial layer, a first carbon nanotube layer and a second carbon nanotube layer. The first epitaxial layer is located on the substrate. The first carbon nanotube layer is located between the substrate and the first epitaxial layer. The second epitaxial layer is located on the first epitaxial layer. The second carbon nanotube layer is located between the first epitaxial layer and the second epitaxial layer. | 2014-04-03 |
20140091437 | CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A package includes a semiconductor device including an active surface having a contact pad. A redistribution layer (RDL) structure includes a first post-passivation interconnection (PPI) line electrically connected to the contact pad and extending on the active surface of the semiconductor device. An under-bump metallurgy (UBM) layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer. | 2014-04-03 |
20140091438 | MULTIPLE METAL LAYER SEMICONDUCTOR DEVICE AND LOW TEMPERATURE STACKING METHOD OF FABRICATING THE SAME - A semiconductor device including a conductive element and an interface surface fabricated atop the conductive element, and a method for fabricating such a device are described. An exemplary device includes a substrate having a conductive element and a metal layer fabricated atop the conductive element. An oxide layer is fabricated atop the metal layer, thus forming an interface surface. During polishing (e.g., planarization), in which an upper portion of the interface surface is removed, the presence of the interface surface greatly reduces the loading on the conductive element. A second substrate fabricated using the same process may be stacked atop the first substrate and bonded using a hybrid bonding process. | 2014-04-03 |
20140091439 | SILICON SHAPING - One embodiment for forming a shaped substrate for an electronic device can form a shaped perimeter to define the substrate shape on the surface of a substrate. The shaped perimeter can extend at least part way into the substrate. A subsequent thinning process can remove substrate material and expose the shaped perimeter effectively forming shaped dies from the substrate. | 2014-04-03 |
20140091440 | SYSTEM IN PACKAGE WITH EMBEDDED RF DIE IN CORELESS SUBSTRATE - Electronic assemblies and their manufacture are described. One assembly includes a coreless substrate comprising a plurality of dielectric layers and electrically conductive pathways, the coreless substrate including a first side and a second side opposite the first side. The assembly includes a first die embedded in the coreless substrate, the first die comprising an RF die, the first die positioned in a dielectric layer that extends to the first side of the coreless substrate. The assembly includes a second die positioned on first side, the second die positioned on the first die. In another aspect, a molding material may be positioned on the die side, wherein the first die and the second die are covered by the molding material. In another aspect, an electrical shielding layer may be positioned over the first side. Other embodiments are described and claimed. | 2014-04-03 |
20140091441 | IC WAFER HAVING ELECTROMAGNETIC SHIELDING EFFECTS AND METHOD FOR MAKING THE SAME - An IC wafer and the method of making the IC wafer, the IC wafer includes an integrated circuit layer having a plurality of solder pads and an insulated layer arranged thereon, a plurality of through holes cut through the insulated layer corresponding to the solder pads respectively for the implantation of a package layer, and an electromagnetic shielding layer formed on the top surface of the insulated layer and electrically isolated from the solder pads of the integrated circuit layer for electromagnetic shielding. Thus, the integrated circuit does not require any further shielding mask, simplifying the fabrication. Further, the design of the through holes facilitates further packaging process. | 2014-04-03 |
20140091442 | HIGH DENSITY SECOND LEVEL INTERCONNECTION FOR BUMPLESS BUILD UP LAYER (BBUL) PACKAGING TECHNOLOGY - An apparatus including a die including a device side; and a build-up carrier including a body including a plurality of alternating layers of conductive material and dielectric material disposed on the device side of the die, an ultimate conductive layer patterned into a plurality of pads or lands; and a grid array including a plurality of conductive posts disposed on respective ones of the plurality of pads of the ultimate conductive layer of the body, at least one of the posts coupled to at least one of the contact points of the die through at least a portion of the conductive material of the body. A method including forming a body of a build-up carrier including a die, the body of the build-up carrier including an ultimate conductive layer and forming a grid array including a plurality of conductive posts on the ultimate conductive layer of the body. | 2014-04-03 |