14th week of 2009 patent applcation highlights part 39 |
Patent application number | Title | Published |
20090087929 | METHOD AND SYSTEM FOR IMPROVING WET CHEMICAL BATH PROCESS STABILITY AND PRODUCTIVITY IN SEMICONDUCTOR MANUFACTURING - A chemical processing bath and system used in semiconductor manufacturing utilizes a dynamic spiking model that essentially constantly monitors chemical concentration in the processing bath and adds fresh chemical on a regular basis to maintain chemical concentrations at desirable levels. Etch rates and etch selectivities are maintained at desirable levels and contamination from undesirable precipitation is avoided. The system and method automatically compare concentration levels to a plurality of control limits associated with various technologies and identify the technology or technologies that may undergo processing. | 2009-04-02 |
20090087930 | Inspection System, Inspection Method, and Method for Manufacturing Semiconductor Device - The present invention provides an inspection system of ID chips that can supply a signal or power supply voltage to an ID chip without contact, and can increase throughput of an inspection process and an inspection method using the inspection system. The inspection system according to the present invention includes a plurality of inspection electrodes, a plurality of inspection antennas, a position control unit, a unit for applying voltage to each of the inspection antennas, and a unit for measuring potentials of the inspection electrodes. One feature of the inspection system is that a plurality of ID chips and the plurality of inspection electrodes are overlapped with a certain space therebetween, and the plurality of ID chips and the plurality of inspection antennas are overlapped with a certain space therebetween, and the plurality of ID chips are interposed between the plurality of inspection electrodes and the plurality of inspection antennas by the position control unit. | 2009-04-02 |
20090087931 | METHOD OF MANUFACTURING LIGHT EMITTING DIODE PACKAGE - Provided is a method of manufacturing an LED package, the method including preparing a mold die which includes an upper surface and a lower surface having an outer circumferential surface and a concave surface surrounded by the outer circumferential surface, the mold die having an outlet extending from the upper surface to the lower surface; preparing a base having a light emitting section formed therein; forming an inlet formed in a predetermined region of the base excluding the region where the light emitting section is formed; positioning the mold die on the light emitting section; forming a mold member by injecting a molding compound into the inlet of the base; and removing the mold die. | 2009-04-02 |
20090087932 | SUBSTRATE SUPPORTING APPARATUS, SUBSTRATE SUPPORTING METHOD, SEMICONDUCTOR MANUFACTURING APPARATUS AND STORAGE MEDIUM - A substrate supporting apparatus includes a substrate supporting portion having a substrate supporting surface facing a rear surface of a substrate; plural protruding portions provided on the substrate supporting surface, for preventing the substrate from being slid on the substrate supporting surface by friction force generated in relation with the substrate; a gas discharge opening provided in the substrate supporting surface, for discharging gas toward the rear surface of the substrate; a gas flow path whose one end is connected to the gas discharge opening; and a temperature control unit for controlling temperature of the gas flowing through the gas flow path, wherein the gas discharged to the rear surface of the substrate flows in a gap between the substrate supporting surface and the substrate, and by Bernoulli effect causing reduction of pressure of the gap, the substrate is attracted to the substrate supporting portion, thereby supporting the substrate. | 2009-04-02 |
20090087933 | Thin Film Transistor Substrate for a Liquid Crystal Display Wherein a Black Matrix Formed on the Substrate Comprises an Inner Aperture Formed Completely Within the Black Matrix - Disclosed is a thin film transistor substrate for a liquid crystal display and a method for repairing the substrate. The substrate comprises an insulating substrate; a black matrix formed on the insulating substrate having apertures in areas of pixels, shaped as a net; an insulating layer covering the black matrix; gate wiring formed on the insulating layer, the gate wiring including gate lines extended in a first direction across the substrate and gate electrodes connected to the gate lines; a gate insulating layer formed over the gate wiring; a semiconductor layer formed over the gate insulating layer; an ohmic contact layer formed over the semiconductor layer; data wiring including source electrodes and drain electrodes formed separated from each other over the ohmic contact layer, and data lines connected to the source electrodes and crossing the gate lines to define pixels; a protection layer formed over the data wiring; and pixel electrodes electrically connected to the drain electrodes. The method comprises the step of shorting the disconnected gate line and the first portion of the black matrix or the disconnected data line and the second portion of the black matrix. | 2009-04-02 |
20090087934 | Method of Manufacturing Nitride Semiconductor Light Emitting Element - In a method for manufacturing a III-V nitride compound semiconductor light emitting element, light emitting element regions ( | 2009-04-02 |
20090087935 | Fabricating method for quantum dot of active layer of LED by nano-lithography - The present invention is to provide a “fabricating method for quantum dot active layer of LED by nano-lithography” for fabricating out a new active layer of LED of nano quantum dot structure in more miniature manner than that of the current fabricating facilities to have high quality LED with features in longer light wavelength, brighter luminance and lower forward bias voltage by directly using the current fabricating facilities without any alteration or redesign of the precision. | 2009-04-02 |
20090087936 | DEPOSITION METHOD OF III GROUP NITRIDE COMPOUND SEMICONDUCTOR LAMINATED STRUCTURE - The present invention provides a deposition method of a multilayered structure composed of a III group nitride compound semiconductor having good crystallinity on a substrate. The multilayered structure comprises at least a buffer layer and an underlying layer from the substrate side, and the buffer layer and the underlying layer are formed by a sputtering method. A deposition temperature of the buffer layer is adjusted to a temperature lower than a deposition temperature of the underlying layer, or the thickness of the buffer layer is adjusted to 5 nm to 500 nm. Furthermore, the multilayered structure comprises at least an underlying layer and a light-emissive layer from the substrate side and the underlying layer is formed by a sputtering method, and the method comprises the step of forming the light-emissive layer by a metal-organic chemical vapor deposition (MOCVD method). | 2009-04-02 |
20090087937 | METHOD FOR MANUFACTURING NITRIDE BASED SINGLE CRYSTAL SUBSTRATE AND METHOD FOR MANUFACTURING NITRIDE BASED LIGHT EMITTING DIODE USING THE SAME - A method for manufacturing a nitride based single crystal substrate and a method for manufacturing a nitride based light emitting diode using the same. The method for manufacturing the nitride based single crystal substrate includes forming a ZnO layer on a base substrate; forming a low-temperature nitride buffer layer on the ZnO layer using dimethyl hydragine (DMHy) as an N source; growing a nitride single crystal on the low-temperature nitride buffer layer; and separating the nitride single crystal from the base substrate by chemically eliminating the ZnO layer. | 2009-04-02 |
20090087938 | Method for Manufacturing Microdevices or Integrated Circuits on Continuous Sheets - Current manufacturing of miniature or micro electronic mechanical optical chemical or biophysical devices utilizes discrete substrates holding one or more said devices. The use of discrete substrates entails several disadvantages with respect to economical manufacturing. This invention is a method of manufacturing devices using flexible carrier sheets with device substrates attached to the carrier sheet, storage/transport devices for the carrier sheet, and process tools capable of continuous processing of the carrier sheets. | 2009-04-02 |
20090087939 | COLUMN STRUCTURE THIN FILM MATERIAL USING METAL OXIDE BEARING SEMICONDUCTOR MATERIAL FOR SOLAR CELL DEVICES - A thin film material structure for solar cell devices. The thin film material structure includes a thickness of material comprises a plurality of single crystal structures. In a specific embodiment, each of the single crystal structure is configured in a column like shape. The column like shape has a dimension of about 0.01 micron to about 10 microns characterizes a first end and a second end. An optical absorption coefficient of greater than 10 | 2009-04-02 |
20090087940 | Method of Successive High-Resistance Buffer Layer/Window Layer (Transparent Conductive Film) Formation for CIS Based Thin-Film Solar Cell and Apparatus for Successive Film Formation for Practicing the Method of Successive Film Formation - A high-resistance buffer layer and a window layer (transparent conductive film) are successively formed by the MOCVD method to obtain the same output characteristics as in conventional film deposition by the solution deposition method and to simplify a film deposition method and apparatus. Thus, the cost of raw materials and the cost of waste treatments are reduced to attain a considerable reduction in production cost. | 2009-04-02 |
20090087941 | Method for producing multijunction solar cell - There is provided a method for producing a multijunction solar cell having four-junctions, the method allowing the area of a device to be increased. On a nucleation site formed on a substrate | 2009-04-02 |
20090087942 | Manufacture of Photovoltaic Devices - A method and apparatus for depositing a film on a substrate includes subjecting material to an energy beam. | 2009-04-02 |
20090087943 | METHOD FOR FORMING LARGE GRAIN POLYSILICON THIN FILM MATERIAL - A method of forming polysilicon thin film material for photovoltaic devices. The method includes providing a polycrystalline silicon substrate. The polycrystalline silicon substrate includes a surface region, a backside region, and a thickness. In a specific embodiment, the method forms a polysilicon thin film material using a deposition process overlying the surface region of the polycrystalline silicon substrate. The polysilicon thin film material is characterized by a grain size greater than about 0.1 mm. | 2009-04-02 |
20090087944 | ELECTRONIC DEVICES WITH HYBRID HIGH-K DIELECTRIC AND FABRICATION METHODS THEREOF - Electronic devices with hybrid high-k dielectric and fabrication methods thereof. The electronic device includes a substrate. A first electrode is disposed on the substrate. Hybrid high-k multi-layers comprising a first dielectric layer and a second dielectric layer are disposed on the substrate, wherein the first dielectric layer and the second dielectric layer are solvable and substantially without interface therebetween. A second electrode is formed on the hybrid multi-layers. | 2009-04-02 |
20090087945 | Phase change memory cell with roundless micro-trenches - A method for constructing a phase change memory device includes forming a first dielectric layer on a substrate; forming a first conductive component in the first dielectric layer; forming a second dielectric layer over the first conductive component in the first dielectric layer; forming a conductive crown in the second dielectric layer, the conductive crown being in contact and alignment with the conductive component; depositing a third dielectric layer in the conductive crown; and forming a trench filled with chalcogenic materials having an amorphous phase and a crystalline phase programmable by controlling a temperature thereof to represent logic states, wherein the trench extends across the conductive crown, such that the trench is free from a rounded end portion caused by lithography during fabrication of the phase change memory device. | 2009-04-02 |
20090087946 | STRUCTURE AND METHOD FOR THIN SINGLE OR MULTICHIP SEMICONDUCTOR QFN PACKAGES - A semiconductor device ( | 2009-04-02 |
20090087947 | FLIP CHIP PACKAGE PROCESS - A flip chip package process is provided. First, a substrate strip including at least one substrate is provided. Next, at least one chip is disposed on the substrate, and the chip is electrically connected to the substrate. Then, a stencil having at least one opening and an air slot hole is disposed on an upper surface of the substrate strip, an air gap is formed between the stencil and the substrate strip, the air gap connects the opening and the air slot hole, and the chip is located in the opening. Finally, a liquid compound is formed into the opening of the stencil to encapsulate the chip, and a vacuum process is performed through the air slot hole and the air gap, so as to prevent the air inside the opening from being encapsulated by the liquid compound to become voids. | 2009-04-02 |
20090087948 | FLIP CHIP PACKAGE WITH ADVANCED ELECTRICAL AND THERMAL PROPERTIES FOR HIGH CURRENT DESIGNS - A QFN package and method of making same is provided comprising a substrate having a metal line extending from a connection element on a perimeter region of the substrate to a high current contact pad on interior region of the substrate. A semiconductor chip having an active surface generally faces the interior region of the substrate, wherein a heat-dissipating patterned metal distribution layer is formed over the active surface and electrically connected to an active component thereon. A solder strip electrically and thermally connects the high current contact pad and the metal distribution layer, and a mold compound generally encapsulates the semiconductor chip. The solder strip is generally uniform in depth and surface area, wherein low electrical resistance and inductance is provided between the high current contact pad and the metal distribution layer. An integrated heat sink may be further formed or placed on a passive surface of the chip. | 2009-04-02 |
20090087949 | Method of Making a Microelectronic Package Using an IHS Stiffener - A method of making a microelectronic package. The method includes: providing a carrier; providing a tacky pad on the carrier; placing a die onto the tacky pad such that an active surface of the die adheres to the tacky pad, bonding an IHS onto a backside of the die after placing to form a die-IHS combination, removing the die-IHS combination from the tacky pad; and mounting the die-IHS combination onto a package substrate to form the package. | 2009-04-02 |
20090087950 | Wafer packaging method - A wafer packaging method is disclosed. | 2009-04-02 |
20090087951 | Method of manufacturing wafer level package - A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased. | 2009-04-02 |
20090087952 | Void free soldering semiconductor chip attachment method for wafer scale chip size - Methods for attaching the wafer scale semiconductor chip, up to 4 square inch (2.times.2 inchs), are comprises of following steps. Stack assembles following materials from bottom to top. First lower integrated heat spreader (IHS). Second thermal interface material (TIM). Third semiconductor chip with backside metallization deposit. Forth polyimide film. Fifth the dummy upper IHS. Then put the stack-assembled set into the metal box and fix in place. Then the metal box and stack-assembled set in it are heated to wetting temperature of TIM. During cool down, the environment temperature must be set at a few degrees lower than the melting point of TIM, to soak the stack-assembled set at melting point of TIM until the TIM completely become solid, then cool down to room temperature. After de-assemble and remove upper IHS and polyimide film, we will get the void free soldering of semiconductor chip on lower IHS. | 2009-04-02 |
20090087953 | Manufacturing process of leadframe-based BGA packages - A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed. | 2009-04-02 |
20090087954 | METHOD FOR FABRICATING PIXEL STRUCTURE - A method for fabricating a pixel structure using a laser ablation process is provided. This fabrication method forms a gate, a channel layer, a source, a drain, a passivation layer, and a pixel electrode sequentially by using a laser ablation process. Particularly, the fabrication method is not similar to a photolithography and etching process, so as to reduce the complicated photolithography and etching processes, such as spin coating process, soft-bake, hard-bake, exposure, developing, etching, and stripping. Therefore, the fabrication method simplifies the process and thus reduces the fabrication cost. | 2009-04-02 |
20090087955 | METHOD FOR REMOVING HARD MASKS ON GATES IN SEMICONDUCTOR MANUFACTURING PROCESS - A method for removing hard masks on gates in a semiconductor manufacturing process is conducted as follows. First of all, a first gate and a second gate with hard masks are formed on a semiconductor substrate, wherein the second gate is larger than the first gate. The first gate and second gate could be associated with silicon-germanium (SiGe) source and drain regions to form p-type transistors. Next, a photoresist layer is deposited, and an opening of the photoresist layer is formed on the hard mask of the second gate. Then, the photoresist layer on the first and second gates is removed completely by etching back. Because there is no photoresist residue, the hard masks on the first and second gates can be removed completely afterwards. | 2009-04-02 |
20090087956 | Dummy Contact Fill to Improve Post Contact Chemical Mechanical Polish Topography - State of the art Integrated Circuits (ICs) encompass a variety of circuits, which have a wide variety of contact densities as measured in regions from 10 to 1000 microns in size. Fabrication processes for contacts have difficulty with high and low contact densities on the same IC, leading to a high incidence of electrical shorts and reduced operating speed of the circuits. This problem is expected to worsen as feature sizes shrink in future technology nodes. This invention is an electrically non-functional contact, known as a dummy contact, that is utilized to attain a more uniform distribution of contacts across an IC, which allows contact fabrication processes to produce ICs with fewer defects, and a method for forming said dummy contacts in ICs. | 2009-04-02 |
20090087957 | Method of fabricating semiconductor device - Photoresist on a metal is removed with less oxidation of the metal surface by the invented ashing. During process, the matching of oxygen gas ratio and wafer temperature under downstream plasma which means no RF bias plasma is controlled for oxidation amount not to depend on ashing time with required photo resist rate in manufacturing. | 2009-04-02 |
20090087958 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof which enable to secure high yield and increase the capacity of a capacitor are provided. The semiconductor device according to the present invention includes: a plurality of capacitor layers laminated, each capacitor layer including a plurality of storage electrodes, a capacity insulating film covering the surface of the storage electrodes, and a plate electrode provided between the storage electrodes, wherein the plate electrode of each of the laminated capacitor layers are electrically connected to each other and the corresponding storage electrode of each of the laminated capacitor layers are electrically connected to each other. | 2009-04-02 |
20090087959 | METHOD FOR FORMING A PATTERN OF A SEMICONDUCTOR DEVICE - In a method for forming a fine pattern of a semiconductor device, forming a spacer for double patterning of a cell region is performed separate from forming a mask pattern that defines a dummy pattern for a pad of a peripheral circuit region. | 2009-04-02 |
20090087960 | METHOD FOR FABRICATING RECESS GATE IN SEMICONDUCTOR DEVICE - A method for fabricating a recess gate in a semiconductor device includes etching a silicon substrate to form a trench that defines an active region, forming a device isolation layer that gap-fills the trench, forming a hard mask layer over the silicon substrate, the hard mask layer comprising a stack of an oxide layer and an amorphous carbon layer, wherein the hard mask layer exposes a channel target region of the active region, and forming a recess region with a dual profile by first etching and second etching the channel target region using the hard mask layer as an etch barrier, wherein the second etching is performed after removing the amorphous carbon layer. | 2009-04-02 |
20090087961 | Process for fabricating semiconductor structures useful for the production of semiconductor-on-insulator substrates, and its applications - The invention relates to a process for fabricating a semiconductor structure, which comprises:
| 2009-04-02 |
20090087962 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING ALIGNMENT KEY AND SEMICONDUCTOR DEVICE FABRICATED THEREBY - In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a semiconductor substrate having a scribe lane region and a cell region. An etch barrier pattern and a gate pattern are formed on the scribe lane region and the cell region respectively. A first interlayer insulating layer is formed to cover the etch barrier pattern and the gate pattern. A preliminary alignment key pattern and a bit line pattern are formed on the first interlayer insulating layer of the scribe lane region and the cell region respectively. A second interlayer insulating layer is formed to cover the preliminary alignment key pattern and the bit line pattern. The second interlayer insulating layer and the first interlayer insulating layer are patterned to expose the etch barrier pattern, thereby forming an alignment key pattern in the scribe lane region, and concurrently, forming a storage node contact opening in the cell region. | 2009-04-02 |
20090087963 | METHOD FOR REDUCING PILLAR STRUCTURE DIMENSIONS OF A SEMICONDUCTOR DEVICE - A method creates pillar structures on a semiconductor wafer and includes the steps of providing a layer of semiconductor. A layer of photoresist is applied over the layer of semiconductor. The layer of photoresist is exposed with an initial pattern of light to effect the layer of photoresist. The photoresist layer is then etched away to provide a photoresist pattern to create the pillar structures. The photoresist pattern is processed in the layer of photoresist after the step of exposing the layer of photoresist and prior to the step of etching to reduce the dimensions of the photoresist pattern in the layer of photoresist. | 2009-04-02 |
20090087964 | Manufacturing Method of Semiconductor Device and Substrate Processing Apparatus - To realize a high productivity while maintaining excellent film deposition characteristics on a substrate even if a plurality of processing gases of different gas species are used. There are provided the step of loading a plurality of substrates into a processing chamber; supplying a first processing gas to an upper stream side of a gas flow outside of a region where a plurality of substrates loaded into a processing chamber are arranged, supplying a second processing gas to the upper stream side of the gas flow outside of the region where the plurality of substrates loaded into the processing chamber are arranged, supplying the first processing gas to a middle part of the gas flow in the region where the plurality of substrates loaded into the processing chamber are arranged, and causing the first processing gas and the second processing gas to react with each other in the processing chamber, to form an amorphous material and form a thin film on main surfaces of the plurality of substrates; and the step of unloading the substrate after forming the thin film from the processing camber. | 2009-04-02 |
20090087965 | STRUCTURE AND METHOD FOR MANUFACTURING PHASE CHANGE MEMORIES - A method for manufacturing at least one resistively switching memory cell including generating a first electrode; depositing a phase change material layer, the phase change material layer including a composition of formula Ga | 2009-04-02 |
20090087966 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor film is formed on a GaAs substrate (semiconductor substrate). An SiO | 2009-04-02 |
20090087967 | PRECURSORS AND PROCESSES FOR LOW TEMPERATURE SELECTIVE EPITAXIAL GROWTH - This invention generally relates to low temperature epitaxy. More specifically, this invention relates to processes for achieving low temperature selective epitaxial growth by chemical vapor deposition of source precursors containing Si or Ge in the presence of bromine or iodine, compositions containing precursors and brominated or iodinated compounds suitable for achieving selective epitaxial growth using the processes, epitaxial layers made using the processes, devices and other types of structures made using the processes, and processes for cleaning epitaxy reactor chambers using a bromine etchant source. | 2009-04-02 |
20090087968 | METHOD FOR FABRICATING FINE PATTERN IN SEMICONDUCTOR DEVICE - A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist over a substrate where an etch target layer is formed, doping at least one impurity selected from group III elements and group V elements, of the periodic table, into the first photoresist, forming a photoresist pattern over the first photoresist, performing a dry etching process using the photoresist pattern to expose the first photoresist, etching the first photoresist by an oxygen-based dry etching to form a first photoresist pattern where a doped region is oxidized, and etching the etch target layer using the first photoresist pattern as an etch barrier. | 2009-04-02 |
20090087969 | METHOD TO IMPROVE A COPPER/DIELECTRIC INTERFACE IN SEMICONDUCTOR DEVICES - Embodiments of methods for improving a copper/dielectric interface in semiconductor devices are generally described herein. Other embodiments may be described and claimed. | 2009-04-02 |
20090087970 | Method of producing a dopant gas species - This invention relates to a method of producing B | 2009-04-02 |
20090087971 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICES WITH REDUCED JUNCTION DIFFUSION - A transistor which includes halo regions disposed in a substrate adjacent to opposing sides of the gate. The halo regions have upper and lower regions. The upper region is a crystalline region with excess vacancies and the lower region is an amorphous region. Source/drain diffusion regions are disposed in the halo regions. The source/drain diffusion regions overlap the upper and lower halo regions. This architecture offers the minimal extension resistance as well as minimum lateral diffusion for better CMOS device scaling. | 2009-04-02 |
20090087972 | FORMATION OF CARBON AND SEMICONDUCTOR NANOMATERIALS USING MOLECULAR ASSEMBLIES - The invention is directed to a method of forming carbon nanomaterials or semiconductor nanomaterials. The method comprises providing a substrate and attaching a molecular precursor to the substrate. The molecular precursor includes a surface binding group for attachment to the substrate and a binding group for attachment of metal-containing species. The metal-containing, species is selected from a metal cation, metal compound, or metal or metal-oxide nanoparticle to form a metallized molecular precursor. The metallized molecular precursor is then subjected to a heat treatment to provide a catalytic site from which the carbon nanomaterials or semiconductor nanomaterials form. The heating of the metallized molecular precursor is conducted under conditions suitable for chemical vapor deposition of the carbon nanomaterials or semiconductor nanomaterials. | 2009-04-02 |
20090087973 | RETENTION IMPROVEMENT IN DUAL-GATE MEMORY - A manufacturing process improves retention capabilties of dual-gate non-volatile memory cells by limiting the effects of lateral charge movement. The process limits lateral extents of the charge storage medium that is an integral part of the memory device within the dual-gate device. | 2009-04-02 |
20090087974 | METHOD OF FORMING HIGH-K GATE ELECTRODE STRUCTURES AFTER TRANSISTOR FABRICATION - A sophisticated high-k metal gate electrode structure may be formed after the deposition of a first part of an interlayer dielectric material, thereby providing a high degree of process compatibility with conventional CMOS techniques. Thus, sophisticated strain-inducing mechanisms may be readily implemented in the overall process flow, while nevertheless avoiding any high temperature processes during the formation of the sophisticated high-k dielectric gate stack. | 2009-04-02 |
20090087975 | METHOD FOR MANUFACTURING A MEMORY - A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer. | 2009-04-02 |
20090087976 | Conductive Spacers Extended Floating Gates - A method for manufacturing on a substrate a semiconductor device with a floating-gate and a control-gate. The method includes the steps of first forming an isolation zone in the substrate, and thereafter forming the floating gate on the substrate. The method further includes extending the floating gate using spacers, and then forming the control gate over the floating gate and the spacers. | 2009-04-02 |
20090087977 | LOW TEMPERATURE CONFORMAL OXIDE FORMATION AND APPLICATIONS - The present invention generally provides apparatus and method for processing a semiconductor substrate. Particularly, embodiments of the present invention relate to a method and apparatus for forming semiconductor devices having a conformal silicon oxide layer formed at low temperature. One embodiment of the present invention provides a method for forming a semiconductor gate structure. The method comprises forming a gate stack on a semiconductor substrate, forming a conformal silicon oxide layer on the semiconductor substrate using a low temperature cyclic method, and forming a spacer layer on the conformal silicon oxide layer. | 2009-04-02 |
20090087978 | INTERCONNECT MANUFACTURING PROCESS - An interconnect process is provided. A substrate is provided. A plurality of gate structures is disposed on the substrate, and doped regions are disposed in the substrate and respectively located between two adjacent gate structure. A liner is conformally formed above the substrate. A dielectric layer is formed above the substrate. A contact opening is formed in the dielectric layer between two neighboring gate structures to expose the liner on the doped region and on a portion of the top surface and a portion of the sidewall of each of the gate structures. A polymer material is deposited on the liner on the portion of the top surface of each of the gate structures and on the doped region. The liner on the doped regions is removed. A conductive layer is filled in the contact opening, which is free of electrical connection to the gate structures. | 2009-04-02 |
20090087979 | DUAL DAMASCENE WITH AMORPHOUS CARBON FOR 3D DEEP VIA/TRENCH APPLICATION - A method for fabricating a 3-D monolithic memory device in which a via and trench are etched using an amorphous carbon hard mask. The via extends in multiple levels of the device as a multi-level vertical interconnect. The trench extends laterally, such as to provide a word line or bit line for memory cells, or to provide other routing paths. A dual damascene process can be used in which the via is formed first and the trench is formed second, or the trench is formed first and the via is formed second. The technique is particularly suitable for deep via applications, such as for via depths of greater than 1 μm. A dielectric antireflective coating, optionally with a bottom antireflective coating, can be used to etch an amorphous carbon layer to provide the amorphous carbon hard mask. | 2009-04-02 |
20090087980 | METHODS OF LOW-K DIELECTRIC AND METAL PROCESS INTEGRATION - An integrated process for forming metallization layers for electronic devices that use damascene structures that include low-k dielectric and metal. According to one embodiment of the present invention, the integrated process includes planarizing a gapfill metal in low-k dielectric structures, generating a protective layer on the low-k dielectric followed by cleaning the surface of the gapfill metal. Another embodiment of the present invention includes a method of protecting low-k dielectrics such as carbon doped silicon oxide. | 2009-04-02 |
20090087981 | VOID-FREE COPPER FILLING OF RECESSED FEATURES FOR SEMICONDUCTOR DEVICES - A method is provided for void-free copper (Cu) filling of recessed features in a semiconductor device. The method includes providing a patterned substrate containing a recessed feature, depositing a barrier film on the patterned substrate, including in the recessed feature, depositing a Ru metal film on the barrier film, and depositing a discontinuous Cu seed layer on the Ru metal film, where the Cu seed layer partially covers the Ru metal film in the recessed feature. The method further includes exposing the substrate to an oxidation source gas that oxidizes the Cu seed layer and the portion of the Ru metal film not covered by the Cu seed layer, heat-treating the oxidized Cu seed layer and the oxidized Ru metal film under high vacuum conditions or in the presence of an inert gas to activate the oxidized Ru metal film for Cu plating, and filling the recessed feature with bulk Cu metal. The exposure to the oxidation source gas can be an air exposure commonly encountered in semiconductor device manufacturing prior to Cu plating. | 2009-04-02 |
20090087982 | SELECTIVE RUTHENIUM DEPOSITION ON COPPER MATERIALS - Embodiments of the invention provide processes for selectively forming a ruthenium-containing film on a copper surface over exposed dielectric surfaces. Thereafter, a copper bulk layer may be deposited on the ruthenium-containing film. In one embodiment, a method for forming layers on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a copper-containing surface and a dielectric surface, exposing the substrate to a ruthenium precursor to selectively form a ruthenium-containing film over the copper-containing surface while leaving exposed the dielectric surface, and depositing a copper bulk layer over the ruthenium-containing film. | 2009-04-02 |
20090087983 | ALUMINUM CONTACT INTEGRATION ON COBALT SILICIDE JUNCTION - Embodiments herein provide methods for forming an aluminum contact on a cobalt silicide junction. In one embodiment, a method for forming materials on a substrate is provided which includes forming a cobalt silicide layer on a silicon-containing surface of the substrate during a silicidation process, forming a fluorinated sublimation film on the cobalt silicide layer during a plasma process, heating the substrate to a sublimation temperature to remove the fluorinated sublimation film, depositing a titanium-containing nucleation layer over the cobalt silicide layer, and depositing an aluminum-containing material over the titanium-containing nucleation layer. In one example, the method further provides forming the cobalt silicide layer by depositing a cobalt-containing layer on the silicon-containing surface, heating the substrate during a rapid thermal annealing (RTA) process, etching away any remaining portions of the cobalt-containing layer from the substrate, and subsequently heating the substrate during another RTA process. | 2009-04-02 |
20090087984 | FORMING METHOD OF ELECTRODE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A forming method of an electrode includes the steps of providing an electrode material on a conductive part; exposing the electrode material at a temperature equal to or higher than a melting point of the electrode material in an oxidizing atmosphere; and exposing the melted electrode material, in a reducing atmosphere, at a temperature equal to or higher than the melting point of the electrode material and lower than the temperature at which the electrode material is exposed in the oxidizing atmosphere. | 2009-04-02 |
20090087985 | Selective formation of a compound comprising a semi-conducting material and a metallic material in a substrate through a germanium oxide layer - An area made from a compound of a metallic material and semi-conducting material is produced selectively in a substrate made from semi-conducting material by previously forming a germanium oxide layer with a thickness comprised between 3 nm and 5 nm over a predefined part of a surface of the substrate and a silicon oxide layer on the rest of the surface. A metallic layer is deposited on the oxide layers. The metallic material is chosen such that its oxide is thermodynamically more stable than germanium oxide and thermodynamically less stable than silicon oxide. Thermal annealing is then performed to obtain reduction of the germanium oxide by said metallic material followed by formation of the compound, at the level of said part of the surface of the substrate. The metallic layer is then removed. | 2009-04-02 |
20090087986 | Semiconductor devices using fine patterns and methods of forming fine patterns - Example embodiments may provide fine patterns for semiconductor devices and methods of forming fine patterns for semiconductor devices. Example methods may include forming a spacer pattern on a substrate and/or an insulating layer pattern adjacent to sides of the spacer pattern and/or disposed at the same level as the spacer pattern, forming a pair of recesses exposing sides of the spacer pattern by removing a portion of the insulating layer pattern, and/or filling a conductive material in the recesses. | 2009-04-02 |
20090087987 | METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING IMPROVED CONTACTS - A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In one embodiment of the invention, the thick region to which contact is made is formed by means of an opening in an underlayer of material. This embodiment of the device includes an underlayer of material having an opening therein; a layer of thin conductive material formed on the underlayer and in the opening; and overlayer of material having a contact hole therethrough formed on the layer of thin conductive material; a conductor contacting the layer of thin conductive material through the contact hole; and wherein the opening in the underlayer is positioned below the contact hole and sized and shaped to form a localized thick region in the layer of thin conductive material within the opening. | 2009-04-02 |
20090087988 | POLISHING LIQUID AND POLISHING METHOD - A polishing liquid is provided which is used for polishing a barrier layer of a semiconductor integrated circuit, the polishing liquid including surface modified particles that include organic polymer particles having at least one inorganic atom selected from the group consisting of Ti, Al, Zr and Si bonded to the organic polymer particles via an oxygen atom present on a surface of the organic polymer particles, an organic acid, an azole compound having at least two carboxyl groups, and an oxidizing agent, the polishing liquid having a pH of from 1 to 7; and a polishing method for polishing a barrier layer of a semiconductor integrated circuit is also provided. | 2009-04-02 |
20090087989 | POLISHING LIQUID AND POLISHING METHOD USING THE SAME - The invention provides a polishing liquid used for chemical mechanical polishing during planarization of a semiconductor integrated circuit, having at least: a benzotriazole compound (A) represented by the following Formula (1); an acid (B); and a water-soluble polymer (C). The invention further provides a polishing method for planarizing a semiconductor integrated circuit, the polishing method includes at least essentially chemically and mechanically polishing a barrier layer of the semiconductor integrated circuit using the polishing liquid. | 2009-04-02 |
20090087990 | Manufacturing method, manufacturing apparatus, control program and program recording medium of semiconductor device - A manufacturing method of a semiconductor device, which etches a layer to be etched on a substrate into a predetermined pattern based on a first pattern of photoresist produced by exposing and developing a photoresist film, the manufacturing method including the steps of forming an SiO | 2009-04-02 |
20090087991 | Manufacturing method, manufacturing apparatus, control program and program recording medium of semicontructor device - A manufacturing method of a semiconductor device, which etches a layer to be etched on a substrate into a predetermined pattern based on a first pattern of photoresist produced by exposing and developing a photoresist film, the manufacturing method includes the steps of, patterning an organic membrane based on a first pattern of the photoresist, forming an SiO | 2009-04-02 |
20090087992 | METHOD OF MINIMIZING VIA SIDEWALL DAMAGES DURING DUAL DAMASCENE TRENCH REACTIVE ION ETCHING IN A VIA FIRST SCHEME - A method of minimizing undercut of a hard mask in an integrated circuit (IC) structure including steps of providing an IC structure having a substrate, a interlayer dielectric layer, and a hard mask, forming a via in said IC structure, and depositing an organic planarizing layer (OPL) over the IC structure such that it fills the vias formed therein. The method also includes steps of forming a masking structure layer over the OPL, forming an opening in the masking structure that has a critical dimension (CD) smaller than an opening design dimension, anisotropic etching the OPL such that sidewall of the via remains covered with the OPL while forming a trench, and removing any remaining OPL on the sidewalls and trench, wherein the undercut of the sidewalls with respect to the hard mask is minimized by the covering of OPL during the anisotropic etching process. | 2009-04-02 |
20090087993 | METHODS AND APPARATUS FOR COST-EFFECTIVELY INCREASING FEATURE DENSITY USING A MASK SHRINKING PROCESS WITH DOUBLE PATTERNING - Methods and apparatus are provided for forming an array of devices. The invention includes forming a stack of material layers, forming a first hardmask over the plurality of material layers, exposing the first hardmask to ozone mixed with a halogenated additive, forming a protective layer over the first hardmask, forming a second mask on the protective layer shifted relative to the first mask, exposing the second hardmask to ozone mixed with the halogenated additive, and etching the plurality of material layers to remove material not covered by the hardmasks. Numerous other aspects are disclosed. | 2009-04-02 |
20090087994 | METHOD OF FORMING FINE PATTERNS AND MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE USING THE SAME - A method of forming a fine pattern begins with providing a c-plane hexagonal semiconductor crystal. A mask having a predetermined pattern is formed on the semiconductor crystal. The semiconductor crystal is dry-etched by using the mask to form a first fine pattern on the semiconductor crystal. The semiconductor crystal including the first fine pattern is wet-etched to expand the first fine pattern in a horizontal direction to form a second fine pattern. The second fine pattern obtained in the wet-etching the semiconductor crystal has a bottom surface and a sidewall that have unique crystal planes, respectively. The present fine-pattern forming process can be advantageously applied to a semiconductor light emitting device, particularly, to a phonic crystal structure required to have fine patterns or a structure using a surface plasmon resonance principle. | 2009-04-02 |
20090087995 | METHOD OF SUBSTRATE TREATMENT, PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE, SUBSTRATE TREATING APPARATUS, AND RECORDING MEDIUM - Substrate processing apparatus | 2009-04-02 |
20090087996 | LINE WIDTH ROUGHNESS CONTROL WITH ARC LAYER OPEN - To achieve the foregoing and in accordance with the purpose of the present invention a method for etching an etch layer disposed below an antireflective coating (ARC) layer below a patterned mask is provided. The ARC layer is opened, and features are etched into the etch layer through the patterned mask. The opening the ARC layer includes (1) providing an ARC opening gas comprising a halogen containing gas, COS, and an oxygen containing gas, (2) forming a plasma from the ARC opening gas to open the ARC layer, and (3) stopping providing the ARC opening gas to stop the plasma. The patterned mask may be a photoresist (PR) mask having a line-space pattern. COS in the ARC opening gas reduces line width roughness (LWR) of the patterned features of the etch layer. | 2009-04-02 |
20090087997 | Passivation film and method of forming the same - A passivation film and a method of forming the same are provided, the passivation film being used in a plasma display panel etc. In the passivation film, a first MgO layer, an intervening layer, and a second MgO layer are laminated and a laser is then irradiated to oxidize the intervening layer. Simultaneously, defects are formed at the interfaces of the first and second MgO layers. Accordingly, a plasma discharge firing voltage greatly decreases, and the total power consumption of the plasma display panel is significantly reduced. | 2009-04-02 |
20090087998 | DIFFUSION BARRIER LAYER AND METHOD FOR MANUFACTURING A DIFFUSION BARRIER LAYER - A diffusion barrier system for a display device comprising a layer system with at least two layers of dielectric material, wherein at least two adjacent layers of that layer system comprise the same material. A respective method for manufacturing such a diffusion barrier system in a single process chamber of a plasma deposition system has the steps of introducing a substrate to be treated in said process chamber, discretely varying in a controlled manner during deposition at least one process parameter in the process chamber, without completely interrupting such process parameter, which results in layers with different properties and finally unloading said substrate from said process. | 2009-04-02 |
20090087999 | TECHNIQUE FOR COMPENSATING FOR A DIFFERENCE IN DEPOSITION BEHAVIOR IN AN INTERLAYER DIELECTRIC MATERIAL - By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer. | 2009-04-02 |
20090088000 | METHOD FOR GROWING AN OXYNITRIDE FILM ON A SUBSTRATE - A method for growing an oxynitride film on a substrate includes positioning the substrate in a process chamber, heating the process chamber, flowing a first wet process gas comprising water vapor into the process chamber, and reacting the substrate with the first wet process gas to grow an oxide film on the substrate. The method further includes flowing a second wet process gas comprising water vapor and a nitriding gas comprising nitric oxide into the process chamber, and reacting the oxide film and the substrate with the second wet process gas to grow an oxynitride film. In another embodiment, the method further comprises annealing the substrate containing the oxynitride film in an annealing gas. According to one embodiment of the method where the substrate is silicon, a silicon oxynitride film can be formed that exhibits a nitrogen peak concentration of approximately 3 atomic % or greater. | 2009-04-02 |
20090088001 | Substrate processing apparatus and manufacturing method of semiconductor device - To provide a large amount of processing gas to substrates. There are provided a processing chamber that stores stacked substrates; a gas supply part provided in the processing chamber along a stacking direction of the substrates, having a plurality of opening parts, for supplying a desired processing gas horizontally to surfaces of the substrates from the opening parts; and an exhaust port that exhausts an atmosphere in the processing chamber, having an upper wall and a lower wall opposed to each other across the opening parts, respectively provided on upper/lower sides of each of the opening parts of the gas supply part, and an interval between the upper wall and the lower wall opposed to each other across the opening parts being set to be gradually larger toward a supply direction of the processing gas. | 2009-04-02 |
20090088002 | METHOD OF FABRICATING A NITROGENATED SILICON OXIDE LAYER AND MOS DEVICE HAVING SAME - A method for fabricating a nitrogen-containing dielectric layer and semiconductor device including the dielectric layer in which a silicon oxide layer is formed on a substrate, such that an interface region resides adjacent to substrate and a surface region resides opposite the interface region. Nitrogen is introduced into the silicon oxide layer by applying a nitrogen plasma. After applying nitrogen plasma, the silicon oxide layer is annealed. The processes of introducing nitrogen into the silicon oxide layer and annealing the silicon oxide layer are repeated to create a bi-modal nitrogen concentration profile in the silicon oxide layer. In the silicon oxide layer, the peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is situated in proximity to the surface region. A method for fabricating a semiconductor device is incorporating the nitrogen-containing silicon oxide layers also disclosed. | 2009-04-02 |
20090088003 | ELECTRICAL CONNECTOR WITH PROTECTIVE MEMBER - A connector for connecting a card edge module to a circuit board includes a housing that extends along a longitudinal axis between opposite first and second end portions. The housing including a card slot configured to receive a mating edge of the card edge module and a channel proximate one of the first and second end portions. A protective member is received in the channel and positioned to inhibit contact between a side edge of the card edge module and the one of the first and second end portions of the housing when the card edge module is loaded into the connector. | 2009-04-02 |
20090088004 | Adapter configured to couple electrical component to slot in host device - In some embodiments, an adapter is configured to couple an electrical component to a slot in a host device. The electrical component can have at least three sides. The adapter including: (a) a first housing piece configured to be coupled to two or more sides of the at least three sides of the electrical component when the adapter is coupled to the electrical component; and (b) a second housing piece coupled to the first housing piece and configured to couple to a first side of the at least three sides of the electrical component. When the adapter is coupled to the electrical component, a portion of the second housing piece can be configured to be located inside the slot in the host device along with the electrical component. When the adapter is coupled to the electrical component and the portion of the second housing piece is located inside the slot in the host device, the first housing piece can be located outside of the slot. Other embodiments are disclosed in this application. | 2009-04-02 |
20090088005 | ELECTRICAL CONNECTOR WITH CONTACT SHORTING PATHS - An electrical connector includes an insulator holding a plurality of contacts in an array corresponding to an array of pads on an electronic device. At least one shorting path electrically connects at least two of the contacts in the array. The insulator includes a plurality of apertures therethrough, with each aperture defining a contact location on the insulator. The insulator includes a channel formed between at least two contact locations. The channel defines a location of a shorting path and the shorting path is at least partially within the insulator. | 2009-04-02 |
20090088006 | SOCKET FOR SEMICONDUCTOR DEVICE - A pressing surface portion of a presser member for selectively holding a semiconductor device is supported to be movable upward and downward in accordance with the up/down motion of a cover member to be close to or away from a alignment plate, as well as to be rotatable between a position directly above the alignment plate and a predetermined waiting position. | 2009-04-02 |
20090088007 | Printed Circuit Board Assembly and Electronic Device - This invention is to provide a printed circuit board assembly, comprising: a flexible printed circuit board comprising a first electrical connection end and a second electrical connection end; a printed circuit board electrically connected to the second electrical connection end; a frame comprising a first protrusion for maintaining the relative positions of the second electrical connection end and the printed circuit board; and a fastener passing through the second electrical connection end and the printed circuit board for fastening the second electrical connection end and the printed circuit board to the frame. | 2009-04-02 |
20090088008 | METHOD FOR HORIZONTAL INSTALLATION OF LGA SOCKETED CHIPS - Method and apparatus for installing a processor into electronic communication with a socket. The land grid array socket connector includes a socket housing secured to a circuit board and an array of upwardly extending pins for electronic communication with contact pads on the processor. The socket connector provides a carriage configured to receiving the processor through a lateral opening and support a perimeter edge of the processor. A mechanical linkage couples the carriage and the socket housing for substantially vertically translating the processor relative to the socket. A plurality of alignment features upwardly extends from the socket housing along the perimeter of the array of pins. Each of the alignment features has an inwardly-facing tapered surface for registering the edge of the processor and biasing the processor into a position where the array of contact pads are aligned with the array of pins as the processor is lowered. | 2009-04-02 |
20090088009 | ELECTRONIC APPARATUS AND CONNECTOR MOUNTED THEREOF - A connector includes a main body, a first input contact, a second input contact, and a plurality of output contacts. The main body includes a first surface and a second surface. The first input contact and the second input contact project out from the first surface and extend in a first direction. The plurality of output contacts project out from the second surface and extend in a second direction. The second direction forms an acute angle with respect to the first direction. | 2009-04-02 |
20090088010 | WEATHERPROOF CONNECTOR - A weatherproof power inlet box and mating plug wherein the inlet box and mating plug are asymmetrical, positively latched and include more robust elements and a visual indicator of the status of the interconnect. Also included is a thermostat that trips to prevent overheating. | 2009-04-02 |
20090088011 | Cable connector module - A cable connector module includes a cable having a first end and a second end, a first plug connector assembled on the first end of the cable, and a second plug connector assembled on the second end of the cable. The second plug connector forms a second mating portion and a second connecting portion. The second mating portion and the second connecting portion offset 90° relative to each other in a horizontal plane, whereby a first mating socket connector and a second mating socket connector are arranged in low profile on a main board. This structure meets trend of miniature. | 2009-04-02 |
20090088012 | CONNECTOR DEVICE AND ELECTRONIC APPARATUS - According to one embodiment, a connector device includes a flexible cable, a housing, a containing portion, a wall portion, and a leaf spring. The containing portion is formed inside the housing, and a terminal of a counter connector device is inserted to the containing portion. The wall portion is opposed to the flexible cable, and forms one surface of the containing portion. The leaf spring is provided inside the containing portion, and adhered to a surface of the flexible cable reverse to a surface in which a conductor portion of the flexible cable is exposed. The leaf spring urges the flexible cable toward the wall portion to hold the terminal with the wall portion. | 2009-04-02 |
20090088013 | MICRO USB RECEPTACLE - A mirco USB receptacle includes a housing surrounding an axis, a terminal seat extending into the housing along the axis, and an engaging unit. The engaging unit has a first engaging member provided on the terminal seat, and a resilient second engaging member provided on the housing and having an engaging hole for retaining the first engaging member therein and an inner surrounding surface that defines the engaging hole. The first engaging member is formed with a stop surface for abutting against the inner surrounding surface of the second engaging member to arrest separation of the terminal seat from the housing. | 2009-04-02 |
20090088014 | Actuating Device for Separable Connector System - A loadbreak connector system and methods for visible break include first and second mating connector assemblies configured to make or break an electrical connection under energized circuit conditions, the first and second mating connectors selectively positionable relative to one another. One of the first and second mating connectors includes an arc follower, and the other of the first and second mating connectors includes an arc interrupter. The arc interrupter is configured to receive the arc follower, and the first and second meting connectors are positionable in an disconnected position wherein the arc follower remains engaged to and is located within the arc interrupter. Arc energy is distributed among multiple locations to reduce arc intensity. | 2009-04-02 |
20090088015 | PICK-AND-PLACE CAP FOR SOCKET ASSEMBLY - Disclosed is a socket assembly for electrically engaging an Integrated Circuit (IC) package with a printed circuit board. The socket assembly includes a socket body and a Pick-and-Place (PnP) cap. The socket body is mounted on the printed circuit board. Further, the PnP cap is capable of detachably mounting on the socket body. An upper surface of the PnP cap includes a raised portion with multiple chamfered portions projecting out from the raised portion. The multiple chamfered portions enable easier detachment of the PnP cap from the socket body. | 2009-04-02 |
20090088016 | Electrical contact with retaining device for clipping solder ball - An electrical contact ( | 2009-04-02 |
20090088017 | Fastening Device For Low-Profile Fuses Of Vehicle - A fastening device for a low-profile fuses of vehicle, which can achieve simple and robust coupling of the low-profile fuse while enabling the fuse to be easily connected to or disconnected from a vehicular junction box, is disclosed. The fastening device serves to connect or disconnect the low-profile fuse to or from the junction box via upward/downward movement thereof while maintaining coupling between the low-profile fuse and the junction box, and includes a socket integrally formed at an upper surface of the junction box and having plug coupling recesses and a fuse connecting recess indented in the upper surface of the junction box, terminals being disposed inside the fuse connecting recess so as to be exposed to the outside, and a plug vertically movably coupled in the socket while being coupled laterally with the low-profile fuse to enable connection or disconnection between the low-profile fuse and the terminals. | 2009-04-02 |
20090088018 | Connector for electrical and optical cables - A plug and socket connector arrangement for electrical or fiber optic cables includes a pair of tubular locking sleeves mounted for axial and rotational displacement on the plug and connector bodies, which locking sleeves have adjacent ends provided with internal and external screw threads, respectively. The adjacent sleeve ends each contain a plurality of circumferentially spaced longitudinal slits that define a plurality of resilient threaded sectors. After the plug and socket connectors are brought into connected engagement, the locking sleeves are successively displaced from retracted separated positions axially together toward an adjacent locked position, whereby the resilient inner sleeve sectors are initially radially expanded, and the resilient outer sleeve sectors are subsequently radially contracted. The inner and outer screw threads are thus brought into threaded engagement, whereupon the locking sleeves are slightly relatively rotated to lock the sleeves together. | 2009-04-02 |
20090088019 | Insulation-displacement connection - An insulation-displacement connection having at least one insulation-displacement element ( | 2009-04-02 |
20090088020 | In-Vehicle Electronic Device - The present invention improves reliability of an in-vehicle electronic device against corrosive gases. A trapping agent that has trap performances (adsorptive performance, suction performance, absorption performance, chemical reactivity, etc.) that are higher than that of water vapor with respect to corrosive gases other than water vapor is held within a connector having a terminal that is insert-molded in a case housing an electronic circuit. Here, the trapping agent may be held in a counterpart connector of the connector integrally formed in the case. | 2009-04-02 |
20090088021 | Photocontrol receptacle - A receptacle assembly for a twist-lock photocontrol that is mounted on a luminaire housing. The assembly includes a receptacle and a spring clamp. The receptacle has a disc portion with a hub extending from the central portion of the back side, a perimeter side wall with a castellated bottom edge that engages stops on the luminaire housing. Three fingers extend from the back side of the disc and terminate at a lip edge. The spring clamp has a substantially flat, ring-shaped body that includes a top surface, an opening, an inner edge, an outer edge, and at least one pair of spring members. The receptacle is attached to a luminaire housing using the spring clamp. The orientation of the receptacle can be adjusted and can be locked into a stationary position without tools. | 2009-04-02 |
20090088022 | CONNECTOR | 2009-04-02 |
20090088023 | Locking Receptacle For Engaging A USB Device - A locking receptacle for engaging a USB device is provided. The locking receptacle comprising a four sided header with a top opening at the top of the header and a bottom opening at the bottom of the header, the top opening and the bottom opening for USB connections; the header connected to a pivotable locking tip on one side, the pivotable locking tip located to engage a standard opening on a side of a USB plug of a USB device when the USB plug is fully inserted in the locking receptacle; and the pivotable locking tip connected to a lever for pivoting the locking tip. | 2009-04-02 |
20090088024 | HIGH SPEED CONNECTOR AND RECEPTACLE WITH BACKWARD COMPATIBILITY TO USB 2.0 - In some embodiments a connector plug includes a plurality of USB 2.0 pins and one or more pins that are not USB 2.0 pins, the one or more pins to enable higher speed data transmission than USB 2.0 data transmission. Other embodiments are described and claimed. | 2009-04-02 |
20090088025 | MICRO USB PLUG - A micro USB plug includes a terminal seat and a terminal unit including two first terminals, two second terminals, and a third terminal. Each of the first, second, and third terminals extends into the terminal seat and has an extending segment formed with a contact projection, an inspection segment connected to the extending segment and having an inspection surface that is flush with a reference surface of the terminal seat and an abutting surface that abuts against the terminal seat, and a soldering segment extending from the inspection segment. The contact projections and the inspection segments of the first and third terminals extend in a same direction. The contact projections and the inspection segments of the second terminals extend in opposite directions. A segment length of the soldering segments of the first terminals differs from that of the soldering segment of the third terminal. | 2009-04-02 |
20090088026 | FUSE PULLER AND ELECTRIC JUNCTION BOX - A fuse puller includes a body, and a first fuse that is permanently engaged with the body in fixed relation thereto. A electric junction box includes the fuse puller and a fuse mounting surface to which a plurality of fuses including the first fuse are mounted so as to be arranged in parallel to each other. | 2009-04-02 |
20090088027 | Block-Out Cover and Removal Tool - A block-out cover is installed in a jack module to prevent entry of undesirable objects. The block-out cover includes at least one window and at least one locking arm. The locking arm secures the cover to the jack module. The window receives a removal tool designed to remove the cover from the jack module. The removal tool includes a body, a lever secured to the body to engage the cover and a prong with a cam surface. The cam surface of the prong deflects the cover from locking engagement with the jack module allowing the removal tool to remove the block-out cover. | 2009-04-02 |
20090088028 | POWER CONNECTORS WITH CONTACT-RETENTION FEATURES - A power receptacle contact may include first and second contact beams that deflect independently of one another during mating of the power receptacle contact with a complementary blade contact. Each beam may extend from abutting respective body portions. The power receptacle contact may include a first clip that extends from the first contact beam. The first clip may define a blade receiving area between the first and second contact beams. A power connector may include a housing and a contact received in the housing. The contact may includes first and second protrusions that prevent the contact from moving in a first direction. | 2009-04-02 |