13th week of 2010 patent applcation highlights part 38 |
Patent application number | Title | Published |
20100081230 | METHOD AND STRUCTURE FOR ADHESION OF ABSORBER MATERIAL FOR THIN FILM PHOTOVOLTAIC CELL - A method for forming a thin film photovoltaic device includes providing a transparent substrate comprising a surface region and forming a first electrode layer overlying the surface region. The method further includes forming a thin layer of copper gallium material overlying the first electrode layer to act as an intermediary adhesive layer to facilitate attachment to the first electrode layer. Additionally, the method includes forming a copper layer overlying the thin layer and forming an indium layer overlying the copper layer to form a multilayered structure and subjecting the multilayered structure to thermal treatment process with sulfur bearing species to form a copper indium disulfide alloy material. The copper indium disulfide alloy material comprises a copper:indium atomic ratio of about 1.2:1 to about 3.0:1 overlying a copper gallium disulfide material converted from the thin layer. Furthermore, the method includes forming a window layer overlying the copper indium disulfide alloy material. | 2010-04-01 |
20100081231 | METHOD FOR FORMING SEMICONDUCTOR THIN FILM AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - A method for forming a semiconductor thin film includes the steps of applying an inorganic semiconductor fine particle-dispersion solution on a substrate and drying the coating to form a semiconductor fine particle layer, and immersing the semiconductor fine particle layer in a solution to form a semiconductor thin film. | 2010-04-01 |
20100081232 | LAYER TRANSFER PROCESS AND FUNCTIONALLY ENHANCED INTEGRATED CIRCUITS PRODUCED THEREBY - A structure for a semiconductor components is provided having a device layer sandwiched on both sides by other active, passive, and interconnecting components. A wafer-level layer transfer process is used to create this planar (2D) IC structure with added functional enhancements. | 2010-04-01 |
20100081233 | METHOD OF MANUFACTURING INTEGRATED CIRCUIT HAVING STACKED STRUCTURE AND THE INTEGRATED CIRCUIT - Provided are a method of manufacturing an integrated circuit having a stacked structure by forming a crystalline semiconductor thin film on a crystalline or amorphous substrate and the integrated circuit. Accordingly, the method of manufacturing the integrated circuit having the stacked structure uses a method of growing a crystalline semiconductor thin film on a polycrystalline or amorphous substrate, so that the method can be easily performed at low costs, and high-speed processing and high-density integration can be achieved. | 2010-04-01 |
20100081234 | METHOD OF FORMING A PACKAGE WITH EXPOSED COMPONENT SURFACES - A method of forming a semiconductor package includes forming a coating over a first device, attaching the first device to a substrate using an adhesive, encapsulating the first device using an encapsulant material, releasing the first device from the substrate using the adhesive, removing a portion of the encapsulant material that is over the first device to expose the coating, and removing the coating over the first device to expose a portion of the first device. | 2010-04-01 |
20100081235 | METHOD FOR MANUFACTURING RF POWDER - A method for manufacturing RF powder wherein the RF powder is composed of a large amount of particles and used as collective RF powder (a powdery entity); and a large amount of RF powder particles can be obtained from a wafer in a stable manner and at a high yield is provided. | 2010-04-01 |
20100081236 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH EMBEDDED INTERPOSER - A method of manufacturing a semiconductor device includes forming printed circuit board (PCB) having an embedded interposer. A semiconductor chip or a semiconductor package is mounted onto the embedded interposer using a conductive adhesive agent. The embedded interposer has substantially the same coefficient of thermal expansion (CTE) as the semiconductor chip. The embedded interposer is formed using a semiconductor wafer. | 2010-04-01 |
20100081237 | Integrated Circuit Assemblies and Methods for Encapsulating a Semiconductor Device - A seal is formed by compressing a cured layer of a composition applied on a substrate. The composition is any liquid, liquefiable, or mastic, which, after application to a surface, is converted or cured to a compressible solid film. The composition includes a flexible polymer as a binding material. The layer on the substrate eliminates the need for a gasket on a contact surface of a mold. The contact surface of the mold compresses the layer during an encapsulation process. The layer remains on the substrate in a finished product. A minimum separation or wall thickness of the mold is defined by the material properties of the mold. The seal eliminates yield loss due to leakage of an encapsulant and reduces maintenance costs associated with the procurement and repeated installation of gaskets on mold tooling. | 2010-04-01 |
20100081238 | MIXED-SCALE ELECTRONIC INTERFACE - Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. A method is provided for fabricating a nanoscale/microscale interface having a microscale layer and a predominantly nanoscale layer. | 2010-04-01 |
20100081239 | Efficient Body Contact Field Effect Transistor with Reduced Body Resistance - A method for forming a body contacted SOI transistor includes forming a semiconductor layer ( | 2010-04-01 |
20100081240 | Semiconductor device and method of manufacturing semiconductor device - A method of manufacturing a semiconductor device includes forming a plurality of Fins including a semiconductor material on an insulation layer; forming gate insulation films on sidewalls of the Fins; forming a gate electrode which extends in a direction of arrangement of the Fins and which is electrically insulated from the Fins, the gate electrode is common in the Fins on the gate insulation film; implanting an impurity into portions of the Fins by using the gate electrode as a mask to form a source-drain diffusion layer, the portions of the Fins extending on both sides of the gate electrodes; and depositing a conductive material on both sides of the Fins to connect the Fins to each other. | 2010-04-01 |
20100081241 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR, CAPACITIVE ELEMENT AND FABRICATION METHOD THEREFOR, AND MIS TYPE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - A semiconductor device includes an operating layer made of a semiconductor and a silicon nitride film formed on the operating layer with the use of a mixed gas that includes mono-silane gas, hydrogen gas, and nitrogen gas, by a plasma CVD apparatus, under a condition that a flow rate of the hydrogen gas is 0.2 percent to 5 percent to an overall flow rate. | 2010-04-01 |
20100081242 | Methods Of Forming DRAM Arrays - Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include carbon monoxide, O | 2010-04-01 |
20100081243 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, includes forming a gate oxide film on an SiC region by a first thermal oxidation treatment in a first oxidizing atmosphere, performing a second thermal oxidation treatment at an oxidation speed of at most 5 nm/hour in a second oxidizing atmosphere having a lower oxygen concentration than the first oxidizing atmosphere, to increase film thickness of the gate oxide film, after the first thermal oxidation treatment, and forming a gate electrode on the gate oxide film with the increased film thickness. | 2010-04-01 |
20100081244 | TRANSISTOR DEVICE COMPRISING AN ASYMMETRIC EMBEDDED SEMICONDUCTOR ALLOY - Transistor characteristics may be adjusted on the basis of asymmetrically formed cavities in the drain and source areas so as to maintain a strain-inducing mechanism while at the same time providing the possibility of obtaining asymmetric configuration of the drain and source areas while avoiding highly complex implantation processes. For this purpose, the removal rate during a corresponding cavity etch process may be asymmetrically modified on the basis of a tilted ion implantation process. | 2010-04-01 |
20100081245 | METHODS FOR FABRICATING MOS DEVICES HAVING HIGHLY STRESSED CHANNELS - Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized polysilicon layer to form a gate electrode, depositing a stress-inducing layer overlying the gate electrode, annealing the silicon-comprising substrate to recrystallize the gate electrode, removing the stress-inducing layer, etching recesses into the substrate using the gate electrode as an etch mask, and epitaxially growing impurity-doped, silicon-comprising regions in the recesses. | 2010-04-01 |
20100081246 | Method of manufacturing a semiconductor - A semiconductor device and a method of manufacturing a semiconductor device, the method including forming a gate insulation layer and a gate electrode on a substrate, forming a silicon nitride layer on the gate electrode and the gate insulation layer, partially implanting ions into the silicon nitride layer to convert an upper portion of the silicon nitride layer into a treated silicon layer including the ions, etching the treated silicon layer to form a spacer on a sidewall of the gate electrode, and forming an impurity region in the substrate adjacent to the gate electrode. | 2010-04-01 |
20100081247 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device such as a thin film transistor using a crystal silicon film is provided. The crystal silicon film is obtained by selectively forming films, particles or clusters containing nickel, iron, cobalt, ruthenium, rhodium, paradium, osmium, iridium, platinum, scandium, titanium, vanadium, chrome, manganese, copper, zinc, gold, silver or silicide thereof in a form of island, line, stripe, dot or film on or under an amorphous silicon film and using them as a starting point, by advancing its crystallization by annealing at a temperature lower than a normal crystallization temperature of an amorphous silicon. A transistor whose leak current is low and a transistor in which a mobility is high are obtained in the same time in structuring a dynamic circuit having a thin film transistor by selectively forming a cover film an a semiconductor layer which is to become an active layer of the transistor and by thermally crystallizing it thereafter. | 2010-04-01 |
20100081248 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises forming a first plate electrode that defines a storage node region over a semiconductor substrate, forming a first dielectric film at sidewalls of the storage node region, forming a storage node over the storage node region, and forming a second dielectric film and a second plate electrode over the resulting structure, thereby preventing collapse of the storage node and also preventing generation of defects by electric short between capacitors. | 2010-04-01 |
20100081249 | Method to reduce leakage in a protection diode structure - A method for forming a protection diode utilizes processing operations and materials used in the formation of the CMOS integrated circuit device and provides a protection diode used in CMOS integrated circuit devices to direct charged particles to benign locations and prevent damage to the devices. The protection diode includes a well region of a first conductivity type formed in a surface of a semiconductor substrate, a heavily doped P-type impurity region disposed within the well region, a heavily doped N-type impurity region disposed within the well region and an STI structure interposed therebetween. A top surface of the STI structure extends above the surface. A silicide resistant block-out layer is formed over the STI structure and extends laterally beyond the STI structure, covering any counterdoped sections that may undesirably be formed in the substrate adjacent the STI structure during implantation operations. | 2010-04-01 |
20100081250 | SEMICONDUCTOR DEVICE HAVING AN OXIDE FILM FORMED ON A SEMICONDUCTOR SUBSTRATE SIDEWALL OF AN ELEMENT REGION AND ON A SIDEWALL OF A GATE ELECTRODE - A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film. | 2010-04-01 |
20100081251 | METHOD FOR MANUFACTURING SOI SUBSTRATE - A single crystal semiconductor substrate is irradiated with accelerated ions to form an embrittled region in the single crystal semiconductor substrate. The single crystal semiconductor substrate and a base substrate are bonded to each other with an insulating layer interposed therebetween. The single crystal semiconductor substrate is separated at the embrittled region to form a semiconductor layer over the base substrate. Heat treatment is performed to reduce defects in the semiconductor layer. The semiconductor layer is then irradiated with laser light. | 2010-04-01 |
20100081252 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Suppression of generation of a stripe pattern (unevenness) when an SOI substrate is manufactured by a glass substrate and a single crystal semiconductor substrate bonded to each other. A single crystal semiconductor substrate is irradiated with ions so that a fragile region is formed in the single crystal semiconductor substrate; a depression or a projection is formed in a region of a surface of an insulating layer provided on the single crystal semiconductor substrate, the region corresponding to the periphery of the single crystal semiconductor substrate; the single crystal semiconductor substrate is bonded to a base substrate; thermal treatment is performed thereon to separate the single crystal semiconductor substrate at the fragile region, so that a single crystal semiconductor layer is formed over the base substrate; and the single crystal semiconductor layer in the region corresponding to the periphery is removed. | 2010-04-01 |
20100081253 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - A step of forming an insulating film over a semiconductor substrate and forming an embrittled region in the semiconductor substrate by irradiating the semiconductor substrate with accelerated ions through the insulating film; a step of disposing a surface of the semiconductor substrate and a surface of a base substrate opposite to each other and bonding the surface of the insulating film to the surface of the base substrate; a step of forming a semiconductor layer over the base substrate with the insulating film interposed therebetween by causing separation along the embrittled region by performing heat treatment after the surface of the insulating film and the surface of the base substrate are bonded to each other; a step of performing etching treatment on the semiconductor layer; a step of irradiating the semiconductor layer subjected to the etching treatment with a laser beam; and a step of irradiating the semiconductor layer irradiated with the laser beam with plasma. | 2010-04-01 |
20100081254 | METHOD FOR MANUFACTURING SOI SUBSTRATE AND METHOD FOR MANUFACTURING SINGLE CRYSTAL SEMICONDUCTOR LAYER - An object is to provide a single crystal semiconductor layer with extremely favorable characteristics without performing CMP treatment or heat treatment at high temperature. Further, an object is to provide a semiconductor substrate (or an SOI substrate) having the above single crystal semiconductor layer. A first single crystal semiconductor layer is formed by a vapor-phase epitaxial growth method on a surface of a second single crystal semiconductor layer over a substrate; the first single crystal semiconductor layer and a base substrate are bonded to each other with an insulating layer interposed therebetween; and the first single crystal semiconductor layer and the second single crystal semiconductor layer are separated from each other at an interface therebetween so as to provide the first single crystal semiconductor layer over the base substrate with the insulating layer interposed therebetween. Thus, an SOI substrate can be manufactured. | 2010-04-01 |
20100081255 | Methods for reducing defects through selective laser scribing - Embodiments of an apparatus and methods of reducing defects through selective laser scribing are described herein. Other embodiments may be described and claimed. | 2010-04-01 |
20100081256 | Method for producing group III nitride compound semiconductor element - A method for producing a Group III nitride compound semiconductor element includes growing an epitaxial layer containing a Group III nitride compound semiconductor using a different kind of substrate as an epitaxial growth substrate, adhering a supporting substrate to the top surface of the epitaxial growth layer through a conductive layer, and then removing the epitaxial growth substrate by laser lift-off. Before adhesion of the epitaxial layer and the supporting substrate, a first groove that at least reaches an interface between the bottom surface of the epitaxial layer and the epitaxial growth substrate from the top surface of the epitaxial layer formed on the epitaxial growth substrate and acts as an air vent communicating with the outside of a wafer when the epitaxial layer and the supporting substrate are joined to each other. Next, the epitaxial layer is divided into each chip by separating the epitaxial growth substrate by laser lift-off, and then removing the epitaxial layer serving as the outer periphery of each chip. Next, the outer peripheral side surface of the epitaxial layer of each chip is at least completely covered with an insulating protective film. Next, the supporting substrate is separated into each chip. | 2010-04-01 |
20100081257 | DICE BY GRIND FOR BACK SURFACE METALLIZED DIES - Semiconductor device processing and methods for dicing a semiconductor wafer into a plurality of individual dies that can have back surface metallization are described. The methods comprise providing a wafer with pre-diced streets in the wafer's front surface, applying a sidewall masking mechanism to the front surface of the wafer so as to substantially fill the pre-diced streets, thinning the back surface of the wafer so as to dice the wafer (e.g., by grinding, etching, or both) and expose a portion of the sidewall masking mechanism from the back surface of the wafer, and applying a material, such as metal, to the back surface of the diced wafer. These methods can prevent the metal from being deposited on die sidewalls and may allow the separation of individual dies without causing the metal to peel from the back surface of one or more adjacent dies. Other embodiments are also described. | 2010-04-01 |
20100081258 | THERMOSETTING DIE-BONDING FILM - A thermosetting die-bonding film having excellent adhesion to an adherent and preferable pickup properties and a dicing die-bonding film having the thermosetting die-bonding film are provided. The thermosetting die-bonding film of the present invention is a thermosetting die-bonding film that is used when manufacturing a semiconductor device and contains 15 to 30% by weight of a thermoplastic resin component and 60 to 70% by weight of a thermosetting resin component as main components, wherein a surface free energy before heat curing is 37 mJ/m | 2010-04-01 |
20100081259 | DISLOCATION ENGINEERING USING A SCANNED LASER - A method for generating patterned strained regions in a semiconductor device is provided. The method includes directing a light-emitting beam locally onto a surface portion of a semiconductor body; and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam, the light-emitting beam being characterized as having a scan speed, so as to produce the patterned strained regions. | 2010-04-01 |
20100081260 | Method for forming a semiconductor film - An apparatus for high-rate chemical vapor (CVD) deposition of semiconductor films comprises a reaction chamber for receiving therein a substrate and a film forming gas, a gas inlet for introducing the film forming gas into the reaction chamber, an incidence window in the reaction chamber for transmission of a laser sheet into the reaction chamber, a laser disposed outside the reaction chamber for generating the laser sheet and an antenna disposed outside the reaction chamber for generating a plasma therein. The film forming gas in the chamber is excited and decomposed by the laser sheet, which passes in parallel with the substrate along a plane spaced apart therefrom, and concurrent ionization effected by the antenna, thereby forming a dense semiconductor film on the substrate at high rate. | 2010-04-01 |
20100081261 | Method of fabricating silicon carbide (SiC) layer - A method of fabricating a silicon carbide (SiC) layer is disclosed, which comprises steps: (S | 2010-04-01 |
20100081262 | METHOD FOR FORMING METAL GATES IN A GATE LAST PROCESS - The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP). | 2010-04-01 |
20100081263 | Methods of manufacturing semiconductor device - A method of manufacturing a semiconductor device includes forming a phase change material pattern on a top surface of an insulating layer including an opening and in the opening, and forming a compressive layer compressing the phase change material pattern on the phase change material pattern. | 2010-04-01 |
20100081264 | METHODS FOR SIMULTANEOUSLY FORMING N-TYPE AND P-TYPE DOPED REGIONS USING NON-CONTACT PRINTING PROCESSES - Methods for simultaneously forming doped regions of opposite conductivity using non-contact printing processes are provided. In one exemplary embodiment, a method comprises the steps of depositing a first liquid dopant comprising first conductivity-determining type dopant elements overlying a first region of a semiconductor material and depositing a second liquid dopant comprising second conductivity-determining type dopant elements overlying a second region of the semiconductor material. The first conductivity-determining type dopant elements and the second conductivity-determining type dopant elements are of opposite conductivity. At least a portion of the first conductivity-determining type dopant elements and at least a portion of the second conductivity-determining type dopant elements are simultaneously diffused into the first region and into the second region, respectively. | 2010-04-01 |
20100081265 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns. | 2010-04-01 |
20100081266 | SEMICONDUCTOR MEMORY INTEGRATED CIRCUIT AND ITS MANUFACTURING METHOD - A method of manufacturing a semiconductor memory integrated circuit intended to improve properties and reliability of its peripheral circuit includes the step of forming a tunnel oxide film ( | 2010-04-01 |
20100081267 | METHOD FOR FORMING SELF-ALIGNED DIELECTRIC CAP ABOVE FLOATING GATE - A method for fabricating a non-volatile storage element. The method comprises forming a layer of polysilicon floating gate material over a substrate and forming a layer of nitride at the surface of the polysilicon floating gate material. Floating gates are formed from the polysilicon floating gate material. Individual dielectric caps are formed from the nitride such that each individual nitride dielectric cap is self-aligned with one of the plurality of floating gates. An inter-gate dielectric layer is formed over the surface of the dielectric caps and the sides of the floating gates. Control gates are then formed with the inter-gate dielectric layer separating the control gates from the floating gates. The layer of nitride may be formed using SPA (slot plane antenna) nitridation. The layer of nitride may be formed prior to or after etching of the polysilicon floating gate material to form floating gates. | 2010-04-01 |
20100081268 | DAMASCENE PROCESS FOR CARBON MEMORY ELEMENT WITH MIIM DIODE - Forming a metal-insulator diode and carbon memory element in a single damascene process is disclosed. A trench having a bottom and a sidewall is formed in an insulator. A first diode electrode is formed in the trench during a single damascene process. A first insulating region comprising a first insulating material is formed in the trench during the single damascene process. A second insulating region comprising a second insulating material is formed in the trench during the single damascene process. A second diode electrode is formed in the trench during the single damascene process. The first insulating region and the second insulating region reside between the first diode electrode and the second diode electrode to form a metal-insulator-insulator-metal (MIIM) diode. A region of carbon is formed in the trench during the single damascene process. At least a portion of the carbon is electrically in series with the MIIM diode. | 2010-04-01 |
20100081269 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING ELECTRODE FOR EXTERNAL CONNECTION - A method for manufacturing semiconductor device which includes forming a first metal film over an electrode pad disposed on a substrate, forming a second metal film on the first metal film, forming a first oxide film on a surface of the first metal film and a second oxide film on a surface of the second metal film by oxidizing the surfaces of the first metal film and the second metal film, removing the first oxide film, and melting the second metal film after removing the first oxide film. | 2010-04-01 |
20100081270 | Method and Apparatus for Strapping Two Polysilicon Lines in a Semiconductor Integrated Circuit Device - A method and apparatus for partially strapping two polysilicon lines, each having a first end and second end, uses a metal line having a plurality of spaced apart metal segments with each metal segment partially strapping a different portion of a polysilicon line. The metal segments are arranged from the first end to the second end with the signals propagating from the second end to the first end. Where two metal segments are used, the segments have lengths of | 2010-04-01 |
20100081271 | METHOD OF FORMING A DIFFUSION BARRIER AND ADHESION LAYER FOR AN INTERCONNECT STRUCTURE - A method of forming an interconnect structure is provided. The method includes depositing a cobalt metal layer in an interconnect opening formed within a dielectric material containing a dielectric reactant element. The method further includes, in any order, thermally reacting at least a portion of the cobalt metal layer with at least a portion of the dielectric material to form a diffusion barrier containing a compound of the reactive metal from the cobalt metal layer and the dielectric reactant element from the dielectric material, and forming a cobalt nitride adhesion layer in the interconnect opening. The method further includes filling the interconnect opening with Cu metal, where the diffusion barrier and the cobalt nitride adhesion layer surround the Cu metal in the interconnect opening. | 2010-04-01 |
20100081272 | Methods of Forming Electrical Interconnects Using Electroless Plating Techniques that Inhibit Void Formation - Methods of forming electrical interconnects include forming a copper pattern on a semiconductor substrate and then forming an electrically insulating capping layer on the copper pattern and an interlayer insulating layer on the electrically insulating capping layer. A contact hole is then formed, which extends through the interlayer insulating layer and the electrically insulating capping layer and exposes an upper surface of the copper pattern. An electroless plating step is then performed to form a copper pattern extension onto the exposed upper surface of the copper pattern. The copper pattern extension may have a thickness that is less than a thickness of the electrically insulating capping layer, which may be formed as a SiCN layer. | 2010-04-01 |
20100081273 | METHOD FOR FABRICATING CONDUCTIVE PATTERN - A method for fabricating a conductive pattern including following steps is provided. A first conductive layer is formed on a substrate. A patterned hard mask layer is formed on the first conductive layer. A portion of the first conductive layer is removed to expose a portion of the substrate by using the patterned hard mask layer as a mask. A dielectric layer covering the patterned hard mask layer is formed on the substrate. A portion of the dielectric layer is removed to expose the patterned hard mask layer. The patterned hard mask layer is removed to form an opening in the dielectric layer. A second conductive layer is formed in the opening. | 2010-04-01 |
20100081274 | METHOD FOR FORMING RUTHENIUM METAL CAP LAYERS - A method is provided for integrating ruthenium (Ru) metal deposition into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. Embodiments of the invention include treating patterned substrates containing metal layers and low-k dielectric materials with NH | 2010-04-01 |
20100081275 | METHOD FOR FORMING COBALT NITRIDE CAP LAYERS - A method is provided for integrating cobalt nitride cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt nitride cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k dielectric regions, and selectively forming a cobalt nitride cap layer on the Cu paths relative to the low-k dielectric regions. | 2010-04-01 |
20100081276 | METHOD FOR FORMING COBALT TUNGSTEN CAP LAYERS - A method is provided for integrating cobalt tungsten cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt tungsten cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k regions, and forming a cobalt tungsten cap layer on the Cu paths. | 2010-04-01 |
20100081277 | METHOD FOR PASSIVATING EXPOSED COPPER SURFACES IN A METALLIZATION LAYER OF A SEMICONDUCTOR DEVICE - When forming sophisticated metallization systems, surface integrity of an exposed metal surface, such as a copper-containing surface, may be enhanced by exposing the surface to a vapor of a passivation agent. Due to the corresponding interaction with the metal surface, enhanced integrity may be accomplished, while at the same time damage of exposed dielectric surface portions may be significantly reduced compared to conventional aggressive wet chemical cleaning processes that are typically used in conventional patterning regimes. | 2010-04-01 |
20100081278 | Methods for Nanoscale Feature Imprint Molding - Methods for fabricating nanoscale features are disclosed. One technique involves depositing onto a substrate, where the first layer may be a silicon layer and may subsequently be etched. A second layer and third layer may be deposited on the etch first layer, followed by the deposition of a silicon cap. The second and third layer may be etched, exposing edges of the second and third layers. The cap and first layer may be removed and either the second or third layer may be etched, creating a nanoscale pattern. | 2010-04-01 |
20100081279 | Method for Forming Through-base Wafer Vias in Fabrication of Stacked Devices - An effective method for forming through-base wafer vias in the fabrication of stacked devices is described. The base wafer can be a silicon wafer in which case the method relates to TSV (through-silicon via) technology. The method affords high removal rates of both silicon and metal (e.g., copper) under appropriate conditions and is tuneable with respect to base wafer material to metal selectivity. | 2010-04-01 |
20100081280 | METHOD OF PRODUCING A MIXED SUBSTRATE - The invention concerns a method of producing a mixed substrate, that is to say a substrate comprising at least one block of material different from the material of the substrate, the method comprising the following successive steps:
| 2010-04-01 |
20100081281 | Abrasive compositions for chemical mechanical polishing and methods for using same - A colloidal dispersion for chemical mechanical polishing comprising: (a) an abrasive component; and (b) from about 0.05% to about 10% by weight of the abrasive component, a water-soluble amphoteric polymer comprising at least one macromolecular chain B and a part A bonded to a single end of the at least one macromolecular chain B, wherein the macromolecular chain B is derived from one or more ethylenically unsaturated monomers having quaternary ammonium groups or inium groups, and wherein the part A is a polymeric or nonpolymeric group comprising at least one anionic group; wherein the dispersion has a pH of between about 1.5 and about 6. The colloidal dispersion is capable of polishing a substrate comprising silicon nitride and silicon oxide with a reverse selectivity ratio of at least about 27, typically at least 50 the reverse selectivity ratio being the ratio of the rate of removal of the silicon nitride to the rate of removal of the silicon oxide. | 2010-04-01 |
20100081282 | PROCESS FOR ADJUSTING THE SIZE AND SHAPE OF NANOSTRUCTURES - In accordance with the invention, a lateral dimension of a microscale device on a substrate is reduced or adjusted by the steps of providing the device with a soft or softened exposed surface; placing a guiding plate adjacent the soft or softened exposed surface; and pressing the guiding plate onto the exposed surface. Under pressure, the soft material flows laterally between the guiding plate and the substrate. Such pressure induced flow can reduce the lateral dimension of line spacing or the size of holes and increase the size of mesas. The same process also can repair defects such as line edge roughness and sloped sidewalls. This process will be referred to herein as pressed self-perfection by liquefaction or P-SPEL. | 2010-04-01 |
20100081283 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method including: sequentially forming a first film and a second film on a base film; processing the second film, thereby forming a second pattern; processing the first film with the second pattern as a mask, thereby forming a first pattern; removing the second pattern; depositing a third film on the base film and on the first pattern; processing the third film, thereby forming a third side wall pattern on a side wall of the first pattern; removing the first pattern; and processing the base film with the third side wall pattern as a mask, thereby forming a target pattern so that, in the target pattern, a space dimension is larger than a pattern dimension. | 2010-04-01 |
20100081284 | METHODS AND APPARATUS FOR IMPROVING FLOW UNIFORMITY IN A PROCESS CHAMBER - Methods and apparatus for processing substrates are provided herein. In some embodiments, an apparatus for processing a substrate includes a flow equalizer configured to control the flow of gases between a process volume and an exhaust port of a process chamber. The flow equalizer includes at least one restrictor plate configured to be disposed in a plane proximate a surface of a substrate to be processed and defines an azimuthally non-uniform gap between an edge of the at least one restrictor plate and one of either a chamber wall or a substrate support when installed in the process chamber. | 2010-04-01 |
20100081285 | Apparatus and Method for Improving Photoresist Properties - The invention can provide apparatus and methods of processing a substrate in real-time using subsystems and processing sequences created to improve the etch resistance of photoresist materials. In addition, the improved photoresist layer can be used to more accurately control gate and/or spacer critical dimensions (CDs), to control gate and/or spacer CD uniformity, and to eliminate line edge roughness (LER) and line width roughness (LWR). | 2010-04-01 |
20100081286 | Method of etching carbon-containing layer, method of forming contact hole using the same, and method of manufacturing semiconductor device using the same - A method of etching a carbon-containing layer, a method of forming a contact hole using the same, and a method of manufacturing a semiconductor device using the same, the method of etching a carbon-containing layer including forming a capping layer pattern on a carbon-containing layer to expose a portion of the carbon-containing layer, and plasma etching the exposed portion of the carbon-containing layer using an etching gas, wherein the etching gas includes oxygen gas and an inert gas, the inert gas being xenon gas or a gas mixture of xenon gas and argon gas. | 2010-04-01 |
20100081287 | DRY ETCHING METHOD - A dry etching method includes: mounting a silicon substrate in a processing chamber; generating a plasma by discharging an etching gas in the processing chamber; and etching the silicon substrate by the plasma. The etching gas is a gaseous mixture including a Cl | 2010-04-01 |
20100081288 | SUBSTRATE PROCESSING APPARATUS AND SEMICONDUCTOR DEVICE PRODUCING METHOD - Disclosed is a substrate processing apparatus which comprises reaction tubes ( | 2010-04-01 |
20100081289 | METHOD OF DEPOSITING MATERIALS ON A NON-PLANAR SURFACE - A carrier for effectuating semiconductor processing on a non-planar substrate is disclosed. The carrier is configured for holding at least one non-planar substrate throughout a semiconductor processing step and concurrently rotating non-planar substrates as they travel down a translational path of a processing chamber. As the non-planar substrates simultaneously rotate and translate down a processing chamber, the rotation exposes the whole or any desired portion of the surface area of the non-planar substrates to the deposition process, allowing for uniform deposition as desired. Alternatively, any predetermined pattern is able to be exposed on the surface of the non-planar substrates. Such a carrier effectuates manufacture of non-planar semiconductor devices, including, but not limited to, non-planar light emitting diodes, non-planar photovoltaic cells, and the like. | 2010-04-01 |
20100081290 | METHOD OF FORMING A GATE DIELECTRIC BY IN-SITU PLASMA - A method of forming a gate dielectric layer includes forming a first dielectric layer over a semiconductor substrate using a first plasma, performing a first in-situ plasma nitridation of the first dielectric layer to form a first nitrided dielectric layer, forming a second dielectric layer over the first dielectric layer using a second plasma, performing a second in-situ plasma nitridation of the second dielectric layer to form a second nitrided dielectric layer; and annealing the first nitrided dielectric layer and the second nitrided dielectric layer, wherein the gate dielectric layer comprises the first nitrided dielectric layer and the second nitrided dielectric layer. In other embodiments, the steps of forming a dielectric layer using a plasma and performing an in-situ plasma nitridation are repeated so that more than two nitrided dielectric layers are formed and used as the gate dielectric layer. | 2010-04-01 |
20100081291 | Very Low Dielectric Constant Plasma-Enhanced CVD Films - The present invention provides a method for depositing nano-porous low dielectric constant films by reacting an oxidizable silicon containing compound or mixture comprising an oxidizable silicon component and an oxidizable non-silicon component having thermally liable groups with nitrous oxide, oxygen, ozone, or other source of reactive oxygen in gas-phase plasma-enhanced reaction. The deposited silicon oxide based film is annealed to form dispersed microscopic voids that remain in a nano-porous silicon oxide based film having a low-density structure. The nano-porous silicon oxide based films are useful for forming layers between metal lines with or without liner or cap layers. The nano-porous silicon oxide based films may also be used as an intermetal dielectric layer for fabricating dual damascene structures. Preferred nano-porous silicon oxide based films are produced by reaction of methylsilyl-1,4-dioxinyl ether or methylsiloxanyl furan and 2,4,6-trisilaoxane or cyclo-1,3,5,7-tetrasilylene-2,6-dioxy-4,8 dimethylene with nitrous oxide or oxygen followed by a cure/anneal that includes a gradual increase in temperature. | 2010-04-01 |
20100081292 | GAS TREATMENT METHOD AND COMPUTER READABLE STORAGE MEDIUM - A gas delivery apparatus comprises: a chamber surrounding a substrate to be processed; a showerhead disposed within the chamber; and gas supply means supplying a gas comprising a mixture of NH | 2010-04-01 |
20100081293 | METHODS FOR FORMING SILICON NITRIDE BASED FILM OR SILICON CARBON BASED FILM - A method for depositing a silicon nitride based dielectric layer is provided. The method includes introducing a silicon precursor and a radical nitrogen precursor to a deposition chamber. The silicon precursor has a N—Si—H bond, N—Si—Si bond and/or Si—Si—H bond. The radical nitrogen precursor is substantially free from included oxygen. The radical nitrogen precursor is generated outside the deposition chamber. The silicon precursor and the radical nitrogen precursor interact to form the silicon nitride based dielectric layer. | 2010-04-01 |
20100081294 | PATTERN DATA CREATING METHOD, PATTERN DATA CREATING PROGRAM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A pattern data creating method according to an embodiment of the present invention comprises: extracting marginal error patterns using a first result obtained by applying process simulation to mask pattern data based on an evaluation target cell pattern, applying the process simulation to mask pattern data based on an evaluation target cell pattern with peripheral environment pattern created by arranging a peripheral environment pattern in the marginal error patterns such that a second result obtained by creating mask pattern data and applying the process simulation to the mask pattern data is more deteriorated than the first result, and correcting the evaluation target cell pattern or the mask pattern data based on the evaluation target cell pattern when there is a fatal error. | 2010-04-01 |
20100081295 | PROCESS MODEL EVALUATION METHOD, PROCESS MODEL GENERATION METHOD AND PROCESS MODEL EVALUATION PROGRAM - According to an aspect of the present invention, there is provided a method for evaluating a process model, the method including: acquiring, for each of given patterns, a dimensional difference amount between: a first pattern that is formed by actually applying a process onto a corresponding one of the given patterns; and a second pattern that is calculated by applying a process model modeling the process to the corresponding one of the given patterns; and evaluating the process model based on an evaluation index, the evaluation index being based on the number of the patterns at which the dimensional difference amount is equal to or less than a threshold value. | 2010-04-01 |
20100081296 | SUBSTRATE FIXING MEMBER AND ELECTRONIC DEVICE - A substrate fixing member that fixes a first substrate having an insertion hole into which a second substrate having mutually opposing an end portion is to be inserted, the substrate fixing member including a fixing member main body portion that covers a top surface portion of a connector having the insertion hole and has a through-hole which the substrate is to be passed through and a substrate support portion having a groove portion slidably holding an end portion of the substrate when the substrate is passed through the through-hole and the insertion hole to connect a substrate-side connection terminal to a connector-side terminal. | 2010-04-01 |
20100081297 | METHOD FOR PREVENTING DAMAGE TO A MEMORY CARD - A memory card connector, within a slot of a host device, for receiving a first memory card having a first row of contact fingers and a second row of contact fingers and a second memory card having only a single row of contact fingers. The memory card connector includes a first row of contact pins, a second row of contact pins and a protrusion. The first row of contact pins are configured to mate with the first row of contact fingers of the first memory card. The second row of contact pins are configured to mate with the second row of contact fingers of the first memory card. The protrusion is received within a contact finger in the second row of contact fingers of the first memory card to allow full insertion of the first memory card into the connector, and abuts against a distal end of one of the contact fingers of the second memory card to prevent full insertion of the second memory card into the connector. | 2010-04-01 |
20100081298 | ASSEMBLY FOR INTERCONNECTING CIRCUIT BOARDS - An electrical connector assembly that is configured to electrically couple first and second circuit boards is provided. The connector assembly includes an electrical connector that is configured to be coupled to the first circuit board. The connector includes a board mating face and an array of connector contacts. The connector contacts are configured to engage the board contacts. The connector also includes a guide assembly that is configured to be coupled to the first and second circuit boards. The guide assembly includes a guide channel and a cam member that slidably engages the guide channel such that the second circuit board is moved during a loading stage along a longitudinal direction until the board contacts are substantially aligned with the array of connector contacts. The second circuit board is also moved during a shifting stage in a direction transverse to the longitudinal direction. | 2010-04-01 |
20100081299 | CONNECTOR CONNECTION TERMINAL AND CONNECTOR INCORPORATING THE SAME - A connector connection terminal has a fixed piece to be inserted to a base of a connector, a coupling portion extending from the fixed piece, and a movable piece extending in parallel to the fixed piece to both sides from a free end of the coupling portion and being operated by an operation lever rotatably assembled to the base. At least one of the fixed piece and the movable piece includes at least one pointed end portion. The connector connection terminal is formed through electroforming. | 2010-04-01 |
20100081300 | ELECTRICAL CONNECTOR HAVING METALLIC LOCK - An electrical connector, for electrically connecting a module to a circuit substrate, comprises an insulative housing for loading a module, a plurality of contacts received in the insulative housing, a cover pivotally connecting to an end of the insulative housing and a pair of metal ears mounted to two sides of another opposed end of the insulative housing. The metal ear has an engaging portion, a spring arm upwardly extending from a top end of the engaging portion to lock the cover and a mounting portion downwardly extending from a bottom end of the engaging portion for soldering to the circuit substrate. The electrical connector can be easily operated and provide a reliable connection. | 2010-04-01 |
20100081301 | TWO-PIN PLUG-IN COMPONENT AND PRINTED CIRCUIT BOARD ENGAGABLE WITH THE SAME - A two-pin plug-in component includes a main body, a first pin, and a second pin. The first pin and the second pin are correspondingly connected to an anode and a cathode of the main body, and are set on a bottom of the main body. The first and second pins are non-centrosymmetric on the bottom of the main body. | 2010-04-01 |
20100081302 | GROUND SLEEVE HAVING IMPROVED IMPEDANCE CONTROL AND HIGH FREQUENCY PERFORMANCE - A waferized connector connects to two twinax cables. The connector includes a molded lead frame, ground sleeve, twinax cable, and overmolded strain relief. The lead frame is molded to retain a lead frame containing both differential signal pins and ground pins. Termination sections are provided at the rear of the lead frame to terminate each of the signal wires of the cables to respective signal lands. The ground sleeve has two general H-shape structures connected together by a center cross-support member. Each of the H-shaped structures having curved legs, each of which fits over the signal wires of one of the twinax cables. The wings of the ground sleeve are terminated to the ground lands of the lead frame and the drain wire of the cable is terminated to the ground sleeve to terminate the drain wire to a ground reference. The ground sleeve controls the impedance in the termination area of the cables, where the twinax foil is removed to expose the wires for termination to the lands. The ground sleeve also shields the cables to reduce crosstalk between themselves and adjacent wafers when arranged in a connector housing. A conductive slab member is formed over the sleeve to provide a capacitive coupling with the conductive foil of the signal cable. | 2010-04-01 |
20100081303 | HIGH DENSITY PLUGGABLE ELECTRICAL AND OPTICAL CONNECTOR - A connector assembly is provided that includes a front end mating connector which is received in a socket. The front end mating connector includes a pluggable transceiver, latching mechanism, and passive optical connector. Standard optical ribbon fibers are provided that plug into the passive connector, which in turn plugs into the transceiver. The passive connector and the transceiver are coupled together by the latching mechanism. The coupled connector then plugs into the socket in a first direction. The socket includes electrical connector wafers. As the transceiver is plugged into the socket, circuit boards within the transceiver move in a second direction to engage the wafers. The transceiver has a circuit that converts the optical signals received by the receiver ribbons into electrical signals that are recognized by the wafers and passed to the circuit board. The circuit also converts the electrical signals received from the circuit board through the wafers in the socket into optical signals for transmission by the optical ribbon fibers. | 2010-04-01 |
20100081304 | HIGH-POWER BREAKER SWITCH FOR A VEHICLE - Breaker switch includes connector, socket, and surrounding housings. The connector housing has contacts and a blocking lever. The socket housing has sockets and a gear rack. An operating lever has a gear mounted to the connector housing and engaged to the gear rack to mount the connector and socket housings such that the connector housing is movable relative to the socket housing between starting and final positions. In the starting position the connector and socket housings disengage such that the contacts and sockets disengage. In the final position the connector and socket housings engage such that the contacts and sockets engage. In the starting and final positions the blocking lever engages the gear to maintain the position of the connector housing. The surrounding housing is connected to the socket housing and has a control edge that releases the blocking lever from the gear to enable the connector housing to move. | 2010-04-01 |
20100081305 | ELECTRICAL CARD CONNECTOR - An electrical card connector comprises an insulative housing ( | 2010-04-01 |
20100081306 | ELECTRICAL PLUG AND SOCKET ASSEMBLY - An electrical plug and socket assembly includes a socket and a plug. The socket includes a socket housing, a plurality of female connectors and a plurality of circuit members. Each of the plurality of circuit members having a non-conductive portion and a conductive portion slidably coupled to one of a live line and a neutral line. The plug includes a plurality of male connectors and a prong structure. The prong structure is capable of pressing the plurality of circuit members, thereby enabling the longitudinal sliding movement. Live female connector and neutral female connector are connected to the live line and the neutral line through the plurality of circuit members. Accordingly, an electrical connection of one of the live line and the neutral line with one of live female connector and neutral female connector may be controlled based upon pressing of the plurality of circuit members by the prong structure. | 2010-04-01 |
20100081307 | Systems and Methods for Blind-Mate Connector Alignment - In accordance with the teachings of the present disclosure, systems and methods for aligning blind-mate connectors are provided. In one embodiment, a system comprises an avionics processing canister that is coupled to a mounting block. The avionics processing canister comprises a first portion of a first blind-mate connector, and a face plate with a surface that defines a pin-hole and a slot. The slot has a short dimension substantially equal to the diameter of the pin-hole and a long dimension perpendicular to the short dimension. The long dimension is longer than the short dimension. The system also comprises a first fastener that is received through the pin-hole and then into a first hole defined by a surface of the mounting block. The pin-hole has a diameter that is substantially equal to an outer diameter of the first fastener. The system also comprises a second fastener that is received through the slot and then into a second hole defined by a surface of the mounting block. The slot is oriented such that the second fastener constrains rotation of the face plate about a center of the pin-hole to align the first portion of the first blind-mate connector to a second portion of the first blind-mate connector. | 2010-04-01 |
20100081308 | RF connector having contact terminal set with movable bridge - A RF connector comprising: an insulative housing defining a space section; an upper fixed contact and a lower movable contact are disposed on two opposite sides of the housing in a first direction, each of said upper fixed contact and said lower movable contact including a contact section in the space section and a solder tail exposed outside of the housing, the lower movable contact having on two opposite sides a pair of bending ends disposed which is a lying U-shape; and an upper case mounted upon the housing and defining a plug insertion passageway; and a metallic shell enclosing said upper case and the housing. | 2010-04-01 |
20100081309 | SEALED, SOLDERLESS I/O CONNECTOR - A sealed, solderless I/O connector for allowing the connection of cables or desk accessories to a mobile communication device while providing a weather tight seal allowing the use of the mobile communication device outdoors. The sealed, solderless I/O connector provides for greater tolerance of mechanical stress due to vibration or dropping because the contact points between the connector and the printed circuit board accomplished with a “U” shaped spring contact. The sealed, solderless I/O connector also provides a locking mechanism to prevent unintended detachment of the cable or desk accessory. | 2010-04-01 |
20100081310 | CONNECTOR CONNECTION TERMINAL AND CONNECTOR USING THE SAME - A connector connection terminal has a fixed piece to be inserted to a base of a connector, a coupling portion extending from the fixed piece, and a movable piece extending in parallel to the fixed piece to both sides from a free end of the coupling portion and being operated by an operation lever rotatably assembled to the base. An aspect ratio of a cross-sectional area of the coupling portion is greater than or equal to 1.2. | 2010-04-01 |
20100081311 | Tamper-Evident Connector - Embodiments of a tamper-evident connector are disclosed which may optionally be used in a trusted computing environment. In an exemplary embodiment, a tamper-evident connection includes a mate-once engaging assembly for providing with a first component, the mate-once engaging assembly including a foldable portion. The tamper-evident connection also includes a receiving chamber for providing with a second component, the mate-once engaging assembly fitting in the receiving chamber to physically secure the first component to the second component, the foldable portion of the mate-once engaging assembly unfolding during removal of the mate-once engaging assembly from the receiving chamber to provide evidence of tampering when the first component has been removed from the second component. Optionally, the first component is a Trusted Platform Module (TPM) and the second component is a system board. | 2010-04-01 |
20100081312 | Electrical Connector - An electrical connector is provided, capable of exerting a sufficient clamping force on a flat cable to reliably provide electrical conductivity while the connector is low-profile. The connector includes a contact having a base, a contact beam, and a pressing arm. The pressing force of a cam of an actuator is transmitted to a base through the pressing arm. Thereby, lift of the base is restrained, and a flat cable is reliably clamped, thereby providing electrical conductivity. Also, elastic deformation of the pressing arm reduces the range of variations in the contact pressure of a contact arm of the contact beam caused by the variations in thickness, gap, dimension, and the like. | 2010-04-01 |
20100081313 | Lever-Type Connector - There is provided a lever-type connector, whereby it is possible to avoid any damage at a mating contact provided at a mating connector, when the mating connector is subjected to so-called twist mating on the pivotal end of arms of a lever. The lever-type connector having a housing that includes a contact receiving area, a slider receiving slot, a slider, a wire cover, an outlet, a lever provided with a connector and being rotatably and detachably disposed on the housing and the cover to slide the slider; a pair of arms that extend from both ends of the connector, and a pair of wall portions arranged at the pivotal end of the arms of the lever. The wall portions extend from a pivotal end of the arms, respectively, and oppose each other at end edges of the wall portions, respectively. The outlet arranged at the wire cover has a width set greater than a width of a contact receiving area in the housing. | 2010-04-01 |
20100081314 | POWER CORD COUPLING DEVICE - A power cord coupling device comprising: a compressible base with a first end and a second end, and the second end is threaded; a threaded cap, configured to thread onto the second end of the compressible base; and where compressible base is configured to compress about a coupled plug and receptacle located within the compressible base upon a tightening of the threaded cap onto the second end of the compressible base. A power cord coupling device comprising: an inner compressible member of a first length, the inner compressible member comprising: a plug-receptacle volume located within the inner compressible member; an inner slot extending along the first length; a first end with a first end slot that is contiguous with the inner slot; a second end, the second end being generally opened; an inner set of teeth located on an outer surface of the inner compressible member; an outer member of a second length, removeably attachable to the inner compressible member; the outer member comprising: an outer slot extending along the second length; a first end, the first end being generally opened; a second end with a second end slot that is contiguous with the inner slot; an outer set of teeth located on an inner surface of the outer member, the outer set of teeth configured to mesh with the inner set of teeth to hold the inner compressible member within the outer member. to be completed upon approval of claim scope | 2010-04-01 |
20100081315 | CONNECTOR BLOCK FEATURE - A memory card connector, within a slot of a host device, for receiving a first memory card having a first row of contact fingers and a second row of contact fingers and a second memory card having only a single row of contact fingers. The memory card connector includes a first row of contact pins, a second row of contact pins and a protrusion. The first row of contact pins are configured to mate with the first row of contact fingers of the first memory card. The second row of contact pins are configured to mate with the second row of contact fingers of the first memory card. The protrusion is received within a contact finger in the second row of contact fingers of the first memory card to allow full insertion of the first memory card into the connector, and abuts against a distal end of one of the contact fingers of the second memory card to prevent full insertion of the second memory card into the connector. | 2010-04-01 |
20100081316 | INSTALLATION SWITCHING DEVICE - An installation switching device comprises a housing having a front and a rear face, a mounting side, at least one front and rear narrow side, two wide sides and having an opening at least on the rear face. The installation switching device further comprises a screwless terminal connection including a clamping spring disposed in a terminal connection space and configured to connect a plurality of connecting conductors and a terminal cover part swivelably connected to the housing and configured to cover the opening, the terminal cover part having a terminal face with a plurality of terminal openings, each corresponding to one of the plurality of connecting conductors to be connected and a guide device molded onto each of the at least one terminal openings and configured to guide the connecting conductors. | 2010-04-01 |
20100081317 | GROUNDING BAND FOR ELECTRICAL CONNECTORS - A conductive band for an electrical connector that includes an elastic metal strap with first and second ends and an array of flexible members extending between the first and second ends. Each of the first and second ends has a terminal lead. A clip is coupled to the terminal leads of the first and second ends. | 2010-04-01 |
20100081318 | POWER OUTLET ORGANIZER - A power outlet organizer for an intravenous pole assembly may include a housing, at least one electrical outlet, an electrical cord, a biasing member, a support mechanism and a fastener. The electrical cord may include a first end portion electrically connected to the at least one electrical outlet and a second end portion electrically connected to an electrical plug. The electrical cord may be movable between a retracted position within the housing and an extended position for connecting the electrical plug to a wall socket. The biasing member may be configured to move the electrical cord to the retracted position. The support mechanism may include an elongated support structure carried by the housing and a plurality of brackets configured on the elongated support structure. Each bracket may be adapted for receiving a power cord of a medical device therein to preclude scattering thereof on a floor. | 2010-04-01 |
20100081319 | Telecommunications Patch - A connecting panel assembly including pivot modules that are pivotally connected to a frame of the assembly. The pivot modules include a plurality of jack modules. The jack modules have a plug opening on one side and wire terminations on an opposite side. The pivot modules are pivotally coupled at opposite ends of the frame. The pivot modules can pivot from a closed position wherein the pivot modules are aligned parallel with the frame, and an open angled position wherein the pivot modules are positioned at an angled position relative to the frame. The assembly also includes a support member that supports the pivot modules in the angled position. | 2010-04-01 |
20100081320 | L-SHAPED COAXIAL CONNECTOR AND THE MANUFACTURING METHOD - An L-shaped coaxial connector manufactured with a relatively small number of processes and a method of manufacturing the L-shaped coaxial connector are provided. A housing of the L-shaped coaxial connector is connected to an outer conductor. A bushing is attached to the housing. A socket is attached to the bushing, and the socket is insulated from the housing through the bushing. The housing includes a crimping portion. The crimping portion is bendable, in a state in which a part of the bushing is exposed, so that the crimping portion is in pressed contact with the bushing. The bushing is in pressed contact with the insulating film with a force from the crimping portion. The socket pierces the insulating film with a force from the bushing to connect to a center conductor of a coaxial cable. | 2010-04-01 |
20100081321 | CABLE CONNECTOR - A coaxial cable connector for coupling a coaxial cable to a mating connector includes a connector body having a forward end and a rearward cable receiving end for receiving a cable. A nut is rotatably coupled to the forward end of the connector body. An annular post is disposed within the connector body, the post having a forward flanged base portion disposed within a rearward extent of the nut, the forward flanged base portion having a forward face. A biasing element is attached to the forward flanged base portion of the post and includes a deflectable portion extending outwardly in a forward direction beyond the forward face of the post shoulder portion. | 2010-04-01 |
20100081322 | Cable Connector - A cable connector configured to couple a cable to another connector or piece of video or audio equipment may include a connector body, a nut, an annular post and a biasing element. The connector body may include a forward end and a rearward end, where the forward end is configured to connect to the second connector and the rearward end is configured to receive a coaxial cable. The nut may be rotatably coupled to the forward end of the connector body and the annular post may be disposed within the connector body. The annular post may also include an annular notch located at the forward end of the connector body. The biasing element may be located in the annular notch. | 2010-04-01 |
20100081323 | HF HOUSING COUPLER AND METHOD FOR PRODUCING THE SAME - An HF housing coupler having a connector part connected to a housing is described, which has a connecting structure, via which a coaxial plug can be detachably connected to the connector part in a fixed manner. | 2010-04-01 |
20100081324 | COAXIAL CABLE CONNECTOR WITH AN INTERNAL COUPLER AND METHOD OF USE THEREOF - A coaxial cable connector is provided, the connector includes: a connector body; a coupling circuit positioned within the connector body and configured to sense an electrical signal flowing through the connector; and an electrical parameter sensing circuit positioned within the connector body and configured to sense a parameter of the electrical signal flowing through the RF port. | 2010-04-01 |
20100081325 | TERMINAL FITTING, A TERMINAL FITTING CHAIN, A WIRE WITH A TERMINAL FITTING AND A PROCESSING DEVICE THEREFOR - A wire with a terminal fitting ( | 2010-04-01 |
20100081326 | CARD CONNECTOR WITH SHELL - An electrical card connector | 2010-04-01 |
20100081327 | METHOD AND APPARATUS FOR COMPONENT HANDLING - A method and apparatus for an adaptor are provided. The adaptor includes a first engaging end including a first connector half configured to mate with a complementary connector half. The first engaging end further includes a first diameter. The adaptor also includes a second engaging end including a second connector half configured to mate with a complementary connector half. The second engaging end further includes a second diameter. The adaptor further includes a body extending between the first engaging end and the second engaging end. The body includes an outer sheath at least partially covering the body and extending at least partially between the first engaging end and the second engaging end wherein the outer sheath includes a third diameter that is greater than at least one of the first and the second diameter. | 2010-04-01 |
20100081328 | LGA socket with having improved standoff - An LGA socket includes an insulative housing, a number of conductive terminals received retained in the housing, a stiffener surrounding the insulative housing, a load plate and a load lever pivotally assembled to the stiffener, and a locking mechanism. The locking mechanism includes a screw attached to the stiffener in a horizontal direction and a washer attached to the support plate in a vertical direction. The locking mechanism is attached to the stiffener before the LGA socket mounting to a printed circuit board. | 2010-04-01 |
20100081329 | ELECTRICAL CONTACT HAVING IMPROVED SOLDERING SECTION OF HIGH COMPLIANCE - An electrical contact ( | 2010-04-01 |