13th week of 2011 patent applcation highlights part 55 |
Patent application number | Title | Published |
20110078323 | RULES-BASED USER PREFERENCES FOR STREAM SWITCHING IN AN INTERNET RADIO PLAYER - An internet radio player provides more personalized streaming audio content by assigning play amounts to different stream sources, and then playing streams from the different sources at a playback device for play times corresponding to the respective play amounts. The play time for a given stream is calculated as a user-defined percentage for the associated stream source multiplied by an expected listening period. The different stream sources can include different musical genres, news, sports, weather, or traffic. Play amounts are automatically adjusted based on user selection of the currently-playing stream source for increased or decreased play. A particular stream can also be played at a predetermined clock time, and the streams can further be ordered for play according to user preference. The present invention accordingly provides a richer listening experience than that attained by listening to a single internet radio stream, even if the single stream already reflects a user's preferences. | 2011-03-31 |
20110078324 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD - There is provided an information processing apparatus including a communication unit which communicates with a distribution server that contains content data for streaming delivery, a buffer unit which temporarily stores stream data obtained from the distribution server, a storage unit which stores an inserting content, a reproduction unit which reproduces the content inserted by the storage unit, and a control unit which measures a bandwidth of the network, determines whether it is possible to reproduce until the end of a next chapter defined by a chapter point set in the content based on a buffer volume of the buffer unit and the bandwidth, and when determined it is impossible, switches the content to be produced by the reproduction unit to the inserting content. | 2011-03-31 |
20110078325 | SYSTEMS AND METHODS FOR DISCONTINUOUS MULTI-MEDIA CONTENT TRANSFER AND HANDLING - Embodiments of the invention broadly provide systems, methods and devices for discontinuous multi-media content transfer and handling. Various embodiments of the invention also provide for multi-media content management such that various policies (for example, DRM policies of multi-media content providers) are efficiently adhered to. | 2011-03-31 |
20110078326 | COMMUNICATION DEVICE AND COMMUNICATION METHOD OF THE SAME - In the gateway device, the global address (GA) of the host table is set to the same value, and the GA and the local port (LP) of the transfer table are respectively set to the same value. In the IP packet analysis unit, the sorting unit analyzes the packet from the WEB client and sorts the destination of the packet, the redirection unit supplies the GA and the global port (GP) to the WEB client that has made a request by the packet according to a result of analysis to perform redirection, and the translation/transfer unit analyzes the packets transmitted through the sorting unit, translates the addresses (GA/LA: local address) and the ports (GP/LP) respectively with each other and transfers the translated packets, and then the procedure after connection establishment is repeated. | 2011-03-31 |
20110078327 | Content delivery utilizing multiple content delivery networks - Content delivery includes receiving a Domain Name Service (DNS) request, selecting from a plurality of Content Delivery Networks (CDNs) a CDN to provide content associated with the DNS request, processing the DNS request and generating a response, the response including a canonical name (CNAME) value that corresponds to the selected CDN, receiving an indication that the content is not presently available at the selected CDN, and returning an Internet Protocol (IP) address of a data source that is configured to provide the content to the selected CDN. | 2011-03-31 |
20110078328 | MODULE COMMUNICATION - A communication network for communicating between a plurality of modules is disclosed. Each module is arranged to be connected to or associated with one of the plurality of communication gateways and each communication gateway is connectable to at least one other communication gateway. The communication gateways each have a dynamic module naming list to enable the communication gateway to determine a route to direct a message to an appropriate recipient module using the recipient module's local communication gateway. | 2011-03-31 |
20110078329 | CUSTOMIZED ALGORITHM AND METHOD OF MIXING MULTIPLE DIFFERENT ALGORITHMS - Methods, devices, and systems are provided such that multiple existing algorithms can be mixed according to a customer's needs to create a customized mixed algorithm. Solutions are provided for dynamically selecting two or more different and existing algorithms to be mixed into a single algorithm. Arbitration rules can be invoked to determine which algorithm in the set of existing algorithms will supersede the other algorithms in the event of a conflict. | 2011-03-31 |
20110078330 | COMMUNICATION SYSTEM, TERMINAL DEVICE AND COMMUNICATION CONTROL DEVICE - A communication system including a communication control device connecting to an external network, a NAT device connecting to the external network, and a terminal device connecting to an internal network under control of the NAT device, the terminal device including a NAT information identification portion, a NAT information transmitting portion that transmits NAT type information to the communication control device, a type request transmitting portion, a type response receiving portion that receives the NAT type information transmitted from the communication control device in response to the type request signal, and a first communication portion that performs communication with another terminal device using the received NAT type information, the communication control device including a NAT information receiving portion, a storage control portion that stores the received NAT type information in a storage device, a type request receiving portion, and a type response transmitting portion that transmits the stored NAT type information. | 2011-03-31 |
20110078331 | MECHANISM FOR ENABLING LAYER TWO HOST ADDRESSES TO BE SHIELDED FROM THE SWITCHES IN A NETWORK - Methods and systems for shielding layer two host addresses (e.g., MAC addresses) from a network are provided. According to one embodiment, a border component of a network of switches receives a first packet intended for a first host having a first L2 address and a first L3 address associated therewith. The first packet includes the first L3 address and a substitute L2 address as destination addresses. The substitute L2 address is associated with a communication channel of the border component. A data structure including information regarding an association between the first L3 address and the first L2 address is accessed by the border component. A determination is made that the destination L2 address for the first packet should be the first L2 address. A first updated packet is derived from the first packet by replacing the substitute L2 address with the first L2 address and sent to the first host. | 2011-03-31 |
20110078332 | METHOD OF SYNCHRONIZING INFORMATION ACROSS MULTIPLE COMPUTING DEVICES - A method of synchronizing data across multiple computing devices, at least one of the computing devices being a mobile device. After at least one modification has been made to data stored by a first computing device, the first computing device compiles synchronization information comprising first information related to the modification and identifying the first computing device. Then, the first computing device sends the synchronization information to a server. The server identifies a second computing device associated with the first computing device, and sends update information to the second computing device. The update information comprises second information related to the modification made to the data stored by the first computing device. In response to receiving the update information, the second computing device modifies data stored on the second computing device in accordance with the second information, or outputs the second information of the update information. | 2011-03-31 |
20110078333 | SYNCHRONIZATION OF SERVER-SIDE COOKIES WITH CLIENT-SIDE COOKIES - Described are methods and systems for synchronizing client-side cookies with server-side cookies. A control that executes on a client computer within the context of a remote application, receives control input that is generated by a remote control that executes on a server within the remote application. In response to receiving the control input, the control generates a content request and forwards the content request to a synchronization agent that executes on the client computer. In many instances, the content request is a request for a cookie. Upon receiving the content request, the synchronization agent determines the type of content requested and responsively issues a synchronization request to a remote synchronization agent that executes on the server. The remote synchronization agent retrieves the requested content from the server and transmits the requested content to the synchronization agent. Upon receiving the requested content, the synchronization agent returns the content to the control. | 2011-03-31 |
20110078334 | METHODS AND APPARATUS FOR MANAGING VIRTUAL PORTS AND LOGICAL UNITS ON STORAGE SYSTEMS - A storage system configured to associate a virtual port | 2011-03-31 |
20110078335 | ELECTRONIC DEVICE AND DATA CONTROL METHOD THEREOF - An electronic device and data control method are provided. The electronic device includes a connector which is connected to an external storage medium storing media data therein; an identification unit which identifies a storage identifier (ID) of the external storage medium connected to the connector; and a controller which performs a media function corresponding to the media data stored in the external storage medium whose storage ID is identified by the identification unit. | 2011-03-31 |
20110078336 | STATE CHANGE IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION - The present disclosure includes methods, devices, and systems for state change in systems having devices coupled in a chained configuration. A number of embodiments include a host and a number of devices coupled to the host in a chained configuration. The chained configuration includes at least one device that is not directly coupled to the host. The at least one device that is not directly coupled to the host is configured to change from a first communication state to a second communication state responsive to receipt of a command from the host. | 2011-03-31 |
20110078337 | Configuration Adaptation Layer for Mapping I/O Device Resources - A configuration adaptation layer (CAL) for I/O devices such as I/O adapters is provided. This configuration adaptation layer (CAL) explicitly provides a mapping between adapter functions and adapter resources in a way such that it is senseable in-band by the computer system using the adapter, e.g., by a virtual machine monitor. | 2011-03-31 |
20110078338 | Card Type Peripheral Apparatus and Host Apparatus - A card type peripheral apparatus connected to a host apparatus for communication therewith according to a specific protocol. The card type peripheral apparatus includes a plurality of configuration registers configured to be accessible by the host apparatus and to be set with diverse set information. At least one of the plurality of configuration registers is a special register configured to be set with data arbitrarily selected and fixedly established by a vendor that either fabricates or markets the card type peripheral apparatus. The special register is set with protocol identification information for discriminating the specific protocol. | 2011-03-31 |
20110078339 | IMAGE PROCESSING DEVICE HAVING A PLURALITY OF CONTROL UNITS - An image processing device includes a memory unit that stores plural sets of user information and a plurality of modes in correspondence with each other so as to specify correspondence between a plurality of users and the plurality of modes, and a plurality of control units that execute a function on image data in one of the plurality of modes corresponding to one of the plurality of users having a predetermined relationship with a current user. | 2011-03-31 |
20110078340 | VIRTUAL ROW BUFFERS FOR USE WITH RANDOM ACCESS MEMORY - Methods, apparatuses and systems to decrease the energy consumption of a memory chip while increasing its effect bandwidth during the execution of any workload. Methods, apparatuses and systems may allow a memory chip utilize a plurality of virtual row buffers to respond to requests for data included in a memory array block. Methods, apparatuses and systems may further eliminate or reduce the cost associated with transferring unnecessary data from a memory array block to row buffers by altering the data transfer size between a memory array block and a row buffer. | 2011-03-31 |
20110078341 | METHOD OF MONITORING HOST ACTIVITY - A method of using a device, including monitoring host activity in an autonomous manner, without the host reporting to the device about its activity. The method also including initiating communications from the device and using resources of the host for such communications, thereby enabling the device to function as a proactive device. | 2011-03-31 |
20110078342 | System and Method for Direct Memory Access Using Offsets - A DMA device may include an offset determination unit configured to determine a first offset for a DMA transfer and a data transfer unit. The data transfer unit may be configured to receive a first buffer starting address identifying a starting location of a first buffer allocated in memory for the DMA transfer and to generate a first buffer offset address by applying the first offset to the first buffer starting address. The data transfer unit may be further configured to use the first buffer offset address as a starting location in the first buffer for data transferred in the DMA transfer. By applying various offsets, such DMA devices may spread memory access workload across multiple memory controllers, thereby achieving better workload balance and performance in the memory system. | 2011-03-31 |
20110078343 | DISTRIBUTED STORAGE NETWORK INCLUDING MEMORY DIVERSITY - A distributed storage processing unit can generate data slices and determine metadata for each of the data slices. The metadata includes information that can be used to determine storage diversity preferences, which can include requirements that data slices generated from a common data segment each be stored in memories of the same (or different) type and model, memories with the same (or different) failure rates, memories having fast read (or write) characteristics, and so on. Decisions about which memory units to use for storing data slices can be made based on how closely the characteristics of the memories match the storage diversity preferences. The decision can be made at a distributed storage processing unit that generates the data slices, at a distributed storage unit receiving the data slices for storage, or elsewhere. | 2011-03-31 |
20110078344 | HARDWARE ASSISTED ENDPOINT IDLENESS DETECTION FOR USB HOST CONTROLLERS - In some embodiments, an electronic apparatus comprises at least one memory module, and a universal serial bus (USB) host controller coupled to the memory, wherein the USB host controller implements hardware assisted idleness endpoint detection. | 2011-03-31 |
20110078345 | MOBILE COMMUNICATIONS TERMINAL USING MULTI-FUNCTIONAL SOCKET AND METHOD THEREOF - A mobile communications terminal using a multi-functional socket and a method thereof, the mobile communications device comprising a connector capable of connecting the mobile communications device to at least one external device for establishing an electrical connection between the at least one external device and the mobile communications device; a switching unit; and a controller cooperating with the connector and the switching unit to perform, sending and/or receiving at least one signal with respect to the at least one external device via at least one dedicated path according to at least one identification signal; and generating a control signal to control the at least one signal, wherein the at least one signal comprises at least one of a power signal and data. | 2011-03-31 |
20110078346 | Computer Networking Device and Method Thereof - A universal computer networking device, in particular an Ethernet switch and the like, comprising a computer networking device having more than one power connection located on the computer networking device, wherein the computer networking device connects to a power source from either a first side or a second side of the computer networking device. Also, a method providing a computer networking device having more than one power connection located on the computer networking device, wherein the computer networking device connects to a power source from either a first side or a second side of the computer networking device, and attaching a power source to a first opening located proximate the first side of the computer networking device or to the second opening located proximate a second side of the computer networking device. Also, a device which contains Copper RJ45 transceiver ports and fiber-optic transceiver ports on the same switch. Additionally, a device and method of performing a high potential voltage test to an electronic device without major disassembly. Lastly, a device and method to transfer heat away from a heat-emitting component located within an electronic device, and in particular, a computer networking device. | 2011-03-31 |
20110078347 | METHOD AND SYSTEM FOR SUPPORTING PORTABLE DESKTOP - A method is disclosed for a portable peripheral memory storage device. The peripheral memory storage device is coupled with a workstation. In a first mode of operation, a portion of the peripheral memory storage device is mounted on the workstation for operation therewith as a storage medium in a first mode of operation. In a second other mode of operation data within the peripheral memory storage device is used to support a personal desktop on the workstation. | 2011-03-31 |
20110078348 | Remote Control Apparatus for Consumer Electronic Appliances - An apparatus for the remote wireless control of a consumer electronic audio visual appliance such as a TV set, and/or for internet uploading, includes a remote control handset and a wireless receiver for connection to the appliance. The remote control unit is adapted to transmit audio and/or visual data (A/V data) and control codes to the receiver. The receiver is responsive to the A/V data and control codes to control the appliance to play and/or display the A/V data. The remote control unit includes a reader for a storage medium for A/V data, or a cable or wireless interface to an A/V acquisition device such as digital video or digital still camera or digital music player or recorder. | 2011-03-31 |
20110078349 | BUS-PROTOCOL CONVERTING DEVICE AND BUS-PROTOCOL CONVERTING METHOD - A bus-protocol converting device includes: a command detecting unit that detects a command sent from an external-memory control device, connected to a primary bus, to a primary bus interface controller; a command converting unit that converts the detected command into a command to be sent from a secondary bus interface controller to an external memory device through a secondary bus; a status detecting unit that detects a status sent from the external memory device; a status converting unit that converts the detected status into a status to be sent from the primary-bus interface controller to the external-memory control device through the primary bus; and a data transfer controller that is provided between the primary bus interface controller and the secondary bus interface controller to perform data transfer between the external-memory control device and the external memory device through a DMA bus. | 2011-03-31 |
20110078350 | METHOD FOR GENERATING MULTIPLE SERIAL BUS CHIP SELECTS USING SINGLE CHIP SELECT SIGNAL AND MODULATION OF CLOCK SIGNAL FREQUENCY - A system includes a serial bus having an electrical net for conveying a clock signal, and a master device and a plurality of slave devices coupled to the serial bus. The master device modulates a clock signal on its output on an electrical net according to first and second manners to select respective first and second of the slave devices. The first manner is distinct from the second manner. In alternate embodiments, the first and second manners are: (1) different frequencies of the clock signal; and (2) pulse trains on the clock signal with different predetermined numbers of clock edges prior to the assertion of a single slave select signal from the master device. In alternate embodiments: (1) each slave detects the first and second manners directly from the master; and (2) a distinct device detects the first and second manners from the master device and generates individual slave selects. | 2011-03-31 |
20110078351 | INFORMATION PROCESSOR SYSTEM - In an information processor system including a memory device (MEMO), a memory control device (SL | 2011-03-31 |
20110078352 | Administering The Polling Of A Number Of Devices For Device Status - Administering the polling of a number of devices for device status including determining whether a task identification for polling the device is in the delayed polling queue; if the task identification for polling the device is not in the delayed polling queue, determining whether the task identification for polling the device is in the immediate polling queue; if the task identification for polling the device is in the immediate polling queue; calculating a new time interval for polling the device in dependence upon a predetermined base period and a random selection of a time offset, wherein the time offset is within a predetermined range; calculating a next polling time for polling the device in dependence upon the current time and the new time interval; inserting the task identification in the delayed polling queue in dependence upon the next polling time. | 2011-03-31 |
20110078353 | COMMUNICATION PROCESSING APPARATUS, COMMUNICATION PROCESSING METHOD, CONTROL METHOD AND COMMUNICATION DEVICE OF COMMUNICATION PROCESSING APPARATUS - A communication processing apparatus ( | 2011-03-31 |
20110078354 | SMART DOCK FOR CHAINING ACCESSORIES - A system for communicating between an accessory and an electronic device includes a first interface, a second interface, and a docking station. The first interface is configured to communicate with the electronic device. The second interface is configured to communicate with the accessory. The docking station is coupled to the first interface and the second interface. The docking station is configured to receive a set of preferences from the accessory and forward the set of preferences to the electronic device. | 2011-03-31 |
20110078355 | Radio-Control Board For Software-Defined Radio Platform - A radio control board exchanges data with a radio frequency (RF) front end using a messaging protocol over an interface that includes separate data and control channels. Training data can also be passed over the interface for tuning the clock phase. | 2011-03-31 |
20110078356 | Providing A Peripheral Component Interconnect (PCI)-Compatible Transaction Level Protocol For A System On A Chip (SoC) - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 2011-03-31 |
20110078357 | MEDIUM VOLTAGE SWITCH UNIT - A medium voltage switch unit comprising an interruption unit and a disconnection unit, wherein the interruption unit comprises a first and a second interruption contact and a first drive unit which moves one of said interruption contacts between a first position in which they are in electrical connection and a second position in which they are spaced apart. The disconnection unit comprises a first and a second fixed disconnection contacts couplable and uncouplable with respective first and second movable disconnection contacts mounted on the interruption unit and electrically connected to the first interruption contact. The interruption unit is mechanically supported by a first fixed conductor and the second interruption contact is electrically connected to said first fixed conductor. The disconnection unit comprises a second drive unit which moves the interruption unit, relative to said first conductor, between: a first disconnector position in which the first movable disconnection contact and the first fixed disconnection contact are coupled while the second movable disconnection contact is isolated from said second fixed disconnection contact; a second disconnector position in which the first and second movable disconnection contacts are isolated from the first and second fixed disconnection contacts; and a third disconnector position in which the second movable disconnection contact and the second fixed disconnection contact are coupled while the first movable disconnection contact is isolated from said first fixed disconnection contact. | 2011-03-31 |
20110078358 | DEFERRED COMPLETE VIRTUAL ADDRESS COMPUTATION FOR LOCAL MEMORY SPACE REQUESTS - One embodiment of the present invention sets forth a technique for computing virtual addresses for accessing thread data. Components of the complete virtual address for a thread group are used to determine whether or not a cache line corresponding to the complete virtual address is not allocated in the cache. Actual computation of the complete virtual address is deferred until after determining that a cache line corresponding to the complete virtual address is not allocated in the cache. | 2011-03-31 |
20110078359 | Systems and Methods for Addressing Physical Memory - One embodiment of the present invention sets forth a technique for computing dynamic random access memory (DRAM) addresses from linear physical addresses for memory subsystems implementing integral power of two virtual page sizes, and an arbitrary number of available partitions. Each DRAM address comprises a row address, column address, bank address, and partition address. The linear physical address is used to generate to the DRAM address in units of a DRAM bank size. Address scrambling may be implemented to overcome transient access contention to specific DRAM pages by multiple client modules. | 2011-03-31 |
20110078360 | DATA HANDLING SYSTEM COMPRISING MEMORY BANKS AND DATA REARRANGEMENT - It is an object of the invention to provide a memory architecture that can handle data interleaving efficiently. This and other objects are achieved by the system according to the invention. The data handling system, is configured for receiving at an input a plurality of commands. The system comprises: a plurality of memory banks; a distributor connected to the input and having a plurality of distributor outputs. Each specific one of the plurality of memory banks ( | 2011-03-31 |
20110078361 | SYSTEM AND METHOD TO ENHANCE MEMORY PROTECTION FOR PROGRAMS IN A VIRTUAL MACHINE ENVIRONMENT - In a computer system supporting execution of virtualization software and at least one instance of virtual system hardware, an interface is provided into the virtualization software to allow a program to directly define the access characteristics of its program data stored in physical memory. The technique includes providing data identifying memory pages and their access characteristics to the virtualization software which then derives the memory access characteristics from the specified data. Optionally, the program may also specify a pre-defined function to be performed upon the occurrence of a fault associated with access to an identified memory page. In this manner, programs operating both internal and external to the virtualization software can protect his memory pages, without intermediation by the operating system software. | 2011-03-31 |
20110078362 | OPERATING AN EMULATED ELECTRICALLY ERASABLE (EEE) MEMORY - An emulated electrically erasable memory system includes a random access memory (RAM) and a non-volatile memory (NVM). A write access to the RAM is received which provides first write data and a first address, where the first write data is stored in the RAM at the first address, and a currently filling sector of the NVM is updated to store both the first write data and the first address as a first record. In response to the write access, based on whether there are any remaining active records in an oldest filled sector of the NVM, a portion of an erase process or a transfer of up to a predetermined number of active records from the oldest filled sector to the currently filling sector is performed. The predetermined number of active records is less than a maximum number of total records that may be stored within the oldest filled sector. | 2011-03-31 |
20110078363 | BLOCK MANAGEMENT METHOD FOR A FLASH MEMORY AND FLASH MEMORY CONTROLLER AND STORAGE SYSTEM USING THE SAME - A block management method for managing a plurality of physical blocks of a flash memory chip is provided. The block management method includes configuring a plurality of logical addresses; mapping the logical addresses to a plurality of logical blocks; and mapping the logical blocks to the physical blocks. Additionally, the block management method also includes obtaining deleting records related to a plurality of deleted logical addresses from a host system, wherein data stored in the deleted logical addresses is recognized as invalid by the host system. And, the block management method further includes obtaining a deleted logical block, marking each of the logical addresses mapped to the deleted logical block as a bad logical address, and linking the physical block mapped to the deleted logical block to a spare area. Accordingly, the block management method can effectively prolong the lifespan of a flash memory chip. | 2011-03-31 |
20110078364 | SOLID STATE STORAGE SYSTEM FOR CONTROLLING RESERVED AREA FLEXIBLY AND METHOD FOR CONTROLLING THE SAME - A solid state storage system includes a flash memory area and a memory controller. The flash memory area includes memory blocks and replacement blocks configured to replace bad blocks occurring within the memory blocks. The memory controller is configured to perform a logical-to-physical address mapping on logical blocks including the replacement blocks, and select the replacement blocks using logical addresses of the logical blocks corresponding to the bad blocks. | 2011-03-31 |
20110078365 | DATA ACCESS METHOD OF A MEMORY DEVICE - The invention provides a data access method of a memory device. In one embodiment, the memory device comprises a plurality of memories. First, a plurality of commands sequentially received from a host is stored in a command queue. A target command is then retrieved from the command queue. A target memory accessed by the target command is then determined. Whether the target memory is in a busy state is then determined. When the target memory is not in a busy state, access operations requested by the target command are then performed. When the target memory is in a busy state, a substitute command is selected from a plurality of subsequent commands stored in the command queue and access operations requested by the substitute command are performed, wherein the sequence of the subsequent commands in the command queue is subsequent to the target command. | 2011-03-31 |
20110078366 | Semiconductor device with non-volatile memory and random access memory - A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data. | 2011-03-31 |
20110078367 | CONFIGURABLE CACHE FOR MULTIPLE CLIENTS - One embodiment of the present invention sets forth a technique for providing a L1 cache that is a central storage resource. The L1 cache services multiple clients with diverse latency and bandwidth requirements. The L1 cache may be reconfigured to create multiple storage spaces enabling the L1 cache may replace dedicated buffers, caches, and FIFOs in previous architectures. A “direct mapped” storage region that is configured within the L1 cache may replace dedicated buffers, FIFOs, and interface paths, allowing clients of the L1 cache to exchange attribute and primitive data. The direct mapped storage region may used as a global register file. A “local and global cache” storage region configured within the L1 cache may be used to support load/store memory requests to multiple spaces. These spaces include global, local, and call-return stack (CRS) memory. | 2011-03-31 |
20110078368 | EFFICIENT CLOCKING SCHEME FOR A BIDIRECTIONAL DATA LINK - A method for communication via a bidirectional data link between a processing device and a memory device. The memory device includes a clock source to generate a clock signal for driving a latching at the memory device of data to and/or from the bidirectional data link. The memory device provides the clock signal to the processing device for driving a latching at the processing device of data to and/or from the bidirectional data link. | 2011-03-31 |
20110078369 | Systems and Methods for Using a Page Table in an Information Handling System Comprising a Semiconductor Storage Device - Systems and methods for using a page table in an information handling system including a semiconductor storage device are disclosed. A page table in an information handling system may be provided. The information handling system may include a memory, and the memory may include a semiconductor storage device. NonDRAM tag data may be stored in the page table. The nonDRAM tag data may indicate one or more attributes of one or more pages in the semiconductor storage device. | 2011-03-31 |
20110078370 | MEMORY LINK INITIALIZATION - Link initialization techniques to decouple the read training from the write training. Read training may be accomplished in a robust manner before write training is performed. These techniques may provide significantly improved link initialization times. A user-programmable register within a dynamic random access memory (DRAM) module may be utilized by the decoupled read training and write training processes. The decoupling may result in shorter and more robust training segments that may support faster training and/or increased link speeds. | 2011-03-31 |
20110078371 | DISTRIBUTED STORAGE NETWORK UTILIZING MEMORY STRIPES - Multiple data slices are generated from an original data segment. The data slices are constructed to prevent recovery of the original data segment using a single related data slice, but to allow recovery of the original data segment using fewer than all of the data slices. Each data slice is stored in the same memory stripe as the other data slices. The memory stripe extends across multiple memory devices and multiple different distributed storage units. The memory device in which each data slice is stored can be determined based on a source name associated with each data slice. | 2011-03-31 |
20110078372 | DISTRIBUTED STORAGE NETWORK MEMORY ACCESS BASED ON MEMORY STATE - A distributed storage unit determines how to handle a read or write request for a data slice based on a state of the memory the data slice is to be read from or written to. When receiving a request to retrieve a data slice, the distributed storage unit, determines a state of the memory in which the data slice is stored. Based on the memory state, one of multiple different methods for obtaining the data slice is selected. The methods include, among others, a direct read from the memory, and reconstructing the data slice using other memories and parity values. In response to a write request, the distributed storage unit can determine whether to use the currently selected memory for writing, or rotate the memory used for writing, based on a state of the memory. | 2011-03-31 |
20110078373 | METHOD AND APPARATUS FOR DISPERSED STORAGE MEMORY DEVICE SELECTION - A method begins when a dispersed storage (DS) processing unit of a DS unit has at least one of DS unit operational data and DS unit operating system algorithm to store. The method continues with the DS processing unit encoding at least a portion of the at least one of DS unit operational data and DS unit operating system algorithm in accordance with an error coding dispersal storage function to produce a plurality of data slices. The method continues with the DS processing unit storing at least some of the plurality of data slices in memory devices of the DS unit in accordance with the error coding dispersal storage function. | 2011-03-31 |
20110078374 | DISK ARRAY APPARATUS - A disk array apparatus improves scalability, performance such as data transfer between different kinds of I/Fs, and maintainability and reliability about boards/PKs configuring the DKC and about a DKC configuration obtained by interconnecting them. The DKC in the disk array apparatus is configured by interconnecting mix PKs each including a base PK and a functional PK which is hierarchically connected to the base PK and on which individually separate functions are mounted. The base PK coexists with and is connectable to a plurality of different I/F-PKs, and includes an intra-package interconnection network for communicating between the functional PKs and with the DKC, and further has a processor interconnection network. The DKC performs a data transfer processing by using the functional PK and the base PK. | 2011-03-31 |
20110078375 | DATA STORAGE - A method and device for executing data access and storage using a host device, the method comprising providing a removable device for the host operable to effect communication between the host and a remote storage service, wherein the removable device is operable to cache data received from and sent to the storage service, the removable device further operable to effect communication between the host device and the storage service using a wireless communication module. | 2011-03-31 |
20110078376 | METHODS AND APPARATUS FOR OBTAINING INTEGRATED CONTENT FROM MULTIPLE NETWORKS - A method and apparatus for obtaining location content from multiple networks is disclosed. The method may comprises: obtaining coarse location content at a wireless communication device (WCD) from a first network using a first protocol, wherein the coarse location content includes information defining locations of geographic coverage regions for one or more second networks which use a second protocol, obtaining WCD location information, determining from the WCD location information and the coarse location content if the WCD is within the geographic coverage region of a second network, accessing the determined second network using the second protocol, receiving from the accessed second network fine location content, and generating an integrated location content item by combining the coarse location content with the fine location content. | 2011-03-31 |
20110078377 | SOCIAL NETWORKING UTILIZING A DISPERSED STORAGE NETWORK - Social networking data is received at the dispersed storage processing unit, the social networking data associated with at least one of a plurality of user devices. Dispersed storage metadata associated with the social networking data is generated. A full record and at least one partial record are generated based on the social networking data and further based on the dispersed storage metadata. The full record is stored in a dispersed storage network. The partial record is pushed to at least one other of the plurality of user devices via the data network. | 2011-03-31 |
20110078378 | METHOD FOR GENERATING PROGRAM AND METHOD FOR OPERATING SYSTEM - An information processing apparatus sequentially selects a function whose execution frequency is high as a selected function that is to be stored in an internal memory, in a source program having a hierarchy structure. The information processing apparatus allocates the selected function to a memory area of the internal memory, allocates a function that is not the selected function and is called from the selected function to an area close to the memory area of the internal memory, and generates an internal load module. The information processing apparatus allocates a remaining function to an external memory coupled to a processor and generates an external load module. Then, a program executed by the processor having the internal memory is generated. By allocating the function with a high execution frequency to the internal memory, it is possible to execute the program at high speed, which may improve performance of a system. | 2011-03-31 |
20110078379 | STORAGE CONTROL UNIT AND DATA MANAGEMENT METHOD - An I/O processor determines whether or not the amount of dirty data on a cache memory exceeds a threshold value and, if the determination is that this threshold value has been exceeded, writes a portion of the dirty data of the cache memory to a storage device. If a power source monitoring and control unit detects a voltage abnormality of the supplied power, the power monitoring and control unit maintains supply of power using power from a battery, so that a processor receives supply of power from the battery and saves the dirty data stored on the cache memory to a non-volatile memory. | 2011-03-31 |
20110078380 | MULTI-LEVEL CACHE PREFETCH - Methods and apparatus relating to multi-level cache prefetch are described. In some embodiments, a data parking logic updates a prefetch request with one or more bits based on the status of a request queue. The one or more bits may in turn cause the corresponding prefetched data to be stored in one of at least two caches. Other embodiments are also described and claimed. | 2011-03-31 |
20110078381 | Cache Operations and Policies For A Multi-Threaded Client - A method for managing a parallel cache hierarchy in a processing unit. The method including receiving an instruction that includes a cache operations modifier that identifies a level of the parallel cache hierarchy in which to cache data associated with the instruction; and implementing a cache replacement policy based on the cache operations modifier. | 2011-03-31 |
20110078382 | Adaptive Linesize in a Cache - A mechanism is provided in a cache for emulating larger linesize in a substrate with smaller linesize using gang fetching and gang replacement. Gang fetching fetches multiple lines on a cache miss to ensure that all smaller lines that make up the larger line are resident in cache at the same time. Gang replacement evicts all smaller lines in cache that would have been evicted had the cache linesize been larger. The mechanism provides adaptive linesize using set dueling by dynamically selecting between multiple linsizes depending on which linesize performs the best at runtime. Set dueling dedicates a portion of sets of the cache to always use smaller linesize and dedicates one or more portions of the sets of cache to always emulate larger linesizes. One or more counters keep track of which linesize has the best performance. The cache uses that linesize for the remainder of the sets. | 2011-03-31 |
20110078383 | Cache Management for Increasing Performance of High-Availability Multi-Core Systems - An apparatus and method for improving performance in high-availability systems are disclosed. In accordance with the illustrative embodiment, pages of memory of a primary system that are to be shadowed are initially copied to a backup system's memory, as well as to a cache in the primary system. A duplication manager process maintains the cache in an intelligent manner that significantly reduces the overhead required to keep the backup system in sync with the primary system, as well as the cache size needed to achieve a given level of performance. Advantageously, the duplication manager is executed on a different processor core than the application process executing transactions, further improving performance. | 2011-03-31 |
20110078384 | MEMORY MIRRORING AND MIGRATION AT HOME AGENT - Methods and apparatus relating to memory mirroring and migration at a Home Agent (HA) are described. In one embodiment, a home agent may mirror its data at a slave agent. In some embodiments, a bit in a directory may indicate status of cache lines. Other embodiments are also disclosed. | 2011-03-31 |
20110078385 | System and Method for Performing Visible and Semi-Visible Read Operations In a Software Transactional Memory - The software transactional memory system described herein may implement a revocable mechanism for managing read ownership in a shared memory. In this system, write ownership may be revoked by readers or writers at any time other than when a writer transaction is in a commit state, wherein its write ownership is irrevocable. An ownership record associated with one or more locations in the shared memory may include an indication of whether the memory locations are owned for writing, and an identifier of the latest writer. A read ownership array may record data indicating which, if any, threads currently own the memory locations for reading. The system may provide an efficient read-validation operation, in which a full read-set validation is avoided unless a change in a global read-write conflict counter value indicates a potential conflict. The system may support a wide range of contention management policies, and may provide implicit privatization. | 2011-03-31 |
20110078386 | BUFFERING IN MEDIA AND PIPELINED PROCESSING COMPONENTS - Methods and apparatus relating to buffering in media and pipelined processing components are described. In one embodiment, a buffer may include an arbiter to receive data structure information from a producer, a memory to store the information, and an address generator to indicate a location in the memory to store the data structure information. Other embodiments are also disclosed. | 2011-03-31 |
20110078387 | WRITING TO MEMORY USING SHARED ADDRESS BUSES - Techniques for writing to memory using shared address buses. A memory device that includes a plurality of memory arrays connected to a common address bus, the common address bus used to broadcast memory addresses simultaneously to the plurality of memory arrays. Each memory array includes a plurality of memory locations and circuitry for: receiving the broadcasted memory addresses from the address bus; selecting a memory address in the memory array from a list of most recent memory addresses received from the address bus; and performing a memory access at the selected memory address, such that at a given point in time at least two of the memory arrays perform the memory access at a different broadcasted address when the memory access is a write. | 2011-03-31 |
20110078388 | FACILITATING MEMORY ACCESSES - In computing environments that use virtual addresses (or other indirectly usable addresses) to access memory, the virtual addresses are translated to absolute addresses (or other directly usable addresses) prior to accessing memory. To facilitate memory access, however, address translation is omitted in certain circumstances, including when the data to be accessed is within the same unit of memory as the instruction accessing the data. In this case, the absolute address of the data is derived from the absolute address of the instruction, thus avoiding address translation for the data. Further, in some circumstances, access checking for the data is also omitted. | 2011-03-31 |
20110078389 | MANAGING AND IMPLEMENTING METADATA IN CENTRAL PROCESSING UNIT USING REGISTER EXTENSIONS - A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers. | 2011-03-31 |
20110078390 | INFORMATION PROCESSING APPARATUS AND SEMICONDUCTOR STORAGE DEVICE - An information processing apparatus includes: a processor configured to perform a computation processing; a storage device configured to store first data in a first number of physical blocks and store second data in a second number of physical blocks, wherein the second data are read more frequently than the first data, and the second number is larger than the first number; and a read control module configured to read the second data from the storage device and send the second data to the processor, wherein when the processor reads the second data N times as much as the second number, N being a positive integer, the same number of the second data are read from each of the second number of physical blocks. | 2011-03-31 |
20110078391 | INFORMATION RECORDING APPARATUS, INFORMATION RECORDING METHOD, AND COMPUTER-READABLE MEDIUM - A recording area of an information recording medium is divided into a plurality of management areas. In the case where one of the management areas is selected and first file data are requested to be written, the scalability of file data that are lastly written in the selected management area is determined. If the scalability is high, the file data are written in the next management area, and, if the scalability is low, the first file data are written in succession to the file data. | 2011-03-31 |
20110078392 | WRITING TO MEMORY USING ADAPTIVE WRITE TECHNIQUES - Techniques for writing to memory using adaptive write techniques. An adaptive write technique includes receiving at a computer a message including a plurality of symbols. The message is written to a memory. The writing to memory includes performing for each symbol in the message: writing a data value to a memory location in the memory and reading contents of the memory location after the data value has been written. The data value is determined at the computer in response to the symbol and to the contents of any memory locations previously read as part of writing the message to the memory. It is determined at the computer if the contents of the memory locations reflect the message. The writing is restarted at the computer in response to determining that the contents of the memory locations do not reflect the message. | 2011-03-31 |
20110078393 | MEMORY DEVICE AND DATA ACCESS METHOD - The invention provides a data access method. First, a plurality of commands received from a host is stored in a command queue. A plurality of logical address ranges of the commands is then calculated. A plurality of write commands is then selected from the commands, wherein the logical address ranges of the write commands are overlapping with each other. Whether at least one read command having a receiving order that is in between the receiving orders of the write commands exists in the command queue is then determined. When the at least one read command does not exist, write data corresponding to the write commands are combined together to obtain combined write data according to the logical address ranges of the write commands. A combined write command and the combined write data are then sent to a memory to request that the memory executes the write commands. | 2011-03-31 |
20110078394 | COMMUNICATION AND ANALYSIS SYSTEMS AND METHODS FOR ORIGINATION AND/OR EXAMINATION OF ASSETS - Systems and methods are provided for communicating information regarding assets. A server may receive a login request and verify the identity of a user. The user may select at least one asset category from a list. The server may provide a list of communication sets for the selected asset category. Each communication set may include one or more individual communications, where each communication set corresponds to a particular asset or asset type. Each of the one or more individual communications may be archived in a data archive. The user may select at least one communication set and receive all communications within the selected communication set. The user may initiate a new communication regarding the particular asset or asset type. The new communication may be archived relative to the selected communication set. The selected communication set may be updated with the new communication and made available for all users. | 2011-03-31 |
20110078395 | COMPUTER SYSTEM MANAGING VOLUME ALLOCATION AND VOLUME ALLOCATION MANAGEMENT METHOD - In a management computer which manages a storage system including a main logical volume and subsidiary logical volumes, when the access volume to the main logical volume exceeds a threshold value, a subsidiary logical volume associated with a physical volume having higher input/output performance than the physical volume associated with the main logical volume is selected. When the migration time of the data stored in the physical volume corresponding to the selected subsidiary logical volume is within a prescribed time period, then data stored in the physical volume corresponding to the main logical volume is migrated to the physical volume corresponding to the selected subsidiary logical volume, and the physical volume corresponding to the selected subsidiary logical volume is associated with the main logical volume. | 2011-03-31 |
20110078396 | REMOTE COPY CONTROL METHOD AND SYSTEM IN STORAGE CLUSTER ENVIRONMENT - The present invention causes an asynchronous remote copy to work together with storage clustering technology. A host computer program for controlling the asynchronous remote copy carries out an asynchronous remote copy pair operation by asynchronously working together with a switchover instruction of a storage clustering control program that performs a host write-destination volume switchover in a storage clustering environment. | 2011-03-31 |
20110078397 | REMOTE COPY SYSTEM - Even when a host does not give a write time to write data, consistency can be kept among data stored in secondary storage systems. The present system has plural primary storage systems each having a source volume and plural secondary storage systems each having a target volume. Once data is received from a host, each of the plural storage systems creates write-data management information having sequential numbers and reference information and sends, to one of the primary storage systems, the data, sequential number and reference information. Each of the secondary storage systems records reference information corresponding to the larges sequential number among serial sequential numbers and stores, in a target volume in an order of sequential numbers, data corresponding to reference information having a value smaller than the reference information based on the smallest value reference information among reference information recorded in each of the plural secondary storage systems. | 2011-03-31 |
20110078398 | METHOD AND SYSTEM FOR DYNAMIC STORAGE TIERING USING ALLOCATE-ON-WRITE SNAPSHOTS - The present disclosure describes a systems and methods for dynamic storage tiering | 2011-03-31 |
20110078399 | Content approving apparatus - The present invention aims to provide an apparatus capable of determining whether or not content is permitted to be taken out, by managing contents permitted to be taken out. One aspect of the invention is characterized by comprising: a storage means that stores therein taking-out-permitted-content identification data which is data generated on the basis of a part or entirety of each content permitted to be taken out; and a generating means that generates the taking-out-permitted-content identification data. Another aspect of the present invention is characterized by comprising: a storage means that stores therein taking-out-permitted-content identification data which is data generated on the basis of a part or entirety of each content permitted to be taken out to the outside; and an approving means that determines whether a content is permitted to be taken out, with reference to the taking-out-permitted-content identification data. | 2011-03-31 |
20110078400 | Battery pack, and method of controlling operation of data flash - A method of controlling the operation of a data flash and a battery pack capable of performing the method. In the method, writing, copying, and deleting operations are performed on two data flashes according to status flags recorded in predetermined respective locations of the data flashes. If one of the data flashes is full of data, it is possible to prevent a data flash failure from occurring when a part of the data is copied from the data flash to the other data flash or the data is deleted from the data flash. | 2011-03-31 |
20110078401 | CONTROL APPARATUS, METHOD FOR CONTROLLING THE CONTROL APPARATUS, AND STORAGE MEDIUM - A method completes background processing within a shortest possible time without degrading an efficiency of main processing executed in a system. The system includes a control apparatus including a plurality of hard disks and a memory controller configured to control an access to the hard disk. The memory controller changes a unit of the background processing, which is changed according to a state of a plurality of storage devices. In changing the unit of processing, the memory controller monitors the presence or absence of an access for the main processing coming from a main controller, and changes the unit of the background processing to a first unit of processing or to a second unit of processing, which is smaller than the first unit of processing according to a result of the monitoring. | 2011-03-31 |
20110078402 | MEMORY SYSTEM - A memory system includes a non-volatile semiconductor memory that includes a plurality of blocks, each of the blocks being a data erasing unit; an erasing time monitoring unit that monitors time required for erasing data from the non-volatile semiconductor memory; a management table for managing the erasing time on a unit of each of the blocks; and a wear-leveling control unit that levels number of rewriting across the blocks based on the management table. The memory system accommodates variations among lots, individual pieces, and blocks, thereby performing highly-accurate wear leveling. | 2011-03-31 |
20110078403 | METHOD AND TERMINAL DEVICE FOR ERASING DATA OF TERMINAL - A method for erasing data of a terminal includes: receiving a data erasing request from a management server; deleting data corresponding to an erasing range node according to a value of a flag bit of the erasing range node in an erasable list; and deleting the erasing range node from the erasable list. | 2011-03-31 |
20110078404 | DYNAMIC MEMORY ALLOCATION FOR APPLICATIONS - Some embodiments of a system and a method to dynamically allocate memory to applications have been presented. For instance, an application interface executing on a processing device running in a computing system receives a request from an application running on the processing device for a predetermined capacity of memory. A kernel running on the processing device may allocate one or more consecutive heaps of memory to the application in response to the request. A total capacity of the heaps allocated is at least the predetermined capacity requested. | 2011-03-31 |
20110078405 | COMPUTER SYSTEM MANAGEMENT APPARATUS AND MANAGEMENT METHOD FOR THE COMPUTER SYSTEM - Provided is a computer system including a plurality of storage apparatuses, in which, if the storage apparatuses employ an external mapping/connection system, the plurality of storage apparatuses can efficiently use each other's storage resources. The computer system includes a plurality of storage apparatuses and a management computer for managing the storage apparatuses. The management computer determines whether or not it is possible to perform external connection between the plurality of storage apparatuses and whether or not it is possible to divert the use of a storage device in one storage apparatus to another storage apparatus, on the basis of a criteria table, and if it is possible to perform external connection between the plurality of storage apparatuses, it is carried out and, if it is not possible, the management computer diverts the use of a storage device in one storage apparatus to another storage apparatus. | 2011-03-31 |
20110078406 | Unified Addressing and Instructions for Accessing Parallel Memory Spaces - One embodiment of the present invention sets forth a technique for unifying the addressing of multiple distinct parallel memory spaces into a single address space for a thread. A unified memory space address is converted into an address that accesses one of the parallel memory spaces for that thread. A single type of load or store instruction may be used that specifies the unified memory space address for a thread instead of using a different type of load or store instruction to access each of the distinct parallel memory spaces. | 2011-03-31 |
20110078407 | DETERMINING AN END OF VALID LOG IN A LOG OF WRITE RECORDS - Provided are a method, computer program product and system for determining an end of valid log in a log of write records. Records are written to a log in a storage device in a sequential order, wherein the records include a next pointer addressing a next record in a write order and a far ahead pointer addressing a far ahead record in the write order following the record. The far ahead pointer and the next pointer in a plurality of records are used to determine an end of valid log from which to start writing further records. | 2011-03-31 |
20110078408 | Method for Protecting a Privilege Level of System Management Mode of a Computer System - A method for protecting a privilege level of a system management mode (SMM) of a computer system is disclosed. A SMM program is loaded into a special memory (SMRAM) area within a system memory of a computer. A first program, a second program, and a vector table are loaded into a general area of the system memory. Before the booting process of the computer has been completed, a reference hash value of the first program is determined by the SMM program, and the reference hash value is stored in the SMRAM area. A hash value of the first program is the computed by the SMM program. After the computer has been operating under an operating environment of an operating system, the computed hash value is compared to the reference hash value. When the computed hash value matches the reference hash value, the first program is called by the SMM program. | 2011-03-31 |
20110078409 | METHOD AND SYSTEM FOR LOCAL MEMORY ADDRESSING IN SINGLE INSTRUCTION, MULTIPLE DATA COMPUTER SYSTEM - A single instruction, multiple data (“SIMD”) computer system includes a central control unit coupled to 256 processing elements (“PEs”) and to 32 static random access memory (“SRAM”) devices. Each group of eight PEs can access respective groups of eight columns in a respective SRAM device. Each PE includes a local column address register that can be loaded through a data bus of the respective PE. A local column address stored in the local column address register is applied to an AND gate, which selects either the local column address or a column address applied to the AND gate by the central control unit. As a result, the central control unit can globally access the SRAM device, or a specific one of the eight columns that can be accessed by each PE can be selected locally by the PE. | 2011-03-31 |
20110078410 | EFFICIENT PIPELINING OF RDMA FOR COMMUNICATIONS - Disclosed are a method of and system for multiple party communications in a processing system including multiple processing subsystems. Each of the processing subsystems includes a central processing unit and one or more network adapters for connecting said each processing subsystem to the other processing subsystems. A multitude of nodes are established or created, and each of these nodes is associated with one of the processing subsystems. A first aspect of the invention involves pipelined communication using RDMA among three nodes, where the first node breaks up a large communication into multiple parts and sends these parts one after the other to the second node using RDMA, and the second node in turn absorbs and forwards each of these parts to a third node before all parts of the communication arrive from the first node. | 2011-03-31 |
20110078411 | DYNAMICALLY MODIFYING PROGRAM EXECUTION CAPACITY - Techniques are described for managing program execution capacity, such as for a group of computing nodes that are provided for executing one or more programs for a user. In some situations, dynamic program execution capacity modifications for a computing node group that is in use may be performed periodically or otherwise in a recurrent manner, such as to aggregate multiple modifications that are requested or otherwise determined to be made during a period of time, and with the aggregation of multiple determined modifications being able to be performed in various manners. Modifications may be requested or otherwise determined in various manners, including based on dynamic instructions specified by the user, and on satisfaction of triggers that are previously defined by the user. In some situations, the techniques are used in conjunction with a fee-based program execution service that executes multiple programs on behalf of multiple users of the service. | 2011-03-31 |
20110078412 | Processor Core Stacking for Efficient Collaboration - A mechanism is provided for improving the performance and efficiency of multi-core processors. A system controller in a data processing system determines an operational function for each primary processor core in a set of primary processor cores in a primary processor core logic layer and for each secondary processor core in a set of secondary processor cores in a secondary processor core logic layer, thereby forming a set of determined operational functions. The system controller then generates an initial configuration, based on the set of determined operational functions, for initializing the set of primary processor cores and the set of secondary processor cores in the three-dimensional processor core architecture. The initial configuration indicates how at least one primary processor core of the set of primary processor cores collaborate with at least one secondary processor core of the set of secondary processor cores. | 2011-03-31 |
20110078413 | ARITHMETIC PROCESSING UNIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND ARITHMETIC PROCESSING METHOD - An arithmetic processing apparatus includes an arithmetic circuit; a first memory configured to store data to be processed in the arithmetic circuit; a second memory configured to be accessed through a first path by the arithmetic circuit; a preloader configured to preload the data from the second memory into the first memory through a second path; a memory controller configured to arbitrate between a first access by the arithmetic circuit using the first path and a second access by the preloader using the second path; and a scheduler configured to control the memory controller. | 2011-03-31 |
20110078414 | MULTIPORTED REGISTER FILE FOR MULTITHREADED PROCESSORS AND PROCESSORS EMPLOYING REGISTER WINDOWS - A processor includes an instruction fetch unit configured to issue instructions for execution, where the instructions are selected from a number of threads, where each given instruction has a corresponding thread identifier, and where at least some of the instructions specify operand(s) via register identifiers. A register file stores operands usable by the instructions, and may include several banks, each corresponding to a register identifiers and including several entries corresponding to the several threads, wherein the entries are configured to store data values. In response to receiving a request to read a particular register identifier for a given thread identifier, the register file may be configured to decode the given thread identifier to retrieve entries from the banks that correspond to the given thread identifier. The register file may further select, from among the retrieved entries, a data value corresponding to the particular register identifier to be output. | 2011-03-31 |
20110078415 | Efficient Predicated Execution For Parallel Processors - The invention set forth herein describes a mechanism for predicated execution of instructions within a parallel processor executing multiple threads or data lanes. Each thread or data lane executing within the parallel processor is associated with a predicate register that stores a set of 1-bit predicates. Each of these predicates can be set using different types of predicate-setting instructions, where each predicate setting instruction specifies one or more source operands, at least one operation to be performed on the source operands, and one or more destination predicates for storing the result of the operation. An instruction can be guarded by a predicate that may influence whether the instruction is executed for a particular thread or data lane or how the instruction is executed for a particular thread or data lane. | 2011-03-31 |
20110078416 | APPARATUS AND METHOD FOR CONTROL PROCESSING IN DUAL PATH PROCESSOR - A computer processor comprises a decode unit and a processing channel. The decode unit decodes a stream of instruction packets from a memory, each instruction packet comprising a plurality of instructions. The processing channel comprises a plurality of functional units and operable to perform control processing operations. The decode unit is operable to receive and decode instruction packets of a bit length of 64 bits and to detect if the instruction packet defines three control instructions each having a length of 21 bits. The decode unit detects that the instruction packet comprises the three control instructions. The control instructions are supplied to the processing channel for execution in the order in which they appear in the instruction packet. The detection uses an identification bit in the instruction packet. | 2011-03-31 |
20110078417 | COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS - One embodiment of the present invention sets forth a technique for performing aggregation operations across multiple threads that execute independently. Aggregation is specified as part of a barrier synchronization or barrier arrival instruction, where in addition to performing the barrier synchronization or arrival, the instruction aggregates (using reduction or scan operations) values supplied by each thread. When a thread executes the barrier aggregation instruction the thread contributes to a scan or reduction result, and waits to execute any more instructions until after all of the threads have executed the barrier aggregation instruction. A reduction result is communicated to each thread after all of the threads have executed the barrier aggregation instruction and a scan result is communicated to each thread as the barrier aggregation instruction is executed by the thread. | 2011-03-31 |
20110078418 | Support for Non-Local Returns in Parallel Thread SIMD Engine - One embodiment of the present invention sets forth a method for executing a non-local return instruction in a parallel thread processor. The method comprises the steps of receiving, within the thread group, a first long jump instruction and, in response, popping a first token from the execution stack. The method also comprises determining whether the first token is a first long jump token that was pushed onto the execution stack when a first push instruction associated with the first long jump instruction was executed, and when the first token is the first long jump token, jumping to the second instruction based on the address specified by the first long jump token, or, when the first token is not the first long jump token, disabling the active thread until the first long jump token is popped from the execution stack. | 2011-03-31 |
20110078419 | SET PROGRAM PARAMETER INSTRUCTION - A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss. | 2011-03-31 |
20110078420 | METHOD FOR ADAPTING AND EXECUTING A COMPUTER PROGRAM AND COMPUTER ARCHITECTURE THEREFORE - A computer architecture ( | 2011-03-31 |
20110078421 | ENHANCED MONITOR FACILITY - A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is generated. In another mode, in response to encountering a monitored event, one or more associated counters are incremented without causing an interrupt. | 2011-03-31 |
20110078422 | IMAGE PROCESSING DEVICE HAVING A PLURALITY OF CONTROL UNITS - An image processing device includes an operating unit and a plurality of control units each configured to control the operating unit in order to execute a function on image data. The plurality of control units include at least a first control unit and a second control unit. When a first mode is selected, the control units control the operating unit to execute the function in cooperation with each other. When a second mode is selected, at least the second control unit controls the operating unit to execute the function without cooperating with the first control unit. | 2011-03-31 |