13th week of 2012 patent applcation highlights part 63 |
Patent application number | Title | Published |
20120079234 | PERFORMING COMPUTATIONS IN A DISTRIBUTED INFRASTRUCTURE - The present invention extends to methods, systems, and computer program products for performing computations in a distributed infrastructure. Embodiments of the invention include a general purpose distributed computation infrastructure that can be used to perform efficient (in-memory), scalable, failure-resilient, atomic, flow-controlled, long-running state-less and state-full distributed computations. Guarantees provided by a distributed computation infrastructure can build upon existent guarantees of an underlying distributed fabric in order to hide the complexities of fault-tolerance, enable large scale highly available processing, allow for efficient resource utilization, and facilitate generic development of stateful and stateless computations. A distributed computation infrastructure can also provide a substrate on which existent distributed computation models can be enhanced to become failure-resilient. | 2012-03-29 |
20120079235 | APPLICATION SCHEDULING IN HETEROGENEOUS MULTIPROCESSOR COMPUTING PLATFORMS - Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed. | 2012-03-29 |
20120079236 | SCALABLE AND PROGRAMMABLE PROCESSOR COMPRISING MULTIPLE COOPERATING PROCESSOR UNITS - A processor comprises a plurality of processor units arranged to operate concurrently and in cooperation with one another, and control logic configured to direct the operation of the processor units. At least a given one of the processor units comprises a memory, an arithmetic engine and a switch fabric. The switch fabric provides controllable connectivity between the memory, the arithmetic engine and input and output ports of the given processor unit, and has control inputs driven by corresponding outputs of the control logic. In an illustrative embodiment, the processor units may be configured to perform computations associated with a key equation solver in a Reed-Solomon (RS) decoder or other type of forward error correction (FEC) decoder. | 2012-03-29 |
20120079237 | Saving Values Corresponding to Parameters Passed Between Microcode Callers and Microcode Subroutines from Microcode Alias Locations to a Destination Storage Location - An apparatus of one aspect includes a microcode storage, a microcode subroutine stored in the microcode storage, and a microcode caller of the microcode subroutine stored in the microcode storage. The microcode caller has a save microinstruction that indicates a destination storage location. The apparatus also includes microcode alias locations. Each of the microcode alias locations is operable to store a value. The value in the microcode alias location corresponds to a parameter passed between the microcode caller and the microcode subroutine. The apparatus includes save logic coupled with the microcode alias locations to receive the values from the microcode alias locations. The save logic is operable, responsive to the save microinstruction, to save the values from the microcode alias locations in the destination storage location indicated by the save microinstruction. | 2012-03-29 |
20120079238 | DATA PROCESSING DEVICE - A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board. | 2012-03-29 |
20120079239 | TIMING MODULE - A timing module and a microcontroller. An independent processing unit, which is provided as a component of at least one closed-loop control circuit, is integrated in the timing module. | 2012-03-29 |
20120079240 | Reduced-Level Shift Overflow Detection - A processor includes a shift overflow detector for rapidly detecting overflows that may result during execution of a shift instruction. Shift indication signals are generated in response to changes in logic state between adjacent pairs of bits of a received shift data word. A received shift amount is decoded to produce decoded shift signals that indicate an amount of shifting for the received shift data word. An overflow condition is detected in response to the generated shift indication signals and the decoded shift signals and an indication of the detected overflow condition is provided. | 2012-03-29 |
20120079241 | INSTRUCTION EXECUTION BASED ON OUTSTANDING LOAD OPERATIONS - One embodiment of the present invention sets forth a technique for scheduling thread execution in a multi-threaded processing environment. A two-level scheduler maintains a small set of active threads called strands to hide function unit pipeline latency and local memory access latency. The strands are a sub-set of a larger set of pending threads that is also maintained by the two-leveler scheduler. Pending threads are promoted to strands and strands are demoted to pending threads based on latency characteristics, such as whether outstanding load operations have been executed. The longer latency of the pending threads is hidden by selecting strands for execution. When the latency for a pending thread is expired, the pending thread may be promoted to a strand and begin (or resume) execution. When a strand encounters a latency event, the strand may be demoted to a pending thread while the latency is incurred. | 2012-03-29 |
20120079242 | PROCESSOR POWER MANAGEMENT BASED ON CLASS AND CONTENT OF INSTRUCTIONS - A processor and method are disclosed. In one embodiment the processor includes a prefetch buffer that stores macro instructions. The processor also includes a clock circuit that can provide a clock signal for at least some of the functional units within the processor. The processor additionally includes macro instruction decode logic that can determine a class of each macro instruction. The processor also includes a clock management unit that can cause the clock signal to remain in a steady state entering at least one of the units in the processor that do not operate on a current macro instruction being decoded. Finally, the processor also includes at least one instruction decoder unit that can decode the first macro instruction into one or more opcodes. | 2012-03-29 |
20120079243 | Next-instruction-type-field - A graphics processing unit core | 2012-03-29 |
20120079244 | METHOD AND APPARATUS FOR UNIVERSAL LOGICAL OPERATIONS - An apparatus and method are described for performing arbitrary logical operations specified by a table. For example, one embodiment of a method for performing a logical operation on a computer processor comprises: reading data from each of two or more source operands; combining the data read from the source operands to generate an index value, the index value identifying a subset of bits within an immediate value transmitted with an instruction; reading the bits from the immediate value; and storing the bits read from the immediate value within a destination register to generate a result of the instruction. | 2012-03-29 |
20120079245 | DYNAMIC OPTIMIZATION FOR CONDITIONAL COMMIT - An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions. | 2012-03-29 |
20120079246 | APPARATUS, METHOD, AND SYSTEM FOR PROVIDING A DECISION MECHANISM FOR CONDITIONAL COMMITS IN AN ATOMIC REGION - An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions. | 2012-03-29 |
20120079247 | DUAL REGISTER DATA PATH ARCHITECTURE - A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit. | 2012-03-29 |
20120079248 | Aliased Parameter Passing Between Microcode Callers and Microcode Subroutines - An apparatus of an aspect includes a plurality of microcode alias locations and a microcode storage. A microinstruction of a microcode subroutine is stored in the microcode storage. The microinstruction has an indication of a microcode alias location. A microcode caller of the microcode subroutine is also stored in the microcode storage. The microcode caller is operable to specify a location of a parameter in the microcode alias location that is indicated by the microinstruction of the microcode subroutine. The apparatus also includes parameter location determination logic that is coupled with the microcode alias locations. The parameter location determination logic is operable, responsive to the microinstruction of the microcode subroutine, to receive the indication of the microcode alias location from the microinstruction and determine the location of the parameter specified in the microcode alias location indicated by the microinstruction. | 2012-03-29 |
20120079249 | Training Decode Unit for Previously-Detected Instruction Type - In an embodiment, a decode unit includes multiple decoders configured to decode different types of instructions. One or more of the decoders may be complex decoders, and the decode unit may disable the complex decoders if an instruction of the corresponding type is not being decoded. In an embodiment, the decode unit may disable the complex decoders by data-gating the instruction into the decoder. The decode unit may also include a control unit that is configured to detect instructions of the type decoded by the complex decoders, and to enable the complex decoders and redirect the fetching in response to the detection. The decode unit may also record an indication of the instruction (e.g. the program counter address (PC) of the instruction) to more rapidly detect the instruction and prevent a redirect in subsequent fetches. | 2012-03-29 |
20120079250 | FUNCTIONAL UNIT CAPABLE OF EXECUTING APPROXIMATIONS OF FUNCTIONS - A semiconductor chip is described having a functional unit that can execute a first instruction and execute a second instruction. The first instruction is an instruction that multiplies two operands. The second instruction is an instruction that approximates a function according to C0+C1X2+C2X2 | 2012-03-29 |
20120079251 | MULTIPLY ADD FUNCTIONAL UNIT CAPABLE OF EXECUTING SCALE, ROUND, GETEXP, ROUND, GETMANT, REDUCE, RANGE AND CLASS INSTRUCTIONS - A method is described that involves executing a first instruction with a functional unit. The first instruction is a multiply-add instruction. The method further includes executing a second instruction with the functional unit. The second instruction is a round instruction. | 2012-03-29 |
20120079252 | PERFORMING A MULTIPLY-MULTIPLY-ACCUMULATE INSTRUCTION - In one embodiment, the present invention includes a processor having multiple execution units, at least one of which includes a circuit having a multiply-accumulate (MAC) unit including multiple multipliers and adders, and to execute a user-level multiply-multiply-accumulate instruction to populate a destination storage with a plurality of elements each corresponding to an absolute value for a pixel of a pixel block. Other embodiments are described and claimed. | 2012-03-29 |
20120079253 | FUNCTIONAL UNIT FOR VECTOR LEADING ZEROES, VECTOR TRAILING ZEROES, VECTOR OPERAND 1s COUNT AND VECTOR PARITY CALCULATION - A method of performing vector operations on a semiconductor chip is described. The method includes performing a first vector instruction with a vector functional unit implemented on the semiconductor chip and performing a second vector instruction with the vector functional unit. The first vector instruction is a vector multiply add instruction. The second vector instruction is a vector leading zeros count instruction. | 2012-03-29 |
20120079254 | Debugging of a data processing apparatus - A data processing apparatus is provided comprising data processing circuitry and debug circuitry. The debug circuitry controls operation of the processing circuitry when operating in a debug mode. The data processing circuitry determines upon entry into a debug mode a current operating state of the data processing apparatus. The data processing circuitry allocates one of a plurality of instruction sets to be used as a debug instruction set depending upon the determined current operating state. | 2012-03-29 |
20120079255 | INDIRECT BRANCH PREDICTION BASED ON BRANCH TARGET BUFFER HYSTERESIS - Methods and apparatus to perform efficient indirect branch prediction operations are described. In one embodiment, a branch target buffer (BTB) stored a target address and a bimodal hysteresis counter for an indirect branch that has been encountered by a front-end of the processor during a time period. An indirect branch prediction logic then generates a prediction for an instruction corresponding to a indirect branch based on the stored bimodal hysteresis counter of the BTB. Other embodiments are also claimed and disclosed. | 2012-03-29 |
20120079256 | Interrupt suppression - A processor receives interrupts of a same type from hardware. The processor determines a rate at which the interrupts are being received. The processor compares the rate at which the interrupts are being received to a threshold rate. In response to determining that the rate at which the interrupts are being received is greater than the threshold rate, the processor sends just the first received interrupt to firmware for processing. All other of the interrupts are not sent from the processor to the firmware but instead are suppressed by the processor. By comparison, in response to determining that the rate at which the interrupts are being received is less than the threshold rate, the processor can send all the interrupts from the processor to firmware for processing. | 2012-03-29 |
20120079257 | METHODS AND SYSTEMS THAT DEFER EXCEPTION HANDLING - Methods and systems thereof for exception handling are described. An event to be handled is identified during execution of a code sequence. A bit is set to indicate that handling of the event is to be deferred. An exception corresponding to the event is generated if the bit is set. | 2012-03-29 |
20120079258 | Detecting State Loss on a Device - This document describes techniques for detecting state loss on a device. These techniques permit a computer connected to a device to forgo, in many cases, reinitializing the device when returning to a normal-power mode. | 2012-03-29 |
20120079259 | METHOD TO ENSURE PLATFORM SILICON CONFIGURATION INTEGRITY - Some aspects include beginning a power on self test (POST) by a BIOS for a computer system; enumerating the computer system by the BIOS; providing, based on the enumeration of the computer system by the BIOS, at least one configuration setting of the computer system to a management engine (ME) of the computer system; and applying a lock to the at least one configuration setting by the ME to manage a change to the at least one configuration setting, all prior to an ending of the POST. | 2012-03-29 |
20120079260 | BASIC INPUT-OUTPUT SYSTEM CIRCUIT AND METHOD FOR USING THE SAME - A BIOS circuit for a computer includes a baseboard management controller (BMC), a central processing unit (CPU), a main basic input-output system (BIOS) storage, and a subsidiary BIOS storage. Both the main BIOS storage and the subsidiary BIOS storage store programs for controlling the computer. The CPU executes the programs stored in the main BIOS storage to control the computer. When data of the programs stored in the main BIOS storage is missing or corrupted, the BMC copies data of the programs stored in the subsidiary BIOS storage to the main BIOS storage to recover the missing or corrupted data in the main BIOS storage. | 2012-03-29 |
20120079261 | Control Word Obfuscation in Secure TV Receiver - A device for descrambling encrypted data includes a descrambler, a secure link, and a secure element that securely transmits a control word to the descrambler in a normal operating mode. The secure element includes a first secure register, a read-only memory having a boot code, a random-access memory for storing a firmware image from an external memory, and a processor coupled to the first secure register, the read-only memory, and the random access memory. The processor executes the boot code to generate the control word, stores the control word in the first secure register, and send the stored control word to the descrambler through a secure communication link. The descrambler may include a second secure register that is connected to the first secure register through the secure link. The first and second secure registers are not scannable during a normal operation. The secure link contains buried signal traces. | 2012-03-29 |
20120079262 | START-UP CONTROL APPARATUS AND METHOD - A start-up control apparatus includes a control chip, an advanced configuration and power management interface (ACPI) controller, and a firmware. The control chip includes an analysis module and a control module. The ACPI controller is used for receiving a trigger signal and sending a start-up signal corresponding to the trigger signal to the control module if a computer system is powered off. The firmware is used for sending a status signal to the analysis module after the firmware finishes initialization. The analysis module is further adapted to send the trigger signal to the ACPI controller after receiving the status signal, and the control module is adapted to send the start-up signal to a power supply to provide power for powering on the computer system. | 2012-03-29 |
20120079263 | Method and Device for Initiating System on Chip - A method and apparatus for starting a system on chip, this method includes: enumerating all interfaces which are able to start after the system on chip is powered on and an initial boot program is started; and reading measurement data of each starting interface in sequence, and when it is detected that a certain starting interface has connected with a starting device and this starting device is the only, load a subsequent boot program from this starting interface to complete system starting. The method solves the problem that the system on chip is only able to be started in the fixed configuration from the fixed interface or device, and the system on chip is unable to be started once the external starting environment changes existing in the prior art. | 2012-03-29 |
20120079264 | SIMPLIFIED CUSTOMIZATION SETTING VERIFICATION - A value of a configuration setting contained within a selected content unit of an application may be used as input for a configuration check algorithm to calculate a control parameter output. The algorithm may include logical operators, conditional statements, mathematical logic, and mathematical functions. The algorithm may be used to verify the correctness of the value. Different control parameter output values may be associated with different options in the automated configuration verification program. The options may include, but are not limited to, modifying an unsupported configuration setting value to a supported value, updating configuration setting values in non-selected content units, exiting the automated program and switching to a manual configuration setting change mode, and automatically updating a configuration setting value to a supported value without further intervention. | 2012-03-29 |
20120079265 | MULTI-MODE HANDHELD WIRELESS DEVICE - Various embodiments of the invention relate to a multi-function handheld user device that may have multiple selectable modes of operation for different areas of the user's life, each mode with its own database, applications, preferences, operational restrictions, and access limitations. Various mechanisms may be provided for switching between modes. Within each mode, context awareness and situational awareness may be used to obtain additional information or perform additional functions not directly requested by the user. | 2012-03-29 |
20120079266 | COMMUNICATION SYSTEM, COMMUNICATION DEVICE, AND COMMUNICATION METHOD - A first communication device includes a security policy storing unit that store a security policy and a default policy applied to communication to which the security policy is not applied, a communication unit that performs communication, and a communication control unit that performs an encryption process and a decryption process according to the default policy when the communication does not correspond to the target of the policy. A second communication device includes an input and output receiving processing unit that receives an input of an encryption key of the default policy of the first communication device, a communication control unit that generates a policy including an encryption method of the default policy and the input encryption key and performs an encryption process and a decryption process in communication with the first communication device according to the policy, and a communication unit that performs communication of a communication packet. | 2012-03-29 |
20120079267 | Securing Locally Stored Web-based Database Data - The present invention extends to methods, systems, and computer program products for locally storing Web-based database data in a secure manner. Embodiments of the present invention permit Web-based database data to be locally stored at a computer system to increase the efficiency of rendering the Web-based database data within a Web browser at the computer system. Web-based database data can be sandboxed per domain to mitigate (and possibly eliminate) the exposure of the Web-based database data to malicious computer systems. A web server may be required to authenticate itself before it may present database data to be locally stored at a computer system. A web server may be required to authenticate itself before being allowed to access database data stored locally at a computer system. | 2012-03-29 |
20120079268 | SEPARATING AUTHORIZATION IDENTITY FROM POLICY ENFORCEMENT IDENTITY - The present invention extends to methods, systems, and computer program products for separating authorization identity from policy enforcement identity. Embodiments of the invention extend the consumption phase for protected information. Two identities, an authorization identity and a policy enforcement identity, are used for acquiring, issuing and enforcing usage license instead of one identity certificate. The authorization identity is used to evaluate against usage policy. The authorization identity is similar to identification information in an identity certificate. The policy enforcement identity is used to ensure the confidentiality of granted permissions and content key. The policy enforcement identity enforces a usage license on an authorization principal's (e.g., recipient's) machine. The policy enforcement identity's enforcement of a usage license is similar use of a cryptographic key in an identity certificate. | 2012-03-29 |
20120079269 | SYNCHRONIZING CERTIFICATES BETWEEN A DEVICE AND SERVER - Systems and methods for processing messages within a wireless communications system are disclosed. A server within the wireless communications system maintains a list of certificates contained in devices that use the server. The server synchronizes or updates the list of certificates based on information contained in message to and from the device. By providing a server with certificates associated with devices that use the server, and providing a system and method for synchronizing the certificates between the device and server, the server can implement powerful features that will improve the efficiency, speed and user satisfaction of the devices. The exemplary embodiments also enable advantageous bandwidth savings by preventing transmission of certificates unnecessarily | 2012-03-29 |
20120079270 | Hardware-Assisted Content Protection for Graphics Processor - Methods, systems, and computer program products for the secure handling of content provider protected multimedia content are disclosed. A method for providing secure handling of provider protected multimedia content, includes: decrypting, in a hardware-based multimedia content protection device (MMCP), the provider protected multimedia content using one or more provider keys; encrypting, in the MMCP, the decrypted multimedia content using one or more local keys to create locally protected multimedia content; and providing the locally protected multimedia content to a graphics processor over a secure connection. In an embodiment, the MMCP and the graphics processor are on the same board. In another embodiment, the MMCP is incorporated in the graphics processor to form a unified chip. | 2012-03-29 |
20120079271 | METHOD AND APPARATUS FOR WIRELESS DEVICE AUTHENTICATION AND ASSOCIATION - Methods and devices controlling association and/or authentication of wireless devices. At a first wireless device which is unassociated and unauthenticated with a second device, a state variable representing the second device may be stored, where the variable indicates that the second device is unassociated and unauthenticated with the first device. A message may be received from the second device requesting to associate. The variable may be changed to indicate that the second device is associated and unauthenticated. A message may be received from the second device requesting to authenticate, and the state variable may be changed to indicate that the second device is authenticated. In some cases, a wireless device stores variable(s) representing a second device, the variables indicating that the second device is unassociated and unauthenticated, receives a message from the second device requesting authentication, and changes a state variable to indicate that the second device is authenticated. | 2012-03-29 |
20120079272 | ONE-TIME USE AUTHORIZATION CODES WITH ENCRYPTED DATA PAYLOADS FOR USE WITH DIAGNOSTIC CONTENT SUPPORTED VIA ELECTRONIC COMMUNICATIONS - In one embodiment, a computing apparatus that receives respective unique identifiers corresponding to a machine and a diagnostic tool and a requested parameter setting for configuring a machine component residing in the machine, and provides an authorization code with a payload comprising the requested parameter setting, the payload encrypted based on the unique identifiers. | 2012-03-29 |
20120079273 | Biometric Key - A biometric key ( | 2012-03-29 |
20120079274 | Key Agreement and Transport Protocol with Implicit Signatures - A key establishment protocol between a pair of correspondents includes the generation by each correspondent of respective signatures. The signatures are derived from information that is private to the correspondent and information that is public. After exchange of signatures, the integrity of exchange messages can be verified by extracting the public information contained in the signature and comparing it with information used to generate the signature. A common session key may then be generated from the public and private information of respective ones of the correspondents. | 2012-03-29 |
20120079275 | CONTENT FILTERING OF SECURE E-MAIL - Content filtering of e-mail in a network environment. The network environment includes a client machine, a policy server and an e-mail server. An e-mail message is authored at the client machine. Filter policy information is obtained by the client machine from the policy server, wherein the filter policy information defines a filtering policy for filtering of e-mail messages. The filter policy information is applied to the e-mail message by the client machine so as to effect the filtering policy. The filtered e-mail message is secured by the client machine, such as by securing based on a key obtained by the client machine from a key store. The secure e-mail message is sent by the client machine to a recipient via the e-mail server. | 2012-03-29 |
20120079276 | CONTENT SELECTION AND DELIVERY FOR RANDOM DEVICES - Intelligent content delivery enables content to be delivered to different devices in formats appropriate for those devices based on the capabilities of those devices. A user might access the same piece of content on two different devices, and can automatically receive a higher quality format on a device capable of playing that higher quality format. The user can purchase rights to content in any format, such that as new formats emerge or the user upgrades to devices with enhanced capabilities, the user can receive the improved formats automatically without having to repurchase the content. Further, the user can pause and resume content between devices even when those devices utilize different formats, and can access content on devices not otherwise associated with the user, receiving content in formats that are appropriate for those unknown devices even if the user has not previously accessed content in those formats. | 2012-03-29 |
20120079277 | VERIFICATION AND PROTECTION OF GENUINE SOFTWARE INSTALLATION USING HARDWARE SUPER KEY - A device, system, and method are disclosed. In one embodiment the device receives a user key from a user application. The device then creates a management engine key by applying a management engine key creation algorithm to the user key. Then the device sends the management engine key to a remote server. Later, the device retrieves a server key from the remote server. The device next performs a hash combination of the user key, the management engine key, and the server key to create a super key. Once the super key has been created, the device authenticates the super key, and if the super key is valid, the device then sends a management engine certification to the user application. | 2012-03-29 |
20120079278 | OBJECT SECURITY OVER NETWORK - The application to a security model to one or more objects that are located on a network. When an object is to be accessed, security data associated with the object is accessed and enforced against the object. For instance, the security data might be used to determine an authentication mechanism to use to authenticate the user or entity that is accessing the object. The security data might also correlated the authenticated user or entity to the authorized actions that may be performed by that entity on the object. The security data might also specify encryption policy regarding the object. | 2012-03-29 |
20120079279 | Generation of SW Encryption Key During Silicon Manufacturing Process - A method of generating an encryption key during the manufacturing process of a device includes randomly generating a seed, encrypting a unique identifier disposed in the device to obtain a first encryption key, encrypting the first encryption key using a public key to obtain a second encryption key, and sending the second encryption key and the seed to a software provider. The method further includes receiving the second encryption key and the seed by the software provider and decrypting the second encryption key using a private key to recover the first encryption key. The manufacturer then encrypts a program code using the recovered first encryption key and installs the seed in a certificate that is associated with the encrypted program code. | 2012-03-29 |
20120079280 | Method, system and secure processor for executing a software application - A host reads host software code and secure processor software code of an software application and passes the secure processor software code to the secure processor that requests an activation sequence for the software application from a remote server. The secure processor receives the activation sequence for the software application and applies it to the secure processor software code to make it executable. The host executes the host software code and calls a procedure of the executable secure processor software code in the secure processor, which executes the procedure of the executable secure processor software code to obtain a response to the call that is then returned. The activation sequence is advantageously software code. The invention can enable protection of a plurality of software titles using a single secure processor that is dynamically adapted for each title. | 2012-03-29 |
20120079281 | SYSTEMS AND METHODS FOR DIVERSIFICATION OF ENCRYPTION ALGORITHMS AND OBFUSCATION SYMBOLS, SYMBOL SPACES AND/OR SCHEMAS - In some embodiments, a method includes generating a round key for each round from one or more rounds for encrypting input data and partitioning the input data into one or more data blocks for each round. A block key is generated for each data block and each data block is encrypted using the round key, the block key and the data block as inputs to a mathematic operation to produce a cipher text. A number of rounds is variable, at least one of a size of the round key or a number of data blocks are variable for each round, or at least one of a size of each data block, a size of the block key for each data block, the mathematic operation for each data block, or a size of the cipher text for each data block are variable for each data block within each round. | 2012-03-29 |
20120079282 | SEAMLESS END-TO-END DATA OBFUSCATION AND ENCRYPTION - A system comprises an input obfuscation module and an input encryption module coupled to the input obfuscation module. The input obfuscation and encryption modules are configured to define a first end of a secure channel for exchanging information with a secure software application module. The system further comprises an output de-obfuscation and decryption module coupled to the input obfuscation and encryption modules and is configured to define a second end of the secure channel, the secure channel having no seams between the first end of the secure channel and the second end of the secure channel. The system further comprises an output de-obfuscation module coupled to the output decryption module. | 2012-03-29 |
20120079283 | MEMORY MANAGEMENT DEVICE AND MEMORY MANAGEMENT METHOD - According to an embodiment, a memory management device increments a lower value of a first counter, updates the counter by incrementing an upper value and resetting the lower value when the lower value overflows, increments to update the lower counter value when the upper value is incremented as a result of writing a second data piece having the upper value in common to a memory, recalculates a first secret value calculated using the first counter values and a root secret value in response to the first counter update, writes a first data piece and the first secret value to the memory, and at reading of the first data piece and the first secret value, calculates a second secret value using the updated first counter values and the root secret value, and compares the first secret value with the second secret value to verify the first data piece. | 2012-03-29 |
20120079284 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD OF INFORMATION PROCESSING APPARATUS, AND PROGRAM - An information processing apparatus includes a decryption processing unit, a backup unit, and a control unit. The decryption processing unit is configured to decrypt encrypted data read from a first storage unit storing the encrypted data. The backup unit is configured to back up the encrypted data stored in the first storage unit to a second storage unit. When the backup unit backs up the encrypted data stored in the first storage unit to a second storage unit, the control unit is configured to control the decryption processing unit to store the encrypted data read from the first storage unit, in the second storage unit without performing decrypting processing. | 2012-03-29 |
20120079285 | TWEAKABLE ENCRYPION MODE FOR MEMORY ENCRYPTION WITH PROTECTION AGAINST REPLAY ATTACKS - A method and apparatus for protecting against hardware attacks on system memory is provided. A mode of operation for block ciphers enhances the standard XTS-AES mode of operation to perform memory encryption by extending a tweak to include a “time stamp” indicator. An incrementing mechanism using the “time stamp” indicator generates a tweak which separates different contexts over different times such that the effect of “Type 2 replay attacks” is mitigated. | 2012-03-29 |
20120079286 | DATA PROCESSING APPARATUS - A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal. | 2012-03-29 |
20120079287 | Firmware Authentication and Deciphering for Secure TV Receiver - A method for authenticating and deciphering an encrypted program file for execution by a secure element includes receiving the program file and a digital certificate that is associated with the program file from an external device. The method stores the program file and the associated certificate in a secure random access memory disposed in the secure element and hashes the program file to obtain a hash. The method authenticates the program file by comparing the obtained hash with a checksum that is stored in the certificate. Additionally, the method writes runtime configuration information stored in the certificate to corresponding configuration registers disposed in the secure element. The method further generates an encryption key using a seed value stored in the certificate and a unique identifier disposed in the secure element and deciphers the program file using the generated encryption key. | 2012-03-29 |
20120079288 | SECURE HOST AUTHENTICATION USING SYMMETRIC KEY CRYTOGRAPHY - Methods of securely authenticating a host to a storage system are provided. A series of authentication sessions are illustratively performed. Each of the authentication sessions includes the host transmitting an authentication request to the storage system. The storage system authenticates the host based at least in part upon a content of the authentication request. After each successful authentication of the host to the storage system, an encryption key that was utilized in encrypting the authentication request that was transmitted to the storage system is deleted. After each encryption key deletion, a new encryption key that is different than the previous key is optionally stored and is utilized in the next authentication session. | 2012-03-29 |
20120079289 | SECURE ERASE SYSTEM FOR A SOLID STATE NON-VOLATILE MEMORY DEVICE - A secure erase system for a solid state memory device is disclosed. A memory area provides a data block for storing data and a key block for storing at least one key. A translation unit maps a logical address to a physical address associated with the memory area. An encryption unit encrypts plaintext data to be written to the memory area with the associated key and decrypts the encrypted data to be read by a host with the associated key. The key associated with a logical erase group to be secure erased is deleted after receiving a command requesting to erase the data associated with the logical erase group. | 2012-03-29 |
20120079290 | PROVIDING PER CORE VOLTAGE AND FREQUENCY CONTROL - In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed. | 2012-03-29 |
20120079291 | DATA BACKUP SYSTEM, STORAGE SYSTEM UTILIZING THE DATA BACKUP SYSTEM, DATA BACKUP METHOD AND COMPUTER READABLE MEDIUM FOR PERFORMING THE DATA BACKUP METHOD - A data backup system comprising: a first storage device; a second storage device; a backup controller; and a backup power supplying device; wherein the data is stored to the first storage device in a first mode via main power, and the backup controller receives backup power from the backup power supplying device to move the data stored in the first storage device to the second storage device in a second mode. | 2012-03-29 |
20120079292 | START-UP CONTROL APPARATUS AND METHOD - A start-up control apparatus r includes a control chip, an advanced configuration and power management interface (ACPI) controller, and a firmware. The ACPI controller is used for receiving a trigger signal and sending a start-up signal corresponding to the trigger signal to the control chip if a computer system is powered off. The firmware is used for sending a status signal to the control chip after the firmware finishes initialization. Wherein the control chip is used for sending the start-up signal to a power supply to provide power for powering on the computer system after receiving the status signal. | 2012-03-29 |
20120079293 | UPGRADE KIT AND POWER MANAGEMENT DEVICE FOR AN UPGRADE KIT - A power management device for an upgrade kit for upgrading a target system to a digital system is provided. The power management device includes a sensor configured to sense a power status of the target system, and a power distribution unit configured to power on or off all subsystems of the upgrade kit according to the power status. | 2012-03-29 |
20120079294 | Power Sharing Between Midspan and Endspan for Higher Power PoE - Methods and systems for higher power PoE are provided. Embodiments overcome system limitations to PSE power scaling by using an endspan-midspan configuration which allocates power to the PD from both an endspan PSE and a midspan PSE. Embodiments are particularly suitable for deployed PoE systems having limited power supplies and/or ports designed for lower power. Further, embodiments include power management schemes to enable the proposed endspan-midspan configuration to intelligently allocate power between the endspan PSE and the midspan PSE according to required PD power. | 2012-03-29 |
20120079295 | TECHNIQUES TO TRANSMIT COMMANDS TO A TARGET DEVICE - Techniques are described to transmit commands to a display device. The commands can be transmitted in header byte fields of secondary data packets. The commands can be used to cause a target device to capture a frame, enter or exit self refresh mode, or reduce power use of a connection. In addition, a request to exit main link standby mode can cause the target enter training mode without explicit command to exit main link standby mode. | 2012-03-29 |
20120079296 | COMMUNICATION DEVICE MANAGEMENT APPARATUS, USER DEVICE, AND SERVICE DEVICE - A communication device management apparatus includes a communication unit for communicating with a user device and a service device, a device information storing unit for storing device information of the service device that is received from the service device via the communication unit, an activation signal processing unit for receiving an activation signal from the user device via the communication unit, a device information transmission unit for transmitting the device information stored in the device information storing unit to the user device via the communication unit, and a power management unit for controlling an operational state. When the activation signal processing unit receives the activation signal, the power management unit shifts the operational state from an idle state to an active state consuming much power. The power management unit shifts the operational state from the active state to the idle state thereafter. | 2012-03-29 |
20120079297 | COMMUNICATION DEVICE, START NODE, SYSTEM, METHOD AND COMPUET PROGRAM PRODUCT - According to one embodiment, a communication device includes a start-up signal reception unit that receives a start-up signal that a start node transmits for starting up a node to be started; a first interface connected to Ethernet; a second interface connected to Ethernet; a power reception unit that receives PoE power through the first interface; a PoE controller that receives the start-up signal and PoE power and gives a transmission instruction of a start-up power signal which is a PoE power signal having a signal pattern corresponding to the start-up signal; and a power transmission unit that receives the transmission instruction from the PoE controller and transmits the start-up power signal through the second interface. | 2012-03-29 |
20120079298 | ENERGY EFFICIENT HETEROGENEOUS SYSTEMS - Low-power systems and methods are disclosed for executing an application software on a general purpose processor and a plurality of accelerators with a runtime controller. The runtime controller splits a workload across the processor and the accelerators to minimize energy. The system includes building one or more performance models in an application-agnostic manner; and monitoring system performance in real-time and adjusting the workload splitting to minimize energy while conforming to a target quality of service (QoS). | 2012-03-29 |
20120079299 | Enclosure Power Controller - A system and method for controlling power consumption is described herein. A computer system includes an enclosure. The enclosure is configured to contain a plurality of removable compute nodes. The enclosure includes a power controller configured to individually control an amount of power consumed by each of the plurality of removable compute nodes. The power controller provides a plurality of power control signals. Each power control signal is provided to and controls the power consumption of one of the plurality of removable compute nodes. | 2012-03-29 |
20120079300 | ELECTRONIC APPARATUS - A power-supply connection portion connects a power supply and a main body device. Operation information for operating the apparatus main body is stored in a volatile memory. A power feeder feeds power fed from the power supply, to the volatile memory. A non-operation state request receiver receives a non-operation state request for moving the apparatus main body from an operation state to a non-operation state. When the non-operation state request is received by the non-operation state request receiver, a power-feeding controller performs control such that the power feeder feeds the power to the volatile memory for a predetermined period. A mode determiner determines a mode of the non-operation state request. A changer is provided with a setter which sets the predetermined period depending on the mode determined by the mode determiner. | 2012-03-29 |
20120079301 | Making Read-Copy Update Free-Running Grace Period Counters Safe Against Lengthy Low Power State Sojourns - A technique for making a free-running grace period counter safe against lengthy low power state processor sojourns. The grace period counter tracks grace periods that determine when processors that are capable executing read operations have passed through a quiescent state that guarantees the readers will no longer maintain references to shared data. Periodically, one or more processors may be placed in a low power state in which the processors discontinue performing grace period detection operations. Such processors may remain in the low power state for a complete cycle of the grace period counter. This scenario can potentially disrupt grace period detection operations if the processors awaken to see the same grace period counter value. To rectify this situation, processors in a low power state may be periodically awakened at a predetermined point selected prevent the low power state from extending for an entire roll over of the grace period counter. | 2012-03-29 |
20120079302 | COMMUNICATION DEVICE AND COMMUNICATION SYSTEM - According to an embodiment, a communication device includes a wake-up signal reception unit configured to receive a wake-up signal to request a change of a state from a second state to a first state, the second state requiring less power consumption than the first state; and a state control unit configured to change the state from the second state to the first state and inform a control unit of the change of the state when the wake-up signal is received, the control unit being configured to process a frame received during the first state. | 2012-03-29 |
20120079303 | METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION IN A PROCESSOR BY POWERING DOWN AN INSTRUCTION FETCH UNIT - An apparatus and method are described for reducing power consumption in a processor by powering down an instruction fetch unit. For example, one embodiment of a method comprises: detecting a branch, the branch having addressing information associated therewith; comparing the addressing information with entries in an instruction prefetch buffer to determine whether an executable instruction loop exists within the prefetch buffer; wherein if an instruction loop is detected as a result of the comparison, then powering down an instruction fetch unit and/or components thereof; and streaming instructions directly from the prefetch buffer until a clearing condition is detected | 2012-03-29 |
20120079304 | PACKAGE LEVEL POWER STATE OPTIMIZATION - Methods and apparatus to optimize package level power state usage are described. In one embodiment, a processor control logic receives a request to enter a lower power consumption state (such as a package level deeper sleep state). The control logic determines the time difference or delta between a last entry into the lower power consumption state and the current time. The control logic then causes the flushing of a last level cache based on a comparison of the time difference and a threshold value corresponding to the lower power consumption state. Other embodiments are also claimed and disclosed. | 2012-03-29 |
20120079305 | Displaying The Operating Efficiency Of A Processor - Methods, apparatuses, and computer program products are provided for displaying the operating efficiency of a processor. Embodiments include determining, by an efficiency monitor, a voltage level that a voltage regulator device provides to a processor; determining, by the efficiency monitor, whether the voltage level is within a predetermined minimum voltage range; and if the voltage level is within the predetermined minimum voltage range, displaying, by the efficiency monitor, a user notification indicating an efficiency of the processor. | 2012-03-29 |
20120079306 | Memory Reconfiguration During System Run-Time - Memory reconfiguration during system run-time is described. In one example, a system includes a memory slot to carry a memory board and to connect the memory board to a memory controller for read and write operations, a logic device having a plurality of status registers to record the status of the memory slot and a plurality of control registers to control the operation of the memory slot, and a bus interface coupled through direct signal lines to the memory slot to communicate status and control signals with the memory slot and coupled through a serial bus to the logic device to communicate status and control signals with the logic device. | 2012-03-29 |
20120079307 | PSU Self-Test - A method and apparatus for testing a power supply unit is disclosed. One aspect of certain embodiments includes a test activation mechanism that is internal to the power supply unit for shorting an active-low, power-on signal to ground and for monitoring a power-good signal intended for the computer. | 2012-03-29 |
20120079308 | USB COMMUNICATION APPARATUS AND METHOD OF REDUCING POWER CONSUMPTION AMOUNT THEREOF - A USB (Universal Serial Bus) communication apparatus includes: a driver circuit connected to a USB bus and configured to transmit a packet onto the USB bus for a packet transmission period which is determined based on a transmission request signal from another unit. A receiver control circuit generates a fixation request signal and a generation control signal in response to the transmission request signal. A receiver circuit connected to the USB bus generates a squelch signal showing that the packet is being transmitting onto the USB bus, and stops generating the squelch signal in response to the generation control signal. A line state signal control circuit is configured to output a specific line state signal based on the squelch signal to notify to another unit that the packet is been transmitting onto the USB bus, and to fix the specific line state signal in response to the fixation request signal. | 2012-03-29 |
20120079309 | METHOD FOR MANAGING THE OPERATION OF A REMOTE INFORMATION SENSOR, AND ASSOCIATED SENSOR - A method for managing the operation of an information sensor for a meter, includes putting the sensor into a deep standby mode, in which a battery of the sensor does not supply electrical power in particular to a module for demodulating signals from the meter; connecting the sensor to the meter; detecting, using a detection module of the sensor, an information signal from the meter; removing the sensor from the deep standby mode in order to put same into an operative mode in which the battery supplies electrical power in particular to the demodulation module. | 2012-03-29 |
20120079310 | COMMUNICATION SYSTEM, COMMUNICATION INTERFACE, AND SYNCHRONIZATION METHOD - An interface board includes a synchronizer that synchronizes a first time that is a time of the interface board to a base time based on a master synchronization signal that is supplied by an external master time source and that defines the base time. The interface board also includes a comparator that compares a phase of a first synchronization signal that synchronizes to the first time with a phase of a shared synchronization signal sent by an interface controller that controls the interface board, and a notifier that notifies another interface board of a comparison result of the comparator. | 2012-03-29 |
20120079311 | STORAGE PROCESSING DEVICE AND FAILOVER CONTROL METHOD - A storage processing device to which a storage medium is connectable configures a failover system together with a different storage processing device. The storage processing device sets information obtained from predetermined random information as identification information of the storage medium, at the start to configure the failover system. | 2012-03-29 |
20120079312 | METHOD AND SYSTEM OF LIVE ERROR RECOVERY - A method and system of error recovery of a device attached to a platform without requiring a system reset. In one embodiment of the invention, a platform detects an error(s) of an attached device and shuts down the communication link with the attached device. The platform corrects the error(s) and automatically re-trains the communication link with the attached device. In this way, no reset of the platform is required to correct the detected error(s) in one embodiment of the invention. | 2012-03-29 |
20120079313 | DISTRIBUTED MEMORY ARRAY SUPPORTING RANDOM ACCESS AND FILE STORAGE OPERATIONS - A distributed memory array that supports both file storage and random access operations is provided. The distributed memory array includes at least one memory assembly for storing data, each memory assembly having a plurality of memory modules coupled together through a bi-directionally cross-strapped network, each memory module having a switching mechanism. The distributed memory array further includes at least one gateway coupled to the at least one memory assembly through the bi-directionally cross-strapped network. The gateway also includes a plurality of user access ports for providing access to the at least one memory assembly, and a file manager that is configured to receive a request from a user for access to the at least one memory assembly at the user access ports for either file storage or random access operations and to allocate at least one allocation unit of available memory in the at least one memory assembly based on the request from the user. The file manager is further configured to translate further requests from the user to memory mapped transactions for accessing the at least one allocation unit. | 2012-03-29 |
20120079314 | MULTI-LEVEL DIMM ERROR REDUCTION - Embodiments of the present invention include computer-implemented methods for selectively applying remedial actions, according to a predefined order, for reducing the error rate in a computer memory system. In one embodiment, an ordered set of remedial actions are sequentially invoked in response to a single-bit error (SBE) in a DIMM reaching successive error thresholds. For example, in an air-cooled system, the remedial actions may include dynamically increasing a DIMM refresh rate, dynamically increasing a rate of airflow used to cool the DIMMs, and dynamically throttling the DIMMs. The remedial actions may be layered as they are successively invoked, to provide a cumulative remedial effect. At least two of the remedial actions may be simultaneously invoked in response to a multi-bit error rate reaching an associated threshold. | 2012-03-29 |
20120079315 | SYSTEM AND METHOD FOR TRANSPARENT RECOVERY OF DAMAGED OR UNAVAILABLE OBJECTS IN A REPLICATED OBJECT STORAGE SYSTEM - A redundant array of independent nodes are networked together. Each node executes an instance of an application that provides object-based storage. The nodes are grouped into a plurality of systems each having multiple nodes. An object recovery method comprises: receiving, by a first system of the plurality of systems from a client application, a read request for an object, the object having been replicated to/from at least one second system among the plurality of systems; if the object of the read request is available in the first system, returning by the first system the object of the read request to the client application; and if the object of the read request is not available in the first system, performing a read from replica process by the first system to access a replica of the object from a second system among the plurality of systems and using the replica of the object to return the object of the read request to the client application. | 2012-03-29 |
20120079316 | Performing Redundant Memory Hopping - In one embodiment, the present invention includes a method for receiving an indication of a loss of redundancy with respect to a pair of mirrored memory regions of a partially redundant memory system, determining new mirrored memory regions, and dynamically migrating information stored in the original mirrored memory regions to the new mirrored memory regions. Other embodiments are described and claimed. | 2012-03-29 |
20120079317 | SYSTEM AND METHOD FOR INFORMATION HANDLING SYSTEM REDUNDANT STORAGE REBUILD - Out-of-order reconstruction of a RAID storage device at a replacement storage device enables the replacement storage device to execute I/O for reconstructed regions during reconstruction of the replacement storage device. In one embodiment, the failed storage device is analyzed to find recoverable information, which is copied to the replacement storage device to reduce the need for reconstruction. In another embodiment, the priority for region's reconstruction is increased upon detection of an I/O to the region. The I/O is queued until reconstruction of the region and then executed after reconstruction of that region so that I/O at the region need not be repeated during reconstruction of the remainder of the replacement storage device. | 2012-03-29 |
20120079318 | ADAPTIVE RAID FOR AN SSD ENVIRONMENT - A system and method for adaptive RAID geometries. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array is configured to determine a first RAID layout for use in storing data, and write a first RAID stripe to the device group according to the first RAID layout. In response to detecting a first condition, the controller is configured to determine a second RAID layout which is different from the first RAID layout, and write a second RAID stripe to the device group according to the second layout, whereby the device group concurrently stores data according to both the first RAID layout and the second RAID layout. | 2012-03-29 |
20120079319 | STORAGE SYSTEM AND FAILOVER CONTROL METHOD - A storage system is capable of configuring a failover system by use of a first storage processing device to which first storage media are connected and a second storage processing device to which second storage media are connected. The storage system sets the RAID level of the second storage media to a RAID level with lower redundancy than the RAID level of the first storage media, if the storage capacity of the second storage media is smaller than the storage capacity of the first storage media. | 2012-03-29 |
20120079320 | SYSTEM AND METHOD FOR PERFORMING A MIRROR SET BASED MEDIUM ERROR HANDLING DURING A CONSISTENCY CHECK OPERATION ON A RAID 1E DISK ARRAY - A system and method for performing a mirror set based error handling during a consistency check operation on a RAID 1E disk array is disclosed. In one embodiment, in a method for performing a mirror set based medium error handling during a consistency check (CC) operation on a RAID 1E disk array, a read operation is performed on a current row. The RAID 1E disk array is formed using mirror sets having rows, where each mirror set includes a pair of disks, and the rows include at least one block in each of the pair of disks. A list of all medium errors found in the current row is formed. The medium errors found in the current row are grouped on mirror set basis and the medium errors that do not have a corresponding medium error in substantially same block in other disk in a mirror set are recovered. | 2012-03-29 |
20120079321 | POWER SUPPLY SYSTEM FOR A DATA STORAGE SYSTEM AND A METHOD OF CONTROLLING A POWER SUPPLY - The invention provides a power supply system for a data storage system, the power supply system comprising: a first power supply unit for supplying power to the storage system; a second power supply unit independent from the first power supply unit for supplying power to the storage system; an auxiliary power supply; a power redundancy controller, arranged to monitor the region of an efficiency curve within which the first and/or second power supplies are operating in and control the first and second power supplies accordingly such that the either or both of the first and second power supplies are providing power at any one time, wherein in the event of failure of a power supply unit when only one of the power supply units is operating, the power redundancy controller is arranged to provide power supply to the data storage system from the auxiliary power supply. | 2012-03-29 |
20120079322 | PREVENTING DATA LOSS IN A STORAGE SYSTEM - Storage servers use a fast, non-volatile or persistent memory to store data until it can be written to slower mass storage devices such as disk drives. If the server crashes before a write can complete, the data remains safely stored in non-volatile memory. If the data cannot be committed to disk when the server reboots (e.g. because the destination mass storage device is unavailable), it is stored in a file. When the disk reappears, the data in the file may be used to restore a file or filesystem on the disk to a consistent state. | 2012-03-29 |
20120079323 | HIGH SPEED PARALLEL DATA EXCHANGE WITH TRANSFER RECOVERY - Systems and methods for transfer of data including establishing two separate connections, the two separate connections including a high speed connection and a high integrity connection. Blocks of data are exchanged over the high speed connection while the high integrity connection facilitates communication of descriptor data regarding data received over the high speed connection. As such, the data transfer speed of the high speed connection is utilized while communication via the high integrity connection allows for data reliability features not provided by the high speed connection. | 2012-03-29 |
20120079324 | FIRMWARE TRACING IN A STORAGE DATA COMMUNICATION SYSTEM - A method includes generating trace data at a device associated with data communication to and from a computer storage device through an appropriate communication link therefor and transmitting the trace data through the appropriate communication link. The trace data is configured to enable debugging of a set of instructions associated with the device. The method also includes capturing the trace data transmitted through the appropriate communication link through a protocol analyzer, a host system or the protocol analyzer coupled to the host system and analyzing the trace data therein to obtain information associated with the set of instructions associated with the device. The protocol analyzer, the host system or the protocol analyzer coupled to the host system is configured to be external to the device associated with the data communication to and from the computer storage device. | 2012-03-29 |
20120079325 | System Health Monitor - Described are computer-based methods and apparatuses, including computer program products, for system health monitoring. Backup set metadata is received, wherein the backup set metadata comprises information about backup data sets that are received by a backup storage system. One or more processes that process the backup set metadata through an emulated processing flow path are executed, wherein the one or more processes are also implemented in the backup storage system. Two or more potential processing states are determined within the emulated processing flow path. A reason code is determined for each backup set metadata entry of the backup set metadata indicative of a reason that the backup set metadata entry is in a processing state of the two or more potential processing states. A problem with the manner in which the backup set metadata is flowing through the emulated processing flow path is identified based on the reason codes. | 2012-03-29 |
20120079326 | System Health Monitor - Backup set metadata is received, wherein the backup set metadata comprises information about backup data sets that are received by a backup storage system that stores the backup data sets. The manner in which the backup data sets flow through a processing flow path of the backup storage system is emulated. One or more processes that process the backup set metadata through an emulated processing flow path are executed, wherein the emulated processing flow path is indicative of the manner in which the backup data sets flow through the processing flow path of the backup storage system when the backup storage system stores the backup data sets. One or more timing statistics are calculated based on the flow of the backup set metadata through the emulated processing flow path. | 2012-03-29 |
20120079327 | METHOD FOR DEBUGGING RECONFIGURABLE ARCHITECTURES - A method for debugging reconfigurable hardware is described. According to this method, all necessary debug information is written in each configuration cycle into a memory, which is then analyzed by the debugger. | 2012-03-29 |
20120079328 | INFORMATION PROCESSING APPARATUS | 2012-03-29 |
20120079329 | ADAPTIVE WIRELESS VIDEO TRANSMISSION SYSTEMS AND METHODS - A method for providing error-resilient video content may include receiving video data reflective of multiple video frames and encoding the video data to generate a plurality of packets. The method may also include transmitting the first group of packets to at least two receivers and receiving feedback information regarding receiving status of respective ones of the plurality of packets, the feedback information being indicative of packets not received correctly. The method may further include examining error indications based on the feedback information and implementing a first error-correction policy if a variation in the error indications among the at least two receivers is below a first error threshold and a second error-correction policy if the variation is above the first error threshold. At least one of the first and second error-correction policies may include transmitting or retransmitting at least one packet using a different coding scheme. | 2012-03-29 |
20120079330 | TEST DEVICE AND TEST METHOD FOR RESISTIVE RANDOM ACCESS MEMORY AND RESISTIVE RANDOM ACCESS MEMORY DEVICE - According to the embodiments, a first write enable signal that changes with a constant period and a second write enable signal that changes at a time portion in which a limit time between activation/deactivation control of word lines and activation/deactivation control of bit lines is checked are input, a plurality of core control signals in which a time interval with which the core control signals change is locally shorter than a period of the first write enable signal based on the first write enable signal and the second write enable signal that are input is generated, and an operation verification of the resistive random access memory is performed by using the generated core control signals, whereby a cycle time in an arbitrary test cycle is locally and arbitrary adjusted. | 2012-03-29 |
20120079331 | MEMORY SYSTEM - A memory system according to the embodiment comprises a cell array including cell units having p or more physical quantity levels (p is a prime of 3 or more); a code generator unit operative to convert binary-represented input data to a write code represented by elements in Zp that is a residue field modulo p; and a code write unit operative to write the write code in the cell unit in accordance with the association of the elements in Zp to different physical quantity levels, wherein the input data is recorded in (p−1) cell units, the (p−1) cell units including no cell unit that applies the same physical quantity level for write in the case where the input data is 0 and for write in the case where only 1 bit is 1. | 2012-03-29 |
20120079332 | DEVICE FOR SECURING A JTAG TYPE BUS - A device to secure a JTAG type bus in its “scan chain” component chaining mode functionality, when several components are connected in series on the JTAG bus, includes a first interface for receiving JTAG signals and a second interface for the JTAG signals originating from a chain of components. The device includes the following modules: a JTAG frame generator module for verifying the continuity of operation of said Bus and components; a module for monitoring the electrical activity of said Bus and components; an alarm module for sending back an alarm detected by the above modules; an alarm module for managing the operating mode of the device; and a security functions activation module AFS. | 2012-03-29 |
20120079333 | LOCK STATE MACHINE OPERATIONS UPON STP DATA CAPTURES AND SHIFTS - A process of selecting alternative test circuitry within an integrated circuit enables a test access port. Scan test instruction data is loaded into an instruction register of a test access port TAP, the instruction data including information for selecting the alternative test circuitry. An Update-IR instruction update operation is performed at the end of the loading to output scan test control signals from the instruction register. A lockout signal is changed to an active state to disable the test access port and enable scan test circuits. | 2012-03-29 |