13th week of 2012 patent applcation highlights part 15 |
Patent application number | Title | Published |
20120074428 | SEMICONDUCTOR MODULE INCLUDING A SWITCH AND NON-CENTRAL DIODE - A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced. | 2012-03-29 |
20120074429 | GROWTH OF NON-POLAR M-PLANE III-NITRIDE FILM USING METALORGANIC CHEMICAL VAPOR DEPOSITION (MOCVD) - A method of growing non-polar m-plane III-nitride film, such as GaN, AlN, AlGaN or InGaN, wherein the non-polar m-plane III-nitride film is grown on a suitable substrate, such as an m-SiC, m-GaN, LiGaO | 2012-03-29 |
20120074430 | Radiating substrate and method for manufacturing the radiating substrate, and luminous element package with the radiating substrate - Disclosed herein is a radiating substrate radiating heat generated from a predetermined heating element to the outside. The radiating substrate includes polymer resins and graphenes distributed in the polymer resins. | 2012-03-29 |
20120074431 | SAPPHIRE SUBSTRATE AND SEMICONDUCTOR - The sapphire substrate has a principal surface for growing a nitride semiconductor to form a nitride semiconductor light emitting device and comprising a plurality of projections of the principal surface, wherein an outer periphery of a bottom surface of each of the projections has at least one depression. This depression is in the horizontal direction. The plurality of projections are arranged so that a straight line passes through the inside of at least any one of projections when the straight line is drawn at any position in any direction in a plane including the bottom surfaces of the plurality of projections. | 2012-03-29 |
20120074432 | LED PACKAGE MODULE AND MANUFACTURING METHOD THEREOF - A light emitting diode (LED) package module and the manufacturing method thereof are presented. A plurality of LEDs and a plurality of semiconductor elements are disposed on a silicon substrate, and then a plurality of lenses is formed above the positions of the plurality of the LEDs, and the plurality of the lenses is corresponding to the plurality of the LEDs. Then, a plurality of package units is defined on the silicon substrate, and each package unit has a semiconductor element and at least one LED. After that, the silicon substrate is cut to form a plurality of LED package modules, and each LED package module has at least one package unit. | 2012-03-29 |
20120074433 | ELECTRONIC APPARATUS - An electronic apparatus is provided that includes a number of first components on a first substrate and a number of second components on a second substrate. A lamination material that includes a conducting material is placed between the first components and the second components. Any one first component can couple to a varied subset of second components. | 2012-03-29 |
20120074434 | LIGHT EMITTING DEVICE PACKAGE AND LIGHTING APPARATUS USING THE SAME - Disclosed is a light emitting device package, which is free from thermal degradation by preventing reactions between moisture and light or between moisture and heat. The light emitting device package includes a light emitting device, a package body supporting the light emitting device, an electrode provided on the package body and electrically connected to the light emitting device, a filler covering the light emitting device, and a protective layer formed on a surface of the package body at which light and/or heat generated by the light emitting device arrives. | 2012-03-29 |
20120074435 | ORGANIC LIGHT EMITTING DISPLAY - An organic light emitting display is disclosed. In one embodiment, the display includes 1) a substrate, 2) a plurality of pixels formed on the substrate, wherein each of the pixels comprises at least one circuit region including i) a first light emission area, ii) a second light emission area iii) at least one transmission area transmitting external light, and iv) a pixel circuit unit and 3) a first pixel electrode formed in the first light emission area and electrically connected to the pixel circuit unit, wherein the first pixel electrode comprises a first transparent conductive layer and a reflective layer. The display may further include 1) a second pixel electrode formed in the second light emission area and electrically connected to the first pixel electrode, wherein the second pixel electrode comprises a second transparent conductive layer, 2) a first opposite electrode substantially directly below or above the first pixel electrode, 3) a second opposite electrode substantially directly below or above the second pixel electrode and 4) an organic emission layer formed between the first pixel electrode and the first opposite electrode and between the second pixel electrode and the second opposite electrode. | 2012-03-29 |
20120074436 | LED UNIT HAVING SELF-CONNECTING LEADS - An LED unit includes a plurality of LEDs connected to each other and a plate supporting the LEDs. Each LED includes a base, a chip mounted on the base, a pair of leads fixed to the base and electrically connected to the chip and an encapsulant sealing the chip. The base includes a main body and a pair of steps. The leads each have two opposite ends protruding from two opposite ends of the main body and located below/above a corresponding step. The protruding ends of the leads of each LED are connected to those of adjacent LEDs to electrically connect the LEDs in series or in parallel. | 2012-03-29 |
20120074437 | LED UNIT HAVING UNIFORM LIGHT EMISSION - An LED unit includes a plurality of LEDs connected to each other and a plate supporting the LEDs. Each LED includes a base, a chip mounted on the base, a pair of leads fixed to the base and electrically connected to the chip and an encapsulant sealing the chip. The base includes a main body and a pair of steps. The leads each have two opposite ends protruding from two opposite ends of the main body and located below/above a corresponding step. The protruding ends of the leads of adjacent LEDs are connected to each other. The encapsulants of adjacent LEDs are continuously connected together. Light emitted from the chips of the LEDs are evenly distributed in the encapsulants whereby the light from the LEDs forms a rectangular, uniform light source. | 2012-03-29 |
20120074438 | METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE, LIGHT EMITTING ELEMENT SUBSTRATE, AND QUALITY MANAGEMENT METHOD - A method for manufacturing a light emitting device includes forming a plurality of light emitting elements on a light emitting element substrate. an identification portion is formed on each of the light emitting elements to allow a pertinent light emitting element to be distinguishable from other light emitting elements. The light emitting elements are separated to form a plurality of light emitting devices. The identification portion may have an external appearance allowing each of the light emitting elements to be distinguishable from the other light emitting elements. | 2012-03-29 |
20120074439 | FLAT PANEL DISPLAY AND METHOD FOR MAKING THE SAME - A flat panel display includes a thin film transistor formed on a substrate; a planarization layer formed on the thin film transistor; a first electrode layer formed on the planarization layer and electrically connected with the thin film transistor through the via hole formed in the planarization layer; a pixel definition layer formed on the planarization layer and in which an opening for at least partially exposing the first electrode layer is formed; an adhesive reinforcement layer formed at least between the planarization layer and the pixel definition layer on the top of the planarization layer; an emitting layer formed on the first electrode layer; and a second electrode layer formed on the emitting layer and the pixel definition layer. The flat panel display has an improved adhesive property between a pixel definition layer and a planarization layer, which prevents a chipping phenomenon of the pixel definition layer. | 2012-03-29 |
20120074440 | ILLUMINATION DEVICE, DISPLAY DEVICE, AND TELEVISION RECEIVER - A backlight unit ( | 2012-03-29 |
20120074441 | WAFER-LEVEL LIGHT EMITTING DIODE PACKAGE AND METHOD OF FABRICATING THE SAME - Exemplary embodiments of the present invention provide a wafer-level light emitting diode (LED) package and a method of fabricating the same. The LED package includes a semiconductor stack including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer; a plurality of contact holes arranged in the second conductive type semiconductor layer and the active layer, the contact holes exposing the first conductive type semiconductor layer; a first bump arranged on a first side of the semiconductor stack, the first bump being electrically connected to the first conductive type semiconductor layer via the plurality of contact holes; a second bump arranged on the first side of the semiconductor stack, the second bump being electrically connected to the second conductive type semiconductor layer; and a protective insulation layer covering a sidewall of the semiconductor stack. | 2012-03-29 |
20120074442 | LIGHT EMITTING DIODE MODULE - A light emitting diode module having improved luminous efficiency is provided. The light emitting diode module includes: a light emitting chip; a phosphor layer formed of phosphor materials emitting light having a wavelength longer than the light emitted from the light emitting chip using light emitted from the light emitting chip as an excitation source; and a reflection plate that is disposed between the light emitting chip and the phosphor layer and that reflects the light emitted by the phosphor layer. | 2012-03-29 |
20120074443 | LED package structure - An LED package structure includes a base, an LED chip, a frame, and a microstructure lens. The LED chip is arranged on the base. The microstructure lens is arranged on the LED chip, and is a first-order optical lens being subject to surface optical microstructure treatment. The frame is provided for securing the microstructure lens on the base. The microstructure lens of the LED package structure can concentrate the light emitted from the LED chip or vary light patterns of the light emitted from the LED chip so as to achieve the purpose of increasing brightness and luminous angles. | 2012-03-29 |
20120074444 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - The disclosure provides a light emitting device comprising a light source and a reflector, having specular ink, surrounding the light source. | 2012-03-29 |
20120074445 | Light emitting element housing package - A light emitting element housing package comprises a ceramic substrate on which a light emitting element is mounted, and a wiring pattern that is formed on the ceramic substrate and to which a light emitting element chip is electrically connected, wherein a white thin film layer formed from a sintered body of white inorganic particles is formed on at least an upper surface of the wiring pattern, except a connection region in the wiring pattern to be connected to the light emitting element chip. | 2012-03-29 |
20120074446 | PHOSPHOR SHEET, LIGHT-EMITTING DEVICE HAVING THE PHOSPHOR SHEET AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a light emitting device including: a substrate; a light emitting diode (LED) chip disposed on the substrate; and a phosphor sheet disposed on an upper portion of the LED chip and including alignment members formed on a lower surface thereof. The alignment members contact the LED chip, such that the phosphor sheet is aligned with the LED chip. | 2012-03-29 |
20120074447 | LIGHT EMITTING DIODE ELEMENT - A light emitting diode element having a light emitting diode; and a glass covering sealing the light emitting diode is provided. The glass of the covering consists essentially of from 30 to 70 mol % of SnO, from 15 to 50 mol % of P | 2012-03-29 |
20120074448 | LIGHT EMITTING DEVICE INCLUDING A PHOTONIC CRYSTAL AND A LUMINESCENT CERAMIC - A semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region and a photonic crystal formed within or on a surface of the semiconductor structure is combined with a ceramic layer which is disposed in a path of light emitted by the light emitting layer. The ceramic layer is composed of or includes a wavelength converting material such as a phosphor. | 2012-03-29 |
20120074449 | QUANTUM DOT-METAL OXIDE COMPLEX, METHOD OF PREPARING THE SAME, AND LIGHT-EMITTING DEVICE COMPRISING THE SAME - Provided is a quantum dot-metal oxide complex including a quantum dot and a metal oxide forming a 3-dimensional network with the quantum dot. In the quantum dot-metal oxide complex, the quantum dot is optically stable without a change in emission wavelength band and its light-emitting performance is enhanced. | 2012-03-29 |
20120074450 | OPTICAL GEL MEMBER, ASSEMBLING METHOD OF OPTICAL DEVICE AND OPTICAL DEVICE USING THE SAME - An optical gel member to be used in a gap between light-emitting diode which is a backlight light source of an optical device and light guide plate, as well as an assembling method for an optical device and an optical device using the same. | 2012-03-29 |
20120074451 | LEAD FRAME STRUCTURE, A PACKAGING STRUCTURE AND A LIGHTING UNIT THEREOF - A lead frame structure, a packaging structure and a lighting unit are disclosed. The lead frame structure includes at least two first lead frame units having a space therebetween, and the two first lead frame units are arranged in an opposite manner. Each the first lead frame unit has a first conducting portion, a second conducting portion, and a first connection portion between the first and the second conducting portions. Moreover, the first connection portion has at least two grooves on a surface thereof. | 2012-03-29 |
20120074452 | LIGHT EMITTING DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A light emitting device package includes a base, a light emitting element, a mask, metal wires, an encapsulating layer and a cover layer. The base has a first surface bearing electrical structure thereon and an opposite second surface. The mask is arranged on the first surface to define a space receiving the light emitting element. Two openings are defined in the mask. The light emitting element has two pads exposed to an outside through the two openings respectively. The metal wires electrically connect the pads and the electrical structures. The encapsulating layer is filled in the space and two through holes in the base and encapsulates the light emitting element. The encapsulating layer is separated from the metal wires. The cover layer covers and protects the mask and the metal wires. A method of manufacturing the package is also provided. | 2012-03-29 |
20120074453 | PATTERNED SUBSTRATE AND LIGHT-EMITTING DIODE HAVING THE SAME - A patterned substrate for epitaxially forming a light-emitting diode includes: a top surface; a plurality of spaced apart recesses, each of which is indented downwardly from the top surface and each of which is defined by a recess-defining wall, the recess-defining wall having a bottom wall face, and a surrounding wall face that extends from the bottom wall face to the top surface; and a plurality of protrusions, each of which protrudes upwardly from the bottom wall face of the recess-defining wall of a respective one of the recesses. A light-emitting diode having the patterned substrate is also disclosed. | 2012-03-29 |
20120074454 | OPTOELECTRIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method is described for manufacturing an optoelectric device comprising the steps of
| 2012-03-29 |
20120074455 | LED PACKAGE STRUCTURE - An LED package structure includes a heat conductive plate defining a concave groove therein, an LED die received in the concave groove, an eutectic layer sandwiched between the heat conductive plate and the substrate, a transparent encapsulant encapsulating the LED die on the heat conductive plate. The heat conductive plate forms an electrode circuit layer on the heat conductive plate around the concave groove. The LED die forms electrodes electrically connected with the electrode circuit layer. An electrically insulating heat conduction grease filled around the substrate and the eutectic layer. | 2012-03-29 |
20120074456 | LIGHT EMITTING DEVICE PACKAGE - A light emitting device package is disclosed. The disclosed light emitting device package includes a body comprising a cavity, and a recess formed at a bottom surface of the body, first and second lead frames mounted in the body, and a light source electrically connected with the first and second lead frames, wherein at least one of the first and second lead frames has a heat sink which is extended from a portion of the first or the second lead frames, and is disposed in the recess. The body includes a first coupler formed on at least a portion of the body. The heat sink includes a second coupler, to which the first coupler is coupled. | 2012-03-29 |
20120074457 | SEMICONDUCTOR LIGHT EMITTING DEVICE WITH A CONTACT FORMED ON A TEXTURED SURFACE - A device includes a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure includes an n-contact region and a p-contact region. A cross section of the n-contact region comprises a plurality of first regions wherein portions of the light emitting layer and p-type region are removed to expose the n-type region. The plurality of first regions are separated by a plurality of second regions wherein the light emitting layer and p-type region remain in the device. The device further includes a first metal contact formed over the semiconductor structure in the p-contact region and a second metal contact formed over the semiconductor structure in the n-contact region. The second metal contact is in electrical contact with at least one of the second regions in the n-contact region. | 2012-03-29 |
20120074458 | QUASI-VERTICAL GATED NPN-PNP ESD PROTECTION DEVICE - Fashioning a quasi-vertical gated NPN-PNP (QVGNP) electrostatic discharge (ESD) protection device is disclosed. The QVGNP ESD protection device has a well having one conductivity type formed adjacent to a deep well having another conductivity type. The device has a desired holding voltage and a substantially homogenous current flow, and is thus highly robust. The device can be fashioned in a cost effective manner by being formed during a BiCMOS or Smart Power fabrication process. | 2012-03-29 |
20120074459 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity type base layer, a second conductivity type base layer, a first conductivity type second semiconductor layer, a gate insulating film, a gate electrode, and a second major electrode. The gate insulating film is provided on a side wall of a trench penetrating the second conductivity type base layer to reach the first conductivity type base layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and electrically connected with the second semiconductor layer. A maximum impurity concentration in the second semiconductor layer is within ten times a maximum impurity concentration in the second conductivity type base layer. | 2012-03-29 |
20120074460 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to an embodiment, a semiconductor device includes a first trench being provided in an N | 2012-03-29 |
20120074461 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region. | 2012-03-29 |
20120074462 | LONG WAVELENGTH INFRARED SENSOR MATERIALS AND METHOD OF SYNTHESIS THEREOF - A dilute nitrogen alloy of InN | 2012-03-29 |
20120074463 | SEMICONDUCTOR WAFER, PHOTOELECTRIC CONVERSION DEVICE, METHOD OF PRODUCING SEMICONDUCTOR WAFER, AND METHOD OF PRODUCING PHOTOELECTRIC CONVERSION DEVICE - Provided is a semiconductor wafer including: a base wafer containing silicon; an inhibitor that has been formed on the base wafer, has an aperture in which a surface of the base wafer is exposed, and inhibits crystal growth; and a light-absorptive structure that has been formed inside the aperture in contact with a surface of the base wafer exposed inside the aperture, where the light-absorptive structure includes a first semiconductor and a second semiconductor. | 2012-03-29 |
20120074464 | Non-planar device having uniaxially strained semiconductor body and method of making same - A method and a device made according to the method. The method comprises providing a substrate including a first material, and providing a fin including a second material, the fin being disposed on the substrate and having a device active portion, the first material and the second material presenting a lattice mismatch between respective crystalline structures thereof. Providing the fin includes providing a biaxially strained film including the second material on the substrate; and removing parts of the biaxially strained film to form a substantially uniaxially strained fin therefrom. | 2012-03-29 |
20120074465 | SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR - A SiGe HBT formed on a silicon substrate is disclosed. An active area is isolated by field oxide regions; a collector region is formed in the active area and extends into the bottom of the field oxide regions; pseudo buried layers are formed at the bottom of the field oxide regions, wherein each pseudo buried layer is separated by a lateral distance from the active area and connected to a lateral extension part of the collector region; first deep hole contacts are formed on top of the pseudo buried layers in the field oxide regions to pick up collector electrodes; a plurality of second deep hole contacts with a floating structure, are formed in the field oxide region on top of a lateral extension part of the collector region, wherein N-type implantation regions are formed at the bottom of the second deep hole contacts. | 2012-03-29 |
20120074466 | 3D MEMORY ARRAY WITH VERTICAL TRANSISTOR - A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell. | 2012-03-29 |
20120074467 | SWITCH ARRAY - According to one embodiment, a switch array includes first and second switches provided in a switch unit. The first switch includes first and second memory cell transistors and a first pass transistor. A second switch includes third and fourth memory cell transistors and a second pass transistor. The first and second memory cell transistor is provided in a first active region. The first pass transistor is provided in a second active region in the substrate. The third and fourth memory cell transistor is provided in the first active region. The second pass transistor is provided in the second active region adjacent to the first pass transistor in the channel length direction. The first and second active regions are adjacent to each other in a channel width direction. | 2012-03-29 |
20120074468 | SEMICONDUCTOR STRUCTURE - A semiconductor structure comprises a substrate, a gate structure, at least a source/drain region, a recess and an epitaxial layer. The substrate includes an up surface. A gate structure is located on the upper surface. The source/drain region is located within the substrate beside the gate structure. The recess is located within the source/drain region. The epitaxial layer fills the recess, and the cross-sectional profile of the epitaxial layer is an octagon. | 2012-03-29 |
20120074469 | ASYMMETRIC WEDGE JFET, RELATED METHOD AND DESIGN STRUCTURE - A junction gate field-effect transistor (JFET) for an integrated circuit (IC) chip is provided comprising a source region, a drain region, a lower gate, and a channel, with an insulating shallow trench isolation (STI) region extending from an inner edge of an upper surface of the source region to an inner edge of an upper surface of the drain region, without an intentionally doped region, e.g., an upper gate, coplanar with an upper surface of the IC chip between the source/drain regions. In addition, an asymmetrical quasi-buried upper gate can be included, disposed under a portion of the STI region, but not extending under a portion of the STI region proximate to the drain region. Embodiments of this invention also include providing an implantation layer, under the source region, to reduce R | 2012-03-29 |
20120074470 | MICROWAVE SEMICONDUCTOR DEVICE USING COMPOUND SEMICONDUCTOR AND METHOD FOR MANUFACTURING THE SAME - An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode | 2012-03-29 |
20120074471 | Transistor Structure for Improved Static Control During Formation of the Transistor - A method of forming a shadow mask vapor deposited transistor includes shadow mask vapor depositing a semiconductor segment. An electrically conductive drain contact is shadow mask vapor deposited on a first part of the semiconductor segment and a first insulator is shadow mask vapor deposited on the drain contact. An electrically conductive source contact is shadow mask vapor deposited on a second part of the semiconductor segment spaced from the drain contact and a second insulator is shadow mask vapor deposited on the source contact. A third insulator is shadow mask vapor deposited over at least part of each of the first and second insulators and the semiconductor segment between the drain contact and the source contact. An electrically conductive gate contact is shadow mask vapor deposited on the third insulator and in spaced relation to the semiconductor segment between the drain contact and the source contact. | 2012-03-29 |
20120074472 | Power Semiconductor Device Having Gate Electrode Coupling Portions for Etchant Control - A general insulated gate power semiconductor active element with many gate electrodes arranged in parallel has a laminated structure including a barrier metal film and a thick aluminum electrode film formed over the gate electrodes via an interlayer insulating film. When the aluminum electrode film is embedded in between the gate electrodes in parallel, voids may be generated with the electrodes. Such voids allow the etchant to penetrate in wet etching, which may promote the etching up to a part of the electrode film in an active cell region which is to be left. Thus, an insulated gate power semiconductor device is provided to include gate electrodes protruding outward from the inside of the active cell region, and a gate electrode coupling portion for coupling the gate electrodes outside the active cell region. The gate electrode coupling portion is covered with a metal electrode covering the active cell region. | 2012-03-29 |
20120074473 | Semiconductor Device - A method for fabricating a semiconductor device comprises forming a partial-insulated substrate comprising an insulating region located below both a channel region of a cell transistor and one of a storage node contact region and a bit line contact region, and forming a cell transistor comprising a fin region on the partial-insulated substrate. | 2012-03-29 |
20120074474 | PHOTOTRANSISTOR AND DISPLAY DEVICE INCLUDING THE SAME - A phototransistor includes a source electrode and a gate electrode which have the same electric potential, a transparent electrode formed on a surface of an interlayer insulating film so as to be located above a channel region, and a refresh controller for reducing a charge accumulated in a portion of the channel region, the portion facing the transparent electrode, by applying a voltage between the transparent electrode, and the gate electrode and the source electrode. | 2012-03-29 |
20120074475 | METAL GATE STRUCTURE OF A SEMICONDUCTOR DEVICE - The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ⅔ of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ⅓ of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region. | 2012-03-29 |
20120074476 | INTEGRATED CIRCUIT - In accordance with an embodiment, an integrated circuit includes a circuit in which first and second spin transistors are connected in series. The first spin transistor has a first node and a second node that are equal to each other in magnetization direction. The second spin transistor has a third node and a fourth node that are opposite to each other in magnetization direction. The second node and the fourth node are electrically connected to each other. | 2012-03-29 |
20120074477 | SEMICONDUCTOR DEVICE HAVING RAISED SOURCE AND DRAIN OF DIFFERING HEIGHTS - This semiconductor device has an MOS transistor equipped with a gate electrode formed on a semiconductor substrate, a source region next to one side of the gate electrode, and a drain region next to another side of the gate electrode, wherein an upper end of the source region and an upper end of the drain region are at positions where are higher than a top surface of the semiconductor substrate, and the height of the upper end of the drain region differs from the height of the upper end of the source region. | 2012-03-29 |
20120074478 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - As for a bypass capacitor, a first capacitor insulating film, together with a tunnel insulating film of a storage element, is formed of a first insulating film, a first electrode being a lower electrode, together with floating gate electrodes of the storage element, is formed of a doped·amorphous silicon film (a crystallized one), a second capacitor insulating film, together with a gate insulating film of transistors of 5 V in a peripheral circuit, is formed of a second insulating film, and a second electrode being an upper electrode, together with control gate electrodes of the storage element and gate electrodes of the transistors in the peripheral circuit, is formed of a polycrystalline silicon film. | 2012-03-29 |
20120074479 | AREA-EFFICIENT ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY CELL - Electrically erasable programmable “read-only” memory (EEPROM) cells in an integrated circuit, and formed by a single polysilicon level. The EEPROM cell consists of a coupling capacitor and a combined read transistor and tunneling capacitor. The capacitance of the coupling capacitor is much larger than that of the tunneling capacitor. In one embodiment, field oxide isolation structures isolate the devices from one another; a lightly-doped region at the source of the read transistor improves breakdown voltage performance. In another embodiment, trench isolation structures and a buried oxide layer surround the well regions at which the coupling capacitor and combined read transistor and tunneling capacitor are formed. | 2012-03-29 |
20120074480 | METHOD OF FORMING LUTETIUM AND LANTHANUM DIELECTRIC STRUCTURES - Methods of forming dielectric structures are shown. Methods of forming dielectric structures are shown that include lutetium oxide and lanthanum aluminum oxide crystals embedded within the lutetium oxide. Specific methods shown include monolayer deposition which yields process improvements such as chemistry control, step coverage, crystallinity/microstructure control. | 2012-03-29 |
20120074481 | SECURITIES, CHIP MOUNTING PRODUCT, AND MANUFACTURING METHOD THEREOF - The invention provides an ID chip with reduced cost, increased impact resistance and attractive design, as well as products and the like mounting the ID chip and a manufacturing method thereof. In view of the foregoing, an integrated circuit having a semiconductor film with a thickness of 0.2 μm or less is mounted on securities including bills, belongings, containers of food and drink, and the like (hereinafter referred to as products and the like). The ID chip of the invention can be reduced in cost and increased in impact resistance as compared with a chip formed over a silicon wafer while maintaining an attractive design. | 2012-03-29 |
20120074482 | EEPROM CELL - A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor. | 2012-03-29 |
20120074483 | EEPROM CELL - A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor. | 2012-03-29 |
20120074484 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device including forming a plurality of gate structures spaced apart from each other on a substrate; forming a first insulation layer covering the gate structures, the first insulation layer including a void between the gate structures; removing an upper portion of the first insulation layer to form a first insulation layer pattern on sidewalls of lower portions of the gate structures and on the substrate between the gate structures, the first insulation layer pattern including a first recess thereon; forming a conductive layer on upper portions of the gate structures exposed by the first insulation layer pattern; reacting the conductive layer with the gate structures; and forming a second insulation layer on the upper portions of the gate structures, the second insulation layer including a second recess therebeneath in fluid communication with the first recess. | 2012-03-29 |
20120074485 | Nonvolatile Memory Device and Manufacturing Method Thereof - A nonvolatile memory device comprises a gate insulating layer, a floating gate and a dielectric layer sequentially formed over a semiconductor substrate, a capping layer formed over the dielectric layer, and a control gate formed over the capping layer, wherein the control gate includes nitrogen or carbon as an additive. | 2012-03-29 |
20120074486 | MULTI-GATE BANDGAP ENGINEERED MEMORY - Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation. | 2012-03-29 |
20120074487 | APPARATUS CONTAINING COBALT TITANIUM OXIDE - Electronic apparatus and methods of forming the electronic apparatus include cobalt titanium oxide on a substrate for use in a variety of electronic systems. The cobalt titanium oxide may be structured as one or more monolayers. The cobalt titanium oxide may be formed by a monolayer by monolayer sequencing process such as atomic layer deposition. | 2012-03-29 |
20120074488 | VERTICAL TRANSISTOR WITH HARDENING IMPLATATION - A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces. | 2012-03-29 |
20120074489 | SUPER-JUNCTION TRENCH MOSFET WITH RESURF STEPPED OXIDES AND TRENCHED CONTACTS - A super-junction trench MOSFET with Resurf Stepped Oxide and trenched contacts is disclosed. The inventive structure can apply additional freedom for better optimization and manufacturing capability by tuning thick oxide thickness to minimize influence of charge imbalance, trapped charges, etc. . . . Furthermore, the fabrication method can be implemented more reliably with lower cost. | 2012-03-29 |
20120074490 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - To realize forming a trench MOSFET in which a depth of a P-body is changed on the same surface as a CMOS by employing steps with good controllability and without greatly increasing the number of manufacturing steps, provided is a trench MOSFET including an extended body region ( | 2012-03-29 |
20120074491 | POWER SEMICONDUCTOR DEVICE - In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other. | 2012-03-29 |
20120074492 | Method of Fabricating A Semicoductor Device Having A Lateral Double Diffused Mosfet Transistor with a Lightly Doped Source and a CMOS Transistor - Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described. | 2012-03-29 |
20120074493 | FIELD EFFECT TRANSISTORS HAVING IMPROVED BREAKDOWN VOLTAGES AND METHODS OF FORMING THE SAME - Transistors having improved breakdown voltages and methods of forming the same are provided herein. In one embodiment, a method of forming a transistor comprises the steps of: forming a drain and a source by doping a semiconductor with a first dopant type to form a first type of semiconductor, the drain and source being separated from one another, wherein the drain comprises a first drain region of a first dopant concentration adjacent a second drain region, such that at least a portion of the second drain region is positioned between the first drain region and the source, and further comprising forming an intermediate region by doping the semiconductor so as to form a second type of semiconductor intermediate the drain and source, the intermediate region spaced apart from the second drain region. | 2012-03-29 |
20120074494 | STRAINED THIN BODY SEMICONDUCTOR-ON-INSULATOR SUBSTRATE AND DEVICE - A method of forming a strained, semiconductor-on-insulator substrate includes forming a second semiconductor layer on a first semiconductor substrate. The second semiconductor is lattice matched to the first semiconductor substrate such that the second semiconductor layer is subjected to a first directional stress. An active device semiconductor layer is formed over the second semiconductor layer such that the active device semiconductor layer is initially in a relaxed state. One or more trench isolation structures are formed through the active device layer and through the second semiconductor layer so as to relax the second semiconductor layer below the active device layer and impart a second directional stress on the active device layer opposite the first directional stress. | 2012-03-29 |
20120074495 | Series FinFET Implementation Schemes - A device includes a first semiconductor fin, and a second semiconductor fin parallel to the first semiconductor fin. A straight gate electrode is formed over the first and the second semiconductor fins, and forms a first fin field-effect transistor (FinFET) and a second FinFET with the first and the second semiconductor fins, respectively, wherein the first and the second FinFETs are of a same conductivity type. A first electrical connection is formed on a side of the straight gate electrode and coupling a first source/drain of the first FinFET to a first source/drain of the second FinFET, wherein a second source/drain of the first FinFET is not connected to a second source/drain of the second FinFET. | 2012-03-29 |
20120074496 | Diode Having A Pocket Implant Blocked And Circuits And Methods Employing Same - Diodes, including gated diodes and shallow trench isolation (STI) diodes, manufacturing methods, and related circuits are provided without at least one halo or pocket implant thereby reducing capacitance of the diode. In this manner, the diode may be used in circuits and other devices having performance sensitive to load capacitance while still obtaining the performance characteristics of the diode. Such characteristics for a gated diode include fast turn-on times and high conductance, making the gated diodes well-suited for electro-static discharge (ESD) protection circuits as one example. Diodes include a semiconductor substrate having a well region and insulating layer thereupon. A gate electrode is formed over the insulating layer. Anode and cathode regions are provided in the well region. A P-N junction is formed. At least one pocket implant is blocked in the diode to reduce capacitance. | 2012-03-29 |
20120074497 | ESD PROTECTION STRUCTURE - A device used as an ESD protection structure, which is a modified N-type LDMOS device is disclosed. A conventional LDMOS includes only one N-type heavily doped region as a drain in an N-type lightly doped region ( | 2012-03-29 |
20120074498 | METHOD AND APPARATUS FOR IMPROVING GATE CONTACT - A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess. | 2012-03-29 |
20120074499 | Integrated Circuits and Methods of Design and Manufacture Thereof - Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives. | 2012-03-29 |
20120074500 | METHOD FOR FORMING TRANSISTOR WITH HIGH BREAKDOWN VOLTAGE - Transistors are formed using pitch multiplication. Each transistor includes a source region and a drain region connected by strips of active area material separated by shallow trench isolation (STI) structures, which are formed by dielectric material filling trenches formed by pitch multiplication. During pitch multiplication, rows of spaced-apart mandrels are formed and spacer material is deposited over the mandrels. The spacer material is etched to define spacers on sidewalls of the mandrels. The mandrels are removed, leaving free-standing spacers. The spacers constitute a mask, through which an underlying substrate is etched to form the trenches and strips of active area material. The trenches are filled to form the STI structures. The substrate is doped, forming source, drain and channel regions. A gate is formed over the channel region. In some embodiments, the STI structures and the strips of material facilitate the formation of transistors having a high breakdown voltage. | 2012-03-29 |
20120074501 | USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES - Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET. | 2012-03-29 |
20120074502 | USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES - Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). One embodiment of this invention includes creating this differential stress by varying the deposition conditions for forming PFET and NFET contacts, for example, the temperature at which the fill materials are deposited, and the rate at which the fill materials are deposited. In another embodiment, the differential stress is created by filling the contacts with differing materials that will impart differential stress due to differing coefficient of thermal expansions. In another embodiment, the differential stress is created by including a silicide layer within the NFET contacts and/or the PFET contacts. | 2012-03-29 |
20120074503 | Planar Silicide Semiconductor Structure - A planar silicide structure and method of fabrication is disclosed. A FET having a silicided raised source-drain structure is formed where the height of the source-drain structures are the same as the height of the gates, simplifying the process of forming contacts on the FET. One embodiment utilizes a replacement metal gate FET and another embodiment utilizes a gate-first FET | 2012-03-29 |
20120074504 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device fabrication method includes forming a first gate electrode via a first gate insulating film on a P-type semiconductor region formed in a surface portion of a semiconductor substrate; forming a second gate electrode via a second gate insulating film on an N-type semiconductor region formed in the surface portion of the semiconductor substrate; forming a first insulating film; forming a second insulating film; forming a mask having a pattern corresponding to the P-type semiconductor region; etching away the second insulating film by using the mask; removing the mask; and forming a first gate electrode sidewall insulating film and forming a second gate electrode sidewall insulating film. | 2012-03-29 |
20120074505 | 3D Integrated circuit in planar process - Techniques related to 3D integrated circuits formed on a single wafer are disclosed. According to one embodiment, an integrated circuit comprises a first device forming a first projection area on a wafer and a second device forming a second projection area on the wafer. The first projection area overlaps with the second projection area partially or completely. The area being shared between the two devices refers to the partial or complete overlapping of the projection areas of the two devices. In one embodiment, two or more devices in different layers of the integrated circuit or two or more devices at different depths in a same layer of the integrated circuit may share an area on the same wafer in a certain manner. Thereby, the area of the chip is saved and the chip cost of the integrated circuit is significantly reduced. | 2012-03-29 |
20120074506 | Semiconductor Package for Higher Power Transistors - A semiconductor package for mounting multiple field effect transistors (FETs) is disclosed. The package includes a drain conductor between each FET's drain connection point and a drain terminal connector on the semiconductor package; a source conductor between each FET's source connection point and a source terminal connector of the source conductor on the semiconductor package, the source conductor containing the common inductance; a dielectric substantially overlaying said source conductor; a gate conductor on the dielectric substantially overlaying the source conductor; and said gate conductor, said dielectric and said source conductor forming a transformer, the transformer creating voltage in the gate conductor which almost exactly cancels voltage in said source conductor. | 2012-03-29 |
20120074507 | INTEGRATION OF AN AMORPHOUS SILICON RESISTIVE SWITCHING DEVICE - An integrated circuit device. The integrated circuit device includes a semiconductor substrate having a surface region. A gate dielectric layer overlies the surface region of the substrate. The device includes a MOS device having a p+ active region. The p+ active region forms a first electrode for a resistive switching device. The resistive switching device includes an amorphous silicon switching material overlying the p+ active region and a metal electrode overlies the first metal conductor structure. The metal electrode includes a metal material, upon application of a positive bias to the metal electrode, forms a metal region in the amorphous silicon switching material. The MOS device provides for a select transistor for the integrated circuit device. | 2012-03-29 |
20120074508 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device less prone to cause a reaction between a metal material for interconnection and an electrode or the like connected to a semiconductor region during the high-temperature operation thereof and less prone to be strained during the high-temperature operation thereof. The power semiconductor device can be an SiC power device or the like in which a first metal layer containing at least one selected from the group consisting of Pt, Ti, Mo, W and Ta is formed on a source electrode formed on the semiconductor region, such as a source region or the like. A second metal layer containing at least one selected from the group consisting of Mo, W and Cu is formed on the first metal layer. A third metal layer containing at least one selected from the group consisting of Pt, Mo and W is formed on the second metal layer. | 2012-03-29 |
20120074509 | WAFER BOND CMUT ARRAY WITH CONDUCTIVE VIAS - A wafer bonded CMUT array comprising a plurality of CMUT elements distributed across a substrates, each element comprising a cavity and a signal electrode formed in the substrate, and a conductive membrane closing the cavity and forming a ground electrode, wherein the membranes of the individual elements form an unbroken ground plane across the surface of the array and wherein electrical connection to the signal electrodes is provided by means of a conductive vias depending therefrom through the substrate from the signal electrode to the rear of the substrate. | 2012-03-29 |
20120074510 | MAGNETIC SENSOR AND MAGNETIC HEAD - A magnetic sensor | 2012-03-29 |
20120074511 | MAGNETIC MEMORY AND METHOD OF MANUFACTURING THE SAME - A magnetic memory according to an embodiment includes: at least one memory cell comprising a magnetoresistive element as a memory element, and first and second electrodes that energize the magnetoresistive element. The magnetoresistive element includes: a first magnetic layer having a variable magnetization direction perpendicular to a film plane; a tunnel barrier layer on the first magnetic layer; and a second magnetic layer on the tunnel barrier layer, and having a fixed magnetization direction perpendicular to the film plane. The first magnetic layer including: a first region; and a second region outside the first region so as to surround the first region, and having a smaller perpendicular magnetic anisotropy energy than that of the first region. The second magnetic layer including: a third region; and a fourth region outside the third region, and having a smaller perpendicular magnetic anisotropy energy than that of the third region. | 2012-03-29 |
20120074512 | COMMUNICATION DEVICE - A communication device according to an embodiment includes an antenna transmitting/receiving a high frequency signal, a semiconductor chip having four corners and four sides processing the high frequency signal, and a substrate on which a first wiring connected to ground, a second wiring supplying power to the semiconductor chip, a third wiring connected to a protection element or circuit of the semiconductor chip, and fourth wirings transmitting a signal from the semiconductor chip are formed by plating, and the semiconductor chip is mounted. | 2012-03-29 |
20120074513 | PHOTOELECTRIC CONVERSION ELEMENT, SOLID-SATE IMAGING ELEMENT, IMAGING APPARATUS, AND METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION ELEMENT - A photoelectric conversion element includes an insulating film, a first electrode, a light receiving layer, and a second electrode. The first electrode is formed on the insulating film and is made of titanium oxynitride. The light receiving layer is formed on the first electrode and includes an organic material. A composition of the first electrode just before forming the light receiving layer meets (1) a requirement that an amount of oxygen contained in the whole of the first electrode is 75 atm % or more of an amount of titanium, or (2) a requirement that in a range of from the substrate side of the first electrode to 10 nm or a range of from the substrate side of the first electrode to ⅔ of the thickness of the first electrode, an amount of oxygen is 40 atm % or more of an amount of titanium. | 2012-03-29 |
20120074514 | ETCH-RESISTANT COATING ON SENSOR WAFERS FOR IN-SITU MEASUREMENT - A sensor wafer may be configured for in-situ measurements of parameters during an etch process. The sensor wafer may include a substrate, a cover, and one or more components positioned between the substrate and the cover. An etch-resistant coating is formed on one or more surfaces of the cover and/or substrate. The coating is configured to resist etch processes that etch the cover and/or substrate for a longer period than standard thin film materials of the same or greater thickness than the protective coating. | 2012-03-29 |
20120074515 | Noise Decoupling Structure with Through-Substrate Vias - A device includes a substrate having a front surface and a back surface; an integrated circuit device at the front surface of the substrate; and a metal plate on the back surface of the substrate, wherein the metal plate overlaps substantially an entirety of the integrated circuit device. A guard ring extends into the substrate and encircles the integrated circuit device. The guard ring is formed of a conductive material. A through substrate via (TSV) penetrates through the substrate and electrically couples to the metal plate. | 2012-03-29 |
20120074516 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having a plate electrode adapted to a plurality of chips, capable of being produced at low cost, and having high heat cycle property. A semiconductor device according to the present invention includes a plurality of semiconductor chips formed on a substrate, and a plate electrode connecting electrodes of the plurality of semiconductor chips. The plate electrode has half-cut portions formed by half-pressing and the raised sides of the half-cut portions are bonded with the electrodes of the semiconductor chips. | 2012-03-29 |
20120074517 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME - One or more embodiments relate to a method for forming a semiconductor structure, including: forming a semiconductor layer; and forming a dielectric layer over a back side of said semiconductor layer. In one or more embodiments, the dielectric layer may be a silicone rubber layer. | 2012-03-29 |
20120074518 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The invention relates to a semiconductor device, wherein a storage node contact hole is made large to solve any problem caused during etching a storage node contact hole with a small CD, a landing plug is formed to lower plug resistance. A semiconductor device according to the invention comprises: first and second active regions formed in a substrate, the first and second active being adjacent to each other, each of the first and second active regions including a bit-line contact region and a storage node contact region and a device isolation structure; a word line provided within a trench formed in the substrate; first and second storage node contact plugs assigned to the first and second active regions, respectively, the first and second storage node contact plugs being separated from each other by a bit line groove; and a bit line formed within the bit-line groove. | 2012-03-29 |
20120074519 | CRACK STOP STRUCTURE ENHANCEMENT OF THE INTEGRATED CIRCUIT SEAL RING - An improved crack stop structure (and method of forming) is provided within a die seal ring of an integrated circuit die to increase crack resistance during the dicing of a semiconductor wafer. The crack stop structure includes a stack layer (of alternating insulating and conductive layers) and an anchor system extending from the stack layer to a predetermined point below the surface of the substrate. A crack stop trench is formed in the substrate and filled with material having good crack resistance to anchor the stack layer to the substrate. | 2012-03-29 |
20120074520 | ELECTRICAL FUSE STRUCTURE AND METHOD OF FABRICATING SAME - A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved. | 2012-03-29 |
20120074521 | METHOD OF MANUFACTURING CAPACITOR, AND CAPACITOR, CIRCUIT SUBSTRATE AND SEMICONDUCTOR APPARATUS - A method of manufacturing a capacitor includes forming a first ceramic film on a first base made of a metal, forming a second ceramic film on a second base made of a metal, forming a first copper electrode pattern and a first copper via-plug on a surface of one of the first and second ceramic films, the electrode pattern and the via-plug being separate from each other, bonding the first and second ceramic films together with the first electrode pattern and the via-plug therebetween, by applying a pulsed voltage between the first base and the second base while the first base and the second base are pressed so that the first ceramic film and the second ceramic film are pressed on each other, and removing the second base. | 2012-03-29 |
20120074522 | VERTICAL ZENER DIODE STRUCTURE AND MANUFACTURING METHOD OF THE SAME - The present invention discloses a vertical zener diode structure, in which a deep N-sinker region and a P-implantation region of the zener diode are formed in an N-well within an epitaxial layer; the P-implantation region is closer to a silicon surface than the deep N-sinker region in a vertical direction. In this structure, as zener breakdown occurs at a position away from the silicon surface, the problem of a drift in the zener breakdown value can be improved. The present invention also discloses a manufacturing method of a vertical zener diode. | 2012-03-29 |
20120074523 | CONTROLLING MICROELECTRONIC SUBSTRATE BOWING - The present disclosure relates to the field of epitaxial structures for microelectronic device formation, particularly to heavily doped, substrates having a compensation component embedded along the dopant to prevent bowing of the substrate during deposition of an epitaxial layer. | 2012-03-29 |
20120074524 | LATERAL GROWTH METHOD FOR DEFECT REDUCTION OF SEMIPOLAR NITRIDE FILMS - A lateral growth method for defect reduction of semipolar nitride films. The process steps include selecting a semipolar nitride plane and composition, selecting a suitable substrate for growth of the semipolar nitride plane and composition, and applying a selective growth process in which the semipolar nitride nucleates on some areas of the substrate at the exclusion of other areas of the substrate, wherein the selective growth process includes lateral growth of nitride material by a lateral epitaxial overgrowth (LEO), sidewall lateral epitaxial overgrowth (SLEO), cantilever epitaxy or nanomasking. | 2012-03-29 |
20120074525 | MISCUT SEMIPOLAR OPTOELECTRONIC DEVICE - A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an In | 2012-03-29 |
20120074526 | DETACHABLE SUBSTRATE AND PROCESSES FOR FABRICATING AND DETACHING SUCH A SUBSTRATE - The invention relates to a detachable substrate for the electronics, optics or optoelectronics industry, that includes a detachable layer resting on a buried weakened region. This substrate is remarkable in that this buried weakened region consists of a semiconductor material that is denser in the liquid state than in the solid state and that contains in places precipitates of naturally volatile impurities. The invention also relates to a process for fabricating and detaching a detachable substrate. | 2012-03-29 |
20120074527 | INTEGRATED CIRCUIT COMPRISING A DEVICE WITH A VERTICAL MOBILE ELEMENT INTEGRATED IN A SUPPORT SUBSTRATE AND METHOD FOR PRODUCING THE DEVICE WITH A MOBILE ELEMENT - The integrated circuit comprises a support substrate having opposite first and second main surfaces. A cavity passes through the support substrate and connects the first and second main surfaces. The integrated circuit comprises a device with a mobile element, the mobile element and a pair of associated electrodes of which are included in a cavity. An anchoring node of the mobile element is located at the level of the first main surface. The integrated circuit comprises a first elementary chip arranged at the level of the first main surface and electrically connected to the device with a mobile element. | 2012-03-29 |