13th week of 2014 patent applcation highlights part 17 |
Patent application number | Title | Published |
20140084407 | IMAGING SYSTEMS WITH CIRCUIT ELEMENT IN CARRIER WAFER - An imaging system may include an image sensor package with an image sensor wafer mounted on a carrier wafer, which may be a silicon substrate. A capacitor may be formed in the carrier wafer. Trenches may be etched in a serpentine pattern in the silicon substrate. Conductive plates of the capacitor may be formed at least partially in the trenches. An insulator material may be formed between the capacitor and the silicon substrate. A dielectric layer may be formed between the conductive plates of the capacitor. The image sensor package may be mounted on a printed circuit board via a ball grid array. Conductive vias may electrically couple the capacitor and the image sensor wafer to the printed circuit board. | 2014-03-27 |
20140084408 | Semiconductor Device and Production Method for a Semiconductor Device - A semiconductor device includes a carrier substrate having at least one conductor track, at least one converter element structured at least partly from a further semiconductor substrate, and conductive structures formed on a respective converter element. The at least one converter element is electrically linked to the at least one conductor track via at least one at least partly conductive supporting element arranged between a contact side of the carrier substrate and an inner side of the converter element. The inner side is oriented toward the carrier substrate. The at least one converter element is arranged on the contact side of the carrier substrate such that the inner side of the converter element is kept spaced apart from the contact side of the carrier substrate. The at least one converter element and the conductive structures formed thereon are completely embedded into at least one insulating material. | 2014-03-27 |
20140084409 | IMAGE SENSORS WITH IN-PIXEL ANTI-BLOOMING DRAINS - An imaging system may include an image sensor having an array of image pixels formed in a substrate. Each image pixel may include a photodiode directly coupled to an anti-blooming diode. The anti-blooming diode may be connected to a positive voltage supply line and may be configured to drain excess charge from the photodiode when the photodiode is saturated. The anti-blooming drain may be formed from an n-type diffusion region partially surrounded by a p-type doped layer. The p-type doped layer may be interposed between and in contact with the n-type diffusion region of the anti-blooming diode and an n-type doped region of the photodiode. The anti-blooming diode may begin to drain excess charge from the photodiode in response to the photodiode reaching a threshold potential during integration. If desired, multiple pixels may share a common anti-blooming diode. | 2014-03-27 |
20140084410 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device has an element substrate that is formed with a plurality of photodiodes, a back-surface electrode, and an electric charge discharging path. A wiring layer for controlling the photodiodes is formed in a front surface of the element substrate. Light is incident upon the photodiodes from a back surface of the element substrate. By applying the back-surface electrode with a voltage in accordance with timing of operation control of the photodiodes, a potential is modulated in the vicinity of the back surface of the element substrate. When an electron inversion layer formed in the vicinity of the back surface of the element substrate upon applying a positive voltage to the back-surface electrode is coupled to a region for accumulating signal charge through a monotonously changing potential gradient, the electric charge that has flowed into the electron inversion layer is discharged through the electric charge discharging path. | 2014-03-27 |
20140084411 | SEMICONDUCTOR-ON-INSULATOR (SOI) DEEP TRENCH CAPACITOR - Aspects of the present invention relate to a semiconductor-on-insulator (SOI) deep trench capacitor. One embodiment includes a method of forming a deep trench capacitor structure. The method includes: providing a SOI structure including a first and second trench opening in a semiconductor layer of the SOI structure, forming a doped semiconductor layer covering the semiconductor layer, forming a first dielectric layer covering the doped semiconductor layer, forming a node metal layer over the first dielectric layer, forming a second dielectric layer covering the node metal layer, filling a remaining portion of each trench opening with a metal layer to form an inner node in each of the trench openings, the metal layer including a plate coupling each of the inner nodes, and forming a node connection structure to conductively connect the node metal layer in the first trench opening with the node metal layer in the second trench opening. | 2014-03-27 |
20140084412 | SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE STRUCTURES - A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure. | 2014-03-27 |
20140084413 | PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME - A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a top surface and a bottom surface opposing the top surface; an insulating protective layer formed on the top surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and passive components provided on or embedded in the interposer. By integrating the passive components into the package substrate, when a chip is provided on the interposer, the conductive path between the chip and the passive components can be shortened, and the pins of the chip have a stable voltage. Therefore, the overall electrical performance is enhanced. | 2014-03-27 |
20140084414 | VERTICAL MEANDER INDUCTOR FOR SMALL CORE VOLTAGE REGULATORS - Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography. | 2014-03-27 |
20140084415 | Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer - A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die. | 2014-03-27 |
20140084416 | Stacked Package and Method of Manufacturing the Same - A stacked package includes a first package substrate having a major surface that defines a horizontal plane, first pads on an upper portion of the first package substrate, a multilayer capacitor on the first pads, and a first semiconductor chip on the first package substrate. A second package substrate is provided on the first semiconductor package, and a second semiconductor chip is on the second package substrate. Conductive bumps are provided between the first package substrate and the second package substrate that are vertically aligned with the multilayer capacitor. Signal characteristics in the stacked package may be improved by the multilayer capacitor. Because the multilayer capacitor is formed in the stacked package it may provide for an increased degree of integration. | 2014-03-27 |
20140084417 | METAL-INSULATOR-METAL (MIM) CAPACITOR - There is disclosed a metal-insulator-metal, MIM, capacitor. The MIM capacitor comprises a MIM stack formed within an interconnect metal layer. The interconnect metal layer is utilised as an electrical connection to a metal layer of the MIM stack. | 2014-03-27 |
20140084418 | LATERAL EPITAXIAL GROWN SOI IN DEEP TRENCH STRUCTURES AND METHODS OF MANUFACTURE - Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer including a substrate, buried oxide layer (BOX) and silicon (SOI) film. The structure includes a wafer including a substrate, buried insulator layer and a layer of silicon on insulator layer (SOI) having a single crystalline structure throughout the layer. The structure further includes a first plate in the substrate and an insulator layer in direct contact with the first plate. A doped polysilicon is in direct contact with the insulator layer and also in direct contact with the single crystalline structure of the SOI. | 2014-03-27 |
20140084419 | CAPACITOR STRUCTURE - A DRAM capacitor structure is disposed on the interior surface of a vertical hollow cylinder of a support structure overlying a semiconductor substrate. The support structure further includes a horizontal supporting layer that is integrally connected with the vertical hollow cylinder. A fabrication method for forming the DRAM capacitor structure is also provided. | 2014-03-27 |
20140084420 | METHOD TO BRIDGE EXTRINSIC AND INTRINSIC BASE BY SELECTIVE EPITAXY IN BICMOS TECHNOLOGY - A method of forming a heterojunction bipolar transistor. The method includes providing a structure comprising at least an intrinsic base region and an emitter pedestal region. A stack is formed on the intrinsic base region. The stack comprises a polysilicon layer and a top sacrificial oxide layer. A trench is formed in the structure. The trench circumscribes the intrinsic base region and the stack. An extrinsic base is formed at two regions around the stack. The extrinsic base is formed by a selective epitaxial growth process to create a bridge over the trench. The bridge connects the two regions. An opening is provided in the stack. The opening exposes a portion of the intrinsic base region. An emitter is formed in the opening. | 2014-03-27 |
20140084421 | Adhesion Promoter Apparatus and Method - A structure comprises a substrate having a plateau region and a trench region, a reflecting layer formed over a top surface of the trench region, a first adhesion promoter layer formed over the reflecting layer, a bottom cladding layer deposited over the first adhesion promoter layer, a core layer formed over the bottom cladding layer and a top cladding layer formed over the core layer. | 2014-03-27 |
20140084422 | Reclaimed Wafer And A Method For Reclaiming A Wafer - Embodiments of the present invention relate to a reclaimed wafer, a method for reclaiming a wafer, a method for reclaiming a batch of wafers, and a method for forming electronic structures. After being reclaimed, the reclaimed wafers are essentially free of a residue. | 2014-03-27 |
20140084423 | PROTECTIVE MEMBER AND WAFER PROCESSING METHOD - A wafer processing method including a fixing step of providing a wafer on a protective member so that a device area of the wafer faces an unevenness absorbing member provided in a recess of the protective member and providing an adhesive outside the device area to thereby fix the protective member and the wafer, a grinding step of holding the protective member on a holding table in the condition where the back side of the wafer is exposed and next grinding the back side of the wafer by using a grinding unit to thereby reduce the thickness of the wafer to a predetermined thickness, and a removing step of removing the protective member from the wafer. The adhesive is locally provided outside of the device area, so that the protective member can be easily removed from the wafer without leaving the adhesive on the front side of each device. | 2014-03-27 |
20140084424 | Semiconductor Device with Protective Structure Around Semiconductor Die for Localized Planarization of Insulating Layer - A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die. | 2014-03-27 |
20140084425 | PERIMETER TRENCH SENSOR ARRAY PACKAGE - One embodiment of a perimeter trench sensor array package can include a thinned substrate device that includes a perimeter trench formed near the edges of the device that can be configured to be thinner than a central portion of the thinned substrate device. The perimeter trench can include bond pads that can couple to electrical elements included in the thinned substrate device. The thinned substrate device can be attached to a core layer that can in turn support one or more resin layers. The core layer and the resin layers can form a printed circuit board assembly, a flex cable assembly or a stand-alone module. | 2014-03-27 |
20140084426 | SUBSTRATE MEMBER AND METHOD OF MANUFACTURING CHIP - A substrate member includes a substrate and a plurality of chip regions formed on the substrate across a scribe line. Each of the plurality of chip regions includes a first region that has contact with the scribe line and in which a plurality of first pattern elements are formed, and a second region that is surrounded by the first region and in which a plurality of second pattern elements are formed. A minimum value of a size of the first pattern elements is greater than a minimum value of a size of the second pattern elements and/or a minimum value of an interval between adjacent first pattern elements is greater than a minimum value of an interval between adjacent second pattern elements. | 2014-03-27 |
20140084427 | MULTI-CORE DIES PRODUCED BY RETICLE SET MODIFICATION - A first reticle set designed for manufacturing dies with a limited number of cores is modified into a second reticle set suitable for manufacturing at least some dies with at least twice as many cores. The first reticle set defines scribe lines to separate the originally defined dies. At least one scribe line is removed from pairs of adjacent but originally distinctly defined dies. Inter-core communication wires are defined to connect the adjacent cores, which are configured to enable the adjacent cores to communicate during operation without connecting to any physical input/output landing pads of the resulting more numerously cored die, which will not carry signals through the inter-core communication wires off the P-core die. The inter-core communication wires may be used for power management coordination purposes or to bypass the external processor bus. | 2014-03-27 |
20140084428 | INTEGRATED CIRCUIT WITH ELECTRICAL THROUGH-CONTACT AND METHOD FOR PRODUCING ELECTRICAL THROUGH-CONTACT - A substrate of an integrated circuit has a first surface and an opposing second surface. A functionalized region is formed at least on the first surface. At least one electrical through-plating is provided as a through-hole which is continuously filled with an electrically conductive material and which runs from the first surface to the second surface through the substrate. To ensure that the through-plating can be reliably produced and is provided in a space-saving manner, the through-hole has at least one gradation on which a transition occurs from a smaller hole cross-section on the side of the first surface to a larger hole cross-section on the side of the second surface. | 2014-03-27 |
20140084429 | EXTREMELY THIN PACKAGE - Techniques for achieving extremely thin package structures are disclosed. In some embodiments, a device comprises an integrated circuit connected to a leadframe or substrate via connections and EMC (Epoxy Molding Compound) surrounding the integrated circuit except at a backside of the integrated circuit and connecting areas via which the integrated circuit is connected to the leadframe or substrate. | 2014-03-27 |
20140084430 | SEMICONDUCTOR CHIP AND FILM AND TAB PACKAGE COMPRISING THE CHIP AND FILM - A semiconductor chip for a TAB package includes a surface including a set of input pads connected to internal circuitry of the chip and for receiving external signals The surface includes output pads. A plurality of input pads are adjacent a first edge and are in a first row substantially parallel to the first edge and extending in a first direction; a plurality of first output pads are adjacent a second edge, and are in a second row substantially parallel to the second edge and extending in the first direction; and a plurality of second output pads are located between the first row and the second row. The plurality of second output pads first and second outermost pads located a certain distance from a respective third edge and fourth edge, and first and second inner pads located a greater distance from the respective third edge and fourth edge. | 2014-03-27 |
20140084431 | Semiconductor Package with Heat Spreader - A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package. | 2014-03-27 |
20140084432 | METHOD AND APPARATUS FOR MULTI-CHIP STRUCTURE SEMICONDUCTOR PACKAGE - A packaged semiconductor device may include a leadframe and a die carrier mounted to the leadframe. The die carrier is formed from an electrically and thermally conductive material. A die is mounted to a surface of the die carrier with die attach material having a melting point in excess of 240° C. A first electrical interconnect couples the die and the leadframe. A housing covers portions of the leadframe, die carrier, die and first electrical interconnect. | 2014-03-27 |
20140084433 | Semiconductor Device Having a Clip Contact - A semiconductor device comprises a carrier. Further, the semiconductor devices comprises a semiconductor chip comprising a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is arranged on the first main surface and the semiconductor chip is mounted on the carrier with the second main surface facing the carrier. Further, an encapsulation body embedding the semiconductor chip is provided. The semiconductor device further comprises a contact clip, wherein the contact clip is an integral part having a bond portion bonded to the first electrode and having a terminal portion forming an external terminal of the semiconductor device. | 2014-03-27 |
20140084434 | SEMICONDUCTOR DEVICE - A semiconductor device is reduced in size. The semiconductor device includes a die pad, a plurality of leads arranged around the die pad, a memory chip and a power source IC chip mounted over the die pad, a logic chip mounted over the memory chip, a plurality of down bonding wires for connecting the semiconductor chip to the die pad, a plurality of lead wires for connecting the semiconductor chip to leads, and a plurality of inter-chip wires. Further, the logic chip is arranged at the central part of the die pad in a plan view, and the power source IC chip is arranged in a corner part region of the die pad in the plan view. This reduces the size of the QFN. | 2014-03-27 |
20140084435 | RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A resin-encapsulated semiconductor device includes: a semiconductor element mounted on a die pad portion; a plurality of lead portions disposed so that distal end parts thereof are opposed to the die pad portion; a metal thin wire for connecting an electrode of the semiconductor element to the lead portion; and an encapsulating resin for partially encapsulating those components. A bottom surface part of the die pad portion, and a bottom surface part, an outer surface part, and an upper end part of the lead portion are exposed from the encapsulating resin. A plated layer is formed on the exposed lead bottom surface part and the exposed lead upper end part. | 2014-03-27 |
20140084436 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To enhance the reliability of connection between a semiconductor chip and a metal plate by ensuring sufficiently the thickness of a conductive material interposed between the semiconductor chip and the metal plate. A lead frame is arranged over a jig and a clip frame is arranged over protruding portions provided on the jig. In this state, a heating process (reflow) is performed. In this case, high melting point solders filling first spaces are melted in a state in which the first space is formed between a High-MOS chip and a High-MOS clip and the first space is formed between a Low-MOS chip and a Low-MOS clip. At this time, even when the high melting point solder is melted in the first space, the size (in particular, the height) of the first space does not change and the first space is maintained. | 2014-03-27 |
20140084437 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CHIP MOUNTED ON LEAD FRAME - A semiconductor device includes a lead frame, a semiconductor chip, a substrate, a plurality of chip parts, a plurality of wires, and a resin member. The lead frame includes a chip mounted section and a plurality of lead sections. The semiconductor chip is mounted on the chip mounted section. The substrate is mounted on the chip mounted section. The chip parts are mounted on the substrate. Each of the chip parts has a first end portion and a second end portion in one direction, and each of the chip parts has a first electrode at the first end portion and a second electrode at the second end portion. Each of the wires couples the second electrode of one of the chip parts and one of the lead sections. The resin member covers the lead frame, the semiconductor chip, the substrate, the chip parts, and the wires. | 2014-03-27 |
20140084438 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device has a plurality of electronic components mounted on an insulating substrate formed with a metal layer, and electrically connected to each other or to the metal layer; a positioning wire member having a predetermined diameter and a predetermined length, and bonded to each of the plurality of electronic components or to the metal layer; a lead frame disposed to bridge and electrically connect the plurality of electronic components to each other or between the metal layer and the electronic components; and an opening having a size capable of inserting the wire member therethrough formed to penetrate through the lead frame, to join the lead frame to each of the electronic components or the metal layer at a predetermined position therein. The lead frame is positioned on the insulating substrate by inserting the wire member into the opening. | 2014-03-27 |
20140084439 | SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a semiconductor chip mounted on the substrate, a plate-like member that is fixed on the semiconductor chip and has a thermal expansion coefficient different from that of the substrate, and a first adhesive that is provided between the substrate and the plate-like member, the first adhesive being connected to the plate-like member and separated from the substrate, or being separated from the plate-like member and connected to the substrate. | 2014-03-27 |
20140084440 | SEMICONDUCTOR DEVICE - In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package. | 2014-03-27 |
20140084441 | STACKED-DIE PACKAGE INCLUDING DIE IN PACKAGE SUBSTRATE - Some embodiments described herein include apparatuses and methods of forming such apparatuses. In one such embodiment, an apparatus may include a substrate, a first die, and a second die coupled to the first die and the substrate. The substrate may include an opening. At least a portion of the die may occupy at least a portion of the opening in the substrate. Other embodiments including additional apparatuses and methods are described. | 2014-03-27 |
20140084442 | Semiconductor Packages Having a Guide Wall and Related Systems and Methods - A semiconductor package includes a first package board, a first semiconductor chip arranged on the first package board, a heat transfer layer arranged on the first semiconductor chip, a heat spreader arranged on the heat transfer layer, and a housing having a molding part arranged on the first package board and directly surrounding side surfaces of the first semiconductor chip and a guide wall arranged on the molding part, with the guide wall spaced apart from the heat spreader and surrounding side surfaces of the heat spreader. | 2014-03-27 |
20140084443 | ASSEMBLY INCLUDING PLURAL THROUGH WAFER VIAS, METHOD OF COOLING THE ASSEMBLY AND METHOD OF FABRICATING THE ASSEMBLY - An assembly includes a chip including an integrated circuit, a casing including an integrated circuit including plural active elements and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. | 2014-03-27 |
20140084444 | Thermal Dissipation Through Seal Rings in 3DIC Structure - A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer. | 2014-03-27 |
20140084445 | Thermal Dissipation Through Seal Rings in 3DIC Structure - A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A heat spreader encircles the die and the interposer. A wire includes a first end bonded to one of the plurality of metal lines, and a second end bonded to the heat spreader. | 2014-03-27 |
20140084446 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICES WITH THE SAME - A semiconductor package includes a substrate, a ground circuit supported by the substrate, at least one semiconductor chip disposed on the substrate and a carbon-containing heat-dissipating part disposed on the substrate and electrically connected to the ground circuit. The heat-dissipating part may include carbon fibers and/or carbon cloth. | 2014-03-27 |
20140084447 | POWER MODULE PACKAGE - Disclosed herein is a power module package including: a body member having a polyhedral shape and made of a metal material; a semiconductor device mounted on the body member; and a block member formed at an edge region of the body member and made of a metal material. | 2014-03-27 |
20140084448 | ASSEMBLY INCLUDING PLURAL THROUGH WAFER VIAS, METHOD OF COOLING THE ASSEMBLY AND METHOD OF FABRICATING THE ASSEMBLY - An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. The card includes an upper card connected to the upper portion of the casing, and a lower card connected to the lower portion of the casing. The upper card includes one of a photosensor, light emitting element, radio frequency (RF) antenna, and radio frequency emitter. The lower card includes an area array input/output. | 2014-03-27 |
20140084449 | Semiconductor Housing with Rear-Side Structuring - A semiconductor housing includes a fixing mechanism and at least one side having structurings. A method for producing a semiconductor device is provided in which a thermally conductive paste is applied on the at least one side of the semiconductor housing and/or of a heat sink. The semiconductor housing is fixed to the heat sink by means of the fixing mechanism. A pressure is exerted on the thermally conductive paste by means of the fixing mechanism and the thermally conductive paste is diverted by means of diversion channels depending on the pressure exerted. | 2014-03-27 |
20140084450 | PROCESSES FOR MULTI-LAYER DEVICES UTILIZING LAYER TRANSFER - A method includes forming a release layer over a donor substrate. A plurality of devices made of a first semiconductor material are formed over the release layer. A first dielectric layer is formed over the plurality of devices such that all exposed surfaces of the plurality of devices are covered by the first dielectric layer. The plurality of devices are chemically attached to a receiving device made of a second semiconductor material different than the first semiconductor material, the receiving device having a receiving substrate attached to a surface of the receiving device opposite the plurality of devices. The release layer is etched to release the donor substrate from the plurality of devices. A second dielectric layer is applied over the plurality of devices and the receiving device to mechanically attach the plurality of devices to the receiving device. | 2014-03-27 |
20140084451 | Split Loop Cut Pattern For Spacer Process - A semiconductor fabrication technique cuts loops formed in a spacer pattern. The spacer pattern is a split loop pattern which generally includes a symmetric arrangement of one or more loops in each of four quadrants which are defines with respect to a reference point. The loops can be peaks or trenches. Each quadrant can include one loop, or multiple nested loops. Further, the space pattern includes a single cross, or multiple nested crosses, which extend between the loops. A cut out area is defined which extends outward from the reference point to closed ends of the loops, also encompassing a central portion of the cross. When a metal wiring layer pattern is formed using the spacer pattern with the cut out area, metal wiring is excluded from the cut out area. The loop ends in the metal wiring layer are broken and can be used as independent active lines. | 2014-03-27 |
20140084452 | ELEMENT MOUNTING BOARD AND SEMICONDUCTOR MODULE - Prepared in advance is a substrate formed of metallic material where slits are formed between mounting regions. Oxide films are generated all over the substrate including end faces of the substrate. Exposed are only lateral faces corresponding to the cross sections cut when tie bars are cut. This structure and the fabrication method minimize the area of cutting faces in the metallic material. | 2014-03-27 |
20140084453 | OVERCOMING CHIP WARPING TO ENHANCE WETTING OF SOLDER BUMPS AND FLIP CHIP ATTACHES IN A FLIP CHIP PACKAGE - Structures and methods for forming good electrical connections between an integrated circuit (IC) chip and a chip carrier of a flip chip package include forming one of: a tensile layer on a front side of the IC chip, which faces a tops surface of the chip carrier, and a compressive layer on the backside of the IC chip. Addition of one of: a tensile layer to the front side of the IC chip and a compressive layer the backside of the IC chip, may reduce or modulate warpage of the IC chip and enhance wetting of opposing solder surfaces of solder bumps on the IC chip and solder formed on flip chip (FC) attaches of a chip carrier during making of the flip chip package. | 2014-03-27 |
20140084454 | DIRECT MULTIPLE SUBSTRATE DIE ASSEMBLY - A direct multiple substrate die assembly can include a first and a second substrate, wherein each substrate can include at least one interlocking edge feature. An electrical interconnection area can be formed adjacent to or within the interlocking edge feature on each substrate and can be configured to couple one or more electrical signals between the substrates. In one embodiment, the interlocking edge feature can include one or more keying features that can enable accurate alignment between the substrates. In yet another embodiment, the direct multiple substrate die assembly can be mounted out of plane with respect to a supporting substrate. | 2014-03-27 |
20140084455 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes: a semiconductor substrate having opposite first and second surfaces; an adhesive layer formed on the first surface of the semiconductor substrate; at least a semiconductor chip disposed on the adhesive layer; an encapsulant formed on the adhesive layer for encapsulating the semiconductor chip; and a plurality of conductive posts penetrating the first and second surfaces of the semiconductor substrate and the adhesive layer and electrically connected to the semiconductor chip, thereby effectively reducing the fabrication cost, shortening the fabrication time and improving the product reliability. | 2014-03-27 |
20140084456 | SEMICONDUCTOR PACKAGES, METHODS OF MANUFACTURING SEMICONDUCTOR PACKAGES, AND SYSTEMS INCLUDING SEMICONDUCTOR PACKAGES - A semiconductor package comprises a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a third semiconductor chip on the second semiconductor chip and a fourth semiconductor chip on the third semiconductor chip. A first underfill layer is positioned between the second semiconductor chip and the first semiconductor chip; a second underfill layer is positioned between the third semiconductor chip and the second semiconductor chip, and a third underfill layer is positioned between the fourth semiconductor chip and the third semiconductor chip. In some embodiments, the second underfill layer comprises a material that is different than the first and third underfill layers. | 2014-03-27 |
20140084457 | BUMP STRUCTURES, ELECTRICAL CONNECTION STRUCTURES, AND METHODS OF FORMING THE SAME - A bump structure may include a body portion spaced apart from a pad disposed on a substrate and a first extension extending from a side of the body portion onto the pad. A second extension extends from another side of the body portion. | 2014-03-27 |
20140084458 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a substrate having a first surface and a second surface; a sensing layer disposed on the first surface of the substrate, wherein the sensing layer has a sensing region; a conducting pad structure disposed on the substrate and electrically connected to the sensing region; a spacer layer disposed on the first surface of the substrate; a semiconductor substrate placed on the spacer layer, wherein the semiconductor substrate, the spacer layer, and the substrate together surround a cavity on the sensing region; and a through-hole extending from a surface of the semiconductor substrate toward the substrate, wherein the through-hole connects to the cavity. | 2014-03-27 |
20140084459 | Multiple Die Packaging Interposer Structure and Method - System and method for providing a multiple die interposer structure. An embodiment comprises a plurality of interposer studs in a molded interposer, with a redirection layer on each side of the interposer. Additionally, the interposer studs may be initially attached to a conductive mounting plate by soldering or wirebond welding prior to molding the interposer, with the mounting plate etched to form one of the redirection layers. Integrated circuit dies may be attached to the redirection layers on each side of the interposer, and interlevel connection structures used to mount and electrically connect a top package having a third integrated circuit to the interposer assembly. | 2014-03-27 |
20140084460 | Contact bumps methods of making contact bumps - Contact bumps between a contact pad and a substrate can include recesses and protrusions that can mate with the material of the substrate. The irregular mating surfaces between the contact bumps and the contact pads can enhance the bonding strength of the contacts, for example, against shear and tension forces, especially for flexible systems such as smart cards. | 2014-03-27 |
20140084461 | FLUX MATERIALS FOR HEATED SOLDER PLACEMENT AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure are directed towards flux materials for heated solder placement and associated techniques and configurations. In one embodiment, a method includes depositing a flux material on one or more pads of a package substrate, the flux material including a rosin material and a thixotropic agent and depositing one or more solder balls on the flux material disposed on the one or more pads, wherein depositing the one or more solder balls on the flux material is performed at a temperature greater than 80° C., and wherein the rosin material and the thixotropic agent are configured to resist softening at the temperature greater than 80° C. Other embodiments may be described and/or claimed. | 2014-03-27 |
20140084462 | Wafer Level Semiconductor Package - There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process. | 2014-03-27 |
20140084463 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure is provided, including: a semiconductor chip having electrode pads disposed thereon and metal bumps disposed on the electrode pads; an encapsulant encapsulating the semiconductor chip; a dielectric layer formed on the encapsulant and having a plurality of patterned intaglios formed therein for exposing the metal bumps; a wiring layer formed in the patterned intaglios of the dielectric layer and electrically connected to the metal bumps; and a metal foil having a plurality of metal posts disposed on a surface thereof such that the metal foil is disposed on the encapsulant with the metal posts penetrating the encapsulant so as to extend to the inactive surface of the semiconductor chip. Compared with the prior art, the present invention reduces the overall thickness of the package structure, increases the electrical transmission efficiency and improves the heat dissipating effect. | 2014-03-27 |
20140084464 | Passivation Scheme - A method includes forming a passivation layer over an electrically conductive pad. A stress buffer layer is formed over the passivation layer. An opening is formed through the stress buffer layer over the electrically conductive pad wherein the opening does not reach the electrically conductive pad. The stress buffer layer is cured. The opening is extended through the passivation layer to reach the electrically conductive pad after the curing. | 2014-03-27 |
20140084465 | SYSTEM AND METHOD OF NOVEL MX TO MX-2 - A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer. | 2014-03-27 |
20140084466 | MANGANESE SILICATE FILM FORMING METHOD, PROCESSING SYSTEM, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - According to an embodiment of present disclosure a manganese silicate film forming method for forming a manganese silicate film by transforming metal manganese to silicate. The method includes forming a metal manganese film on a silicon-containing base by using a manganese compound gas; annealing the metal manganese film in an oxidizing atmosphere after the formation of the metal manganese film; and forming a manganese silicate film by annealing the metal manganese film in a reducing atmosphere after the annealing of the metal manganese film in the oxidizing atmosphere. | 2014-03-27 |
20140084467 | FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material. | 2014-03-27 |
20140084468 | SEMICONDUCTOR DEVICE CONNECTED BY ANISOTROPIC CONDUCTIVE FILM - A semiconductor device includes a first connecting member having a first electrode, a second connecting member having a second electrode, and an anisotropic conductive film between the first connecting member and the second connecting member, the anisotropic conductive film electrically connecting the first and second electrodes to each other. The anisotropic conductive film includes a polymer binder resin, an epoxy resin, conductive particles, and a curing agent. The epoxy resin includes a naphthalene ring-containing epoxy resin and a dicyclopentadiene ring-containing epoxy resin. The naphthalene ring-containing epoxy resin is included in an amount of 100 parts by weight to 500 parts by weight based on 100 parts by weight of the dicyclopentadiene ring-containing epoxy resin. | 2014-03-27 |
20140084469 | METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned dielectric layer with a plurality of openings is formed on the substrate. A barrier layer is deposited in the openings by a first tool and a sacrificing protection layer is deposited on the barrier layer by the first tool. The sacrificing layer is removed and a metal layer is deposited on the barrier layer by a second tool. | 2014-03-27 |
20140084470 | Seed Layer Structure and Method - A seed layer comprises a bottom seed layer portion formed on the bottom of a via opening, a sidewall seed layer portion formed on an upper portion of the sidewall of the via opening and a corner seed layer portion formed between the bottom seed layer portion and the sidewall seed layer portion. The sidewall seed layer portion is of a first thickness. The corner seed layer portion is of a second thickness and the second thickness is greater than the first thickness. | 2014-03-27 |
20140084471 | Interconnect Structures Comprising Flexible Buffer Layers - A structure includes a substrate, a low-k dielectric layer over the substrate, and a conductive barrier layer extending into the low-k dielectric layer. The conductive barrier layer includes a sidewall portion. A metal line in the low-k dielectric layer adjoins the conductive barrier layer. An organic buffer layer is between the sidewall portion of the conductive barrier layer and the low-k dielectric layer. | 2014-03-27 |
20140084472 | COMPOUND DIELECTRIC ANTI-COPPER-DIFFUSION BARRIER LAYER FOR COPPER CONNECTION AND MANUFACTURING METHOD THEREOF - The disclosure belongs to the field of manufacturing and interconnection of integrated circuits, and in particular relates to compound dielectric anti-copper-diffusion barrier layer for copper interconnection and a manufacturing method thereof The disclosure uses compound dielectric (oxide & metal) as the anti-copper-diffusion barrier layer. First, it can enhance the capable of metal for anti-copper-diffusion efficiently, and prevent the barrier layer for valid owing to oxidized and prolong the life of the barrier layer. Second, it can reduce the effective dielectric constant of the interconnection circuits and furthermore reduce the RC delay of the whole interconnection circuits. Besides, the alloy is firmly adhered to the copper, and the metal copper can be directly electroplated without growing a layer of seed crystal copper. The method is simple and feasible and is expected to be applied to manufacturing of the anti-copper-diffusion barrier layers for copper interconnections. | 2014-03-27 |
20140084473 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Provided are semiconductor devices and methods of fabricating the same. The device may include a substrate including a first surface and a second surface opposing each other, a through-silicon-via (TSV) electrode provided in a via hole that may be formed to penetrate the substrate, and an integrated circuit provided adjacent to the through electrode on the first surface. The through electrode includes a metal layer filling a portion of the via hole and an alloy layer filling a remaining portion of the via hole. The alloy layer contains at least two metallic elements, one of which may be the same as that contained in the metal layer, and the other of which may be different from that contained in the metal layer. | 2014-03-27 |
20140084474 | METHOD FOR FORMING A VERTICAL ELECTRICAL CONNECTION IN A LAYERED SEMICONDUCTOR STRUCTURE - The invention proposes a method for forming a vertical electrical connection ( | 2014-03-27 |
20140084475 | SEMICONDUCTOR PACKAGE SUBSTRATES HAVING PILLARS AND RELATED METHODS - The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern. | 2014-03-27 |
20140084476 | Thermal Dissipation Through Seal Rings in 3DIC Structure - A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via. | 2014-03-27 |
20140084477 | NOISE ATTENUATION WALL - An embodiment of an apparatus is disclosed. For this embodiment of the apparatus, an interposer has first vias. First interconnects and second interconnects respectively are coupled on opposite surfaces of the interposer. A first portion of the first interconnects and a second portion of the first interconnects are spaced apart from one another defining an isolation region between them. A substrate has second vias. Third interconnects and the second interconnects are respectively coupled on opposite surfaces of the package substrate. A first portion of the first vias and a first portion of the second vias are both in the isolation region and are coupled to one another with a first portion of the second interconnects. | 2014-03-27 |
20140084478 | MOLD CHASE FOR INTEGRATED CIRCUIT PACKAGE ASSEMBLY AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure are directed towards a mold chase for integrated circuit package assembly and associated techniques and configurations. In one embodiment, a method includes receiving a package substrate, the package substrate including a first die mounted on the package substrate by a plurality of first interconnect structures, and a plurality of second interconnect structures disposed on the package substrate and configured to route electrical signals of a second die, protecting a top surface of individual interconnect structures of the plurality of second interconnect structures from deposition of a mold material, and depositing the mold material on the package substrate between the individual interconnect structures of the plurality of second interconnect structures. Other embodiments may be described and/or claimed. | 2014-03-27 |
20140084479 | Integrated Circuit Formed Using Spacer-Like Copper Deposition - A method of forming a semiconductor device includes depositing a metal spacer over a core supported by a first extremely low-k dielectric layer having metal contacts embedded therein, etching away an upper portion of the metal spacer to expose the core between remaining lower portions of the metal spacer, removing the core from between the remaining lower portions of the metal spacer, and depositing a second extremely low-k dielectric layer over the remaining lower portions of the metal spacer. | 2014-03-27 |
20140084480 | SEMICONDUCTOR PACKAGE SUBSTRATES HAVING LAYERED CIRCUIT SEGMENTS AND RELATED METHODS - The package substrate includes a core, a plurality of first circuit segments, and a plurality of conductive pillars. Each of the first circuit segments has a patterned metal layer disposed on the core, a barrier layer disposed on the patterned metal layer, and an upper metal pattern disposed on the barrier layer. The conductive pillars penetrate the core, the patterned metal layer, and the barrier layer, and contact the upper metal pattern. The conductive pillars are formed from a material that can be selectively removed without affecting the barrier layer. | 2014-03-27 |
20140084481 | SYSTEM AND METHOD OF NOVEL ENCAPSULATED MULTI METAL BRANCH FOOT STRUCTURES FOR ADVANCED BACK END OF LINE - A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between metal tracks in the intermetal dielectric layers. | 2014-03-27 |
20140084482 | MICRO DEVICE STABILIZATION POST - A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface. | 2014-03-27 |
20140084483 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A package structure comprises a substrate, a plurality of first electronic components, at least a second electronic component, a first covering layer and a wiring layer. A surface of the substrate includes a first region and a second region. The first electronic components are disposed in the first region, wherein at least one of the first electronic components has a first conductive contact. The second electronic component is disposed in the second region. The first covering layer includes a recess and a first exposing region for exposing the first conductive contact. The wiring layer is formed on the recess and electronically coupled to the first conductive contact. | 2014-03-27 |
20140084484 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top surface of the interposer; a redistribution layer formed on the encapsulant and the top surface of the interposer; and at least a semiconductor element disposed on the redistribution layer. The top surface of the interposer is flush with a surface of the encapsulant so as for the redistribution layer to have a planar surface for disposing the semiconductor element, thereby preventing warpage of the interposer and improving the reliability of electrical connection between the redistribution layer and the semiconductor element. | 2014-03-27 |
20140084485 | RELIABLE PACKAGING AND INTERCONNECT STRUCTURES - Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure. | 2014-03-27 |
20140084486 | RELIABLE INTERCONNECT FOR SEMICONDUCTOR DEVICE - A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material. | 2014-03-27 |
20140084487 | PoP STRUCTURE WITH ELECTRICALLY INSULATING MATERIAL BETWEEN PACKAGES - A PoP (package-on-package) package includes a bottom package coupled to a top package. Terminals on the top of the bottom package are coupled to terminals on the bottom of the top package with an electrically insulating material located between the upper surface of the bottom package and the lower surface of the top package. The bottom package and the top package are coupled during a process that applies force to bring the packages together while heating the packages. | 2014-03-27 |
20140084488 | MULTI-CHIP SEMICONDUCTOR DEVICE - A multi-chip semiconductor device includes a plate-shaped first semiconductor chip having a first connection portion in which a first semiconductor chip electrode is formed on a first main surface of the first semiconductor chip or on a first side surface vertical to the first main surface, and a plate-shaped second semiconductor chip having a second connection portion in which a second semiconductor chip electrode is formed on a second side surface vertical to a second main surface of the second semiconductor chip. Each of the first and second connection portions includes at least an inclined surface that is inclined with respect to each of the first and second main surfaces. The first connection portion and the second connection portion are connected to each other such that the first main surface of the first semiconductor chip and the second main surface of the second semiconductor chip are vertical to each other. | 2014-03-27 |
20140084489 | ASSEMBLING THIN SILICON CHIPS ON A CONTACT LENS - A contact lens having a thin silicon chip integrated therein is provided along with methods for assembling the silicon chip within the contact lens. In an aspect, a method includes creating a plurality of lens contact pads on a lens substrate and creating a plurality of chip contact pads on a chip. The method further involves applying assembly bonding material to the each of the plurality of lens contact pads or chip contact pads, aligning the plurality of lens contact pads with the plurality of chip contact pads, bonding the chip to the lens substrate via the assembly bonding material using flip chip bonding, and forming a contact lens with the lens substrate. | 2014-03-27 |
20140084490 | DICING TAPE-INTEGRATED WAFER BACK SURFACE PROTECTIVE FILM - The present invention provides a dicing tape-integrated wafer back surface protective film including: a dicing tape including a base material and a pressure-sensitive adhesive layer formed on the base material; and a wafer back surface protective film formed on the pressure-sensitive adhesive layer of the dicing tape, in which the wafer back surface protective film is colored. It is preferable that the colored wafer back surface protective film has a laser marking ability. The dicing tape-integrated wafer back surface protective film can be suitably used for a flip chip-mounted semiconductor device. | 2014-03-27 |
20140084491 | METHOD FOR MANUFACTURING ELECTRONIC DEVICE AND ELECTRONIC DEVICE - A method for manufacturing an electronic device, the method includes: applying an adhesive film on a package board; placing an electronic component on the package board with a bump therebetween; applying a first load to the electronic component while heating the electronic component to a first temperature higher than a reaction start temperature of the adhesive film and lower than a melting point of the bump; reducing the first load to a second load lower than the first load while maintaining the first temperature; and heating the electronic component to a second temperature higher than or equal to the melting point of the bump while maintaining the second load. | 2014-03-27 |
20140084492 | FAN ASSEMBLY - A fan assembly includes a body housing an impeller and motor for driving to the impeller to generate an air flow. A nozzle is mounted on the body for emitting the air flow. The nozzle defines an opening through which air from outside the fan assembly is drawn by the air emitted from the nozzle. A nozzle retaining mechanism is provided for releasably retaining the nozzle on the body. The mechanism is moveable from a first configuration in which the nozzle is retained on the body to a second configuration in which the nozzle is released for removal from the body. The mechanism includes a depressible member for effecting movement of the mechanism from the first configuration to the second configuration. | 2014-03-27 |
20140084493 | SIMPLE STARTUP CARBURETOR - A carburetor improves the starting performance of an engine. The carburetor includes a main body, a pump oil ball and a fuel-air mixing channel which extends through the main body. The pump oil ball is mounted to an air strangler spindle via a spiral groove. When the pump oil ball is pressed, the air strangler spindle is driven to rotate by the spiral groove and thus to control the air strangler spindle between the fully open state and the fully closed state. The carburetor dramatically improves the starting performance of the engine. | 2014-03-27 |
20140084494 | VENTURI INSERT FOR A CARBURETOR, AND CARBURETOR, SYSTEM AND APPARATUS INCORPORATING THE SAME - A venturi insert for a carburetor, and a carburetor, system and apparatus incorporating the same. In one embodiment, the invention is a carburetor for an internal combustion engine comprising: a carburetor body comprising a plurality of throttle bores extending through the carburetor body, and for each of the throttle bores a fuel delivery passage terminating at a sidewall of the throttle bore; an insert comprising a plurality of venturi tubes and a linking member connecting the venturi tubes together, each of the venturi tubes comprising a venturi passage and a fuel port for introducing fuel into the venturi passage; and the insert secured to the carburetor body so that the venturi tubes extend into the throttle bores and the fuel ports are in fluid communication with the fuel delivery passages, and the linking member is in contact with the carburetor body. | 2014-03-27 |
20140084495 | CONVERTIBLE HUMIDIFIER - A convertible humidifier that includes a base portion that produces mist, a control panel that controls the production of the mist by the base portion, a reservoir, detachably connectable to the base portion, which holds water to be used by the base portion to produce the mist, and a nozzle configured to direct the mist. The reservoir includes a pass-through connection that allows the mist produced by the base portion to be directed to an opening on a top surface of the reservoir. The nozzle is detachably connected to the opening on the top surface in a first operation mode, and the nozzle is detachably connected to an extending portion, which is detachably connected to the opening on the top surface, in a second operation mode. | 2014-03-27 |
20140084496 | PACKING ELEMENT - An improved packing element configured to reduce or eliminate nesting between packing elements in a column. | 2014-03-27 |
20140084497 | THERMAL HUMIDIFIER - A thermal humidifier includes an upper housing provided with a steam outlet for conveying steam into a room and combined with a fundamental base having a PTC heating tube installed therein. A water-absorption member is mounted around the PTC heating tube and has a large portion soaked in a water box for absorbing liquid or water from the water box. The water-absorption member, after fully soaking up water, contacts with the PTC heating tube to enable the PTC heating tube to quickly heat the water of the water-absorption member to produce steam to be sent into a room through the steam outlet of the upper housing. | 2014-03-27 |
20140084498 | LENS WITH FILTER AND METHOD OF MANUFACTURING THEREOF - A method of forming an optical plastic lens includes prepare an molding material and thermal color-changeable or photo color-changeable material; the thermal color-changeable or photo color-changeable material is mixed into the molding material when the molding process is performed to allow the thermal color-changeable or photo color-changeable material exist in the plastic lens uniformly to change the color under photo change or thermal change. | 2014-03-27 |
20140084499 | SOLUTION OF AROMATIC POLYAMIDE FOR PRODUCING DISPLAY ELEMENT, OPTICAL ELEMENT, OR ILLUMINATION ELEMENT - The present disclosure is directed toward solutions, transparent films prepared from aromatic copolyamides, and a display element, an optical element or an illumination element using the solutions and/or the films. The copolyamides, which contain pendant carboxylic groups are solution cast into films using cresol, xylene, N,N-dimethylacetamide (DMAc), N-methyl-2-pyrrolidinone (NMP), dimethylsulfoxide (DMSO), or butyl cellosolve or other solvents or mixed solvent which has more than two solvents. When the films are thermally cured at temperatures near the copolymer glass transition temperature, after curing, the polymer films display transmittances >80% from 400 to 750 nm, have coefficients of thermal expansion of less than 20 ppm, and are solvent resistant. | 2014-03-27 |
20140084500 | MOLDING OF NONUNIFORM OBJECT HAVING UNDERCUT STRUCTURE - Various embodiments are disclosed herein that relate to the molding of an item having a non-uniform thickness and an undercut structure. One disclosed embodiment provides an injection molding device for molding a part having a non-uniform thickness and an undercut structure, the injection molding device comprising a pair of opposing end walls, a first mold surface being stationary with respect to the pair of opposing end walls, and a second mold surface being movable toward the first mold surface such that a first end of the second mold surface is movable a larger travel distance toward the first mold surface than a second end during a molding process. Further, the pair of opposing end walls comprises a slider with an undercut mold surface that is movable in a direction transverse to a direction in which the second mold surface is movable toward the first mold surface. | 2014-03-27 |
20140084501 | SYSTEM FOR FORMING AND MODIFYING LENSES AND LENSES FORMED THEREBY - A lens for placement in a human eye, such as intraocular lens, has at least some of its optical properties formed with a laser. The laser forms modified loci in the lens when the modified loci have a different refractive index than the refractive index of the material before modification. Different patterns of modified loci can provide selected dioptic power, toric adjustment, and/or aspheric adjustment provided. Preferably both the anterior and posterior surfaces of the lens are planar for ease of placement in the human eye. | 2014-03-27 |
20140084502 | METHOD FOR PRODUCING WAFER LENS, DEVICE FOR PRODUCING WAFER LENS, AND METHOD FOR PRODUCING OPTICAL ELEMENT - A purpose is to provide a method for producing a wafer lens and a device, capable of forming a wafer lens provided with a plurality of optical elements having intended properties. In order to adjust the gap between a molding die | 2014-03-27 |
20140084503 | FLAME SPRAY PYROLYSIS METHOD FOR FORMING NANOSCALE LITHIUM METAL PHOSPHATE POWDERS - A flame spray pyrolysis method for making nanoscale, lithium ion-conductive ceramic powders comprises providing a precursor solution comprising chemical precursors dissolved in an organic solvent, and spraying the precursor solution into an oxidizing flame to form a nanoscale, lithium ion-conductive ceramic powder, wherein a concentration of the chemical precursors in the solvent ranges from 1 to 20 M. The precursor solution can comprise 1-20% excess lithium with respect to a stoichiometric composition of the ceramic powder. Nominal compositions of the nanoscale, ceramic powders are Li | 2014-03-27 |
20140084504 | Process and Apparatus for Direct Crystallization of Polymers Under Inert Gas - An apparatus for continuous pelletization and crystallization of a polymer includes a unit for forming a polymer pellet material and cooling the pellet material in a liquid cooling medium. An after-connected drying unit has an exit opening for exporting gas and a crystallizer for crystallizing the pellet material. The crystallizer communicates via a connection line with the pre-connected unit for separating the liquid cooling medium from the pellet material and drying the pellet material. The crystallizer communicates with an inert gas tank, whereby the pressure in the crystallizer can be increased relative to the pressure in the drying unit. A related process is also disclosed. | 2014-03-27 |
20140084505 | BLENDED ALUMINAS TO CONTROL ALUMINUM TITANATE PROPERTIES - A method of making an aluminum titanate ceramic article including:
| 2014-03-27 |
20140084506 | MOULDING METHOD - The invention provides for a method of manufacturing a hollow article, which includes the step of introducing a polymeric composition that is settable into an article that has a shape-retaining property and at the same time a degree of flexibility which is yet insufficient to cause distortion of the article on the application of normal force. | 2014-03-27 |