12th week of 2012 patent applcation highlights part 60 |
Patent application number | Title | Published |
20120072717 | Dynamic identity authentication system - An authenticating device ( | 2012-03-22 |
20120072718 | System And Methods For Online Authentication - A method of establishing a communication channel between a network client and a computer server over a network is described. The network client may be configured to communicate with the computer server over the network and to communicate with a token manager. The token manager may be configured with a parent digital certificate that is associated with the token manager. The token manager or network client generates a credential from the parent digital certificate, and transmits the credential to the computer server. The credential may be associated with the computer server. The network client may establish the communications channel with the computer server in accordance with an outcome of a determination of validity of the credential by the computer server. | 2012-03-22 |
20120072719 | Method Enabling Real-Time Data Service, Realization, Real-Time Data Service System and Mobile Terminal - The present invention discloses a method for implementing a real-time data service, a real-time data service system and a mobile terminal. Said method for implementing a real-time data service includes the following steps: before encapsulating a Media Access Control Protocol Data Unit (MPDU), a Wireless Local Area Network Privacy Infrastructure (WPI) module in an Access Point (AP) needs to determine the type of the data to be encapsulated in the MPDU; if the data is a control signalling message of a real-time data service, the WPI module encrypts said data, then encapsulates the encrypted data in a data (e.g. PDU) field of the MPDU, and transmits the encapsulated data to the mobile terminal; if the data is an audio/video data message of a real-time data service, the data is not to be encrypted, but is encapsulated directly into the data (e.g. PDU) field of the MPDU in plaintext, and then transmitted to the mobile terminal. The present invention can reduce the processing load and the software and hardware costs of the AP and the mobile terminal. | 2012-03-22 |
20120072720 | Certificate Revocation - A communication system includes a plurality of nodes, the communication system being arranged to assign each of the plurality of nodes a certificate by means of which it can authenticate itself to other nodes in the communication system and periodically distribute to the plurality of nodes an update formed by compressing a data set representing the validity of the certificates assigned to the plurality of nodes. The update is such that a node may not be able to unambiguously determine from the update whether or not a particular certificate is valid. The system further provides the plurality of nodes with a source of information about the validity of the plurality of certificates that is different from the update and by means of which a node may resolve an ambiguity in the update regarding a particular certificate's validity. | 2012-03-22 |
20120072721 | Certificate Revocation - A communication system includes a plurality of nodes, the communication system being arranged to assign each of the plurality of nodes a certificate by means of which it can authenticate itself to other nodes in the communication system. The communication system further includes an authentication node arranged to determine that a certificate should be revoked and to, responsive to that determination, write an indicator of that certificate's revocation to a location in the communication system that is external to the authentication node and to which the node assigned the revoked certificate is not permitted to write. | 2012-03-22 |
20120072722 | SYSTEM AND METHOD OF PROTECTING DATA ON A COMMUNICATION DEVICE - A system and method of protecting data on a communication device are provided. Data received when the communication device is in a first operational state is encrypted using a first cryptographic key and algorithm. When the communication device is in a second operational state, received data is encrypted using a second cryptographic key and algorithm. Received data is stored on the communication device in encrypted form. | 2012-03-22 |
20120072723 | SYSTEMS AND METHODS FOR SECURE DATA SHARING - Systems and methods are provided for creating and using a sharable file-level key to secure data files. The sharable file-level key is generated based on a workgroup key associated with the data file, as well as unique information associated with the data file. The sharable file-level key may be used to encrypt and split data using a Secure Parser. Systems and methods are also provided for sharing data without replicating the data on the machine of the end user. Data is encrypted and split across an external/consumer network and an enterprise/producer network. Access to the data is provided using a computing image generated by a server in the enterprise/producer network and then distributed to end users of the external/consumer network. This computing image may include preloaded files that provide pointers to the data that was encrypted and split. No access or replication of the data on the enterprise/producer network is needed in order for a user of the external/consumer network to access the data. | 2012-03-22 |
20120072724 | COMPUTER PROGRAM AND METHOD FOR BIOMETRICALLY SECURED, TRANSPARENT ENCRYPTION AND DECRYPTION - A computer program for secure encryption and decryption provides a user interface that allows a user to drag and drop files into and out of a secure repository, wherein the program automatically encrypts files transferred into the repository and automatically decrypts files transferred out of the repository. The user can transfer file folders into the repository, wherein the program encrypts all of the files within the folder and retains the original file/folder structure, such that individual files can be moved within the repository, moved out of the repository, and opened or executed directly from the repository. The program requires the user to submit biometric data and grants access to the secure repository only if the biometric data is authenticated. The program generates an encryption key based at least in part on biometric data received from the user. Additionally, the program destroys the key after termination of each encryption/decryption session. | 2012-03-22 |
20120072725 | CLOUD-BASED APPLICATION WHITELISTING - Systems and methods for allowing authorized code to execute on a computer system are provided. According to one embodiment, an in-memory cache is maintained having entries containing execution authorization information regarding recently used modules. After verifying a module, its execution authorization information is added to the cache. Activity relating to a module is intercepted. A hash value of the module is generated. The module is verified with reference to a multi-level whitelist including a global whitelist, a local whitelist and the cache. The verification includes first consulting the cache and if the module is not found, then looking up its hash value in the local whitelist and if it is not found, then looking it up in the global whitelist. Finally, the module is allowed to be executed if the code module is approved by the multi-level whitelist database architecture. | 2012-03-22 |
20120072726 | DATA STORAGE AND REMOVAL - A system and method for data storage and removal includes providing databases and providing encryption keys. Each database is associated with a database time period and each encryption key is associated with an encryption time period. Data items are received and each data item is encrypted using the encryption key associated with the encryption time period that corresponds to a time associated with the data item. Each encrypted data item is stored in the database associated with the database time period that corresponds to the time associated with the data item. Each encryption key is deactivated at a predetermined time after the associated encryption time period ends. Each database is made irretrievable upon a determination that all of the encryption keys associated with the data items stored in that database have been deactivated. | 2012-03-22 |
20120072727 | MULTI-ISP CONTROLLED ACCESS TO IP NETWORKS, BASED ON THIRD-PARTY OPERATED UNTRUSTED ACCESS STATIONS - A mechanism that allows sharing of an existing infrastructure for access to public or private IP networks, such as the public Internet or private LANs is provided. Specifically, infrastructure owners lease the infrastructure resources on a short-term basis to different Internet Service Providers (ISPs). An ISP uses these resources to provide Internet services to subscribing customers or users. The ISP controls all aspects of the Internet service provided to the subscriber, including billing, bandwidth management, and e-mail. The ISP also ensures privacy for the subscriber by means of encryption. Leasing network resources from an existing network infrastructure frees the ISP from building an expensive access infrastructure itself while the infrastructure owner is given an opportunity to generate additional revenue from infrastructure. Importantly, neither the user, nor the ISP need to trust the access station (i.e.: the access station is untrusted) through which the access to the IP network is accomplished. | 2012-03-22 |
20120072728 | RETRIEVING AND USING CLOUD BASED STORAGE CREDENTIALS - The present invention extends to methods, systems, and computer program products for retrieving and using cloud based storage credentials. Embodiments of the invention include automatically retrieving cloud based credentials (e.g., storage keys) as needed, such as, for example, on demand. Automatically retrieving credentials reduces administrator workloads and mitigates the potential for human errors. Embodiments of the invention also include using credentials (e.g., storage keys) in the deployment and ongoing operation of services (e.g., computing workers) in a resource cloud. Embodiments of the invention also include propagating credentials (e.g., storage keys) to instances running in the cloud during deployment. | 2012-03-22 |
20120072729 | WATERMARK EXTRACTION AND CONTENT SCREENING IN A NETWORKED ENVIRONMENT - Methods, devices, and computer program products facilitate the application of a content use policy based on watermarks that are embedded in a content. Watermark extraction and content screening operations, which can include the application of content usage enforcement actions, may be organized such that some or all of the operations can be conducted at different times by different devices. The watermark extraction results can be stored in a secure location and accessed by other devices at different times. These operations can be conducted by one or more trusted devices that reside in a home network. The home network can also include a gateway device that can coordinate the operations of the various network devices and/or delegate the various watermark extraction and content screening operations. | 2012-03-22 |
20120072730 | CONTEXT ACCESS MANAGEMENT USING WATERMARK EXTRACTION INFORMATION - Methods, devices, and computer program products facilitate the application of a content use policy based on watermarks that are embedded in a content. Watermark extraction and content screening operations, which can include the application of content usage enforcement actions, may be organized such that some or all of the operations can be conducted at different times by different devices. These operations can be conducted by one or more trusted devices that reside in a networked environment. Real-time access to a content can also be facilitated by utilizing existing watermark extraction records. To facilitate real-time access to the content, the extraction records may contain segmented authentication information that correspond to particular segments of the content that is being accessed. Additionally, or alternatively, new watermark extraction operations can be conducted in real-time to produce new watermark extraction records. | 2012-03-22 |
20120072731 | SECURE AND EFFICIENT CONTENT SCREENING IN A NETWORKED ENVIRONMENT - Methods, devices, and computer program products facilitate the application of a content use policy based on watermarks that are embedded in a content. Watermark extraction and content screening operations, which can include the application of content usage enforcement actions, may be organized such that some or all of the operations can be conducted at different times by different devices. These operations can be conducted by one or more trusted devices that reside in a networked environment. The authenticity of various devices can be verified through the exchange of certificates that can further enable such devices to ascertain capabilities of one another. Based on the ascertained capabilities, an operational configuration for conducting watermark extraction and content screening can be determined. | 2012-03-22 |
20120072732 | CRYPTOGRAPHIC METHOD FOR ANONYMOUS AUTHENTICATION AND SEPARATE IDENTIFICATION OF A USER - The invention relates to cryptographic method for the anonymous authentication and the identification of a user entity (U | 2012-03-22 |
20120072733 | WEARABLE TIME-BRACKETED VIDEO AUTHENTICATION - A wearable video recording system with time-bracketed authentication is provided and includes a article, including a spine, wearable by a user, a recording device, supported on the spine, to generate a recording of a scene, an affecter subsystem, supported on the spine, to influence the scene being recorded with unpredictable data and an untrusted controller coupled to the recording device and the affecter subsystem, the untrusted controller being receptive of the unpredictable data, which the untrusted controller communicates to the affecter subsystem, and being configured to transmit at least hashed digests of the recording to one or more repositories. | 2012-03-22 |
20120072734 | PLATFORM FIRMWARE ARMORING TECHNOLOGY - A method, apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the method includes is a processor. The processor includes switching a platform firmware update mechanism located in a computer platform to a platform firmware armoring technology (PFAT) mode on a boot of the computer platform. The computer platform includes a platform firmware storage location that stores a platform firmware. The method then persistently locks the platform firmware storage location in response to the platform firmware update mechanism switching to the PFAT mode. When persistently locked, writes are only allowed to the platform firmware storage location by an Authenticated Code Module in the running platform and only after a platform firmware update mechanism unlocking procedure. | 2012-03-22 |
20120072735 | STORAGE DEVICE, PROTECTION METHOD, AND ELECTRONIC DEVICE - According to one embodiment, a storage device encrypts/decrypts data with an encryption key to write/read the data to/from the storage area. In the storage device, an elapsed time counter starts counting triggered by turning on of the storage device. A receiver receives a command containing a password and time information from a host device. The time information indicates current date and time. A calculator calculates elapsed time from last command input to current command input based on the time information and a counter value. An adder adds the elapsed time to time information contained in a command received last time. A time information determination module determines the consistency of the time information. A disabling module disables the encryption key if the time information is not consistent. An authentication module authenticates the password if the time information is consistent and allows access to the storage area if the password is successfully authenticated. | 2012-03-22 |
20120072736 | MEMORY DEVICE, MEMORY SYSTEM, AND AUTHENTICATION METHOD - According to one embodiment, a memory device includes a third partial key write module, an encryption key write module, and a decryption module. The third partial key write module is configured to combine a second partial key received from the current host device with the first partial key in the partial key memory device and to write a generated third partial key into the volatile memory after the device authentication. The encryption key write module is configured to combine the third partial key with the second user authentication information and to write a generated encryption key into the volatile memory after the user authentication. The decryption module is configured to decrypt the encrypted data based on the encryption key in the volatile memory based on a read request received from the current host device and to output obtained data to the current host device when the user authentication has succeeded. | 2012-03-22 |
20120072737 | SYSTEM FOR ESTABLISHING A CRYPTOGRAPHIC KEY DEPENDING ON A PHYSICAL SYSTEM - In systems for establishing a cryptographic key depending on a physical uncloneable function (PUF) it may be a problem that internal information correlated with the cryptographic key is leaked to the outside of the system via a side-channel. To mitigate this problem a cryptographic system for reproducibly establishing a cryptographic key is presented. The system comprises a physical system comprising a physical, at least partially random, configuration of components from which an initial bit-string is derived. An error corrector corrects deviations occurring in the initial bit-string. Through the use of randomization the error corrector operates on a randomized data. Information leaking through a side channel is thereby reduced. After error correction a cryptographic key may be derived from the initial bit-string. | 2012-03-22 |
20120072738 | REDUCING LATENCY WHEN ACTIVATING A POWER SUPPLY UNIT - A method for reducing latency using a charging module when activating a power supply unit (PSU) among a plurality of PSUs in a power supply system. The method includes: Receiving, by the PSU from a power input feed, input power; receiving, from a supply bus shared by the plurality of PSUs, a first controlled signal designating a status of the PSU as standby; disabling, in response to the first controlled signal, a switching regulator of the PSU; receiving, from a voltage rail of the supply bus, charge flowing through a resistor of the charging module to maintain a charge of an output capacitor of the switching regulator; receiving a second controlled signal designating the status of the PSU as active; enabling the switching regulator; outputting a voltage from the PSU through the charging module to the voltage rail; and charging the output capacitor using the PSU. | 2012-03-22 |
20120072739 | SHORT CIRCUIT CONTROL FOR HIGH CURRENT PULSE POWER SUPPLY - A power supply circuit apparatus, and method for controlling the same, includes multiple power supplies connected to a load via power channels and a controller. The controller detects a short circuit in the power supply based on a measured load input current. | 2012-03-22 |
20120072740 | Power Booting Sequence Control System and Control Method Thereof - The present invention discloses a power booting sequence control system and the control method thereof, which optimizes a power booting sequence of a plurality of power switches in an integrated circuit. An initial module initializes a target charge value, a preset current budget and a plurality of time intervals. A current lookup module obtains a booting current across a power switch from a built-in current lookup table. A first computing unit and a second computing unit compute a first and a second power switch numbers respectively. A processing module selects the small number of the first and the second power switch number to get a maximum number of power booting switches under the time intervals, and opens the maximum number of the power booting switches. Therefore, the system keeps the in-rush current value under the preset current budget and speeds up the ramp-up time in a power booting state. | 2012-03-22 |
20120072741 | COMPUTER SYSTEM, POWER SUPPLY APPARATUS AND CONTROL METHOD THEREOF - A computer system includes at least one device, a connector which is connected to a power supply apparatus which supplies power having a predetermined level to operate the computer system, a power unit which converts and provides the power supplied from the power supply apparatus to the at least one device, and a controller which analyzes a signal waveform of power supplied from the power supply apparatus and identifies information of the power supply apparatus carried by the signal waveform. Accordingly, an abnormal operation of the computer system can be prevented by transmitting power information such as a power capacity of the power supply apparatus to the computer system. | 2012-03-22 |
20120072742 | SYSTEM AND METHOD FOR TESTING WOL FUNCITON OF COMPUTERS - In a system and method for testing a wake-up on LAN (WOL) function of a computer, the computer connects to a server through a local area network (LAN). The system constructs a network connection between the server and the computer according to an Internet protocol (IP) address, a media access control (MAC) address and a name of the computer, and enables the computer in a wake-up mode when the server connects to the computer through the LAN. A wake-up command is generated for waking up a WOL function of the computer, the computer performs a WOL function test process according to the wake-up command. The sever detects a current status of the computer from a data packet when the data packet is received from the computer, and records the current status as a test result of the WOL function of the computer. | 2012-03-22 |
20120072743 | Hierarchical Power Management Circuit, Power Management Method Using the Same, and System on Chip Including the Hierarchical Power Management Circuit - A hierarchical power management circuit includes N power management circuits respectively included in N power domains each including at least one intellectual property (IP), wherein N is a natural number greater than one. The i-th (1 | 2012-03-22 |
20120072744 | SYSTEMS AND METHODS TO IMPROVE POWER EFFICIENCY IN HYBRID STORAGE CLUSTERS - Systems and methods for reducing power consumption and power leakage in hybrid storage clusters is provided. More specifically, the systems and methods for reducing power consumption select a particular cache (memory) technology in hybrid storage clusters based on performance requirements and/or other parameters associated with an application (file or process). The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The program instructions are operable to monitor access patterns of one or more applications in one or more memory technologies in a computing system. The program instructions are also operable to select a memory technology to store the one or more applications based on the access patterns of one or more applications. | 2012-03-22 |
20120072745 | SERVER POWER MANAGEMENT WITH AUTOMATICALLY-EXPIRING SERVER POWER ALLOCATIONS - One embodiment provides a power management method for servers in a data center. A group of servers is selected, and the total power allocated to a group of servers is limited to within a group power budget. A separate server power allocation is individually requested for each of a plurality of the servers. Within the constraints of the group power budget, the requested server power allocations are selectively granted for a specified magnitude and duration. The granted server power allocations are also selectively renewed, either automatically or upon request of the servers. Each server that has not received a renewed server power allocation from a group power management entity upon the expiration of the specified duration automatically reduces its own power consumption, such as by the server powering itself off. | 2012-03-22 |
20120072746 | FACILITATING POWER MANAGEMENT IN A MULTI-CORE PROCESSOR - The disclosed embodiments provide a system that facilitates power management in a multi-core processor. During operation, the system detects a change related to a number of active processor cores in the multi-core processor. (Within this system, a given processor core can reside in an active state, wherein the given processor core can draw an active power, or alternatively in a constrained state, wherein the given processor core can draw a constrained power, which is less than the active power.) In response to detecting the change, the system computes a new current limit I | 2012-03-22 |
20120072747 | IMAGE PROCESSING APPARATUS CAPABLE OF SHIFTING TO POWER SAVING MODE, CONTROL METHOD FOR THE IMAGE PROCESSING APPARATUS, AND PROGRAM - An image processing apparatus capable of shifting to a power saving mode. The image processing apparatus includes a storing unit configured to store a document in a storage device, a notification unit configured to periodically notify an apparatus of a predetermined destination of information about a document that has been newly stored by the storing unit into the storage device, and a control unit configured to restrict shifting to a power saving mode in which the notification unit cannot make the notification after storage of a document by the storing unit has been completed and until the notification unit notifies at least information about the document. | 2012-03-22 |
20120072748 | RADIO DEVICE - A method including configuring a processor to determine whether a radio device is communicating with an additional device, configuring the radio device to enter into a power stale in response to whether the radio device is communicating with the additional device, and modifying an amount of power supplied to the radio device in response to the power slate of the radio device. | 2012-03-22 |
20120072749 | MULTI-CORE POWER MANAGEMENT - The disclosed embodiments provide a system that operates a processor in a multi-core processor system. During operation, the system detects the creation of an asynchronous wakeup event for the processor. In response to detecting the creation of the asynchronous wakeup event, when the processor is subsequently placed into an idle state, the system configures the processor to resume operation at a reduced frequency that is a fraction of an operating frequency for the multi-core processor system, wherein the reduced frequency allows more power to be allocated to other processors in the multi-core processor system. | 2012-03-22 |
20120072750 | METHOD AND APPARATUS FOR A ZERO VOLTAGE PROCESSOR SLEEP STATE - Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory. | 2012-03-22 |
20120072751 | POWER CONSERVATION IN WIRELESS CLIENT TERMINALS AND SYSTEM LATENCY REDUCTION USING A PROXY DEVICE - A scheme is provided for conserving power in client terminals and/or reducing latency in wireless systems by using a proxy device. The client terminal may have a primary communication interface for communications with an access node and a secondary communication interface to communicate with the proxy device. The client terminal may indicate to the access node a short cycle rate for monitoring its signaling/control channel(s). The client terminal may the power off its primary communication interface without informing the access node. Prior to powering off its primary communication interface, the client terminal may assign the proxy device to act as its proxy and monitor the signaling/control channel with the access node. The proxy device monitors the signaling/control channel(s) according to the indicated short cycle rate. Upon detection of a message for the client terminal, the proxy device forwards the message to the client terminal via a secondary communication interface. | 2012-03-22 |
20120072752 | METHOD AND APPARATUS FOR PROVIDING POWER MANAGEMENT ENHANCEMENTS - A method and apparatus for providing power management enhancements. In an embodiment, the method comprises receiving an indication that the computing device is in a non-user-interactable state and powering down non-essential device components such that the computing device is configured to enter a low power state. In another embodiment, the method comprises selecting a duration for a battery life of the computing device and selecting a power profile for the computing device to ensure that the computing device operates for at least as long as the selected duration. In an embodiment, the apparatus comprises a computing device comprising means for providing battery power and means for altering a power profile of the computing device. | 2012-03-22 |
20120072753 | ELECTRONIC SYSTEM WITH ROUTER AND CHARGER FUNCTIONS, AND METHOD FOR OPERATING THE SAME - An electronic system with router and charger functions and a method for operating router and charger functions are disclosed. The electronic system connects to an electronic device and includes a router module, a charger module, and a connection interface. In which, the router module has a processing unit and a communication unit, and the charger module has a rechargeable battery. The processing unit and the communication unit may provide data routing capabilities so that the connected electronic device can share the Internet resources to other devices. At the same time, the rechargeable battery of the electronic system may provide electric power to the electronic device for charging the battery within. | 2012-03-22 |
20120072754 | METHOD FOR SYSTEM ENERGY USE MANAGEMENT OF CURRENT SHARED POWER SUPPLIES - A non-transitory computer readable storage medium having computer readable program code embodied therein, where the computer readable program code is adapted to, when executed by a processor, implement a method for managing a power supply system. The method includes identifying a number of power supplies included in the power supply system, and determining a first system mode for the power supply system. The method also includes determining a first operating order for the power supplies, and assigning a first ACTIVE ON threshold to each of the power supplies to obtain a number of first ACTIVE ON thresholds. The method further includes assigning a first ACTIVE STANDBY OFF threshold to each of the power supplies to obtain a number of first ACTIVE STANDBY OFF thresholds, where the power supply system provides electrical power to at least one computer system. | 2012-03-22 |
20120072755 | METHOD OF CONTROLLING OPERATION MODE OF STORAGE DEVICE, AND STORAGE DEVICE IMPLEMENTING THE STORAGE - A method and apparatus control an operation mode of a storage device, including determining, by the storage device, an external power connection state of a host device connected to the storage device; and determining the operation mode of the storage device according to the determined external power connection state. The operation mode is determined to be a first mode when external power is connected to the host device and the operation mode is determined to be a second mode when the external power is not connected to the host device, where power consumption in the second mode being smaller than power consumption in the first mode. | 2012-03-22 |
20120072756 | Power Management of Components Having Clock Processing Circuits - A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a clock signal. | 2012-03-22 |
20120072757 | Session Redundancy Using a Replay Model - A mechanism for synchronizing states of components in a first routing engine to corresponding components in a second routing engine is provided. In order to reduce the amount of data required to synchronize the state of the components and the time and resources required to perform the synchronization, the state-related information transmitted from the first routing engine to the second routing engine is limited to information used to build states of a subset of the components associated with the first routing engine. That subset of components is limited to those components that receive stimuli (e.g., data streams or data packets) from sources external to the routing engine. Other components on the second routing engine synchronize state by receiving information from those components on the second routing engine that received the external stimuli information. | 2012-03-22 |
20120072758 | ANALYSIS AND VISUALIZATION OF CLUSTER RESOURCE UTILIZATION - An analysis and visualization depicts how an application is leveraging processor cores of a distributed computing system, such as a computer cluster, in time. The analysis and visualization enables a developer to readily identify the degree of concurrency exploited by an application at runtime and the amount of overhead used by libraries or middleware. Information regarding processes or threads running on the nodes over time is received, analyzed, and presented to indicate portions of computer cluster that are used by the application, idle, other processes, and libraries in the system. The analysis and visualization can help a developer understand or confirm contention for or under-utilization of system resources for the application and libraries. | 2012-03-22 |
20120072759 | Timing Error Correction System and Method - A timing error correction method used at the transmitting end in high-speed serial data transmission system comprises inputting a predefined parallel data training sequence and a clock signal, converting the training sequence into serial data, counting the number of the rising or falling edges of the serial data within a certain period, sending an adjustment signal for adjusting the time delay of the clock signal, obtaining a reasonable serialization timing, so that the number of the rising edges or falling edges of the serial data being equal to a predefined correct number. The corresponding timing error correction system comprises a data path, an adjustable delay clock path, a serialization unit for converting the parallel data into serial data, a driver unit, and a counting judging unit for counting the number of the rising or falling edges of the serial data and sending an adjustment signal to the adjustable delay clock path so as to control the timing of the serialization unit. | 2012-03-22 |
20120072760 | TIMER, METHOD OF IMPLEMENTING SYSTEM TIME USING A TIMER, AND INTEGRATED CIRCUIT DEVICE INCLUDING THE SAME - A method of implementing a system time in an electronic device using a timer is disclosed. The method comprises storing a first count reset value in the electronic device; increasing a count value; comparing the first count reset value with the count value at a first particular time; resetting the count value when the count value is the same as the first count reset value at the first particular time; and generating an interrupt request signal when the count value is reset. | 2012-03-22 |
20120072761 | Device and method for implementing clock transparent transmission - The present invention discloses a device and method for implementing a transparent clock. The device comprises: a clock module, a data identification module and a data correction module, wherein the clock module is connected with the data identification module and the data correction module respectively, and used for providing clock information to the data identification module and the data correction module; the data identification module is used for receiving data and acquiring current time information from the clock module; and the data correction module is connected with the data identification module, and is used for accumulating a positive or negative value of the current time information with the time information included in the data according to an outputting direction of the data and outputting the accumulated time information together with the data. By adopting the present invention, the residence time information of the data in the switching node is acquired by a hardware device, and the time information included in the data is corrected according to the residence time information, so that the transparent clock of the data can be effectively implemented, and the acquired residence time information is of a high precision and is acquired stably. | 2012-03-22 |
20120072762 | METHODS AND SYSTEMS FOR DYNAMICALLY MANAGING REQUESTS FOR COMPUTING CAPACITY - Embodiments of systems and methods are described for dynamically managing requests for computing capacity from a provider of computing resources. Illustratively, the computing resources may include program execution capabilities, data storage or management capabilities, network bandwidth, etc. The systems or methods automatically allocate computing resources for execution of one or more programs associated with the user. The systems and methods may enable the user to make changes to the allocated resources after execution of the one or more programs has started. | 2012-03-22 |
20120072763 | SYSTEM AND METHOD OF FILE LOCKING IN A NETWORK FILE SYSTEM FEDERATED NAMESPACE - A method, system and apparatus of a file locking within a network file system federated namespace is disclosed. In one embodiment, a method includes accessing a target file in a storage medium over a network through an intermediate proxy server using a processor. The storage medium may be any one storage medium of a group of storage mediums on the network forming a data sharing cluster. In addition, the method includes locking the target file in the storage medium through a lock protocol to enable an access to modify the target file to at most one user at any given time, via the intermediate proxy server. | 2012-03-22 |
20120072764 | SYSTEMS AND METHODS FOR NETWORK INFORMATION COLLECTION - A network device may include logic configured to receive a problem report from a second network device, store and analyze data included in the problem report, filter data in the problem report to determine when the problem report is to be transmitted to a third network device, and transmit the problem report to the third network device when the filtering determines that the problem report is to be transmitted. | 2012-03-22 |
20120072765 | JOB MIGRATION IN RESPONSE TO LOSS OR DEGRADATION OF A SEMI-REDUNDANT COMPONENT - A computer program product and method of managing the workload in a computer system having one or more semi-redundant hardware components are provided. The method comprises detecting loss or degradation of the level of performance of one or more of the semi-redundant hardware components, identifying hardware components that are affected by the loss or degradation of the one or more semi-redundant components, migrating a critical job from an affected hardware component to an unaffected hardware component, and performing less-critical jobs on an affected hardware component. Loss or degradation of the semi-redundant component reduces the capacity of affected hardware components in the computer system without entirely disabling the computer system. Jobs identified as being critical are run on hardware components having the most capacity and reliability, while allowing less-critical jobs to make use of the remaining capacity of affected hardware components. Optionally, the semi-redundant hardware component may be selected from a memory module, CPU core, Ethernet port, power supply, fan, disk drive, and an input output port. | 2012-03-22 |
20120072766 | FAULT HANDLING SYSTEMS AND METHODS - Systems and methods for fault handling are presented. In one embodiment, a fault handling method includes: performing an error type detection process including determining if an error is a media error or a connectivity error; performing a detachment determination process to establish an appropriate detachment scenario, wherein the appropriate detachment scenario includes not detaching any mirrors if the connectivity error involves all mirrors; and returning an application write with a failure. In one embodiment, the detachment determination process detaches a mirror in accordance with results of a read-write-back process. In one exemplary implementation, the detachment determination process includes a connectivity status inquiry and mirrors are detached in accordance with results of the connectivity status inquiry. In one exemplary implementation, the connectivity status inquiry includes a SCSI connectivity inquiry. In one embodiment, consistency and synchronization is maintained between the mirrors by utilizing a read-write-back operation. | 2012-03-22 |
20120072767 | RECOVERY OF FAILED DISKS IN AN ARRAY OF DISKS - A disk recovery system and method is provided for recovering data from a redundant array of independent (or inexpensive) disks. The method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The computer readable storage medium is operable to: determine input/output (I/O) characteristics of one or more disks in an array; monitor the one or more disks in the array to determine when any of the one or more of the disks have failed in the array; and automatically rebuild the failed disk from a standby pool by nominating a disk in the standby pool based on the I/O characteristics of the one or more failed disks prior to failure. | 2012-03-22 |
20120072768 | DYNAMIC PHYSICAL MEMORY REPLACEMENT THROUGH ADDRESS SWAPPING - An apparatus, system, method, and machine-readable medium are disclosed. In one embodiment the apparatus includes an address swap cache. The apparatus also includes memory segment swap logic that is capable of detecting a reproducible fault at a first address targeting a memory segment. Once detected, the logic remaps the first address targeting the faulty memory segment with a second address targeting another memory segment. The logic stores the two addresses in an entry in the address swap cache. Then the memory segment swap logic receives a memory transaction that is targeting the first physical address and use the address to perform a lookup process in the address swap cache to determine if an entry exists that has the faulty address. If an entry does exist for that address, the logic then swaps the second address into the memory transaction for the first address. | 2012-03-22 |
20120072769 | REPAIR-POLICY REFINEMENT IN DISTRIBUTED SYSTEMS - In a distributed system a plurality of devices (including computing units, storage and communication units) are monitored by an automated repair service that uses sensors and performs one or more repair actions on computing devices that are found to fail according to repair policies. The repair actions include automated repair actions and non-automated repair actions. The health of the computing devices is recorded in the form of states along with the repair actions that were performed on the computing devices and the times at which the repair actions were performed, and events generated by both sensors and the devices themselves. After some period of the time, the history of states of each device, the events, and the repair actions performed on the computing devices are analyzed to determine the effectiveness of the repair actions. A statistical analysis is performed based on the cost of each repair action and the determined effectiveness of each repair action, and one or more of the policies may be adjusted, as well as determining from the signals and events from the sensors whether the sensors themselves require adjustment | 2012-03-22 |
20120072770 | Data Corruption Diagnostic Engine - A computer is programmed to execute a diagnostic procedure either on a pre-set schedule or asynchronously in response to an event, such as an error message, or a user command. When executed, the diagnostic procedure automatically checks for integrity of one or more portions of data in the computer, to identify any failure(s). In some embodiments, the failure(s) may be displayed to a human, after revalidation to exclude any failure that no longer exists. | 2012-03-22 |
20120072771 | Fast, Non-Write-Cycle-Limited Persistent Memory for Secure Containers - Techniques for providing fast, non-write-cycle-limited persistent memory within secure containers, while maintaining the security of the secure containers, are described herein. The secure containers may reside within respective computing devices (e.g., desktop computers, laptop computers, etc.) and may include both volatile storage (e.g., Random Access Memory (RAM), etc.) and non-volatile storage (NVRAM, etc.). In addition, the secure containers may couple to auxiliary power supplies that are located externally thereto and that power the secure containers at least temporarily in the event of a power failure. These auxiliary power supplies may be implemented as short-term power sources, such as capacitors, batteries, or any other suitable power supplies. | 2012-03-22 |
20120072772 | METHOD FOR DETECTING A FAILURE IN A SAS/SATA TOPOLOGY - A method for detecting a failure in a serial topology. The method may comprise sending a predetermined pattern to a plurality of devices communicatively connected to an initiator in a serial topology; receiving a return result from each of the plurality of devices in response to the predetermined pattern; recognizing a problem associated with a particular device among the plurality of devices, the problem being recognized based on the return result from the particular device; sending a plurality of test patterns to the particular device; receiving a plurality of test results from the particular device in response to the plurality of test patterns; and determining a cause of the problem based on the plurality of test results, the cause of the problem being at least one of: a cable failure and a device failure. | 2012-03-22 |
20120072773 | Panel Driving Circuit That Generates Panel Test Pattern and Panel Test Method Thereof - A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device. | 2012-03-22 |
20120072774 | Test Program Set Obsolescence Mitigation Through Software and Automatic Test Equipment Processes - Electronic test system including hardware and software components and method of use which provide obsolescence mitigation. A test program set (TPS) including a test program test is created to enable units to be tested. When a new component is introduced, the change is detected and a new TPS is created with at least part of the test program test. If the new TPS complies with defined, governing rules for the system, testing using the new TPS is possible. If not, a determination is made as to whether any component of the TPS is obsolete and if not, the units can be tested using the new TPS without redefining the rules. When a component of the TPS is obsolete, the rules are reviewed to ascertain the effect of removal of the component and optionally redefined to enable the new component to be used in combination with the remaining components. | 2012-03-22 |
20120072775 | METHOD OF COLLECTING INFORMATION IN SYSTEM NETWORK - To quickly establish an inferring result when a problem is detected in an operation management system equipped with a rule-based inference processing function, there is provided a method of collecting information for managing a computer system equipped with a plurality of devices. The computer system holds rule for associating a plurality of events with a conclusion output when all of the plurality of events have been detected. The method includes: executing, at a first interval, polling to obtain information indicating whether each of the plurality of events has been detected; judging whether the plurality of events have been detected; and executing, upon judgment that at least one of the plurality of events has been detected and none of the remaining events have been detected, before execution of next polling at the first interval, polling to obtain information indicating whether at least one of the undetected remaining events has been detected. | 2012-03-22 |
20120072776 | FAULT ISOLATION USING CODE PATHS - Techniques are provided for isolating faults in a software program by providing at least two code paths that are capable of performing the same operation. When a fault occurs while the one of the code paths is being used to perform an operation, data that indicates the circumstances under which the fault occurred is stored. For example, a fault-recording mechanism may store data that indicates the entities that were involved in the failed operation. Because they were involved in an operation that experienced a fault, one or more of those entities may be “quarantined”. When subsequent requests arrive to perform the operation, a check may be performed to determine whether the requested operation involves any of the quarantined entities. If the requested operation involves a quarantined entity, a different code path is used to perform the operation, rather than the code path from which the entity is quarantined. | 2012-03-22 |
20120072777 | DEBUGGING DEVICE, DEBUGGING METHOD, AND COMPUTER PROGRAM FOR SEQUENCE PROGRAM - To provide a debugging device for a sequence program that provides a debugging environment in which debugging of a sequence program can be executed easily and efficiently. A range setting unit that sets a skipping range to be skipped when a sequence program is executed; an extracting unit that extracts an output contact that is included in the skipping range, and that outputs a value to another range; and a value setting unit that sets a value to the extracted output contact are included. | 2012-03-22 |
20120072778 | DIAGNOSIS SYSTEM FOR REMOVABLE MEDIA DRIVE - Systems and methods are provided for performing diagnostics on a removable media drive. An example system includes a monitoring unit configured to collect information about a media access to the media drive and a media access to a removable media contained in the media drive. The example system also includes a storage unit having a threshold table with at least one threshold value for the media access to the media drive. A processing unit is configured to compare the collected information of the monitoring unit to the at least one threshold value contained in the threshold table. The processing unit is also configured to determine diagnostic data relating to the removable media drive in accordance with the comparison. | 2012-03-22 |
20120072779 | MEMORY LEAK MONITORING DEVICE AND METHOD FOR MONITORING MEMORY LEAK - The memory leak monitoring device for monitoring a memory leak occurring by an executed program reserving a memory area, the memory leak monitoring device comprising a retention period acquisition unit that acquires a retention period of each program indicating an elapsed time after a memory area used by the program is reserved, and a detection unit that detects a program in which a memory leak may occur by comparing the acquired retention period with a reference time. | 2012-03-22 |
20120072780 | Continuous System Health Indicator For Managing Computer System Alerts - A method is provided for detecting when users are being adversely impacted by poor system performance. A system health indicator is determined that is based on the amount of work that is blocked waiting for each of a set of an external events and combined with a heuristic that is based on the number of users waiting for the work to complete. The system health indicator is compared to a threshold such that an alert is generated when the system health indicator crosses the threshold. However, the system health indicator is designed so that an alert is only generated when a significant user base is or will in the near future experience a problem with the system. Furthermore, the system health indicator is designed to vary smoothly to maintain its suitability for the application of predictive technology. | 2012-03-22 |
20120072781 | PREDICTIVE INCIDENT MANAGEMENT - An incident predictor system is described herein for predicting impactful incidents in which server computer system operations fail or perform poorly. According to one embodiment of the invention, the incident prediction system trains a generalized linear model (GLM) to predict when a system health indicator will reach a level that represents an incident for the server system. | 2012-03-22 |
20120072782 | CORRELATION OF NETWORK ALARM MESSAGES BASED ON ALARM TIME - Problems in a network may be diagnosed based on alarm messages received from devices in the network and based on logical circuit path information of the network. In one implementation, a device may log alarm messages, in which each of the logged alarm messages may identify a network device that generated the alarm message and each of the alarm messages are associated with a time value. The device may group the alarm messages in the log of alarm messages based on the time values of the alarm messages to obtain one or more alarm message clusters and analyze the alarm message clusters to locate potential causes of the logged alarm messages. | 2012-03-22 |
20120072783 | MECHANISM FOR FACILITATING EFFICIENT ERROR HANDLING IN A NETWORK ENVIRONMENT - In accordance with embodiments, there are provided methods and systems for facilitating efficient error handling in a network environment. A method of embodiments includes receiving a validation request having configuration parameters of error dialogs relating to errors, and validating the configuration parameters and the errors. The validating includes mapping each error with a corresponding dialog. The method further includes transmitting a validating report having results of validation of the configuration parameters and the errors. The validation report is used to assign an order to each error and its corresponding dialog. | 2012-03-22 |
20120072784 | CIRCUITRY ON AN INTEGRATED CIRCUIT FOR PERFORMING OR FACILITATING OSCILLOSCOPE, JITTER, AND/OR BIT-ERROR-RATE TESTER OPERATIONS - An integrated circuit (“IC”) may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc. | 2012-03-22 |
20120072785 | BIT ERROR RATE CHECKER RECEIVING SERIAL DATA SIGNAL FROM AN EYE VIEWER - An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate. | 2012-03-22 |
20120072786 | USE OF HASHING FUNCTION TO DISTINGUISH RANDOM AND REPEAT ERRORS IN A MEMORY SYSTEM - One embodiment provides an error detection method wherein single-bit errors in a memory module are detected and identified as being a random error or a repeat error. Each identified random error and each identified repeat error occurring in a time interval is counted. An alert is generated in response to a number of identified random errors reaching a random-error threshold or a number of identified repeat errors reaching a repeat-error threshold during the predefined interval. The repeat-error threshold is set lower than the random-error threshold. A hashing process may be applied to the memory address of each detected error to map the location of the error in the memory system to a corresponding location in an electronic table. | 2012-03-22 |
20120072787 | Memory Controller with Loopback Test Interface - In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect. | 2012-03-22 |
20120072788 | INTEGRATED CIRCUIT WITH MEMORY BUILT-IN SELF TEST (MBIST) CIRCUITRY HAVING ENHANCED FEATURES AND METHODS - Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage. | 2012-03-22 |
20120072789 | MEMORY BUILT-IN SELF TEST (MBIST) CIRCUITRY CONFIGURED TO FACILITATE PRODUCTION OF PRE-STRESSED INTEGRATED CIRCUITS AND METHODS - Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, MBST circuitry is used set memory elements of arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage. Preferably, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. | 2012-03-22 |
20120072790 | On-Chip Memory Testing - An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware. The wrapper circuit is configured to provide an access port to the memory array. A test controller is formed on the substrate and coupled in parallel with the access wrapper circuit to the address and data lines of the memory array and to the control lines of the dedicated support hardware, wherein the test controller is operable to perform a test of the memory array by manipulating control signals to the support hardware in addition to those required to write data patterns into the memory array and to read the contents of the memory array. | 2012-03-22 |
20120072791 | Debugger Based Memory Dump Using Built in Self Test - A method and apparatus for performing a memory dump. The method includes providing a memory location from a debugger to a memory array through a BIST wrapper, and receiving data by the debugger read from the memory location in the memory array. The method can include sending a dump enable signal from the debugger, and the BIST wrapper selectively providing the memory location to the memory array in response to the dump enable signal. The method can include sending the dump enable signal to a multiplexer coupled to a register in the BIST wrapper, the dump enable signal causing the multiplexer to load the register with the memory location. The method can include asynchronously sending a write disable signal to the memory array before reading the data from the memory location. The received data can be selected from a larger set of data read from the memory location. | 2012-03-22 |
20120072792 | MEMORY TESTER AND COMPILER WHICH MATCHES A TEST PROGRAM - According to one embodiment, a memory tester is provided. The memory tester has first and second operation registers, a first selector, and first and second burst address generating circuits. The first operation register stores a first operation variable. The second operation register stores a second operation variable. The first selector outputs the first and second operation variables stored in the first and second operation registers selectively, as a burst address operation variable, based on a selection signal. The first and second burst address generating circuits are capable of generating first and second burst address signals based on the first and second operation variables outputted from the first selector, respectively. | 2012-03-22 |
20120072793 | Registers with Full Scan Capability - A scan test of a first latch and a second latch couples a given scan value to the input of the first latch, to switch the first latch to a state corresponding to the scan value, uncouples the scan value from the first latch to latch the first latch at that state, couples the output of the first latch while latched at that state to the input of the second latch to switch the second latch to that state, and uncoupling the output of the first latch from the input of the second latch to latch the second latch at that state. | 2012-03-22 |
20120072794 | NON-VOLATILE MEMORY (NVM) WITH IMMINENT ERROR PREDICTION - A method and system are provided for determining an imminent failure of a non-volatile memory array. The method includes: performing a first array integrity read of the memory array until an error is detected; determining that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage; performing a second array integrity read of the memory array until all bits of the memory array indicate a predetermined state, wherein a second word line voltage associated with all of the bits indicating the predetermined state is a second threshold voltage; and comparing a difference between the first and second threshold voltages to a predetermined value. | 2012-03-22 |
20120072795 | SEMICONDUCTOR MEMORY DEVICE AND CONTROLLING METHOD - According to one embodiment, a semiconductor memory device includes a plurality of semiconductor memory chips configured to store therein information depending on an amount of accumulated charge; a plurality of parameter storage units that are provided in correspondence with the semiconductor memory chips, each of the plurality of parameter storage units being configured to store therein a parameter that defines an electrical characteristic of a signal used for writing information into or reading information from a corresponding one of the semiconductor memory chips; an error correction encoding unit configured to generate a first correction code capable of correcting an error in the information stored in a number of semiconductor memory chips no greater than a predetermined number out of the semiconductor memory chips, from the information stored in the semiconductor memory chips; and a parameter processing unit configured to change the parameters respectively corresponding to the number of semiconductor memory chips no greater than the predetermined number, and writes the parameters changed into the parameter storage units, respectively. | 2012-03-22 |
20120072796 | MEMORY CONTROLLER WITH AUTOMATIC ERROR DETECTION AND CORRECTION - A memory validation manager reserves a block of time for exclusive accesses to a memory bank having lines of memory for which validation codes provide a degree of error detection and correction for each memory line. The memory validation manager reads, processes, and corrects at least some of the contents of each memory line based on indications of validity encountered for each memory line. New data is written in response to a validation code. Likewise, a valid field for each line can be updated and a new validation code written for a memory when the valid field indicates that a validation code has not yet been written for a memory line. The memory validation manager processes data read from a first memory line while either reading or writing to another memory line to minimize the latency of the process of scrubbing memory lines. | 2012-03-22 |
20120072797 | DESIGN-FOR-TEST TECHNIQUE TO REDUCE TEST VOLUME INCLUDING A CLOCK GATE CONTROLLER - Clock control circuitry for an integrated circuit, a method of testing an integrated circuit having a clock gate, an integrated circuit and a library of cells including the clock control circuitry are provided. In one embodiment, the integrated circuit includes: (1) a clock gate configured to apply a clock signal to at least a first scan chain of the integrated circuit, (2) combinational logic coupled to an input of the clock gate and (3) Design-for-Test logic located external to the combinational logic and coupled to the clock gate and a first cell of a second scan chain of the integrated circuit, the Design-for-Test logic configured to control operation of the clock gate based on a logic value of the first cell. | 2012-03-22 |
20120072798 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a NAND flash memory, an error correction unit, and a table. The NAND flash memory is configured to hold data. The error correction unit detects and corrects errors in the data. The table holds information on an error correction method associated with each piece of data. The error correction unit selects an error correction method to be applied for each piece of data in accordance with the information in the table. | 2012-03-22 |
20120072799 | DATA TRANSMISSION DEVICE, DATA RECEPTON DEVICE, AND TRANSMISSION METHOD - The present invention provides a data transmission system that reduces the number of data transitions on signal lines in data transmission via parallel buses between devices such as memory interfaces and liquid crystal interfaces, and can realize a lower power consumption and lower EMI noise. A data transmission device ( | 2012-03-22 |
20120072800 | TECHNIQUES FOR SUCCESSIVE REFINEMENT OF METRICS STORED FOR HARQ COMBINING - An embodiment of the present invention provides a method of efficiently storing metrics for Hybrid Automatic Retransmission Request (HARQ) combining and enabling saving of memory buffer in communication systems, comprising using non-linear quantization of the metrics and managing an aggregated buffer for all HARQ channels. | 2012-03-22 |
20120072801 | DATA PROCESSING APPARATUS, CONTROL DEVICE AND DATA STORAGE DEVICE - When write data D is high rewritten data, a PC | 2012-03-22 |
20120072802 | CHANNEL ESTIMATION IN ADAPTIVE MODULATION SYSTEMS | 2012-03-22 |
20120072803 | SEMICONDUCTOR STORAGE DEVICE, MEMORY CONTROL DEVICE, AND CONTROL METHOD OF SEMICONDUCTOR MEMORY - According to one embodiment, a semiconductor storage device includes a semiconductor memory which includes two or more cell peripheral circuits and two or more storage cells at least one of reading and writing of which is controlled by the cell peripheral circuits in each of the cell peripheral circuits. Further, the semiconductor storage device includes a memory control unit configured to instruct to form 1 symbol as a unit for creating an error correction code by the data held by the storage cells controlled by the same cell peripheral circuit and creating an error correction code to the symbol created base of the instruction. | 2012-03-22 |
20120072804 | DATA READ-OUT CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA READING IN SEMICONDUCTOR MEMORY DEVICE - A data read-out circuit is provided with a sense amplifier circuit and a selector. The sense amplifier circuit senses a stored data stored in a memory cell array by using a plurality of reference levels to generate a plurality of read data, respectively. Thus, the sense amplifier circuit outputs the plurality of read data with regard to the stored data. The selector selects a data corresponding to any one of the plurality of read data based on a control signal and outputs the selected data as an output data. | 2012-03-22 |
20120072805 | MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD THEREOF FOR GENERATING LOG LIKELIHOOD RATIO - A memory storage device, a memory controller, and a log likelihood ratio (LLR) generation method are provided. A read data corresponding to a first storage state is obtained from memory cells of a flash memory chip in the memory storage device by using bit data read voltages. An error checking and correcting procedure is performed on the read data to obtain a second storage state corresponding to the read data when the read data is written. An amount of storage error is obtained in storage states satisfying a statistic number, and a storage error means that data is in the second storage state when being written and is in the first storage state when being read. A logarithmic operation is executed according to the statistic number, an amount of the storage states, and the amount of storage error to generate a first LLR of the read data. | 2012-03-22 |
20120072806 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory including an array of memory cells. A buffer comprises latches to hold data from the memory cells. The latches constitute latch groups. The latches of each latch group are connected to corresponding one common line through a transfer circuit. An error corrector is connected to the common lines and detects an error bit in received data. A data transfer controller causes the buffer to read out data from memory cells to be verified, repeats reading out of all data in the latches in one latch group to corresponding one of common lines as to-be-verified data segment for different latch groups, and transfers the to-be-verified data segments to the error corrector. A verify controller causes the error corrector to determine whether an error bit is included in to-be-verified data includes the to-be-verified data segments. | 2012-03-22 |
20120072807 | ACCESSING METADATA WITH AN EXTERNAL HOST - Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the external host and/or at least a portion of the metadata may be modified based on the analysis. Modified metadata may be transmitted from the external host to a memory controller of the host. | 2012-03-22 |
20120072808 | SYSTEM AND METHOD FOR IMPROVING SIGNALING CHANNEL ROBUSTNESS - A system and method for improving signaling channel robustness. Additional error correction is provided for (L1) dynamic signaling that is carried in P2 symbols in such way that high time diversity can be provided. In other embodiments, transmitted services are scheduled such that services will rotate or “move” between frames, thereby ensuring that a first slot for a service is not always transmitted in the same frequency. | 2012-03-22 |
20120072809 | DECODER, METHOD OF OPERATING THE SAME, AND APPARATUSES INCLUDING THE SAME - A decoder, a method of decoding and systems implementing the same are disclosed. In one example, the method includes calculating syndrome values from input codewords, generating an error location polynomial about the codewords using the syndrome values, determining an error count in the codewords using the error location polynomial, and adjusting power consumption of a circuit in response to the determined error count in the codewords. In one example, a frequency of a clock signal to be provided to a search circuit may be determined based on the error count, and the clock signal may be provided having the determined frequency to a search circuit, such as a Chien search circuit. | 2012-03-22 |
20120072810 | ERROR CORRECTION CIRCUIT AND METHOD, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE CIRCUIT - An error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit are provided. The error correction circuit includes a partial syndrome generator, first and second error position detectors, a coefficient calculator, and a determiner. The partial syndrome generator calculates at least two partial syndromes using coded data. The first error position detector calculates a first error position using a part of the partial syndromes. The coefficient calculator calculates coefficients of an error position equation using the at least two partial syndromes. The determiner determines an error type based on the coefficients. The second error position detector optionally calculates a second error position based on the error type. | 2012-03-22 |
20120072811 | CONTROLLER, STORAGE APPARATUS, AND COMPUTER PROGRAM PRODUCT - According to one embodiment, a controller controls writing into and reading from a storage apparatus that includes a first data-storage unit and a second data-storage unit. The second data-storage unit stores user data and parity data of the user data. The first data-storage unit stores the parity data. The controller includes a parity updating unit and a parity writing unit. When parity data is updated, the parity updating unit writes the updated parity data into the first data-storage unit. When a certain requirement is satisfied, the parity writing unit reads the parity data written in the first data-storage unit, and writes the parity data thus read into the second data-storage unit. | 2012-03-22 |
20120072812 | DISTRIBUTED CHECKSUM COMPUTATION - Data is divided into parts and each part provided to a different processor. Each processor processes the provided data part to produce a partial CRC result. The partial CRC results from each of the different processors are XORed to produce a CRC of the data. | 2012-03-22 |
20120072813 | METHOD AND SYSTEM FOR DISPLAYING A WEB PAGE ADVERTISEMENT - Presented is a method of displaying a web page advertisement on a computing device. A web page advertisement is segregated from content on the web page during a web browsing session. The web page advertisement is then cached on the computing device for display at a time later to the web browsing session. | 2012-03-22 |
20120072814 | POINT OF NEED ACCESS TO AN ELECTRONIC MAINTENANCE MANUAL UTILIZING CURRENT MACHINE STATUS - A method and system for providing point of need diagnostic information in an electronic service manual. A rendering device can be configured to transmit machine diagnostics related reports to a computer. The diagnostics are then integrated into an electronic service manual. In this way a reference can be created which includes point of need diagnostic information related to the machine, thereby increasing the productivity of user time spent on maintenance activities associated with the machine. | 2012-03-22 |
20120072815 | METHOD FOR INTEGRATING REALLY SIMPLE SYNDICATION DOCUMENTS - A method for integrating Really Simple Syndication (RSS) documents includes extracting a data element set from an item of an RSS document and data elements contained in the data element set through a tag processing procedure; establishing a menu pool for displaying the content of the data element set and the content of the data elements; executing an editor to compose and edit the selected data element set and data elements, so as to combine the selected data element set and ata elements into a new item; and outputting the new item as a target output document. Through the method, the content of various RSS documents is integrated into a customized Hypertext Markup Language (HTML) or RSS document meeting the requirements of a user. | 2012-03-22 |
20120072816 | WEB LINK ASSOCIATION METHOD AND SYSTEM - A link association method and system. The method includes receiving by a computer processor from a user, a first link for a first Webpage and a second link for a second Webpage. The user determines that the first Webpage is related to the second Webpage. The computer processor receives a specification command indicating that the first Webpage is related to the second Webpage and in response the computer processor associates the first link with the second link. The computer processor stores the first link associated with the second link and generates a report indicating that the first link is related to the second link. | 2012-03-22 |