12th week of 2012 patent applcation highlights part 59 |
Patent application number | Title | Published |
20120072617 | Electronic Device, Control Method for an Electronic Device, and Recording Medium Storing a Program Executed by a Control Unit that Controls the Electronic Device - An electronic device that connects to external devices through a plurality of interfaces can operate efficiently according to the type of interface connected to the external device. An electronic device has a plurality of interfaces that can connect to a host computer; an external device interface that is connected to an external device; and an output unit that outputs data for external output received from the host computer to the external device interface. The output unit can form a plurality of output channels that output the data for external output received from the host computer to the external device interface. | 2012-03-22 |
20120072618 | MEMORY SYSTEM HAVING HIGH DATA TRANSFER EFFICIENCY AND HOST CONTROLLER - According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor. | 2012-03-22 |
20120072619 | Memory Overcommit by Using an Emulated IOMMU in a Computer System with a Host IOMMU - A method and system for managing direct memory access (DMA) in a computer system that hosts virtual machines and allows memory overcommit. The computer receives an indication that a bus address is to be used by a device to perform DMA to a buffer. In response to the indication, the computer determines a host device identifier for the device, and pins a memory page addressed by a host address that is associated with the bus address and a guest address. The computer also records, in a host I/O memory management unit (IOMMU), a mapping of the bus address and the host device identifier to the host address. After the device completes the DMA, the computer removes the mapping from the host IOMMU to prevent further direct access to the host address. | 2012-03-22 |
20120072620 | TERMINAL AND WIRELESS COMMUNICATION METHOD THEREOF - There are provided a terminal capable of selecting a suitable wireless module among a plurality of wireless modules depending on a situation and providing an optimal image even in a state in which a display unit is separated from a main body by performing wireless communication, and a wireless communication method thereof. To enable this, the terminal includes a main body generating and transmitting image data in response to an external input; a display unit mountable on or demountable from the main body, receiving the image data from the main body and displaying an image corresponding to the image data; and a wireless communication unit provided in each of the main body and the display unit, switching a wireless communication frequency band on the basis of a transmission rate of the image data and transmitting the image data to the display unit. | 2012-03-22 |
20120072621 | DYNAMIC BALANCING OF IO RESOURCES ON NUMA PLATFORMS - A method for binding input/output (I/O) objects to nodes. The method includes receiving, by an I/O Subsystem, a request to use an I/O device from a process, determining a first resource to service the request, and generating a first I/O object corresponding to the first resource. The method includes sending the first I/O object to a NUMA I/O Framework, obtaining a first I/O object effective load from the first I/O object, and obtaining a first I/O load capacity of a first NUMA node of a plurality of NUMA nodes. The method includes comparing the first I/O load capacity and the first I/O object effective load, selecting the first NUMA node based on a determination that the first I/O load capacity is greater than the first I/O object effective load, binding the first I/O object to the first NUMA node, and processing the first resource corresponding to the first I/O object. | 2012-03-22 |
20120072622 | USING PROCESS LOCATION TO BIND IO RESOURCES ON NUMA ARCHITECTURES - In general, in one aspect, the invention relates to a method for binding input/output (I/O) objects to nodes. The method includes receiving a request to use an I/O device from a process, determining a resource to service the request, generating a first I/O object corresponding to the resource, wherein the first I/O object is unbound, and generating a proc object, wherein the proc object comprises a reference to the process requesting to use the I/O device. The method also includes sending the first I/O object and the proc object to a Non-Uniform Memory Access (NUMA) I/O Framework, determining that the process is executing on a first NUMA node, selecting the first NUMA, binding the first I/O object to the first NUMA node, and servicing the request by processing, on the first NUMA node, the resource corresponding to the first I/O object. | 2012-03-22 |
20120072623 | Storage control device and raid group extension method - The storage system includes a first storage subsystem having a first logical volume to be accessed by a host computer, and a second storage subsystem connected to the first storage subsystem and having a second logical volume to be mapped to the first logical volume. The first storage subsystem includes a memory having definition information for defining a plurality of logical paths that transfer, to the second logical volume, I/O from the host computer to the first logical volume, and a transfer mode of the I/O to the plurality of logical paths. At least two or more logical paths among the plurality of logical paths are defined as active, and the controller transfers the I/O to the at least two or more logical paths set as active. | 2012-03-22 |
20120072624 | NUMA I/O FRAMEWORK - A method for binding input/output (I/O) objects to nodes includes an subsystem receiving a request to use an I/O device from a process, determining a first resource to service the request, generating a first I/O object corresponding to the first resource, wherein the first I/O object is unbound, and sending the first I/O object to a Non-Uniform Memory Access (NUMA) I/O Framework. The method further includes the NUMA I/O Framework selecting a first NUMA node of a plurality of NUMA nodes, to which to bind the first I/O object and binding the first I/O object to the first NUMA node. The method further includes servicing the request by processing, on the first NUMA node, the first resource corresponding to the first I/O object. | 2012-03-22 |
20120072625 | DATA PROCESSING APPARATUS CAPABLE OF COMMUNICATING WITH EXTERNAL DEVICE VIA A PLURALITY OF LOGICAL LINE, DATA PROCESSING SYSTEM, DATA PROCESSING DEVICE STORING DATA PROCESSING PROGRAM, AND DEVICE DRIVER - A data processing apparatus includes a data processing unit, a communication unit communicating with an external device via at least two logical lines including a first logical line and a second logical line having priority higher than the first logical line, a storage unit including a first buffer area storing data received by the communication unit via the first logical line and a second buffer area storing data received by the communication unit via the second logical line, and a control unit determining if the second buffer area stores data. According to determination that the second buffer area stores data, the control unit reads data from the second buffer area and controls the data processing unit to process the data read from the second buffer area, and according to determination that the second buffer area stores no data, the control unit determines if the first buffer area stores data. | 2012-03-22 |
20120072626 | Automatic Addressing Protocol for a Shared Bus - An automatic addressing protocol for a shared bus is described. In an embodiment, devices connected in a chain by a shared bus are also connected by an independent electrical connection between each pair of neighboring devices. A protocol is used over the independent electrical connections which is independent of that used on the shared bus. Devices in the chain receive at least one device ID from an upstream neighbor via the independent electrical connection and either use this received ID as their ID or use the received ID to compute their ID. Where the device has a downstream neighbor, a device then transmits at least one device ID to the downstream neighbor via the independent electrical connection and this transmitted ID may be their ID or an ID generated based on their ID, for example, by incrementing the ID by one. The process is repeated by devices along the chain. | 2012-03-22 |
20120072627 | DYNAMIC CREATION AND DESTRUCTION OF IO RESOURCES BASED ON ACTUAL LOAD AND RESOURCE AVAILABILITY - A method for binding input/output (I/O) objects to nodes. The method includes binding an I/O object group to a NUMA node of a plurality of NUMA nodes on a system, obtaining an I/O object group size of the I/O object group, and determining an I/O object group target size based on an I/O object group aggregate load of the I/O object group. The method further includes comparing, by the NUMA I/O Framework, the I/O object group target size and the I/O object group aggregate load, determining, by the NUMA I/O Framework, that a difference between the I/O object group target size and the I/O object group aggregate load exceeds a threshold, and instructing, by the NUMA I/O Framework, an I/O Subsystem associated with the I/O object group to change the I/O object group size, wherein the I/O Subsystem changes, in response to the instruction, the I/O object group size. | 2012-03-22 |
20120072628 | REMOTE MULTIPLEXING DEVICES ON A SERIAL PERIPHERAL INTERFACE BUS - A serial peripheral interface (SPI) bus and method of communicating over an SPI bus to multiple slave devices without requiring the master device to have an independent slave select pin for each slave device. The SPI bus comprises an SPI master device coupled to an SPI multiplex slave device and a plurality of SPI non-multiplex slave devices. The SPI multiplex slave device includes an independent slave select (SS) output pin coupled to each one of the SPI non-multiplex slave devices for sending an activation signal to a selected SPI slave device in response to receiving a command from the master device containing identification of the selected SPI slave device. | 2012-03-22 |
20120072629 | COMMUNICATION SYSTEM, MASTER DEVICE AND SLAVE DEVICE, AND COMMUNICATION METHOD - A communication system includes a master device and slave devices. Each slave device includes a request signal generation part configured to, when data to transmit is generated, generate a request signal indicating a transmission request to a master device; and a transmission part configured to transmit the request signal to the master device. The master device includes a request signal reception part configured to receive the request signals from the slave devices; a selection part acting configured to select one of the slave devices according to the request signals received by the reception part; a transmission part configured to transmit a signal indicating to allow data transmission to the slave device selected by the selection part; and a data reception part configured to receive data from the selected slave device. | 2012-03-22 |
20120072630 | TIME AND EVENT BASED MESSAGE TRANSMISSION - A system, apparatus and method for efficient utilization of available band-width on the system's bus connection. The system includes a scheduler configured to receive a virtual schedule that provides at least one slot for sending a message over the communication bus and to confirm a trigger condition. A module is configured to send a message over the communication bus when the trigger condition is confirmed. | 2012-03-22 |
20120072631 | Multilayer Arbitration for Access to Multiple Destinations - An arbiter is provided for arbitrating for access to a shared resource by a plurality of requesters and by a background requester in a processing system. A priority value is assigned to each of the plurality of requestors. A multilayer arbitration contest is performed to resolve each conflict in transaction requests to the shared resource, however, a requester of the plurality of requesters having a highest priority value does not always win an arbitration contest. An arbitration contest will be overridden whenever the background requester initiates a transaction request, such that the background requester always wins the overridden arbitration contest. The shared resource is accessed by the winner of each arbitration contest. | 2012-03-22 |
20120072632 | Deterministic and non-Deterministic Execution in One Processor - An application in a data processing system may automatically select when it needs determinism and when it does not. The ability to have the system automatically select when to use each allows optimum system performance while maintaining hard real-time requirements when needed. | 2012-03-22 |
20120072633 | Hot Plug Process in a Distributed Interconnect Bus - A distributed PCIe adapted to support a hot-plug process triggered by any change in a status of a distributed link, comprises an upstream bus unit including a first bridge connected to a root component and adapted to maintain a first configuration space and a copy of a second configuration space, the first configuration space bridge includes at least hot-plug registers specifying at least capabilities and status of a slot of the first bridge; and a second bridge connected to an endpoint component and adapted to maintain the second configuration space, the second configuration space includes at least hot-plug registers specifying at least capabilities and status of a slot of the second bridge. | 2012-03-22 |
20120072634 | FULLY INTEGRATED, LOW AREA UNIVERSAL SERIAL BUS DEVICE TRANSCEIVER - A transceiver apparatus includes a process, a first type of transceiver circuit for data transmission, a second type of transceiver circuit for data transmission, and a communications interface for communicating between the first type of transceiver circuit and an external device. The first type of transceiver circuit is co-located with a physical layer associated with the first type of transceiver circuit. In some embodiments, the first type of transceiver circuit can be, for example, a USB 2.0 transceiver circuit, and the second type of transceiver circuit can be a USB 3.0 transceiver circuit. The aforementioned external device can be an external USB device. | 2012-03-22 |
20120072635 | RELAY DEVICE - A relay device includes: an input buffer for receiving data units, each of which includes a header, to which multiple pieces of destination information have been added, and data associated with the header; multiple virtual channels for storing data units, each of the multiple virtual channels storing a data unit in accordance with the destination information; a destination comparing section for determining the order of allocation of virtual channels at a relay device on the receiving end with respect to the data units that are stored on the multiple virtual channels by seeing if their destinations are the same; and an output section for outputting the stored data units preferentially through one of the virtual channels that has already allocated at the relay device on the receiving end. | 2012-03-22 |
20120072636 | POWER-OPTIMIZED FRAME SYNCHRONIZATION FOR MULTIPLE USB CONTROLLERS WITH NON-UNIFORM FRAME RATES - A method, apparatus, and system to synchronize multiple host controllers with non-uniform frame rates. The apparatus includes a first host controller, a second host controller, and logic. The first host controller is configured to access memory at a first frame rate. The second host controller is configured to access the memory at a second frame rate which is different from the first frame rate. The logic is coupled to the first and second host controllers to synchronize the memory accesses of the first and second host controllers at a common frame rate. Other embodiments are described. | 2012-03-22 |
20120072637 | I/O BRIDGE DEVICE, RESPONSE-REPORTING METHOD, AND PROGRAM - An I/O bridge device includes: a command receiver that receives a command signal indicating a command to a memory controller from a peripheral component; a converter that converts the command signal into a command packet including the command and identification information for identifying the command signal; a command transmitter that transmits the command packet to the memory controller; a response receiver that receives, from the memory controller, a response packet to the command packet, the response packet including the identification information; and a write command transmitter that transmits a write command signal to the peripheral component that is a transmission source of the command signal, the write command signal indicating a command for the writing a content of the response packet to an internal memory of the peripheral component. | 2012-03-22 |
20120072638 | SINGLE STEP PROCESSING OF MEMORY MAPPED ACCESSES IN A HYPERVISOR - Trapping and/or processing of read/write accesses to hardware devices represented to the host through a memory mapped space may be performed without knowledge of the processor's instruction set or semantics of the processor's instructions. A single step routine may be executed to recognize page faults occurring from read/write accesses to emulated memory pages and causing the guest to retry the operation on a single step buffer. The hypervisor may perform post-operation processing on the single step buffer after the guest retries and completes the read or write access. For example, on a read request, the single step routine may place the guest value in the single step buffer for reading by the guest on a retry operation. On a write request, the single step routine may direct the guest to retry the write operation into the single step buffer. After the retry operation the single step routine may read the guest value from the single step buffer and place the guest value in a register of an appropriate emulated system. | 2012-03-22 |
20120072639 | Selection of Units for Garbage Collection in Flash Memory - A data structure is formed that references a garbage collection metric for each of a plurality of associated garbage collection units of a flash memory device. Each garbage collection metric is based on one or more device state characteristics of the associated garbage collection unit. In response to a threshold change in the one or more device state variables, a region of interest within the data structure is sorted based on the garbage collection metrics. One or more garbage collection units are selected for garbage collection operations from the sorted region of interest. | 2012-03-22 |
20120072640 | TRANSFERRING LEARNING METADATA BETWEEN STORAGE SERVERS HAVING CLUSTERS VIA COPY SERVICES OPERATIONS ON A SHARED VIRTUAL LOGICAL UNIT THAT STORES THE LEARNING METADATA - A virtual logical unit that stores learning metadata is allocated in a first storage server having a first plurality of clusters, wherein the learning metadata indicates a type of storage device in which selected data of the first plurality of clusters of the first storage server are stored. A copy services command is received to copy the selected data from the first storage server to a second storage server having a second plurality of clusters. The virtual logical unit that stores the learning metadata is copied, from the first storage server to the second storage server, via the copy services command. Selected logical units corresponding to the selected data are copied from the first storage server to the second storage server, and the learning metadata is used to place the selected data in the type of storage device indicated by the learning metadata. | 2012-03-22 |
20120072641 | SEMICONDUCTOR STORAGE DEVICE AND DATA CONTROL METHOD THEREOF - The flash memory controller compresses data in response to a write request. On condition that there is a compression effect with respect to the compressed data, the flash memory controller writes the compressed data to the base area of a physical block of a flash memory. As physical pages assigned to the physical block, the flash memory controller reduces the physical pages assigned to the base area from 102 down to 59, and increases the physical pages assigned to the update area from 26 up to 69. Therefore, it is possible to suppress exhaustion of physical pages which are assigned to the update area, to reduce the number of erases of the physical block, and to consequently prolong device operating life. | 2012-03-22 |
20120072642 | STORAGE APPARATUS AND CONTROL METHOD OF STORAGE APPARATUS - Storage drives of a plurality of types are mounted on a storage device together. A storage apparatus includes: an I/O controller that receives an access request sent from an information apparatus and writes data to or reads data from a storage drive; a storage drive mounting unit in which the storage drive is detachably mounted; a drive power supplying unit that supplies drive power to the storage drive mounted in the storage drive mounting unit; and a drive voltage identifying unit that identifies a voltage allowing data write to or data read from the storage drive mounted in the storage drive mounting unit, by raising a drive voltage applied to the storage drive from a voltage below a rated drive voltage of the storage drive. When the I/O controller writes data to or reads data from the storage drive, the drive power supplying unit applies the identified voltage to the storage drive to drive the storage drive. | 2012-03-22 |
20120072643 | METHOD OF MANAGING DATA IN A PORTABLE ELECTRONIC DEVICE HAVING A PLURALITY OF CONTROLLERS - The invention is a method of managing data in a portable electronic device comprising first and second controllers. The first controller comprises a first microprocessor and a first non volatile memory. The first microprocessor comprises a first piece of code. The second controller comprises a second microprocessor and a second non volatile memory. The second non volatile memory comprises a first executable data. The method comprises the following steps of: a) loading and activating the first piece of code in the first microprocessor, b) sending by the first controller a first request for retrieving the first executable data from the second non volatile memory, c) loading the first executable data into the first controller, and d) executing the first executable data by the first microprocessor. | 2012-03-22 |
20120072644 | SEMICONDUCTOR MEMORY CONTROLLING DEVICE - According to one embodiment, upon request from an information processor, a semiconductor storage controller writes pieces of data in predetermined units into storage locations in which no data has been written in erased areas within a semiconductor chip's storage area. A third table and a second table which is a subset thereof include physical addresses each indicating a storage location of each of pieces of the data within the semiconductor chip. The first table includes either information specifying a second table entry or information specifying a third table entry. The semiconductor storage controller records the first and the second tables into a volatile memory or records the first table into a volatile memory and the third table into a nonvolatile memory. | 2012-03-22 |
20120072645 | NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a nonvolatile semiconductor memory includes a memory cell array with a block including word lines, and each word line connected to memory cells, a controller which controls a data erase of the memory cells in the block, and a verify circuit which verifies whether or not the data erase is completed. The controller comprises being executed a verification by the verify circuit after being executed a first block erase in a predetermined condition, being executed a second block erase continuously when the number of memory cells which are judged by the verification as a completion of the data erase is n (n is a natural number) or less, and being executed a page erase continuously when the number of memory cells which are judged by the verification as a completion of the data erase is more than n. | 2012-03-22 |
20120072646 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING MEMORY - According to one embodiment, a semiconductor integrated circuit device includes a non-volatile memory, a storing module, and a processing module. The non-volatile memory is having a first area and a second area. The storing module is configured to store a second program for downloading a first program from an outside to the first area. The processing module is configured to execute the first and the second programs. The non-volatile memory is having a first area and a second area. The storing module is configured to store a second program for downloading a first program from an outside to the first area. The processing module is configured to execute the first and the second programs. The first area is capable of being written and erased by the first program, and the second area is not capable of being erased by the first program. | 2012-03-22 |
20120072647 | Different types of memory integrated in one chip by using a novel protocol - A semiconductor chip contains four different memory types, EEPROM, NAND Flash, NOR Flash and SRAM, and a plurality of major serial/parallel interfaces such as I | 2012-03-22 |
20120072648 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device in accordance with an embodiment includes: a memory cell array having electrically rewritable nonvolatile memory cells; and a control unit. The control unit performs control of repeating a write operation, a write verify operation, and a step-up operation, the write verify operation being an operation to verify whether data write is completed or not, and the step-up operation being an operation to raise the write pulse voltage if data write is not completed. The control unit, during the write operation, raises a first write pulse voltage with a first gradient, and then raises a second write pulse voltage with a second gradient, thereby executing the write operation, the first write pulse voltage including at least a write pulse voltage generated at first, the second write pulse voltage being generated after the first write pulse voltage, and the second gradient being larger than the first gradient. | 2012-03-22 |
20120072649 | NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device. | 2012-03-22 |
20120072650 | MEMORY SYSTEM AND DRAM CONTROLLER - According to one embodiment, a DRAM controller includes a clock generating and switching unit for supplying a first clock to a DRAM in a normal operation and generating a second clock having a lower speed than the first clock and supplying the generated second clock to the DRAM in an initialization processing, and a DRAM access circuit having a DLL circuit for regulating a fetch timing of data output from the DRAM based on the first clock, and fetching, in a fetch timing regulated by the DLL circuit, data output from the DRAM in a timing based on the second clock in relation to the initialization processing and the transfer data output from the DRAM in a timing based on the first clock in the initialization processing and the normal processing, respectively. | 2012-03-22 |
20120072651 | MEMORY CONTROLLER INTERFACE - A memory controller interface, mobile device and method are provided. The memory controller interface can allow a processor designed and configured to operate with NOR flash and static random access memory SRAM devices to instead operate using NAND flash and synchronous dynamic random access memory SDRAM. The system accomplishes this by caching sectors out of NAND flash into SDRAM, where the data can be randomly accessed by the processor as though it were accessing data from NOR flash/SRAM. Sectors containing data required by the processor are read out of NAND flash and written into SDRAM, where the data can be randomly accessed by the processor. Boot code is stored in memory accessible to the processor and is read out of the memory for execution. The boot code is scanned for a predetermined signature, and if the predetermined signature is found, a portion of the memory is write-protected. | 2012-03-22 |
20120072652 | MULTI-LEVEL BUFFER POOL EXTENSIONS - A buffer manager that manages blocks of memory amongst multiple levels of buffer pools. For instance, there may be a first level buffer pool for blocks in first level memory, and a second level buffer pool for blocks in second level memory. The first level buffer pool evicts blocks to the second level buffer pool if the blocks are not used above a first threshold level. The second level buffer pool evicts blocks to a yet lower level if they have not used above a second threshold level. The first level memory may be dynamic random access memory, whereas the second level memory may be storage class memory, such as a solid state disk. By using such a storage class memory, the working block set of the buffer manager may be increased without resorting to lower efficiency random block access from yet lower level memory such as disk. | 2012-03-22 |
20120072653 | MEMORY DEVICE WITH USER CONFIGURABLE DENSITY/PERFORMANCE - The memory device is comprised of a memory array having a plurality of memory cells that are organized into memory blocks. Each memory cell is capable of storing a selectable quantity of data bits (e.g., multiple level cells or a single bit per cell). Control circuitry controls the density configuration of read or write operations to the memory blocks in response to a configuration command. In one embodiment, the configuration command is part of the read or write command. In another embodiment, the configuration command is read from a configuration register. | 2012-03-22 |
20120072654 | Flash Memory Controller Garbage Collection Operations Performed Independently In Multiple Flash Memory Groups - A flash memory controller connected to multiple flash memory groups performs independent garbage collection operations in each group. For each group, the controller independently determines the amount of free space and performs garbage collection operations if the amount falls below a threshold. | 2012-03-22 |
20120072655 | STORAGE DEVICE AND ACCESS CONTROL SYSTEM THEREOF, SD CARD AND DATA ACCESS CONTROL METHOD THEREOF - The present disclosure relates to smart card technology, and provides a SD card and a data access control method thereof. The SD card includes an interface module, a control module, and a storage module including a public storage unit and a private storage unit. The control module includes a SD card direct access unit for controlling an external device to access the public storage unit, a storage isolating firmware unit for stopping the external device from unauthorized accessing the private storage unit, and a virtual machine operating system unit for installing some applications according to the requirements of user, and perform the application in a protected mode combined with the storage isolating firmware unit. The present disclosure can guarantee convenience of accession and stored of large capacity SD data, and installs some applications according to the requirements, performs the applications, storeds and accesses the data in a protected mode. | 2012-03-22 |
20120072656 | MULTI-TIER CACHING - A method for maintaining an index in multi-tier data structure includes providing a plurality of a storage devices forming the multi-tier data structure, caching an index of key-value pairs across the multi-tier data structure, wherein each of the key-value pairs includes a key, and one of a data value and a data pointer, the key-value pairs stored in the multi-tier data structure, providing a journal for interfacing with the multi-tier data structure, providing a plurality of zone allocators recording which zones of the multi-tier data structure are in used, and providing a plurality of zone managers for controlling access to cache lines of the multi-tier data structure through the journal and zone allocators, wherein each zone manager maintains a header object pointing to data to be stored in an allocated zone. | 2012-03-22 |
20120072657 | SYSTEM AND METHOD TO WRITE DATA USING PHASE-CHANGE RAM - A data recording system includes a file system configured to manage block-based input/output of data, a phase-change random access memory (PRAM) configured to write first data among the data in units of sub blocks, and a block abstract layer configured to receive a write command of the first data to a first particular block in the PRAM from the file system and log changed data information to a second particular block in the PRAM in units of sub blocks, and a method to provide the same. | 2012-03-22 |
20120072658 | PROGRAM, CONTROL METHOD, AND CONTROL DEVICE - Provided is a program, control method, and control device that can shorten start-up time. Page table entry is rewritten for a Memory Management Unit (MMU) table, on a computer system equipped with an MMU, so that a page fault will occur at every page, for all the pages necessary for the operation of a software program. Upon start-up, the stored memory image is loaded in page units for page faults that have occurred on the RAM to be accessed. Loading of unnecessary pages will not be executed, because such loading was executed, and the start-up time can be shortened worth that time. This program, control method, and control device can be applied to personal computers, and electronic devices equipped with built-in type computers. | 2012-03-22 |
20120072659 | DATA REPLICA CONTROL - A replica control system includes software to control replication in virtual environments. The replica control system identifies a plurality of data blocks within an underlying storage volume in response to a request to update a replica of a target storage volume, identifies changed data blocks of the plurality of data blocks within the underlying storage volume, and identifies a subset of the changed data blocks with which to update the replica of the target storage volume based on a characteristic of the changed data blocks. | 2012-03-22 |
20120072660 | OPTICAL DISC RECORDER AND BUFFER MANAGEMENT METHOD THEREOF - A buffer management method is provided. A host issues a read command requesting access for a read data block and a write command requesting recording of a write data block. A write buffer is dedicated to store the write data block. A read buffer is dedicated to store the read data block. The method comprises entering the optical disc recorder into a write loop. During the write loop, the optical disc recorder triggering a write command handling procedure in response to the write command; triggering a read command handling procedure in response to the read command; and triggering a pre-recording procedure to prepare the write data block in the write buffer for recording. Wherein contents between the write buffer and read buffer are exchangeable during the write handling procedure, the read handling procedure or the pre-recording procedure. | 2012-03-22 |
20120072661 | HYBRID RAID CONTROLLER HAVING MULTI PCI BUS SWITCHING - Embodiments of the present invention provide a hybrid RAID controller with multi PCI bus switching for a storage device of a PCI-Express (PCI-e) type that supports a low-speed data processing speed for a host. Specifically, embodiments of this invention provide a hybrid RAID controller having multiple (e.g., two or more) sets of RAID circuitry that are interconnected/coupled to on another via a PCI bus to enable real-time switching. Each set of RAID circuitry is coupled to a one or more (i.e., a set of) semiconductor storage device (SSD) memory disk units and/or HDD/Flash memory units. Among other things, the SSD memory disk units and/or HDD/Flash memory units adjust a synchronization of a data signal transmitted/received between the host and a memory disk during data communications between the host and the memory disk through a PCI-Express interface and simultaneously support a high-speed data processing speed for the memory disk, thereby supporting the performance of the memory to enable high-speed processing in an existing interface environment at the maximum. | 2012-03-22 |
20120072662 | ANALYZING SUB-LUN GRANULARITY FOR DYNAMIC STORAGE TIERING - A method for metadata management in a storage system may include providing a metadata queue of a maximum size; determining whether the metadata for a particular sub-LUN is held in the metadata queue; updating the metadata for the particular sub-LUN when the metadata for the particular sub-LUN is held in the metadata queue; inserting the metadata for the particular sub-LUN at the head of the metadata queue when the metadata queue is not full and the metadata is not held in the metadata queue; replacing an entry in the metadata queue with the metadata for the particular sub-LUN and moving the metadata to the head of the metadata queue when the metadata queue is full and the metadata is not held in the metadata queue; and controlling the number of sub-LUNs in the storage system to manage data accessed with respect to an amount of available data storage. | 2012-03-22 |
20120072663 | Storage control device and RAID group extension method - The present invention provides a storage system having a controller that can extend an old RAID group to a new RAID group without decreasing a processing speed. A conversion part reads the data from an unconverted area A | 2012-03-22 |
20120072664 | STORAGE CONTROLLER, STORAGE CONTROL SYSTEM, AND STORAGE CONTROL METHOD - There is provided a storage control system and a method in which various controls to a plurality of storage controllers connected to each other can be effectively performed. The storage control system and method controls first and second storage controllers, in which a second storage controller is connected to a first storage controller to which a host system is connected. With reference to a memory in which a table defining correspondence relationships between internal logical volumes and a host logical volume of the second storage controller is stored, a channel adapter of the first storage controller controls power supplies of driving mechanisms of storage devices corresponding to the internal logical volumes. | 2012-03-22 |
20120072665 | Caching of a Site Model in a Hierarchical Modeling System for Network Sites - Disclosed are various embodiments for caching of a hierarchical model of a network site. Upon receiving a request to resolve a network site, a hierarchical site model associated with a network site is retrieved. A directory model associated with the network site is also retrieved. A caching process is initiated that retrieves at least a subset of page models and loads them into a cache. The caching process is executed in parallel with the processing of the hierarchical site model. | 2012-03-22 |
20120072666 | INTEGRATED CIRCUIT COMPRISING TRACE LOGIC AND METHOD FOR PROVIDING TRACE INFORMATION - An integrated circuit comprises trace logic for operably coupling to at least one memory element and for providing trace information for a signal processing system. The trace logic comprises trigger detection logic for detecting at least one trace trigger, memory access logic arranged to perform, upon detection of the at least one trace trigger, at least one read operation for at least one memory location of the at least one memory element associated with the at least one detected trigger, memory content message generation logic arranged to generate at least one memory content message comprising information relating to a result of the at least one read operation performed by the memory access logic, and output logic for outputting the at least one memory content message. | 2012-03-22 |
20120072667 | VARIABLE LINE SIZE PREFETCHER FOR MULTIPLE MEMORY REQUESTORS - A prefetch unit generates prefetch addresses in response to an initial received memory read request, an address associated with the initial received memory read request, a line length of the requestor of the initial received memory read request, and a request type width of the initial received memory read request. Prefetch operations are generated using the generated prefetch addresses, wherein each generated prefetch address is stored in a prefetch buffer slot that is selected by a prefetch FIFO (First In First Out) prefetch counter. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request. | 2012-03-22 |
20120072668 | SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS - A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, where each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots. Each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request. | 2012-03-22 |
20120072669 | COMPUTER-READABLE, NON-TRANSITORY MEDIUM STORING MEMORY ACCESS CONTROL PROGRAM, MEMORY ACCESS CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS - A method of causing an information processing apparatus to execute, the method including: performing a management procedure to accept addresses of respective page tables generated for each of operation modes from an operating system that manages the virtual address space and to associate the addresses with the operating system to be recorded in page table correspondence information storage; executing a control procedure to set a second access right indicating a value lower than the first access right in accordance with the operation mode of the operating system; and processing a processing procedure to cause the memory management device to execute a flush of a translation look-aside buffer, and to set the second access right indicating a value for validating the first access right, wherein the memory management device performs a control on the memory access while the second access right is prioritized over the first access right. | 2012-03-22 |
20120072670 | METHOD FOR COUPLING SUB-LUN LOAD MEASURING METADATA SIZE TO STORAGE TIER UTILIZATION IN DYNAMIC STORAGE TIERING - A method for metadata management in a storage system configured for supporting sub-LUN tiering. The method may comprise providing a metadata queue of a specific size; determining whether the metadata for a particular sub-LUN is cached in the metadata queue; updating the metadata for the particular sub-LUN when the metadata for the particular sub-LUN is cached in the metadata queue; inserting the metadata for the particular sub-LUN to the metadata queue when the metadata queue is not full and the metadata is not cached; replacing an entry in the metadata queue with the metadata for the particular sub-LUN when the metadata queue is full and the metadata is not cached; and identifying at least one frequently accessed sub-LUN for moving to a higher performing tier in the storage system, the at least one frequently accessed sub-LUN being identified based on the metadata cached in the metadata queue. | 2012-03-22 |
20120072671 | PREFETCH STREAM FILTER WITH FIFO ALLOCATION AND STREAM DIRECTION PREDICTION - A prefetch filter receives a memory read request having an associated address for accessing data that is stored in a line of memory. An address window is determined that has an address range that encompasses an address space that is twice as large as the line of memory. In response to a determination of in which half the address window includes the requested line of memory, a prefetch direction is to a first direction or to an opposite direction. The prefetch filter can include an array of slots for storing a portion of a next predicted access and determine a memory stream in response to a hit on the array by a subsequent memory request. The prefetch filter FIFO counter cycles through the slots of the array before wrapping around to a first slot of the array for storing a next predicted address portion. | 2012-03-22 |
20120072672 | PREFETCH ADDRESS HIT PREDICTION TO REDUCE MEMORY ACCESS LATENCY - A prefetch unit receives a memory read request having an associated address for accessing data that is stored in memory. A next predicted address is determined in response to a prefetch address stored in a slot of an array for storing portions of predicted addresses and associated with a slot in accordance with an order in which a prefetch FIFO counter is modified to select the slots of the array. Data is prefetched from a lower-level hierarchical memory in accordance with a next predicted address and provisioned the prefetched data to minimize a read time for reading the prefetched data. The provisioned prefetched data is read-out when the address of the memory request is associated with the next predicted address. | 2012-03-22 |
20120072673 | SPECULATION-AWARE MEMORY CONTROLLER ARBITER - A memory arbiter minimizes latency of memory accesses in a system having multiple processors. The memory arbiter improves overall system performance by managing the memory requests from each processor individually before those requests are sent to a central memory arbiter for handling memory requests for the shared resources from the multiple processors. The local memory arbiter buffers the memory requests from a local processor, analyzes the buffered memory requests, and optimizes the requests by reordering commands according to a rule set, and by performing write merging and prefetch squashing in certain conditions. | 2012-03-22 |
20120072674 | DOUBLE-BUFFERED DATA STORAGE TO REDUCE PREFETCH GENERATION STALLS - A prefetch unit includes a program prefetch address generator that receives memory read requests and in response to addresses associated with the memory read request generates prefetch addresses and stores the prefetch addresses in slots of the prefetch unit buffer. Each slot includes a buffer for storing a prefetch address, two data buffers for storing data that is prefetched using the prefetch address of the slot, and a data buffer selector for alternating the functionality of the two data buffers. A first buffer is used to hold data that is returned in response to a received memory request, and a second buffer is used to hold data from a subsequent prefetch operation having a subsequent prefetch address, such that the data in the first buffer is not overwritten even when the data in the first buffer is still in the process of being read out. | 2012-03-22 |
20120072675 | DATA PROCESSOR FOR PROCESSING DECORATED INSTRUCTIONS WITH CACHE BYPASS - A method includes determining if a data processing instruction is a decorated access instruction with cache bypass, and determining if the data processing instruction generates a cache hit to a cache. When the data processing instruction is determined to be a decorated access instruction with cache bypass and the data processing instruction is determined to generate a cache hit, the method further includes invalidating a cache entry of the cache associated with the cache hit; and performing by a memory controller of the memory, a decoration operation specified by the data processor instruction on a location in the memory designated by a target address of the data processor instruction, wherein the performing the decorated access includes the memory controller performing a read of a value of the location in memory, modifying the value to generate a modified value, and writing the modified value to the location | 2012-03-22 |
20120072676 | SELECTIVE MEMORY COMPRESSION FOR MULTI-THREADED APPLICATIONS - A method, system, and computer usable program product for selective memory compression for multi-threaded applications are provided in the illustrative embodiments. An identification of a memory region that is shared by a plurality of threads in an application is received at a first entity in a data processing system. A request for a second entity in the data processing system to keep the memory region uncompressed when compressing at least one of a plurality of memory regions that comprise the memory region is provided from the first entity to the second entity. | 2012-03-22 |
20120072677 | Multi-Ported Memory Controller with Ports Associated with Traffic Classes - In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline. | 2012-03-22 |
20120072678 | Dynamic QoS upgrading - In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline. | 2012-03-22 |
20120072679 | Reordering in the Memory Controller - In an embodiment, a memory controller includes multiple ports. Each port may be dedicated to a different type of traffic. In an embodiment, quality of service (QoS) parameters may be defined for the traffic types, and different traffic types may have different QoS parameter definitions. The memory controller may be configured to scheduled operations received on the different ports based on the QoS parameters. In an embodiment, the memory controller may support upgrade of the QoS parameters when subsequent operations are received that have higher QoS parameters, via sideband request, and/or via aging of operations. In an embodiment, the memory controller is configured to reduce emphasis on QoS parameters and increase emphasis on memory bandwidth optimization as operations flow through the memory controller pipeline. | 2012-03-22 |
20120072680 | SEMICONDUCTOR MEMORY CONTROLLING DEVICE - According to one embodiment, a semiconductor memory controlling device includes a write control unit that writes a predetermined number of pieces of first data and redundant information calculated by using the predetermined number of pieces of the first data and used for correcting an error in the first data into different semiconductor storage drives, respectively; a constructing unit that constructs a storage area for storing therein a table by using driver information, the table showing an association between a logical address and a physical address of the first data and identification information for associating the predetermined number of pieces of first data with the redundant information; and a table controlling unit that stores, into the storage area, the table associated with the identification information, the physical address and the logical address of the predetermined number of pieces of the first data, and a physical address of the redundant information. | 2012-03-22 |
20120072681 | MEMORY CONTROL APPARATUS AND MEMORY CONTROL METHOD - Memory accesses to a memory device that is in a power saving mode depend on the order of the issuance thereof. Thus, a period of time during which the memory is placed in the power saving mode is sometimes shortened, resulting in less effective power savings. A memory control apparatus, which is connected with a plurality of masters and a plurality of memories having a power saving mode, arbitrates memory accesses from the plurality of the masters, monitors whether each of the plurality of the memories is in the power saving state, and determines the priorities of the memory accesses according to the result of the detection of the power saving mode. | 2012-03-22 |
20120072682 | DETECTION CIRCUIT FOR MIXED ASYNCHRONOUS AND SYNCHRONOUS MEMORY OPERATION - A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation. | 2012-03-22 |
20120072683 | Managing Write Operations in a Computerized Memory - A method and apparatus for managing write operations in memory. The method includes a memory including units, each of the units including subunits. Data updates are written “out-of-place”, in that new data does not overwrite the memory locations (subunits) where the data is currently stored. The at least one subunit containing the outdated data is marked as invalid. As a result, a subunit can contain up to date data in a valid subunit next to invalid subunits. For reclaiming units for erasure, it is searched amongst the units to identify a unit or units that match a predetermined criterion. The data of valid subunits of such identified unit is rewritten to another unit or units. | 2012-03-22 |
20120072684 | STORAGE APPARATUS AND CONTROLLING METHOD - A storage apparatus includes a storage medium configured to store data and a control unit configured to control access to the storage medium. The control unit includes first storage configured to store data to be stored in the storage medium, a second storage configured to store data, a control information generator configured to generate control information indicating a storage state of the data in the first storage and a transfer controller configured to control transfer of the data stored in the first storage to the second storage on the basis of the control information generated by the control information generator when the supply of power to the control unit is stopped. | 2012-03-22 |
20120072685 | METHOD AND APPARATUS FOR BACKUP OF VIRTUAL MACHINE DATA - Embodiments of the invention provide backup of virtual machine data and preferably simplify the backup system, especially in the virtual machine environment that uses an external storage subsystem. A system includes a storage system coupled via a network to a server and a management server. The storage system includes a plurality of storage volumes. The server includes virtual machines running thereon and has virtual machine data stored on the storage volumes. The management server comprises a processor, a memory, and a backup control module, which is configured to detect a virtual machine on the server which is suspended or terminated; identify one or more storage volumes which are used by the detected virtual machine; and direct the storage system to create a backup volume of the determined one or more storage volumes to back up data of the identified one or more storage volumes. | 2012-03-22 |
20120072686 | INTELLIGENT COMPUTER MEMORY MANAGEMENT - A plurality of memory allocators are initialized within a computing system. At least a first memory allocator and a second memory allocator in the plurality of memory allocators are each customizable to efficiently handle a set of different memory request size distributions. The first memory allocator is configured to handle a first memory request size distribution. The second memory allocator is configured to handle a second memory request size distribution. The second memory request size distribution is different than the first memory request size distribution. At least the first memory allocator and the second memory allocator that have been configured are deployed within the computing system in support of at least one application. Deploying at least the first memory allocator and the second memory allocator within the computing system improves at least one of performance and memory utilization of the at least one application. | 2012-03-22 |
20120072687 | COMPUTER SYSTEM, STORAGE VOLUME MANAGEMENT METHOD, AND COMPUTER-READABLE STORAGE MEDIUM - A computer system in an embodiment comprises a storage apparatus, a host computer, and a copy control program. The storage apparatus performs copy operations of volumes allocated to a guest OS of the host computer. The copy control program obtains volume information of the guest OS from a VM control program at a given time. The control program compares the information with previous volume information of the guest OS and performs volume copy control for the guest OS in accordance with the comparison result. This process achieve appropriate copy operations even if the association relationship between the guest OS and volumes is changed during system operation. | 2012-03-22 |
20120072688 | STORAGE SYSTEM AND DATA RESTORATION METHOD THEREOF - This storage system includes a first storage sub system having a first logical volume where a first data area is dynamically allocated to each prescribed area, and which stores data transmitted from a host computer in the first data area, and a second storage sub system having a second data area for backing up the first logical volume; wherein the first storage sub system includes: a first management unit for managing the status of the first data area allocated to each of the areas of the first logical volume; a transfer unit for transferring the data stored in the first data area allocated to each of the areas of the first logical volume to the second storage sub system; and a restoration unit for restoring the first logical volume based on the status of the first data area managed by the first management unit and/or the data transferred from the second storage sub system. | 2012-03-22 |
20120072689 | Method of data replication in a distributed data storage system and corresponding device - The present invention generally relates to distributed data storage systems. In particular, the present invention relates to optimization of the distributed storage system in terms of number of data replicas needed to ensure a desired level of data replication. | 2012-03-22 |
20120072690 | MEMORY DEVICE AND METHOD OF TRANSFERRING DATA - A USB-SATA conversion circuit board of a memory device includes a data traffic counter that retains a data traffic transferred in accordance with a reading command within a certain time period. Subsequently, the data transfer is prohibited when it is determined that the data is transferred from the memory device to the host device at a speed faster than a data transfer speed requisite at the time of playing of a motion image based on a value retained by the data traffic counter. | 2012-03-22 |
20120072691 | Storage System and Control Method for the Same - An externally-connected volume of a main storage is correlated to an AOU volume inside of an external storage. The AOU volume is allocated with a not-yet-used page in a pool in accordance with data writing. When a command is issued to the externally-connected volume for formatting or others, a first controller in the main storage converts the command into a format command or an area deallocation command with respect to the AOU volume in the external storage. As such, the external AOU volume is subjected to a write process in its entirety, thereby being able to prevent any unnecessary page allocation. With such a configuration, the storage system of the present invention can use pages in the pool with good efficiency. | 2012-03-22 |
20120072692 | DATA ACCESS MANAGEMENT - Apparatus, systems, and methods may operate to assert a first semi-exclusive write lock with respect to a storage medium area by storing lock information when assertion of another semi-exclusive write lock with respect to the area is not detected. Additional activities may include writing data to the area by a writing entity that has asserted the first semi-exclusive write lock after determining the lock information has not changed, while substantially simultaneously de-asserting the first semi-exclusive write lock. Reading from the area may be determined as successful by determining that the semi-exclusive write lock was not asserted prior to or during the reading by checking the status of the lock information. Additional apparatus, systems, and methods are disclosed. | 2012-03-22 |
20120072693 | COMPUTER SYSTEM AND METHOD FOR MANAGING THE SAME - The present invention provides a technique capable of preventing data loss due to relocation of physical storage devices. When a request to relocate a logical storage area is issued, it is determined if the logical storage area to be relocated, which is composed of the physical storage devices in the source storage apparatus, can be configured in the destination storage apparatus, and if it is, the physical storage devices that constitute the logical storage area to be relocated are switched into a write-inhibit state in the source storage apparatus, and the write-inhibit state of the physical storage devices is maintained until the physical storage devices are set up and the logical storage area to be relocated is configured in the destination storage apparatus. | 2012-03-22 |
20120072694 | VIRTUALIZED STORAGE SYSTEM AND METHOD OF OPERATING THEREOF - A storage system and method is provided including physical storage devices controlled by storage control devices constituting a storage control layer operatively coupled to the physical storage devices and hosts. The storage control layer includes a first virtual layer interfacing with the hosts, operable to represent a logical address space available to said hosts and characterized by an Internal Virtual Address Space (IVAS); a second virtual layer characterized by a Physical Virtual Address Space (PVAS), interfacing with the physical storage devices, and operable to represent an available storage space; and an allocation module operatively coupled to the first and second virtual layers and providing mapping between IVAP and PVAS. Each address in PVAS is configured to have a corresponding address in IVAS. The allocation module facilitates management of IVAS and PVAS, enabling separation of a process of deleting certain logical object into processes performing changes in IVAS and PVAS, respectively. | 2012-03-22 |
20120072695 | METHODS AND SYSTEM OF POOLING STORAGE DEVICES - A system and method are provided for pooling storage devices in a virtual library for performing a storage operation. A storage management device determines a storage characteristic of a plurality of storage devices with respect to performing a storage operation. Based on a storage characteristic relating to performing the storage operation, the storage management device associates at least two storage devices in a virtual library. The storage management device may continuously monitor the virtual library and detect a change in storage characteristics of the storage devices. When changes in storage characteristics are detected, the storage management device may change associations of the storage device in the virtual library. | 2012-03-22 |
20120072696 | METHOD FOR DIAGNOSING A MEMORY OF AN ELECTRONIC DEVICE - A electronic device includes a diagnosing system, a processor, a storage system, a memory, and one or more programs. The one or more programs includes a determining module, an obtaining module, a processing module, and a display module. The determining module determines whether there is a bad sector in the memory. If there is a bad sector in the memory, the determining module generates an obtaining signal. The obtaining module obtains the virtual address of the bad sector according to the obtaining signal. The processing module converts the virtual address into the corresponding physical address. | 2012-03-22 |
20120072697 | SYSTEM AND METHOD FOR IDENTIFYING TLB ENTRIES ASSOCIATED WITH A PHYSICAL ADDRESS OF A SPECIFIED RANGE - A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB. | 2012-03-22 |
20120072698 | MEMORY MANAGEMENT DEVICE AND METHOD FOR MANAGING ACCESS TO A NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a memory management device includes a history management unit, an address translation table, an address management unit, and a data management unit. The history management unit manages an access history for data stored in a nonvolatile semiconductor memory. The address translation table includes a translation table of a logical address and a physical address corresponding to the data. The address management unit specifies, based on the access history, second data to be accessed after access to first data being stored in the nonvolatile semiconductor memory, and registers a second physical address corresponding to the second data in the address translation table in association with a first logical address corresponding to the first data. The data management unit reads out the second data from the nonvolatile semiconductor memory to a buffer. | 2012-03-22 |
20120072699 | LOGIC CELL ARRAY AND BUS SYSTEM - A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points. | 2012-03-22 |
20120072700 | MULTI-LEVEL REGISTER FILE SUPPORTING MULTIPLE THREADS - A processor includes an instruction fetch unit, an issue queue coupled to the instruction fetch unit, an execution unit coupled to the issue queue, and a multi-level register file including a first level register file having lower access latency and a second level register file having higher access latency. Each of the first and second level register files includes a plurality of physical registers for holding operands that is concurrently shared by a plurality of threads. The processor further includes a mapper that, at dispatch of an instruction specifying a source logical register from the instruction fetch unit to the issue queue, initiates a swap of a first operand associated with the source logical register that is in the second level register file with a second operand held in the first level register file. The issue queue, following the swap, issues the instruction to the execution unit for execution. | 2012-03-22 |
20120072701 | Method Macro Expander - One embodiment of the present invention sets forth a [TODO once claims are reviewed] | 2012-03-22 |
20120072702 | PREFETCHER WITH ARBITRARY DOWNSTREAM PREFETCH CANCELATION - A prefetch cancelation arbiter improves access to a shared memory resource by arbitrarily canceling speculative prefetches. The prefetch cancelation arbiter applies a set of arbitrary policies to speculative prefetches to select one or more of the received speculative prefetches to cancel. The selected speculative prefetches are canceled and a cancelation notification of each canceled speculative prefetch is sent to a higher-level memory component such as a prefetch unit or a local memory arbiter that is local to the processor associated with the canceled speculative prefetch. The set of arbitrary policies is used to reduce memory accesses to the shared memory resource. | 2012-03-22 |
20120072703 | SPLIT PATH MULTIPLY ACCUMULATE UNIT - In one embodiment, a processor includes a multiply-accumulate (MAC) unit having a first path to handle execution of an instruction if a difference between at least a portion of first and second operands and a third operand is less than a threshold value, and a second path to handle the instruction execution if the difference is greater than the threshold value. Based on the difference, at least part of the third operand is to be provided to a multiplier of the MAC unit or to a compressor of the second path. Other embodiments are described and claimed. | 2012-03-22 |
20120072704 | "OR" BIT MATRIX MULTIPLY VECTOR INSTRUCTION - A processor is operable to execute a bit matrix multiply instruction. In further examples, the processor is operable to perform a vector bit matrix multiply instruction, and is a part of a computerized system. | 2012-03-22 |
20120072705 | Obtaining And Releasing Hardware Threads Without Hypervisor Involvement - A first hardware thread executes a software program instruction, which instructs the first hardware thread to initiate a second hardware thread. As such, the first hardware thread identifies one or more register values accessible by the first hardware thread. Next, the first hardware thread copies the identified register values to one or more registers accessible by the second hardware thread. In turn, the second hardware thread accesses the copied register values included in the accessible registers and executes software code accordingly. | 2012-03-22 |
20120072706 | Microcode for Transport Triggered Architecture Central Processing Units - The different advantageous embodiments provide an apparatus comprising a central processing unit, a microcode store, and a number of functional units. The central processing unit utilizes transport triggered architecture and is configured to execute microcoded instructions that allow a single instruction to be executed as multiple instructions. The microcode store includes a number of microcoded instruction implementations. The number of functional units includes a number of useful entry points into the microcode store. | 2012-03-22 |
20120072707 | Scaleable Status Tracking Of Multiple Assist Hardware Threads - A processor includes an initiating hardware thread, which initiates a first assist hardware thread to execute a first code segment. Next, the initiating hardware thread sets an assist thread executing indicator in response to initiating the first assist hardware thread. The set assist thread executing indicator indicates whether assist hardware threads are executing. A second assist hardware thread initiates and begins executing a second code segment. In turn, the initiating hardware thread detects a change in the assist thread executing indicator, which signifies that both the first assist hardware thread and the second assist hardware thread terminated. As such, the initiating hardware thread evaluates assist hardware thread results in response to both of the assist hardware threads terminating. | 2012-03-22 |
20120072708 | HISTORY BASED PIPELINED BRANCH PREDICTION - Systems and methods for history based pipelined branch prediction. In one embodiment, access to prediction information to predict a plurality of branches within an instruction block is initiated in a same clock cycle of the computer processor as a fetch of the instruction block. The prediction information may be available to the predictor not later than a clock cycle of the computer processor in which the plurality of branches are decoded. | 2012-03-22 |
20120072709 | Unstacking Software Components for Migration to Virtualized Environments - Techniques for unstacking software components are provided. The techniques include discovering a plurality of software components and one or more dependencies between the software components in a computer system, designing a plurality of unstacking options for unstacking said components, and selecting one of said unstacking options to unstack said components. | 2012-03-22 |
20120072710 | DIRECT SCATTER LOADING OF EXECUTABLE SOFTWARE IMAGE FROM A PRIMARY PROCESSOR TO ONE OR MORE SECONDARY PROCESSOR IN A MULTI-PROCESSOR SYSTEM - In a multi-processor system, an executable software image including an image header and a segmented data image is scatter loaded from a first processor to a second processor. The image header contains the target locations for the data image segments to be scatter loaded into memory of the second processor. Once the image header has been processed, the data segments may be directly loaded into the memory of the second processor without further CPU involvement from the second processor. | 2012-03-22 |
20120072711 | Computer Apparatus and Method for Charging Portable Electronic Device Using the Computer Apparatus - A computer apparatus and a method for charging a portable electronic device are provided. The method is implemented in a computer apparatus including a connector. The method includes: (a) detecting whether the portable electronic device is plugged and connected to the connected when the computer apparatus is in a power off state; (b) causing the computer apparatus to execute a boot process if the portable electronic device is plugged and connected to the connector; (c) determining whether the portable electronic device is a predetermined device; (d) sending a charging command to the portable electronic device such that the portable electronic device derives a charging current from the computer apparatus if the portable electronic device is the predetermined device; and (e) causing the computer apparatus to shut down before an operating system is loaded. | 2012-03-22 |
20120072712 | SEMICONDUCTOR INTEGRATED CIRCUIT AND TELEVISION - The present invention provides a low-cost semiconductor integrated circuit on which two CPUs are mounted. The semiconductor integrated circuit integrated in a single chip includes a standby microcomputer, a main microcomputer, and a block circuit which blocks a signal between both microcomputers. The standby microcomputer includes a first Read Only Memory (ROM) which stores a first boot program and a first processing unit which executes the first boot program. The main microcomputer includes a second ROM which stores a second boot program and a second processing unit which executes the second boot program. The first processing unit executes the first boot program when the first power source is switched ON, while the second processing unit executes the second boot program when the second power source is switched ON. | 2012-03-22 |
20120072713 | General Purpose Distributed Encrypted File System - A general purpose distributed encrypted file system generates a block key on a client machine. The client machine encrypts a file using the block key. Then, the client encrypts the block key on the first client machine with a public key of a keystore associated with a user and associates the encrypted block key with the encrypted data block as crypto metadata. The client machine caches the encrypted data block and the crypto metadata and sends the encrypted data block and the crypto metadata to a network file system server. When the client machine receives a return code from the network file system server indicating successful writes of the encrypted data block and the crypto metadata, the client machine clears the cached encrypted data block and the crypto metadata. | 2012-03-22 |
20120072714 | Methods and Systems for Secure Authentication of a User by a Host System - A method and system for securely logging onto a banking system authentication server so that a user credential never appears in the clear during interaction with the system in which a user's credential is DES encrypted, and the DES key is PKI encrypted with the public key of an application server by an encryption applet before being transmitted to the application server. Within the HSM of the application server, the HSM decrypts and re-encrypts the credential under a new DES key known to the authentication server, the re-encrypted credential is forwarded to the authentication server, decrypted with the new DES key known to the authentication server, and verified by the authentication server. | 2012-03-22 |
20120072715 | Authorizing Equipment on a Sub-Network - Systems and methods for authorizing a customer premise equipment (CPE) device to join a network through a network termination unit (NTU). The CPE device can send an encrypted connection request, and an authorization server can decrypt the connection request and provide a network membership key (NMK) associated with the CPE device to the NTU. The authorization server can encrypt the NMK associated with the CPE device using a device access key (DAK) associated with the NTU. | 2012-03-22 |
20120072716 | MULTITENANT-AWARE PROTECTION SERVICE - Implementing a data protection service. One method includes receiving a request to provision a first tenant among a plurality of tenants managed by a single data protection service. A tenant is defined as an entity among a plurality of entities. A single data protection service provides data protection services to all tenants in the plurality of tenants. A first encryption key used to decrypt the first tenant's data at the data store is stored. The first encryption key is specific to the first tenant and thus cannot be used to decrypt other tenants' data at the data store from among the plurality of tenants. Rather each tenant in the plurality of tenants is associated with an encryption key, not usable by other tenants, used at the data store to decrypt data on a tenant and corresponding key basis. | 2012-03-22 |