12th week of 2009 patent applcation highlights part 65 |
Patent application number | Title | Published |
20090077320 | DIRECT ACCESS OF CACHE LOCK SET DATA WITHOUT BACKING MEMORY - Apparatus and system for quickly accessing data residing in a cache of one processor, by another processor, while avoiding lengthy accesses to main memory are provided. A portion of the cache may be placed in a lock set mode by the processor in which it resides. While in the lock set mode, this portion of the cache may be accessed directly by another processor without lengthy “backing” writes of the accessed data to main memory. | 2009-03-19 |
20090077321 | Microprocessor with Improved Data Stream Prefetching - A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch priority. The microprocessor also includes a load/store unit that generates load/store requests to transfer data between the system memory and the microprocessor. The microprocessor also includes a stream prefetch unit that generates a plurality of prefetch requests to prefetch the data stream from the system memory into the microprocessor. The prefetch requests specify the stream prefetch priority. The microprocessor also includes a bus interface unit (BIU) that generates transaction requests on the bus to transfer data between the system memory and the microprocessor in response to the load/store requests and the prefetch requests. The BIU prioritizes the bus transaction requests for the prefetch requests relative to the bus transaction requests for the load/store requests based on the stream prefetch priority. | 2009-03-19 |
20090077322 | System and Method for Getllar Hit Cache Line Data Forward Via Data-Only Transfer Protocol Through BEB Bus - A system and method for using a data-only transfer protocol to store atomic cache line data in a local storage area is presented. A processing engine includes an atomic cache and a local storage. When the processing engine encounters a request to transfer cache line data from the atomic cache to the local storage (e.g., GETTLAR command), the processing engine utilizes a data-only transfer protocol to pass cache line data through the external bus node and back to the processing engine. The data-only transfer protocol comprises a data phase and does not include a prior command phase or snoop phase due to the fact that the processing engine communicates to the bus node instead of an entire computer system when the processing engine sends a data request to transfer data to itself. | 2009-03-19 |
20090077323 | Bus Controller Initiated Write-Through Mechanism with Hardware Automatically Generated Clean Command - A write-through cache scheme is created. A store data command is sent to a cache line of a cache array from a processing unit. It is then determined whether the address of the store data is valid, wherein the original data from the store's address has been previously loaded into the cache. A write-through command is sent to a system bus as a function of whether the address of the store data is valid. The bus controller is employed to sense the write-through command. If the write-through command is sensed, a clean command is generated by the bus controller. If the write-through command is sensed, the store data is written into the cache array, and the data is marked as modified. If the write-through command is sensed, the clean command is sent onto the system bus by the bus controller, thereby causing modified data to be written to memory. | 2009-03-19 |
20090077324 | METHODS AND SYSTEMS FOR EXCHANGING DATA - A method for exchanging data between a producer and a consumer is provided. The method includes writing the data with the producer without blocking the consumer and without waiting for access to the consumer. The method also includes reading the data with the consumer without blocking the producer and without waiting for access to the producer. The data is exchanged from the producer to the consumer upon reading the data. | 2009-03-19 |
20090077325 | Method and arrangements for memory access - In one embodiment a memory system is disclosed having a first requester group, a first access control module coupled to the first requester group to receive access requests from the first requester group, a second requestor group and a second access control module coupled to the second requestor group to receive access requests from the second requestor group and memory. The memory can be segmented into a plurality of address blocks, where the plurality of address blocks can have an address range. The controller can sequentially rotate write access among the plurality of address blocks to distribute the sequential data among the plurality of address blocks. | 2009-03-19 |
20090077326 | Multiprocessor system - A memory mapping unit requests allocation of a remote memory to memory mapping units of other processor nodes via a second communication unit, and requests creation of a mapping connection to a memory-mapping managing unit of a first processor node via the second communication unit. The memory-mapping managing unit creates the mapping connection between a processor node and other processor nodes according to a connection creation request from the memory mapping unit, and then transmits a memory mapping instruction for instructing execution of a memory mapping to the memory mapping unit via a first communication unit of the first processor node. | 2009-03-19 |
20090077327 | Method and apparatus for enabling a NAS system to utilize thin provisioning - A NAS (network attached storage) controller managing file system data is configured for use in a storage system having thin provisioning capability. Physical storage capacity is used efficiently by making it possible for the NAS controller to identify to a disk array system having thin provisioning capability which segments of a thin provisioned volume are no longer in use. File system blocks or block groups no longer in use by the NAS controller are identified by the NAS controller. The NAS controller sends a release request to the disk array system specifying thin provisioning segments that correspond to the identified FS blocks or block groups. The release request instructs the disk array system to release chunks of physical storage capacity assigned to the specified thin provisioning segments so that the physical storage capacity can be made available for reuse in the disk array storage system. | 2009-03-19 |
20090077328 | Methods and apparatuses for heat management in storage systems - An information system includes a storage system having a controller in communication with a plurality of storage devices. In some embodiments, the storage devices are divided into at least a first group and a second group, with a first temperature sensor sensing a temperature condition for the first group, and a second temperature sensor for sensing a temperature condition for the second group. A heat distribution rule designates the first groups to be high temperature groups and the second groups to be low temperature groups. The heat distribution rule is implemented by designating a higher load of input/output (I/O) operations to the high temperature groups than to the low temperature groups, such as by migrating volumes having high I/O loads to the high temperature groups. In other embodiments, there are multiple storage systems, and each storage system is designated as a high temperature system or a low temperature system. | 2009-03-19 |
20090077329 | Non-broadcast signature-based transactional memory - A coherence controller in hardware of an apparatus in an example detects conflicts on coherence requests through direct, non-broadcast employment of signatures that: summarize read-sets and write-sets of memory transactions; and provide false positives but no false negatives for the conflicts on the coherence requests. The signatures comprise fixed-size representations of a substantially arbitrary set of addresses for the read-sets and the write-sets of the memory transactions. | 2009-03-19 |
20090077330 | MODIFIED BRANCH METRIC CALCULATOR TO REDUCE INTERLEAVER MEMORY AND IMPROVE PERFORMANCE IN A FIXED-POINT TURBO DECODER - A turbo decoder that calculates alpha, beta and gamma (branch metric) values does not normalize the branch metric but instead applies the normalization factor to the newly calculated extrinsic values before writing them to interleaving memory, resulting in use of less memory than in prior turbo decoders. A compensating factor is applied when the extrinsics are read from interleaving memory. The absence of normalization in the gamma calculation not only conserves memory but also enhances decoder sensitivity. | 2009-03-19 |
20090077331 | Data migration and copying in a storage system with dynamically expansible volumes - When migrating data stored in a storage region assigned to a volume to another storage region, the connection status of the host computer and volume is confirmed. When the host computer and volume are connected, the maximum capacity of the volume requested by the host computer is reserved so that it is exclusively secured in another storage region to which data is to be migrated, and when the host computer and volume are not connected, the current capacity of the volume is reserved so that it is exclusively secured in another storage region. | 2009-03-19 |
20090077332 | Content management system - A content management system constructed by a plurality of storage apparatuses that can communicate with one another. A 1st storage apparatus, which is one of the storage apparatuses, stores therein, in correspondence, a content and copy destination information and sends the content and the copy destination information therefrom to a 2nd storage apparatus, which is another one of the storage apparatuses. Yet another one of the storage apparatuses that is indicated by the copy destination information stores therein, in correspondence, the content and copy source information and, after the 1st storage apparatus has sent the content and the copy destination information to the 2nd storage apparatus, rewrite the copy source information such that the copy source information indicates the 2nd storage apparatus. | 2009-03-19 |
20090077333 | DOUBLE DEGRADED ARRAY PROTECTION IN AN INTEGRATED NETWORK ATTACHED STORAGE DEVICE - In one embodiment, the invention provides a method for accessing a physical storage-device array comprising a plurality of storage devices. The method includes (1) obtaining at least one parameter from a profile selected from two or more profiles concurrently defining two or more virtual arrays, each profile defining (i) a different virtual array associated with a corresponding set of storage devices and (ii) a parameter set of one or more parameters used for accessing the virtual array; and (2) generating an instruction, based on the at least one parameter, for accessing, or disallowing access to, information in the virtual array defined by the selected profile, wherein a parameter in each the parameter set defined by each profile indicates whether two or more storage devices in the corresponding virtual array are degraded. | 2009-03-19 |
20090077334 | Storage Apparatus for Preventing Falsification of Data - When a file server is to create data that does not permit falsification in an external storage, it is not possible to guarantee that the rewriting of this data can be prevented from a computer connected to the external storage without going through a file server. Provided is a storage system configured from a first storage having a file I/O processing unit and a second storage connected to this first storage, wherein the first storage includes a unit for requesting a change of access authority to the storage area in the own storage and in the second storage provided to the own storage. An access request to a storage area in a second storage from a computer connected to a second storage without going through a file I/O processing unit is restricted based on the change of access authority executed by the second storage upon receiving the request from the first storage. | 2009-03-19 |
20090077335 | SYSTEM AND METHODS FOR AVOIDING BASE ADDRESS COLLISIONS - Processes are monitored as components are loaded into memory. Relocation of a component to an alternate base address instead of its preferred base address, causes an alternate component to be created corresponding to the relocated component. The alternate component is a copy of the relocated component, but the preferred base address of the alternate component is reset to be the alternate base address of the relocated component. Additional alternate components may be created for each relocated component, with each additional alternate component being optimized in a different manner. Alternate components may be implemented as alternate data stream of the corresponding relocated components. In response to subsequent requests to load a selected component into memory, it is determined whether the selected component has at least one corresponding alternate component. If so, one of the corresponding alternate components is loaded into memory instead of the selected component. | 2009-03-19 |
20090077336 | STORAGE SYSTEM AND STORAGE SYSTEM DATA MIGRATION METHOD - This storage system modifies the migration plan in accordance with the state of the migration destination when a plurality of volumes are migrated all at once. Migration-source volumes are migrated collectively to volumes inside the migration-destination storage apparatus. The user can make settings related to migration-source volumes and migration-destination volumes in a migration plan, and can establish a mid-process control plan for modifying the migration plan in the middle of processing. If a failure occurs in the migration-destination storage apparatus subsequent to the commencement of data migration processing, a processing method controller either cancels or temporarily halts the data migration processing, or changes the migration destination, on the basis of the mid-process control plan. When changing the migration destination, a previously selected alternate storage apparatus is selected as the new migration-destination storage apparatus. When a failure occurs in the alternate storage apparatus, yet another alternate storage apparatus is selected. | 2009-03-19 |
20090077337 | DATA READING METHOD FOR SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE - The present invention provides a data reading method suitable for use in a semiconductor memory device equipped with a plurality of semiconductor memory chips, which is capable of suppressing an increase in layout area as compared with a required storage capacity, and a semiconductor memory device. Two memory chips are sequentially selected in the way of combinations different from each other from within a plurality of memory chips each having a first storage area and a second storage area. Data are simultaneously read from the first storage area of one of the selected two memory chips and the second storage area of the other thereof. | 2009-03-19 |
20090077338 | Apparatus and Method for Managing Storage Systems - An apparatus for controlling a configuration change in a storage system having a plurality of storage appliances with an I/O handler local to each storage appliance for transmitting and receiving I/O requests. A local volume mapper local to each storage appliance maps storage local to the storage appliance; a remote volume mapper local to each storage appliance maps storage remote from the or each storage appliance; and a spanning host interface layer responsive to detection of the configuration change receives and redirects I/O requests among the plurality of storage appliances. | 2009-03-19 |
20090077339 | OBJECT BASED CONFLICT DETECTION IN A SOFTWARE TRANSACTIONAL MEMORY - Object-based conflict detection is described in the context of software transactional memory. In one example, a pointer is received for a block of instructions, the block of instructions having allocated objects. The lower bits of the pointer are masked if the pointer is in a small object space to obtain a block header for the block, and a size of the allocated objects is determined using the block header. | 2009-03-19 |
20090077340 | STORAGE AREA NETWORK (SAN) FORECASTING IN A HETEROGENEOUS ENVIRONMENT - The present invention provides an approach for SAN forecasting in a heterogeneous environment. Specifically, under the present invention capacity data on the heterogeneous environment is gathered. Capacity management techniques will then be used to analyze the SAN utilization, identify growth trends and patterns. Proactively, plans are made to account for these changes. Thereafter, a Capacity Planning Margin (CPM) will be applied to the forecast to reflect actual customer usage. The CPM adjusted forecasts will then be reviewed. Then, the SAN environment can be monitored by comparing actual vs. planned and return to adjust the forecast accordingly. | 2009-03-19 |
20090077341 | Method and System for Automated Memory Reallocating and Optimization Between Logical Partitions - A method and system for reallocating memory in a logically partitioned environment. The invention comprises a Performance Enhancement Program (PEP) and a Reallocation Program (RP). The PEP allows an administrator to designate several parameters and identify donor and recipient candidates. The RP compiles the performance data for the memory and calculates a composite parameter. For each memory block in the donor candidate pool, the RP compares the composite parameter to the donor load threshold to determine if the memory is a donor. For each memory block in the recipient candidate pool, the RP compares the composite parameter to the recipient load threshold to determine if the memory is a recipient. The RP calculates the recipient workload ratio and allocates the memory from the donors to the recipients. The RP monitors and update the workload statistics based on either a moving window or a discrete window sampling system. | 2009-03-19 |
20090077342 | METHOD TO ACHIEVE PARTIAL STRUCTURE ALIGNMENT - A computer-implemented method including receiving a set of data having a mapping. The set of data has groups of subsets of data. The mapping describes in what order the groups of subsets of data are to be stored in a memory. The mapping also describes the offsets of the groups of subsets of data in the memory. The mapping is not changed when the set of data is stored in the memory. The method also includes determining a starting address for the set of data. The starting address corresponds to an address in the memory. The starting address is determined such that an optimum number of subsets of data in the groups of subsets of data are aligned. The method also includes storing the set of data in the memory, wherein the mapping is unaffected when the set of data is stored in the memory. | 2009-03-19 |
20090077343 | STORAGE APPARATUS HAVING VIRTUAL-TO-ACTUAL DEVICE ADDRESSING SCHEME - A storage apparatus includes a storage unit and a controller, wherein control of inputting/outputting data from/to a device provided in said storage unit is executed in accordance with a request received by said storage apparatus. An actual device of the storage apparatus corresponds to a virtual device which is external to said storage apparatus. The controller operates to perform a process for mapping an actual device address corresponding to a virtual device address, in accordance with a specification of the actual device to be mounted or unmounted to correspond to the virtual device, and storing and retaining mapping information obtained from the mapping in a first table. The controller also performs data input/output process for receiving, an access request for data input/output in which said virtual device address is specified, obtaining the actual device address mapped to said specified virtual device address in said first table, and accessing the actual device by said obtained actual device address. | 2009-03-19 |
20090077344 | Method for bus testing and addressing in mass memory components - A method and apparatus for addressing a plurality of mass memory components coupled to a host device. The memory components can be arranged in a chain or in a ring configuration. In a ring, each memory component receives a bit pattern from the preceding stage and sends a bit pattern to the next stage in consecutive clock periods. Based on the received bit pattern, a recipient component knows the bus width between itself and the sending component. In a chain, each memory component also sends the received bit pattern back to the preceding stage. The memory component can generate its own address by counting clock periods. Alternatively, a recipient component changes its received bit pattern before sending the bit pattern to the next stage. As such, the recipient component knows its address based on the received bit pattern. | 2009-03-19 |
20090077345 | SIMD DOT PRODUCT OPERATIONS WITH OVERLAPPED OPERANDS - A data processing system includes a plurality of general purpose registers, and processor circuitry for executing one or more instructions, including a vector dot product instruction for simultaneously performing at least two dot products. The vector dot product instruction identifies a first and second source register, each for storing a plurality of vector elements, where a first dot product is to be performed between a first subset of vector elements of the first source register and a first subset of vector elements of the second source register, and a second dot product is to be performed between a second subset of vector elements of the first source register and a second subset of vector elements of the second source register. The first and second subsets of the second source register are different and at least two vector elements of the first and second subsets of the second source register overlap. | 2009-03-19 |
20090077346 | PROCESSING MODULE, PROCESSOR CIRCUIT, INSTRUCTION SET FOR PROCESSING DATA, AND METHOD FOR SYNCHRONIZING THE PROCESSING OF CODES - A processing module, a processor circuit, an instruction set for processing data, and a method for synchronizing the processing of codes are provided. In an embodiment of the invention, a processing module for processing instructions, the instructions relating to user data and control data according to a communication protocol. The processing module includes a first processing circuit configured to process the instructions relating to the control data, and a second processing circuit configured to process the instructions relating to the user data. | 2009-03-19 |
20090077347 | Systems and methods for wake on event in a network - Embodiments include systems and methods for allowing a host CPU to sleep while service presence packets and responses to search requests are sent by an alternate processor. While the CPU is in a low power state, the alternate processor monitors the network for incoming request packets. Also, while the CPU is asleep, the alternate processor periodically may transmit presence packets, announcing the presence of a service available from the host system of the CPU. In one embodiment, the alternate processor is a low power processor. If a search request is received when the CPU is in a low power state, the alternate processor responds to the search request according to whether the PC provides that service. If a service request is received, then the ME wakes the CPU of the PC to provide the requested service. In the wireless case, when the CPU is asleep, portions of the wireless upper MAC are implemented by the ME. When the CPU is awake the wireless upper MAC is implemented in the CPU. Thus, embodiments enable the PC to appear available to wireless devices when the CPU is asleep. | 2009-03-19 |
20090077348 | Providing a dedicated communication path for compliant sequencers - In one embodiment, the present invention includes a method for communicating an assertion signal from a first instruction sequencer to a plurality of accelerators coupled to the first instruction sequencer via a dedicated interconnect, detecting the assertion signal in the accelerators and communicating a request for a lock on a second interconnect coupled to the first instruction sequencer and the accelerators, and registering an accelerator that achieves the lock by communication of a registration message for the accelerator to the first instruction sequencer via the second interconnect. Other embodiments are described and claimed. | 2009-03-19 |
20090077349 | METHOD OF MANAGING INSTRUCTION CACHE AND PROCESSOR USING THE METHOD - A method of managing an instruction cache and a process of using the method are provided. The processor includes a processor core which has an active mode and an inactive mode, and an instruction cache which pre-traces a first instruction and detects a cache miss during the inactive mode, wherein the first instruction is performed by the processor core during the active mode. | 2009-03-19 |
20090077350 | DATA PROCESSING SYSTEM AND METHOD - A method, system and computer program for modifying an executing application, comprising monitoring the executing application to identify at least one of a hot load instruction, a hot store instruction and an active prefetch instruction that contributes to cache congestion; where the monitoring identifies a hot load instruction, enabling at least one prefetch associated with the hot load instruction; where the monitoring identifies a hot store instruction, enabling at least one prefetch associated with the hot store instruction; and where the monitoring identifies an active prefetch instruction that contributes to cache congestion, one of disabling the active prefetch instruction and reducing the effectiveness of the active prefetch instructions. | 2009-03-19 |
20090077351 | Information processing device and compiler - Devices, compilers and methods to reduce energy consumption associated with execution of a program by adjusting a computational capability of a CPU with higher accuracy than before. A device sets an appropriate computational capability to the CPU. It includes: changing a computational capability of the CPU every time each of a plurality of program areas included in the execution program is executed while the execution program is being executed, and measuring execution time each of the program areas; deciding an optimal computational capability required to execute the program area using the CPU, based on the execution time for each of the computational capabilities measured for the respective program areas; and performing setting of the optimal computational capability for executing the program area, which is to be used when executing the program area again in the course of executing the execution program, for each of the program areas. | 2009-03-19 |
20090077352 | PERFORMANCE OF AN IN-ORDER PROCESSOR BY NO LONGER REQUIRING A UNIFORM COMPLETION POINT ACROSS DIFFERENT EXECUTION PIPELINES - A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detected in the regular pipeline. By maintaining a backup copy of the instructions issued to the regular pipeline, instructions may not need to be flushed from separate execution pipelines and re-fetched. As a result, one may complete the results of the execution units to the architected state out of order thereby allowing the completion point to vary among the different execution pipelines. | 2009-03-19 |
20090077353 | PROGRAMMING LANGUAGE TYPE SYSTEM WITH AUTOMATIC CONVERSIONS - A programming language type system includes, in a memory, a set of numeric type including integer types, fixed-point types and floating-point types, a set of type propagation rules to automatically determine result types of any combination of integer types, fixed-point types and floating-point types, constant annotations to explicitly specify a result type of a literal constant, context-sensitive constants whose type is determined from a context of a constant according to the set of type propagation rules, an assignment operator to explicitly specify a type of a value or computation, and operator annotations to explicitly specify a result type of a computation. | 2009-03-19 |
20090077354 | Techniques for Predicated Execution in an Out-of-Order Processor - A technique for handling predicated code in an out-of-order processor includes detecting a predicate defining instruction associated with a predicated code region. Renaming of predicated instructions, within the predicated code region, is then stalled until a predicate of the predicate defining instruction is resolved. | 2009-03-19 |
20090077355 | INSTRUCTION EXPLOITATION THROUGH LOADER LATE FIX UP - A method, computer program product, and data processing system for substituting a candidate instruction in application code being loaded during load time. Responsive to identifying the candidate instruction, a determination is made whether a hardware facility of the data processing system is present to execute the candidate instruction. If the hardware facility is absent from the data processing system, the candidate instruction is substituted with a second set of instructions. | 2009-03-19 |
20090077356 | LOAD TIME INSTRUCTION SUBSTITUTION - A method, computer program product, and data processing system for substituting a candidate instruction in application code being loaded during load time. Responsive to identifying the candidate instruction, a determination is made whether a hardware facility of the data processing system is present to execute the candidate instruction. If the hardware facility is absent from the data processing system, the candidate instruction is substituted with a second set of instructions. | 2009-03-19 |
20090077357 | Method of Power Simulation and Power Simulator - Disclosed are a method of simulating power and a power simulator. The power simulator includes a static information extracting unit that extracts static information with respect to execution of the second instruction; a dynamic information extracting unit that extracts dynamic information with respect to the execution of the second instruction; and a calculation unit that calculates an estimated power of the processor based on the static information and the dynamic information. | 2009-03-19 |
20090077358 | MICROPROCESSOR CONTROL APPARATUS AS WELL AS METHOD AND PROGRAM FOR THE SAME - There is provided with a microprocessor control apparatus for controlling an operating speed of a microprocessor which executes a program including instruction codes, including: a state observing unit observing an execution state of the program at predetermined timings before execution of a deadline instruction code; prediction data of a remaining calculation amount required before execution of the deadline instruction code completes for each of predefined execution states; a predicted calculation amount acquiring unit acquiring a remaining calculation amount corresponding to an observed execution state as a remaining predicted calculation amount; a remaining time calculating unit calculating a remaining time until the deadline of the deadline instruction code; an operating speed calculating unit calculating a minimum operation speed of the microprocessor that is required to process the remaining predicted calculation amount within the remaining time; and
| 2009-03-19 |
20090077359 | ARCHITECTURE RE-UTILIZING COMPUTATIONAL BLOCKS FOR PROCESSING OF HETEROGENEOUS DATA STREAMS - An architecture for heterogeneous data processing which reuses the same hardware to process different data in different manners is disclosed. The different processing has a substantial similarity; such as performing different variations of a computation. For example, the computation may involve the same mathematical operations but use different constants or coefficients, or performing similar arithmetic operations that can be switched such as addition and subtraction, or performing arithmetic operations in different orders, etc. The different processing might be applying different convolution kernels depending on the pixel color. The differences between the kernels could include different kernel sizes, different coefficient locations, and different coefficient values. The same hardware is re-used for all of the similar computations, under the control of external control logic that allows hardware re-use. | 2009-03-19 |
20090077360 | Software constructed stands for execution on a multi-core architecture - In one embodiment, the present invention includes a software-controlled method of forming instruction strands. The software may include instructions to obtain code of a superblock including a plurality of basic blocks, build a dependency directed acyclic graph (DAG) for the code, sort nodes coupled by edges of the dependency DAG into a topological order, form strands from the nodes based on hardware constraints, rule constraints, and scheduling constraints, and generate executable code for the strands and store the executable code in a storage. Other embodiments are described and claimed. | 2009-03-19 |
20090077361 | DETECTING SPIN LOOPS IN A VIRTUAL MACHINE ENVIRONMENT - Embodiments of apparatuses, methods, and systems detecting spin loops in a virtual machine environment are disclosed. In one embodiment, an apparatus includes detection logic and virtualization logic. The detection logic is to detect whether a guest is executing a spin loop. The virtualization logic is to transfer control of the apparatus from the guest to a host in response to the detection logic detecting that the guest is executing the spin loop | 2009-03-19 |
20090077362 | CONFIGURABLE ACCESS KERNAL - A highly configurable kernel supports a wide variety of content protection systems. The kernel may reside in a host that interacts with a secure processor maintaining content protection clients. After establishing communication with the secure processor, the host receives messages from content protection clients requesting rules for message handling operations to support client operations. This flexible configuration allows for dynamic reconfiguration of host and secure processor operation. | 2009-03-19 |
20090077363 | SYSTEMS AND METHODS OF CREATING AND ACCESSING SOFTWARE SIMULATED COMPUTERS - The system and methods of the present application comprise one or more computers that generate and maintain a plurality of software-simulated computers. Each software-simulated computer is adapted to efficiently run an installed application program. Additional security layers provide access to the installed application through a remote user interface installed on a user's computing device. The system generates a new copy of the software-simulated computer for each user session, that prevents configuration problems from interfering with the proper operation of the application program, thereby consistently running the application in an optimized fashion, regardless of changes made to the software-simulated computer by the user or a virus. These software-simulated computers are unaffected by changes a user makes on their own client device. To this end, the system provides robust, web accessible capabilities to application software that may not have been adapted for use on the Internet. | 2009-03-19 |
20090077364 | DATA-PROCESSING ARRANGEMENT - A data-processing arrangement (MPS) comprises a main processor (MPR) and an auxiliary processor (APR). A system-program code (SYS) causes the main processor to write an application-program code (APCi+1) into a shared memory (DPRAM). The system-program code further causes the main processor to write an address indication, which indicates where the application-program code has been written into the shared memory, into a predefined memory location. A startup-program code (SPC) causes the auxiliary processor to retrieve the address indication from the predefined memory location so as to subsequently transfer the application-program code from the shared memory to an application-program memory (APM), which belongs to the auxiliary processor. | 2009-03-19 |
20090077365 | System and method for analyzing CPU performance from a serial link front side bus - Monitoring of boot progress for a multiprocessor information handling system is performed with a test module running on a CPLD. RAM integrated in the CPLD stores boot progress information passed through an I/O buffer located between the processors and the firmware that boots the processors. Downloading of the boot progress from the RAM to an external device, such as through a serial port, provides a processor trace that is analysis and debugging of the firmware by recording processor operations through the boot progress. | 2009-03-19 |
20090077366 | Workflow Management to Automatically Load a Blank Hardware System with an Operating System, Products, and Service - The exemplary embodiments provide a computer implemented method, apparatus, and computer usable program code for managing a workflow for assembling a data processing system according to a specific customized software configuration. An installation request from a remote data processing system is received. The installation request comprises an identity associated with the remote data processing system. An order associated with the identity is retrieved. A process configuration based on the order is determined. A system image associated with the process configuration is retrieved, forming an associated system image. The associated system image is transferred to the remote data processing system. | 2009-03-19 |
20090077367 | MANAGING REBOOT OPERATIONS - The disclosure provides a mechanism which is activated when a user opts to hibernate their computer (at the end of the day) rather than switching it off. In particular, on receipt of a hibernate request, an embodiment provides a mechanism for determining whether (as a result of, for example, a distribution or installation of software to a computer) there are any outstanding reboot operations for the computer. | 2009-03-19 |
20090077368 | Controller for a Mass Memory and Method for Providing Data for a Start Process of a Computer - In the process for providing data for a start process of a computer by a controller ( | 2009-03-19 |
20090077369 | Data Processing Device And Data Processing Method - A technology is provided which manages an environment appropriately when processing data. An operating environment information acquisition part acquires information on the operating environment of a document processing apparatus, such as information on computer hardware, and information including environment parameters for defining the operation of the document processing apparatus itself when the document processing apparatus starts up. An environment DOM generation part generates a DOM tree which contains those pieces of information. Each of the DOM nodes registers a functional block for dealing with a change of the information on that node, such as an operating environment control part, as a listener. When the nodes are changed, mutation events are issued to respective functional blocks. For example, necessary processing is performed such that a functional block for performing plug-in installation installs a plug-in. | 2009-03-19 |
20090077370 | Failover Of Blade Servers In A Data Center - Failover of blade servers in a data center, including powering off by a system management server a failing blade server, the failing blade server characterized by a machine type, the failing blade server mapped to remote computer boot storage administered through a Storage Management Initiative—Specification (‘SMI-S’) provider; identifying, by the system management server by use of the SMI-S provider from a pool of standby blade servers, a replacement blade server; remapping by the system management server through the SMI-S provider the remote computer boot storage of the failing blade server to the replacement blade server; and powering on the replacement blade server by the system management server. | 2009-03-19 |
20090077371 | SYSTEMS AND METHODS FOR A TEMPLATE-BASED ENCRYPTION MANAGEMENT SYSTEM - An encryption management system provides a solution for embedded system device authentication, secure server-to-device communications, and encryption key management. It reduces implementation times and costs associated with using cryptography for authentication and data privacy with embedded systems applications by freeing application developers from having to develop, manage, or update security-based features in their server-based applications. The template-based approach of the system provides highly customable and accessible security functionalities. To utilize services provided by the encryption management system in some embodiments, calling applications provide input parameters and function calls in the form of a template at runtime, and the output in the form of encrypted and secured messages are either sent to the client devices automatically or returned to the calling applications. As such, security functionalities and objects, though segregated in the encryption management system to provide enhanced protection, can still be easily accessed and can be updated without recompiling the calling applications. | 2009-03-19 |
20090077372 | PROCESS FOR TRANSMITTING AN ELECTRONIC MESSAGE IN A TRANSPORT NETWORK - In a process for transmitting an electronic message that contains protected and unprotected content, the authenticity of the header elements HE is ensured by obtaining a subsequent authenticity verification of the sender. For this purpose, a checking device which is inserted into the transmission network transforms the header elements of the original message into a new message whose contents are protected by known encryption methods. The new message is sent back to the sender which decrypts it and checks the header elements. If the sender verifies the authenticity of the transmitted data, the header elements on which the original message is based are also considered to be verified. According to the invention, the sender who sends the message, and is later requested to verify its authenticity, may be the mail server (Message Transfer Agent “MTA”) as well as the client of the MTA (and thus, the author of the message, who first forwards the message to the MTA). | 2009-03-19 |
20090077373 | SYSTEM AND METHOD FOR PROVIDING VERIFIED INFORMATION REGARDING A NETWORKED SITE - A system and method are disclosed for presenting a message relating to a networked site on an end-user device, the message preferably originating from a third party that is not a provider of the site. The end-user device receives a message blob containing the message and associated verification information when the networked site is accessed. A verification application then sends a request to verify the authenticity of a message blob to a verification server. If the verification server verifies that the message blob is authentic based on the verification information, presentation of the site-specific information on the end-user device is enabled. | 2009-03-19 |
20090077374 | Method and System for Secure Remote Transfer of Master Key for Automated Teller Banking Machine - A method for securely transferring a master key from a host to a terminal, such as an automated teller machine, is disclosed. Each of the host and terminal is initialized with a certificate, signed by a certificate authority, and containing a public key used in used in connection with public key infrastructure communication schemes. An identifier of an authorized host is stored in the terminal. Upon receiving a communication from a host including a host certificate, the terminal validates whether it is already bound to a host, if not, whether the host identifier of the remote host matches the preloaded authorized host identifier, before further communicating with the remote host, including the exchange of certificates. In this way, the terminal is protected against attacks or intruders. Following the exchange of certificates, the host may securely transfer the master key to the terminal in a message encrypted under the terminal's public key. The terminal may decrypt the message, including the master key, using its corresponding secret key. | 2009-03-19 |
20090077375 | Encapsulation of secure encrypted data in a deployable, secure communication system allowing benign, secure commercial transport - Sensitive, Type 1 KIV-encrypted data is encapsulated into IP packets in a remotely deployed, secure communication system. The IP packets are addressed to a matching IP encapsulator/decapsulator device over the public Internet or other IP protocol network, that then passes it to a similar Type 1 KIV device for decryption. Thus, sensitive, encrypted data is made to appear as if it were any other commercial network data, cloaking it in the vast and busy world of the Internet. The present invention is embodied in a system that provides secure Voice-Over-IP (VoIP), video and data network functionality in a single, small size deployable case, to a remote user. Most importantly, the embodiment allows for the routing of bulk encrypted (i.e., secure) data over a public network, e.g., the Internet. | 2009-03-19 |
20090077376 | Method and a system for secure execution of workflow tasks in a distributed workflow management system within a decentralized network system - There are provided a method, a system and an initiator server for a secure execution of workflow tasks of a workflow to be executed according to a given execution pattern in a distributed workflow management system within a decentralized network system with a plurality of servers (b | 2009-03-19 |
20090077377 | System and method of protecting content of an electronic file for sending and receiving - A system and method of protecting the content of an electronic file for sending and receiving. The invention includes providing unique local encryption key data correspondingly associated with a sender, and providing unique remote encryption key data correspondingly associated with a receiver. In addition, the method includes orienting the electronic file in an encrypted mode by utilizing at least one set of the unique local encryption key data and at least one set of the remote encryption key data. | 2009-03-19 |
20090077378 | QUERYING ENCRYPTED DATA IN A RELATIONAL DATABASE SYSTEM - A client-server relational database system, wherein data from the client computer is encrypted by the client computer and hosted by the server computer, the encrypted data is operated upon by the server computer, using one or more operators selected from a group of operators comprising: (a) inequality logic operators, (b) aggregation operators, and (c) wildcard matching operators, to produce an intermediate results set, the intermediate results set is sent from the server computer to the client computer, and the intermediate results set is decrypted and filtered by the client computer to produce actual results. The group of operators is limited because the encrypted results set, when decrypted, includes inaccuracies therein. The client computer applies a set of correction procedures to the decrypted results set to remove the inaccuracies therein. | 2009-03-19 |
20090077379 | Network Security System - A system for restricting access to encrypted content stored in a consuming device ( | 2009-03-19 |
20090077380 | Resource scheduling in workflow management systems - A system for improved scheduling of resources within a Workflow-Management-System or a computer system with comparable functionality (WFMS). Based on a new resource specification comprised within a process model and associated with an activity, the WFMS determines the resources required for execution of said activity. The invention further schedules a request for allocation of said resources on behalf and in advance of starting execution of said activity. This approach reduces the execution time of the activity as all resources required by the activity will be available when execution of the activity begins; the activity does not have to wait for these resources. Moreover, a WFMS knowing the required resources of the activities it is administrating is able to schedule resource requests to avoid resource conflicts between the activities. | 2009-03-19 |
20090077381 | SYSTEMS AND METHOD FOR THE TRANSPARENT MANAGEMENT OF DOCUMENT RIGHTS - Systems and methods are described for enabling documents to be controlled by a sender, in a manner which is transparent to any end recipients. The invention include mechanisms enabling a sender to control documents sent to recipient, in a manner that (1) encrypts the message to ensure its security, and (2) restricts operations the recipient may perform on the received message. The recipient and sender need not agree on a control protocol in advance of the communication. Wide distribution of a Digital Rights Management System may be facilitated by use of self-installing modules, which integrate with existing software used for document publishing and retrieval. The modules are forwarded to unregistered recipients upon authentication of the recipient, and install automatically on the recipient's computer. The modules authenticate instructions from a sender, and, per instructions from the sender, may pre-empt certain types of operations on the e-mail by the recipient | 2009-03-19 |
20090077382 | METHOD FOR THE PREPARATION OF A CHIP CARD FOR ELECTRONIC SIGNATURE SERVICES - The invention relates to a method for preparing a chip card for electronic signature services. According to said method, data is exchanged between a chip card user and a signature portal, an asymmetric pair of keys and a signature PIN that is associated with the asymmetric pair of keys being generated on the chip card by means of a software application which can be executed on the chip card, and the chip card communicating the signature PIN to the user. | 2009-03-19 |
20090077383 | SYSTEM AND METHOD FOR AUTHENTICATION, DATA TRANSFER, AND PROTECTION AGAINST PHISHING - Methods and systems for secure electronic data communication over public communication networks. A secure data communication component may be utilized to implement a communication protocol. New versions of the data communication component may be generated, with each version containing a different communication protocol. Source code of the data communication component may be modified using a polymorph engine to create a functionally-equivalent component having a different code structure. An anti-phishing component may intercept a link in an electronic communication activated by a user, analyze the link and the electronic communication, determine a phishing risk to the user posed by the link, and direct the user to a location indicated by the link or redirect the user to a valid location. A server authentication component may detect and prevent DNS attacks, injections, and defacing activities. | 2009-03-19 |
20090077384 | Accelerated signature verification on an elliptic curve - A public key encryption system exchanges information between a pair of correspondents. The recipient performs computations on the received data to recover the transmitted data or verify the identity of the sender. The data transferred includes supplementary information that relates to intermediate steps in the computations performed by the recipient. | 2009-03-19 |
20090077385 | Authenticating An Object - A method of authenticating an object is disclosed. The method starts by receiving indicating data. The indicating data was generated in response to sensing of a coded data portion provided on or in a surface associated with the object. The indicating data is indicative of an identity, a position of the coded data portion, and a fragment of a signature. The signature is a digital signature of at least the identity, and comprises a plurality of signature fragments. The method then proceeds by determining from the indicating data, a received identity, a received signature fragment and the position of the coded data portion. Using the position, a received signature fragment identifier is then determined. Next, using the received identity, a determined signature is determined. A determined signature fragment is also determined using the determined signature and the received signature fragment identifier. Finally, the determined signature fragment is compared to the received signature fragment, and the object is authenticated using the result of the comparison. | 2009-03-19 |
20090077386 | NOTARY ENFORCEMENT - FRAUD PREVENTION - A system for electronically signing a document and verifying the signor's identity includes a computer having a processor, an input device, and a memory. A biometric scanner is in electronic communication with the computer for scanning at least one biometric feature of a signor. An instruction set is stored within the memory for execution by the processor wherein execution of at least a portion of the instruction set operates to create an electronic signature and integrates at least one biometric characteristic of the biometric feature within the electronic signature. | 2009-03-19 |
20090077387 | Authenticating Software Using Protected Master Key - A processing unit includes a read-only encryption key. Software is loaded into a system memory area from a non-volatile storage device. Software code image that resides in the system storage area includes a prefix value and a suffix value. The prefix value is combined with the master key from the processing unit to create a random value that is the seed for a hashing algorithm. The hashing algorithm uses the seed value with a signature formed from the blocks of code to form a result. Finally, after the last block has been processed, a final result remains. The suffix value is combined with the master key, this hash result is compared with the result that was created using the hashing algorithm on the code. If the two results match, the code is authenticated and is executed. If the results do not match, the code is not loaded. | 2009-03-19 |
20090077388 | INFORMATION PROCESSING APPARATUS AND COMPUTER READABLE MEDIUM - An information processing apparatus includes an information acceptance unit, a calculation unit and an encryption unit. The information acceptance unit accepts information relevant to a program. The calculation unit calculates one of a one-way function and a pseudo one-way function using one of the information relevant to the program accepted by the information acceptance unit and a part of the information. The encryption unit performs encryption processing for one of code of the program and the conversion result of the code and a part thereof using one of the calculation result of the calculation unit and a part of the result. | 2009-03-19 |
20090077389 | SECURITY FEATURES IN AN ELECTRONIC DEVICE - A method of establishing security in an electronic device. The method includes generating a statistically unique root key value and storing the root key value in a one-time programmable memory of the device. The method also includes isolating firmware in the device from access to the root key value. The root key value is used as a root of trust that ensures that each electronic device has its own key. In general, the root key is used to encrypt other keys in the device. In different aspects, a root key test value, which is utilized to test the root key, and other security features such as a re-purpose number and a cipher block chaining re-purpose value are included to protect the electronic device from unauthorized access. An electronic device that includes these security features is also provided. | 2009-03-19 |
20090077390 | Electronic file protection system having one or more removable memory devices - The electronic file protection system includes at least one first memory device removably disposable in communicative relation with one or more computers, wherein the first memory device includes a unique identifier. The system further includes unique, non-reproducible encryption key data disposed or otherwise saved on the first memory device. The encryption key data is structured to be utilized in conjunction with at least one encryption algorithm so as to at least partially protect the electronic file, or otherwise orient the electronic file in an encrypted mode. Further, the unique identifier is reproducible and disposable in associated relation with a replacement memory device. | 2009-03-19 |
20090077391 | Method and apparatus for protecting data during storage/retrieval - For protecting data during transmission between a host device and a data storage device, the host device encrypts command-related information and sends the encrypted command-related information to the data storage device. The data storage device decrypts the encrypted command-related information, interprets the decrypted command-related information to generate interpreted commands, and executes the interpreted commands. | 2009-03-19 |
20090077392 | COMPUTER APPARATUS, STORAGE APPARATUS, SYSTEM MANAGEMENT APPARATUS, AND HARD DISK UNIT POWER SUPPLY CONTROLLING METHOD - To provide a storage system capable of minimizing a performance deterioration, saving power consumption, and realizing a high reliability. A storage system according to the present invention includes a computer, a storage apparatus | 2009-03-19 |
20090077393 | CARD-TYPE ELECTRONIC DEVICE AND HOST DEVICE - A card type electronic device according to the present invention comprises a p MOS switch ( | 2009-03-19 |
20090077394 | TECHNIQUES FOR COMMUNICATIONS BASED POWER MANAGEMENT - Techniques for communications based power management are described. An apparatus may comprise a managed power system having a communications sub-system and a computing sub-system, the communications sub-system to include a network state module operative to determine communications power state information, and send a power management message with the communications power state information. The apparatus may further comprise a power management module to receive the power management message, retrieve the communications power state information from the power management message, and manage power states for the computing sub-system based on the communications power state information. Other embodiments are described and claimed. | 2009-03-19 |
20090077395 | TECHNIQUES FOR COMMUNICATIONS POWER MANAGEMENT BASED ON SYSTEM STATES - Techniques for communications based power management based on system states are described. An apparatus may comprise a communications sub-system having a control policy module, a controller and a first transceiver capable of operating at different communications rates. The control policy module may be operative to receive computing power state information and communications state information, determine a communications rate parameter for the first transceiver based on the computing power state information and the communications state information, and instruct the controller to modify a communications rate for the first transceiver based on the communications rate parameter. Other embodiments are described and claimed. | 2009-03-19 |
20090077396 | TECHNIQUES FOR COLLABORATIVE POWER MANAGEMENT FOR HETEROGENEOUS NETWORKS - Techniques for collaborative power management for heterogeneous networks are described. An apparatus may include a first node having a managed power system and a power management module to manage power states for the managed power system. The power management module may be operative to communicate power state information with a second node over a communications connection, and manage the power states for the managed power system based on power state information for the second node. Other embodiments are described and claimed. | 2009-03-19 |
20090077397 | USER INTERFACE FOR DEMAND SIDE ENERGY MANAGEMENT - A user interface is visibly displayed on a display device operatively connected to a first computer. The user interface enables an end user to enter at least one energy management rule for each of a plurality of electrical loads at a location, each rule including a command to be transmitted to the electrical load associated with the rule if a condition is met. The energy management rules for each of the plurality of electrical loads are received by a second computer. An energy management profile containing the energy management rules for each of the plurality of electrical loads at the location is created and stored using a second computer. The energy management profile is activated using the second computer. For each of the energy management rules where the condition has been met, the command associated with the rule is transmitted to the electrical load associated with the rule. | 2009-03-19 |
20090077398 | Workload Apportionment According to Mean and Variance - An improved method is provided for managing workload on a multi-server computer system. In one embodiment, a subset of servers is selected according to an anticipated net workload. The remaining servers in the system may be powered off to conserve energy and prolong equipment life. Workload is dynamically apportioned among the subset of servers at selected intervals to more uniformly distribute the mean and variance of the workload among the subset of servers. More particularly, the mean and the variance for each of a plurality of workload units are equally weighed in determining a ranking of the workload units. The workload units may be ordered according to a mathematical combination of the mean and variance, such as the sum or product of mean and variance for each workload unit. The workload units are allocated among the subset of servers in according to rank, such as by assigning the workload units to the servers in a reverse round-robin fashion according to rank. Predictive power management schemes such as DVS and DVFS may then be used to control power to the servers. | 2009-03-19 |
20090077399 | CONTROLLING APPARATUS, CONTROLLING METHOD, COMPUTER READABLE MEDIUM, IMAGE FORMING APPARATUS AND INFORMATION PROCESSING APPARATUS - The controlling apparatus is provided with: a memory that stores application software; a setting part that sets an operational manner related to power consumption of an apparatus running the application software, corresponding to the application software stored in the memory; and a controller that controls the power consumption of the apparatus according to the operational manner set by the setting part. | 2009-03-19 |
20090077400 | POWER CONTROL SYSTEM - A power mode designating unit of a main system outputs an operation mode designating signal to a sub system. Upon shifting from the normal operation mode to the power-saving mode, a control unit of the sub system outputs a power-saving mode shift enable signal indicating that shifting to the power-saving mode is possible to a power control unit of the sub system. When the operation mode designating signal designates the power-saving mode and the power-saving mode shift enable signal indicates that shifting to the power-saving mode is possible, the power control unit supplies a power-saving mode voltage to the control unit. | 2009-03-19 |
20090077401 | BUFFERING TECHNIQUES FOR POWER MANAGEMENT - Buffering techniques for power management are described. A method may comprise modifying a power state for a communications sub-system and a computing sub-system from a higher power state to a lower power state, storing packets of information in a buffer for the communications sub-system during a communications idle duration period, generating a variable receive threshold value for the buffer, and transferring the stored packets of information from the buffer to the computing sub-system based on a variable receive threshold value. Other embodiments are described and claimed. | 2009-03-19 |
20090077402 | Voltage-controlled device, method and computer device capable of dynamically regulating voltage and effectively saving energy - The invention provides a voltage-controlled device, method and computer device capable of dynamically regulating voltage and effectively saving energy. The voltage-controlled device receives a VID from a CPU, determines a core voltage according to a load line defined therein, and supplies the core voltage to the CPU. The voltage-controlled device has a load line register set and a write logic. The load line register set has a plurality of registers, and the values of which represent the defined load line. The write logic changes the values of the registers in the load line register set according to a write signal. | 2009-03-19 |
20090077403 | Integrated device, layout method thereof, and program - An integrated device includes at least one data processing device and at least one memory macro accessible by the data processing device. The data processing device and the memory macro are laid out so that a memory address and a power consumption have a correlation. | 2009-03-19 |
20090077404 | Method and system of reducing power consumption of system on chip based on analog-to-digital control circuitry - Methods and system of reducing power consumption of system on chip based on analog-to-digital control circuitry are disclosed. In one embodiment, a method includes converting an analog signal of external device coupled to the system on chip to a digital signal using an analog-to-digital converter (ADC) of the system on chip with a processor of the system on chip in a sleep mode or power down mode. The method further includes waking up the processor of the system on ship to perform an exception event based on a comparison of the digital signal with a threshold value associated with the external device. | 2009-03-19 |
20090077405 | AUDIO-VISUAL SYSTEM ENERGY SAVINGS USING A MESH NETWORK - In embodiments of the present invention, improved capabilities are described for powering, controlling, and operating a home audio visual system using a mesh network that includes an energy savings mode based at least in part on intermittently powered mesh network nodes that are associated with the home audio-visual system. In embodiments, the intermittently powered mesh network nodes may periodically wake up, listen for wake up calls and/or initiate a full power mode in the home audio visual system when a intermittently power mesh network node is awakened and receives a subsequent full power instruction. Intermittently powered mesh network nodes may be further associated with instruction routing that utilizes silent acknowledgement. | 2009-03-19 |
20090077406 | Computer, Power Saving Method And Method For Reducing Output Current Of A Web Camera - A computer, a power saving method and a method for reducing output current are disclosed. The computer includes a driving module, an application module, and a daemon module. The driving module initializes the web camera when the web camera connects to the computer. When the web camera outputs signals to the application module, a signal channel is established. The daemon module detects the signal channel. When the signal channel stops, the daemon module set the web camera into the standby mode through the driving module. | 2009-03-19 |
20090077407 | Apparatus, system and method for power management - An apparatus which communicates with another apparatus includes a control unit which monitors a power consumption of the apparatus, supplies a power to the another apparatus when the power consumption includes a surplus, and requests the another apparatus to supply the power when the power consumption includes a shortage, and an adjusting unit which adjusts the power consumption of the apparatus according to an operation of the control unit. | 2009-03-19 |
20090077408 | INFORMATION PRESERVATION ON A PORTABLE ELECTRONIC DEVICE - A system and method for information preservation on a portable electronic device is disclosed. A signal indicating an energy capacity threshold remaining in the battery of a hand held device may be generated. Then, responsive to such a signal, information may be copied from a volatile memory into a non-volatile memory. The non-volatile memory may be configured to provide instructions for direct execution by a processor, or the non-volatile storage may be attached via an expansion interface. The non-volatile memory may be a removable card. The copy function is typically done in low power modes. Alternatively, the information is only copied provided sufficient battery capacity remains to perform the copy function. | 2009-03-19 |
20090077409 | CIRCUITS TO DELAY A SIGNAL FROM A MEMORY DEVICE - A circuit for delaying an input control signal, comprises a clock circuit to generate a clock signal having a frequency different from an input clock signal to delay and including a clock signal input, a derivative clock signal output, an input to program a frequency ratio between its input clock frequency and its output clock frequency. A clock capturing circuit provides a determined number of delay elements required to provide a delay of an amount of the period of the signal provided by the clock circuit. A delay calculation circuit receives the determined number of delay elements and calculates a number of delay elements needed to delay the input control signal by an amount of time. A delay circuit includes a control signal input, a select input for receiving the number of delay elements provided by the delay calculation circuit. | 2009-03-19 |
20090077410 | METHOD FOR SETTING ACTUAL OPERTATION FREQUENCY OF MEMORY AND SETTING MODULE THEREOF - A method for setting an actual operation frequency of a memory is provided. The method includes the following steps. First, a memory model list is provided for selecting a memory model. Then, an estimation operation frequency of the memory is obtained according to the selected model. Finally, the operation frequency of a front side bus (FSB) is adjusted and cooperated with a frequency transformation ratio to generate the actual operation frequency of the memory according to the estimation operation frequency. | 2009-03-19 |
20090077411 | MEMORY CONTROL CIRCUIT, DELAY TIME CONTROL DEVICE, AND DELAY TIME CONTROL METHOD - A memory control circuit has a write leveling function and controls read/write operations by supplying a clock signal to a plurality of memories through a clock signal line which is wired to the plurality of memories through daisy chain connection. For each of the plurality of memories, a first variable delay unit delays, in a write operation, a data strobe signal output to the memory by a first delay time that is set by utilizing the write leveling function and a second variable delay unit delays, in a read operation, a data signal input from the memory by a second delay time that is set based on the first delay time. | 2009-03-19 |
20090077412 | Administering A System Dump On A Redundant Node Controller In A Computer System - Administering a system dump on a redundant node controller including detecting a communications failure between a system controller and the redundant node controller; generating a unique identifier for the communications failure; instructing a primary node controller to provoke a system dump on the redundant node controller; provoking the system dump on the redundant node controller including suspending a processor of the redundant node controller and storing during the suspension of the processor the unique identifier for the communications failure and an instruction to execute the system dump on the redundant node controller; releasing the processor of the redundant node controller from suspension; in response to releasing the processor from suspension, identifying the unique identifier for the communications failure and the instruction to execute the system dump; and executing the system dump including associating the system dump with the unique identifier. | 2009-03-19 |
20090077413 | APPARATUS, SYSTEM, AND METHOD FOR SERVER FAILOVER TO STANDBY SERVER DURING BROADCAST STORM OR DENIAL-OF-SERVICE ATTACK - An apparatus, system, and method are disclosed to failover to a standby server when a primary server is under broadcast storm or denial-of-service (“DoS”) attack. A primary attack sensing module is included to monitor a rate of incoming data from a computer network to a primary server and to determine if the rate of incoming data is above a primary data rate threshold. A standby contact module is included to request a standby data rate status from a standby server in response to the primary attack module determining that the rate of incoming data to the primary server is above the primary data rate threshold. The standby server is connected to the primary server over a private network. The standby data rate status includes a determination by the standby server of whether a rate of data received by the standby server is above a standby data rate threshold. A standby receiver module is included to receive a standby data rate status from the standby server over the private network. A switchover module is included to deactivate the primary server and to send a command to activate the standby server as a primary server in response to the received standby data rate status indicating that the rate of data received by the standby server has not exceeded the standby data rate threshold. | 2009-03-19 |
20090077414 | APPARATUS AND PROGRAM STORAGE DEVICE FOR PROVIDING TRIAD COPY OF STORAGE DATA - An apparatus and program storage device for maintaining data is provided that includes receiving primary data at a first node, receiving mirrored data from a second and third node at the first node, and mirroring data received at the first node to a second and third node. | 2009-03-19 |
20090077415 | CONTROL FLOW PROTECTION MECHANISM - A method is provided of protecting a program executing on a device at least to some extent from execution flow errors caused by physical disturbances, such as device failures and voltage spikes, that cause program execution to jump to an unexpected memory location. The executing program follows an execution path that proceeds through a plurality of regions (B′[m], B′[f]). A first check value (wisb) is provided at a randomly accessible memory location. It is determined at least once (e.g. in TERM[m]) in at least one region (B′[m]) whether the first check value (wisb) has an expected value (s[m]) for that region (B′[m]). The first check value (wisb) is updated (e.g. in “set-up for call to f”), as execution passes from a first region (B′[m]) into a second region (B′[f]) in which such a determination is made, so as to have a value (s[f]) expected in the second region (B′[f]). An error handling procedure is performed if such a determination is negative. | 2009-03-19 |
20090077416 | METHOD FOR MANAGING A DATA STORAGE SYSTEM - A RAID storage system is provided with a plurality of disk drive modules in communication with a processor through a RAID controller. Tools and processes are provided for managing failure of individual modules in the RAID, identifying and managing excess spare modules, and migrating modules among array sites to produce uniform or near-uniform array sites. | 2009-03-19 |
20090077417 | METHOD, DATA PROCESSING APPARATUS AND WIRELESS DEVICE - Embodiments of the invention relate generally to a method, to a data processing apparatus and to a wireless device. In an embodiment of the invention a data processing apparatus is provided. The data processing apparatus may include a chip-integrated unit to select a check location of an external memory and to generate a check value, an internal memory associated with the chip-integrated unit, the internal memory to save the check location and the check value, and an external memory coupled to the chip-integrated unit, the external memory to store the check value at the check location. | 2009-03-19 |
20090077418 | Control of Sparing in Storage Systems - Embodiments include methods, apparatus, and systems for controlling of sparing in a storage system. In one embodiment, a method compares a first amount of time to complete sparing of data from a failed disk in a storage system with a second amount of time to complete a user request to the storage system in order to determine when to create a copy of the data from the failed disk. | 2009-03-19 |
20090077419 | Monitoring System with Trusted Corrective Actions - A system and computer program product for monitoring a data processing system is proposed. The system and computer program product involve the measuring of state parameters of the system. Indicators of the performance of the system are then inferred from the state parameters by applying fuzzy-logic rules. The proposed solution is based on the idea of estimating a trust value, based on the effectiveness of the corrective actions. If the previous corrective actions prove to be effective than the trust value is enhanced and the system is allowed a higher level of autonomy. Otherwise the intervention of an operator might be invoked. | 2009-03-19 |