12th week of 2009 patent applcation highlights part 46 |
Patent application number | Title | Published |
20090075413 | Nitride semiconductor light emitting device, method of manufacturing nitride semiconductor light emitting device, and nitride semiconductor transistor device - Provided are a nitride semiconductor light emitting device including a coat film formed at a light emitting portion and including an aluminum nitride crystal or an aluminum oxynitride crystal, and a method of manufacturing the nitride semiconductor light emitting device. Also provided is a nitride semiconductor transistor device including a nitride semiconductor layer and a gate insulating film which is in contact with the nitride semiconductor layer and includes an aluminium nitride crystal or an aluminum oxynitride crystal. | 2009-03-19 |
20090075414 | BIOCHIP AND METHOD OF FABRICATION - A method of fabricating a biochip and a biochip fabricated by the method are provided. The method can include providing a substrate including a plurality of first areas separated from each other by a second area, forming a plurality of activation patterns on each of the first areas, coupling a plurality of probes to each of the activation patterns, and cutting the substrate along the second area to form a plurality of chips. | 2009-03-19 |
20090075415 | Method for manufacturing semiconductor device - The present invention provides a method for manufacturing a semiconductor device which has an integrated circuit provided on a semiconductor substrate and a movable part which is movable relative to the substrate. This manufacturing method includes: a step of covering the movable part with a sacrificial film; a step of covering the sacrificial film with a first sealing layer which is formed of a material having a tensile stress; a step of forming a through-hole in the first sealing layer; a step of removing the sacrificial film through the through-hole to form a void around the movable part; and a step of film-forming a second sealing layer on the first sealing layer to close the through-hole. | 2009-03-19 |
20090075416 | Semiconductor imaging device and fabrication process thereof - A semiconductor imaging device includes a photodetection region formed of a diffusion region of a first conductivity type formed in an active region of a silicon substrate at a first side of a gate electrode such that a top part thereof is separated from a surface of the silicon substrate and such that an inner edge part invades underneath a channel region right underneath the gate electrode, a shielding layer formed of a second conductivity type at a surface of the silicon substrate at the first side of the gate electrode such that an inner edge part thereof is aligned with a sidewall surface of the gate electrode at the first side, a floating diffusion region formed in the active region at a second side of the gate electrode, and a channel region formed right underneath said gate electrode, wherein the channel region includes a first channel region part formed adjacent to the shielding layer and a second channel region part formed adjacent to the floating diffusion region, wherein the second channel region part contains an impurity element with a concentration level lower than the impurity concentration level of the first channel region part. | 2009-03-19 |
20090075417 | SOLID-STATE IMAGING DEVICE AND METHOD FOR PRODUCING THE SAME - In the solid-state imaging device of the present invention having a photoelectric conversion section and a charge transfer section equipped with a charge transfer electrode for transferring an electric charge generated in the photoelectric conversion section, the charge transfer electrode has an alternate arrangement of a first layer electrode comprising a first layer electrically conducting film and a second layer electrode comprising a second layer electrically conducting film, which are formed on a gate oxide film comprising a laminate film consisting of a silicon oxide film and a metal oxide thin film, and the first layer electrode and the second layer electrode are separated by insulation with an interelectrode insulating film comprising a sidewall insulating film formed by a CVD process to cover the lateral wall of the first layer electrode. | 2009-03-19 |
20090075418 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THEREOF AS WELL AS DRIVING METHOD OF SOLID-STATE IMAGING DEVICE - A solid-state imaging device with a structure such that an electrode for reading a signal charge is provided on one side of a light-receiving sensor portion constituting a pixel; a predetermined voltage signal V is applied to a light-shielding film formed to cover an image pickup area except the light-receiving sensor portion; a second-conductivity-type semiconductor area is formed in the center on the surface of a first-conductivity-type semiconductor area constituting a photo-electric conversion area of the light-receiving sensor portion; and areas containing a lower impurity concentration than that of the second-conductivity-type semiconductor area is formed on the surface of the first-conductivity-type semiconductor area at the end on the side of the electrode and at the opposite end on the side of a pixel-separation area. | 2009-03-19 |
20090075419 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD FOR THE SAME - A solid-state imaging device includes a semiconductor substrate including: a plurality of light-receptive portions that are arranged one-dimensionally or two-dimensionally; a vertical transfer portion that transfers signal electric charge read out from the light-receptive portions in a vertical direction; a horizontal transfer portion that transfers the signal electric charge transferred by the vertical transfer portion in a horizontal direction; a barrier region adjacent to the horizontal transfer portion, the barrier region letting only surplus electric charge of the horizontal transfer portion pass therethough; a drain region adjacent to the barrier region, into which the surplus electric charge passing through the barrier region is discharged; and an insulation film adjacent to the drain region. A portion of the drain region is located beneath the insulation film. | 2009-03-19 |
20090075420 | METHOD OF FORMING CHALCOGENIDE LAYER INCLUDING TE AND METHOD OF FABRICATING PHASE-CHANGE MEMORY DEVICE - The method of forming a Te-containing chalcogenide layer includes radicalizing a first source that contains Te to form a radicalized Te source, and forming a Te-containing chalcogenide layer by supplying the radicalized Te source into a reaction chamber. A method fabricating a phase change memory device includes loading a substrate on which a lower electrode is formed into a reaction chamber, radicalizing a first source that contains Te to form a radicalized Te source, forming a phase change material film containing Te on the lower electrode by supplying the radicalized Te source into the reaction chamber, and forming an upper electrode on the phase change material film. | 2009-03-19 |
20090075421 | Wet etching of zinc tin oxide thin films - A method of wet etching semiconductor zinc tin oxide includes submerging a semiconductor zinc tin oxide film in a bath solution. The film is partially covered with a pattern of protective material, and the bath solution etches semiconductor zinc tin oxide film not covered by the protective material. A system for wet etching semiconductor zinc tin oxide includes a bath containing a bath solution. The bath solution is effective to wet etch the semiconductor zinc tin oxide. | 2009-03-19 |
20090075422 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An internal connecting terminal | 2009-03-19 |
20090075423 | METHOD OF BONDING CHIPS ON A STRAINED SUBSTRATE AND METHOD OF PLACING UNDER STRAIN A SEMICONDUCTOR READING CIRCUIT - The invention concerns a method of collective bonding of individual chips on a strained substrate ( | 2009-03-19 |
20090075424 | Process for making microelectronic element chips - Apparatus including a chip substrate having a first chip surface facing away from a second chip surface; an array of microelectronic elements on the first chip surface; and an array of conductors each in communication with one of the microelectronic elements, the conductors passing through the chip substrate and fully spanning a distance between the first and second chip surfaces. Process including: providing an apparatus including a chip substrate having a first chip surface facing away from a second chip surface, an array of microelectronic elements being on the first chip surface, an array of conductors each being in communication with one of the microelectronic elements and partially spanning an average distance between the first and second chip surfaces; bonding a temporary support carrier onto the array of microelectronic elements; removing a portion of the chip substrate, thereby reducing the average distance between the first and second chip surfaces; and forming an under bump metallization pad at the second chip surface in electrical communication with a conductor. | 2009-03-19 |
20090075425 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The adhesive property of the mold resin exposed to the ball face side of a semiconductor package and under-filling resin is improved, and the manufacturing method of the semiconductor device which can prevent peeling at both interface is obtained. The sputtering step which does sputtering of the ball face side of the semiconductor package whose mold resin in which wax or fatty acid was included exposed to the ball face side by Ar plasma, the step which does flip chip junction of the semiconductor package at wiring substrate upper part after the sputtering step, and the step fills up with under-filling resin between the semiconductor package and the wiring substrate are included. | 2009-03-19 |
20090075426 | Method for Fabricating Multi-Chip Stacked Package - A multi-chips stacked package method which includes providing a lead frame includes a top surface and a reverse surface formed by a plurality of inner leads and a plurality of outer leads; fixing a first chip on the reverse surface of the lead frame and the active surface of the first chip includes a plurality of first pads closed to the central region; forming a plurality of first metal wires, and the first pads are electrically connected to the first inner leads and the second inner leads by the first metal wires; forming a plurality of metal spacers on the thermal fin of the lead frame; fixing a second chip to electrically connect to the top surface of the first inner leads and the second inner leads; forming a plurality of second metal wires, and the second pads are electrically connected to the top surface of the first inner leads and the second inner leads; and flowing a molding to form an encapsulated material to cover the first chip, the first metal wires, the second chip, the second metal wires, the first inner leads and the second inner leads and the outer leads being exposed. | 2009-03-19 |
20090075427 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding. Accordingly, when cutting the suspending leads, corner portions of the back surface of the sealing body can be supported by a flat portion of a holder portion in a cutting die which flat portion has an area sufficiently wider than a cutting allowance of the suspending leads, whereby it is possible to prevent chipping of the resin and improve the quality of the semiconductor device (QFN). | 2009-03-19 |
20090075428 | ELECTROMAGNETIC SHIELD FORMATION FOR INTEGRATED CIRCUIT DIE PACKAGE - Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure. | 2009-03-19 |
20090075429 | Sheet-Like Underfill Material and Semiconductor Device Manufacturing Method - A sheet-like underfill material includes a base and adhesive layer provided peelably on the base for use in a flip chip mounting process in the manufacture of a semiconductor device. The process includes laminating a sheet-like underfill material onto a circuit face of a semiconductor wafer having bumps on its circuit face and, simultaneously, allowing the bumps to pierce the adhesive layer and allowing the tops of the bumps to penetrate the base. The base has a storage elastic modulus of 1.0×10 | 2009-03-19 |
20090075430 | THERMAL INTERMEDIATE APPARATUS, SYSTEMS, AND METHODS - Apparatus and system, as well as fabrication methods therefor, may include a thermal intermediate structure comprised of a plurality of carbon nanotubes some of which have organic moieties attached thereto to tether the nanotubes to at least one of a die and a heat sink. The organic moieties include thiol linkers and amide linkers. | 2009-03-19 |
20090075431 | Wafer level package with cavities for active devices - According to one exemplary embodiment, a method for forming a wafer level package includes fabricating an active device on a substrate in a semiconductor wafer, forming polymer walls around the active device, and applying a blanket film over the semiconductor wafer and the polymer walls to house the active device in a substantially enclosed cavity formed by the polymer walls and the blanket film. By way of examples and without limitation, the active device can be a microelectromechanical systems (“MEMS”) device, a bulk acoustic wave (“BAW”) filter, or a surface acoustic wave (“SAW”) filter. According to one embodiment, solder bumps can be applied to interconnect traces of the active device, and the semiconductor wafer can then be diced to form an individual die. According to another embodiment, the semiconductor wafer can be diced to form an individual die, then the individual die is wire bonded to a circuit board. | 2009-03-19 |
20090075432 | SEMICONDUCTOR MEMORY DEVICE - In a multiport SRAM memory cell of the present invention, an access transistor of a first port is disposed in a p-type well, and an access transistor of a second port is disposed in a p-type well. The gates of all of transistors disposed in a memory cell extend in the same direction. With the configuration, a semiconductor memory device having a low-power consumption type SRAM memory cell with an increased margin of variations in manufacturing, by which a bit line can be shortened in a multiport SRAM memory cell or an associative memory, can be obtained. | 2009-03-19 |
20090075433 | Manufacturing Method of Semiconductor Device - A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area includes a first base layer of a second conductivity type, a source layer and a control electrode formed in the first base layer and the source layer. The device also includes a terminating portion formed in the drift layer including a second base layer of a second conductivity type, an impurity diffused layer of a second conductivity type, and a metallic compound whose end surface on the terminating portion side is positioned on the cell portion side away from the end surface of the impurity diffused layer on the terminal portion side. | 2009-03-19 |
20090075434 | METHOD OF REMOVING DEFECTS FROM A DIELECTRIC MATERIAL IN A SEMICONDUCTOR - A method of forming a semiconductor device includes forming a high dielectric constant material over a semiconductor substrate, forming a conductive material over the high dielectric constant material, and performing an anneal in a non-oxidizing ambient using ultraviolet radiation to remove defects in the high dielectric constant material. Examples of a non-oxidizing ambient include for example nitrogen, deuterium, a deuterated forming gas (N | 2009-03-19 |
20090075435 | JFET With Built In Back Gate in Either SOI or Bulk Silicon - A process for manufacturing a Junction Field-Effect Transistor, comprises doping a semiconductor material formed on an insulating substrate with impurities of a first conductivity type to form a well region. The process continues by implanting impurities of a second conductivity type into said well region to form a channel region, and by implanting impurities of the first conductivity type in said well region to form a back gate region. The process continues by forming a trench to expose at least one sidewall of said channel region, wherein the trench extends far enough along the sidewall to expose at least a portion of said back gate region. The process continues by depositing polysilicon to fill said trench along the at least one sidewall of said channel region and at least a portion of said back gate region, wherein at least a portion of the polysilicon will form a gate contact. The polysilicon is then doped with impurities of a first conductivity type. The process concludes by annealing the polysilicon to activate the doped impurities and to cause the doped impurities to diffuse along the at least one sidewall of said channel region so as to form a top gate region. The top gate region extends far enough to make electrical contact with said back gate region. | 2009-03-19 |
20090075436 | METHOD OF MANUFACTURING A THIN-FILM TRANSISTOR - A method of manufacturing a thin-film transistor (TFT) includes forming an amorphous silicon layer on a substrate, crystallizing the amorphous silicon layer into a polycrystalline silicon layer using a laser beam, and selectively etching a protrusion formed at a grain boundary in the polycrystalline silicon layer using a hydroxide etchant. | 2009-03-19 |
20090075437 | THIN FILM TRANSISTOR MANUFACTURING METHOD AND SUBSTRATE STRUCTURE - A method of TFT (Thin Film Transistor) manufacturing and a substrate structure are provided. The structure includes a substrate and a self-alignment mask. A self-alignment mask on a substrate is first manufactured and then the self-alignment mask may synchronously extend with the substrate during the thermal process. When an exposure light source is provided on the side without a TFT formed, the self-alignment mask can overcome the problem that when a plastic substrate extends, the positions of the source and drain to be formed on the plastic substrate are incorrect, which has a great effect on the accuracy of alignment. As the result, the positions of the source and drain can be defined accurately. | 2009-03-19 |
20090075438 | METHOD OF FABRICATING ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE - In a method of fabricating organic light emitting diode display, a planarization layer is annealed, cured, provided with an ashing treatment, and surface-treated to reduce roughness of the planarization layer. Therefore, it is possible to improve reduce problems such as a decrease in reflectivity and variation of color coordinates of the organic light emitting diode display due to the roughness of the planarization layer. | 2009-03-19 |
20090075439 | MICROELECTRONIC STRUCTURE BY SELECTIVE DEPOSITION - A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology. | 2009-03-19 |
20090075440 | DISPLAY AND MANUFACTURING METHOD THEREOF - A display includes a substrate, a control electrode formed on the substrate, input and output electrodes formed on the substrate having facing sides facing each other with respect to the control electrode, a semiconductor layer contacting the input and the output electrodes, and an insulating layer formed between the control electrode and the semiconductor layer. At least one of the facing sides of the input and output electrodes on the semiconductor layer has a plurality of protrusions. The channel between the input and output electrodes is formed with various shapes, the length of the channel is prevented from being extending by a skew phenomenon, and the width of the channel may be extended. | 2009-03-19 |
20090075441 | Method of removing a spacer, method of manufacturing a metal-oxide-semiconductor transistor device, and metal-oxide-semiconductor transistor device - A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer. | 2009-03-19 |
20090075442 | Metal Stress Memorization Technology - A semiconductor device and method for manufacturing a tensile strained NMOS and a compressive strained PMOS transistor pair, wherein a stressor material is sacrificial is disclosed. The method provides for a substrate, which includes a source/drain for an NMOS transistor, and a PMOS transistor. A first barrier layer is formed on the substrate and a first stressor material is formed on the first barrier layer. The first barrier layer is selectively removed from the PMOS transistor. The substrate is flash annealed and the remaining first stressor material and barrier layer is removed from the substrate. | 2009-03-19 |
20090075443 | METHOD OF FABRICATING FLASH MEMORY - A method of fabricating a flash memory includes providing a substrate with a mask layer thereon, forming pluralities of shallow trenches in the substrate, forming a first oxide layer on the substrate and in the shallow trenches, removing a portion of the first oxide layer above the mask layer, forming a second oxide layer on the mask layer and the first oxide layer, wherein the first and second oxide layers have different etching ratios, removing a portion of the second oxide layer positioned above the mask layer so that an STI is formed with the first and the second oxide layers in each shallow trench, removing the mask layer to form recess portions between adjacent STIs, and filling the recess portions with a conductive layer to form floating gates in the recess portions. | 2009-03-19 |
20090075444 | Method of forming semiconductor device having three-dimensional channel structure - A method of forming a semiconductor device is provided. A hollowed portion is formed over an active region of a semiconductor substrate. The bottom of the hollowed portion is lowered in level than the surface of an isolation region of the substrate. A first mask is formed in the hollowed portion, except on a side region that is adjacent to the boundary between the active region and the isolation region. A trench is formed in the side region of the active region by using the first mask and the isolation region as a mask. | 2009-03-19 |
20090075445 | Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress - A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form Si | 2009-03-19 |
20090075446 | METHOD OF FABRICATING A HETEROJUNCTION BIPOLAR TRANSISTOR - The invention provides a method for fabricating a heterojunction bipolar transistor with a base connecting region ( | 2009-03-19 |
20090075447 | Method and fabricating a mono-crystalline emitter - Fabrication of a mono-crystalline emitter using a combination of selective and differential growth modes. The steps include providing a trench ( | 2009-03-19 |
20090075448 | Method of Forming Inside Rough and Outside Smooth HSG Electrodes and Capacitor Structure - A container capacitor and method of forming the container capacitor are provided. The container capacitor comprises a lower electrode fabricated by forming a layer of doped polysilicon within a container in an insulative layer disposed on a substrate; forming a barrier layer over the polysilicon layer within the container; removing the insulative layer to expose the polysilicon layer outside the container; nitridizing the exposed polysilicon layer at a low temperature, preferably by remote plasma nitridation; removing the barrier layer to expose the inner surface of the polysilicon layer within the container; and forming HSG polysilicon over the inner surface of the polysilicon layer. The capacitor can be completed by forming a dielectric layer over the lower electrode, and an upper electrode over the dielectric layer. The cup-shaped bottom electrode formed within the container defines an interior surface comprising HSG polysilicon, and an exterior surface comprising smooth polysilicon. | 2009-03-19 |
20090075449 | INTEGRATED HIGH VOLTAGE CAPACITOR HAVING CAPACITANCE UNIFORMITY STRUCTURES AND A METHOD OF MANUFACTURE THEREFOR - The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate ( | 2009-03-19 |
20090075450 | Method of manufacturing stack-type capacitor and semiconductor memory device having the stack-type capacitor - A stack-type capacitor includes a lower electrode, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer, wherein the lower electrode includes a first metal layer having a cylindrical shape and a second metal layer filled in the first metal layer. In the capacitor, an amount of oxygen included in the lower electrode is decreased to suppress oxidation of a TiN layer. Thus, a stable stack-type capacitor may be formed, which increases greatly the performance of highly integrated DRAMs. | 2009-03-19 |
20090075451 | Method for manufacturing semiconductor substrate - The present invention provides a method for manufacturing a semiconductor substrate in which a semiconductor wafer, formed of a material less likely to increase the hole diameter, is processed to a semiconductor substrate actually applicable to an existing manufacture line. An SiC wafer | 2009-03-19 |
20090075452 | SUBSTRATE PROVIDED WITH AN ALIGNMENT MARK IN A SUBSTANTIALLY TRANSMISSIVE PROCESS LAYER, MASK FOR EXPOSING SAID MARK, DEVICE MANUFACTURING METHOD, AND DEVICE MANUFACTURED THEREBY - A substrate provided with an alignment mark in a substantially transmissive process layer overlying the substrate, said mark comprising high reflectance areas for reflecting radiation of an alignment beam of radiation, and low reflectance areas for reflecting less radiation of the alignment beam, wherein the high reflectance areas comprise at least one substantially linear sub-grating. In one example, a substantially linear sub-grating comprises a plurality of spaced square regions. | 2009-03-19 |
20090075453 | METHOD OF PRODUCING SEMICONDUCTOR SUBSTRATE - There is provided a method for suppressing the occurrence of defects such as voids or blisters even in the laminated wafer having an oxide film of a thickness thinner than the conventional one, wherein hydrogen ions are implanted into a wafer for active layer having an oxide film of not more than 50 nm in thickness to form a hydrogen ion implanted layer, and ions other than hydrogen are implanted up to a position that a depth from the surface side the hydrogen ion implantation is shallower than the hydrogen ion implanted layer, and the wafer for active layer is laminated onto a wafer for support substrate through the oxide film, and then the wafer for active layer is exfoliated at the hydrogen ion implanted layer. | 2009-03-19 |
20090075454 | Method and High Gapfill Capability for Semiconductor Devices - A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench. | 2009-03-19 |
20090075455 | Growing N-polar III-nitride Structures - Methods of forming a stable N-polar III-nitride structure are described. A Ga-polar device can be formed on a substrate. A carrier wafer is attached to the Ga-polar surface. The substrate is removed from the assembly. The N-polar surface that remains is offcut and, optionally, subsequent layers are formed on the offcut surface. | 2009-03-19 |
20090075456 | Method for manufacturing SOI substrate and method for manufacturing semiconductor device - A highly reliable semiconductor device capable of high speed operation is manufactured over a flexible substrate at a high yield. A separation layer is formed over an insulating substrate by a sputtering method; the separation layer is flattened by a reverse sputtering method; an insulating film is formed over the flattened separation layer; a damaged area is formed by introducing hydrogen or the like into a semiconductor substrate; an insulating film is formed over the semiconductor substrate in which the damaged area is formed; the insulating film formed over the insulating substrate is bonded to the insulating film formed over the semiconductor substrate, the semiconductor substrate is separated at the damaged area so that a semiconductor layer is formed over the insulating substrate; the semiconductor layer is flattened so as to form an SOI substrate; and the semiconductor device is formed over the SOI substrate. | 2009-03-19 |
20090075457 | MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS - Alignment patterns are formed in scribe regions of a semiconductor substrate, and through grooves for exposing the scribe regions are disposed in an insulating layer formed on the semiconductor substrate. Formation positions of wiring patterns are aligned based on the alignment patterns, and a metal layer is patterned and the wiring patterns are formed. | 2009-03-19 |
20090075458 | METHOD OF MANUFACTURING DEVICE HAVING ADHESIVE FILM ON BACK-SIDE SURFACE THEREOF - A method of manufacturing a device, including: an adhesive film attaching step of attaching an adhesive film to a back-side surface of a wafer in which devices are formed respectively in a plurality of regions demarcated by planned dividing lines formed in a grid pattern in a face-side surface of the wafer; a wafer supporting step of adhering the adhesive film side of the wafer with the adhesive film attached thereto to a surface of a dicing tape attached to an annular frame; a wafer cutting step of holding the dicing tape side of the wafer adhered to the surface of the dicing tape onto a chuck table of a cutting apparatus, and cutting the wafer along the planned dividing lines by use of a cutting blade having an annular knife edge which is V-shaped in sectional shape of a peripheral part thereof; and an adhesive film breaking step of breaking said adhesive film along cutting grooves formed in the wafer, by expanding the dicing tape so as to exert tension on the adhesive film, after the wafer cutting step is performed. | 2009-03-19 |
20090075459 | Apparatus and method for picking-up semiconductor dies - A die pick-up apparatus and method using a die stage having an adherence surface, a suction window formed in the adherence surface and larger than a semiconductor die to be picked up, and a cover plate that slides along the adherence surface and opens and closes the suction window. When picking up the semiconductor die, the surface of the cover plate is caused to be closely contacted to a dicing sheet that is attached to the die so that the die is within the boundary of the upper surface of the cover plate that closes the suction window, and then the dicing sheet is sequentially peeled off as, while the die is being suctioned by a collet, the cover plate gradually slides to sequentially open the suction window and allow the dicing sheet to be suctioned into the opened suction window. | 2009-03-19 |
20090075460 | PROCESS FOR FABRICATING SEMICONDUCTOR DEVICE - A process for fabricating a semiconductor device comprising the steps of introducing into an amorphous silicon film, a metallic element which accelerates the crystallization of the amorphous silicon film; applying heat treatment to the amorphous silicon film to obtain a crystalline silicon film; irradiating a laser beam or an intense light to the crystalline silicon film; and heat treating the crystalline silicon film irradiated with a laser beam or an intense light. | 2009-03-19 |
20090075461 | METHOD OF PROCESSING SEMICONDUCTOR WAFER - Formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed on the semiconductor substrate for at least three times to form all semiconductor layers, of the epitaxial layers. Thereby, impurity concentration profiles of the semiconductor layers can be uniform, and pn junctions can be formed vertically to a wafer surface. Furthermore, the semiconductor layers can each be formed with a narrow width, so that impurity concentrations thereof are increased. With this configuration, high breakdown voltage and low resistance can be achieved. | 2009-03-19 |
20090075462 | Method of Fabricating a Semiconductor Device - The invention relates to a method of fabricating an integrated circuit, including the steps of providing at least one layer; performing a first implantation step, wherein particles are implanted into the layer under a first direction of incidence; performing a second implantation step, wherein particles are implanted into the layer under a second direction of incidence which is different from the first direction of incidence; performing a removal step, wherein the layer is partially removed depending on the local implant dose generated by the first and the second implantation step. | 2009-03-19 |
20090075463 | METHOD OF FABRICATING T-GATE - A method of fabricating a T-gate is provided. The method includes the steps of: forming a photoresist layer on a substrate; patterning the photoresist layer formed on the substrate and forming a first opening; forming a first insulating layer on the photoresist layer and the substrate; removing the first insulating layer and forming a second opening to expose the substrate; forming a second insulating layer on the first insulating layer; removing the second insulating layer and forming a third opening to expose the substrate; forming a metal layer on the second insulating layer on which the photoresist layer and the third opening are formed; and removing the metal layer formed on the photoresist layer. Accordingly, a uniform and elaborate opening defining the length of a gate may be formed by deposition of the insulating layer and a blanket dry etching process, and thus a more elaborate micro T-gate electrode may be fabricated. | 2009-03-19 |
20090075464 | Semiconductor device and manufacturing method thereof - A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less. | 2009-03-19 |
20090075465 | METHODS OF FORMING A CONDUCTIVE INTERCONNECT IN A PIXEL OF AN IMAGER AND IN OTHER INTEGRATED CIRCUITRY - A method of forming conductive interconnects includes forming a node of a circuit component on a substrate. A conductive metal line is formed at a first metal routing level that is elevationally outward of the circuit component. Insulative material is deposited above the first metal routing level over the conductive metal line and the circuit component. In a common masking step, a first opening is etched through the insulative material to the conductive metal line and a second opening is etched through the insulative material to the node of the circuit component that is received elevationally inward of the conductive metal line. Conductive material is concurrently deposited to within the first and second openings in respective conductive connection with the conductive metal line and the node of the circuit component. A first metal line at a second metal routing level that is above the first metal routing level is formed in conductive connection with the conductive material in the first opening. A second metal line at the second metal routing level is formed in conductive connection with the conductive material in the second opening. | 2009-03-19 |
20090075466 | Method of manufacturing a non-volatile memory device - A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line. | 2009-03-19 |
20090075467 | METHOD FOR MANUFACTURING A FLASH MEMORY DEVICE - A method for forming a semiconductor device includes providing a substrate and forming conductor patterns and openings on the substrate. Next the openings are filled with a mask layer and upper portions of the conductor patterns are etched to form cavities. Following, a portion of the mask layer is removed to form a trench between two neighboring conductor patterns, wherein the trench exposes the substrate and the sidewalls of the two neighboring conductor patterns. Next, an insulating layer on the cavities and the trench is conformably formed, a second conductive layer is formed on the insulating layer and the trench is filled with the second conductive layer. | 2009-03-19 |
20090075468 | System and Process for Producing Nanowire Composites and Electronic Substrates Therefrom - The present invention relates to a system and process for producing a nanowire-material composite. A substrate having nanowires attached to a portion of at least one surface is provided. A material is deposited over the portion to form the nanowire-material composite. The process further optionally includes separating the nanowire-material composite from the substrate to form a freestanding nanowire-material composite. The freestanding nanowire material composite is optionally further processed into a electronic substrate. A variety of electronic substrates can be produced using the methods described herein. For example, a multi-color light-emitting diode can be produced from multiple, stacked layers of nanowire-material composites, each composite layer emitting light at a different wavelength. | 2009-03-19 |
20090075469 | THERMO-COMPRESSION BONDED ELECTRICAL INTERCONNECT STRUCTURE AND METHOD - An electrical structure and method for forming electrical interconnects. The method includes positioning a sacrificial carrier substrate such that a first surface of a non-solder metallic core structure within the sacrificial carrier substrate is in contact with a first electrically conductive pad. The first surface is thermo-compression bonded to the first electrically conductive pad. The sacrificial carrier substrate is removed from the non-solder metallic core structure. A solder structure is formed on a second electrically conductive pad. The first substrate comprising the non-solder metallic core structure is positioned such that a second surface of the non-solder metallic core structure is in contact with the solder structure. The solder structure is heated to a temperature sufficient to cause the solder structure to melt and form an electrical and mechanical connection between the second surface of the non-solder metallic core structure and the second electrically conductive pad. | 2009-03-19 |
20090075470 | Method for Manufacturing Interconnect Structures Incorporating Air-Gap Spacers - Methods for manufacturing air-gap (e.g., side wall air-gap) containing metal/insulator interconnect structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging comprise forming the air-gap spacers by deviating from a conventional dual-damascene etch process in order to avoid damage to the dielectric, and instead utilize intentional and controlled chemical damage of the Si, C, O, H containing dielectric by appropriate strip/ash etch chemistries after the trench etch and/or after via etch. The damaged dielectric layer is left in place after etch and the stack is taken through metallization and chemical mechanical planarization (CMP) processes. Subsequent to this, selective removal of the oxide-like damaged layer takes place by exposure to appropriate chemistries such as dilute HF, leaving behind air-gap spacers. Pinch-off cap deposition ensures integration of the air-gap for narrow air-gaps or perforated caps for wide air-gaps. | 2009-03-19 |
20090075471 | Method of manufacturing semiconductor memory device - A nonvolatile semiconductor memory device includes a semiconductor substrate, a first floating gate formed on a main surface of the semiconductor substrate, a second floating gate formed on the main surface of the semiconductor substrate, a first control gate formed on the first floating gate, a second control gate formed on the second floating gate, an interlayer insulating film, and a gap formed in the interlayer insulating film in at least a portion located between the first and second floating gates. Accordingly, a nonvolatile semiconductor memory device for which variations in threshold voltage of a memory cell can be suppressed and an appropriate read operation can be carried out, as well as a method of manufacturing the nonvolatile semiconductor memory device are provided. Further, a capacitance formed between interconnect lines can be reduced and the drive speed can be improved. | 2009-03-19 |
20090075472 | METHODS TO MITIGATE PLASMA DAMAGE IN ORGANOSILICATE DIELECTRICS - Methods of minimizing or eliminating plasma damage to low k and ultra low k organosilicate intermetal dielectric layers are provided. The reduction of the plasma damage is effected by interrupting the etch and strip process flow at a suitable point to add an inventive treatment which protects the intermetal dielectric layer from plasma damage during the plasma strip process. Reduction or elimination of a plasma damaged region in this manner also enables reduction of the line bias between a line pattern in a photoresist and a metal line formed therefrom, and changes in the line width of the line trench due to a wet clean after the reactive ion etch employed for formation of the line trench and a via cavity. The reduced line bias has a beneficial effect on electrical yields of a metal interconnect structure. | 2009-03-19 |
20090075473 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device capable of improving electrical junction capability between a pad metal line and an upper metal line by removing a foreign substance present on the surface of the pad metal line prior to formation of the upper metal line. | 2009-03-19 |
20090075474 | METHODS FOR FORMING DUAL DAMASCENE WIRING USING POROGEN CONTAINING SACRIFICIAL VIA FILLER MATERIAL - Methods for fabricating dual damascene interconnect structures are provided in which a sacrificial material containing porogen (a pore forming agent) is used for filling via holes in an interlayer dielectric layer such that the sacrificial material can be transformed to porous material that can be quickly and efficiently removed from the via holes without damaging or removing the interlayer dielectric layer. | 2009-03-19 |
20090075475 | METHOD OF SUBSTRATE TREATMENT, PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE, SUBSTRATE TREATING APPARATUS, AND RECORDING MEDIUM - Substrate processing apparatus | 2009-03-19 |
20090075476 | MANUFACTURING METHOD OF SUBSTRATE HAVING CONDUCTIVE LAYER AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The manufacturing method of a substrate having a conductive layer has the steps of: forming an inorganic insulating layer over a substrate; forming an organic resin layer with a desired shape over the inorganic insulating layer; forming a low wettability layer with respect to a composition containing conductive particles on a first exposed portion of the inorganic insulating layer; removing the organic resin layer; and coating a second exposed portion of the inorganic insulating layer with a composition containing conductive particles and baking, thereby forming a conductive layer. | 2009-03-19 |
20090075477 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to an aspect of an embodiment, a method of manufacturing a semiconductor device has forming a silicon-containing layer over a semiconductor substrate, forming a metal layer over the semiconductor substrate and the silicon-containing layer, forming a silicide-containing layer over the semiconductor substrate and the silicon-containing layer by heat treatment of the semiconductor substrate and the silicon-containing layer, and applying flash annealing to the silicide-containing layer. | 2009-03-19 |
20090075478 | SEMICONDUCTOR DEVICE,HAVING A THROUGH ELECTRODE, SEMICONDUCTOR MODULE EMPLOYING THEREOF AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING A THROUGH ELECTRODE - The layout density of the through electrodes in the horizontal plane of the substrate is enhanced. Through holes | 2009-03-19 |
20090075479 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A substrate having a copper wiring is prepared. An insulating film is formed on the copper wiring. The insulating film is etched with a gas containing fluorine to form an opening reaching the copper wiring. A plasma treatment is carried out on a surface of copper exposed at a bottom of the opening without turning plasma discharge of f after forming the opening in the same chamber as the formation of the opening. | 2009-03-19 |
20090075480 | Silicon Carbide Doped Oxide Hardmask For Single and Dual Damascene Integration - Interconnects of integrated circuits (ICs) utilize low-k dielectrics, copper metal lines, dual damascene processing and amplified photoresist chemistry to build ICs with features smaller than 100 nm. Photolithographic processing of interconnects with these elements are subject to resist poisoning from nitrogen in etch stop and hard mask dielectric layers. Attempts to solve this problem cause lower IC circuit performance or higher fabrication process cost and complexity. This invention comprises a method of fabricating interconnects in an IC using layers of silicon carbide doped oxide (SiCO) in a via etch stop layer, in a trench etch stop layer, as a via etch hard mask and as a trench etch hard mask. | 2009-03-19 |
20090075481 | METHOD OF FABRICATING SEMICONDUCTOR SUBSTRATE BY USE OF HETEROGENEOUS SUBSTRATE AND RECYCLING HETEROGENEOUS SUBSTRATE DURING FABRICATION THEREOF - The invention discloses a method of fabricating a first substrate and a method of recycling a second substrate during fabrication of the first substrate. The second substrate is heterogeneous for the first substrate. First, the fabricating method according to the invention is to prepare the second substrate. Subsequently, the fabricating method is to deposit a buffer layer on the second substrate. Then, the fabricating method is to deposit a semiconductor material layer on the buffer layer. The buffer layer assists the epitaxial growth of the semiconductor material layer, and serves as a lift-off layer. Finally, with an etching solution, the fabricating method is to only etch the lift-off layer to debond the second substrate away from the semiconductor material layer, where the semiconductor material layer serves as the first substrate. | 2009-03-19 |
20090075482 | PROCESS FOR FORMING A PATTERN INCLUDING ON A SEMICONDUCTOR DEVICE - An objective of this invention is to prevent resist poisoning and sensitivity deterioration in a chemically amplified resist. The chemically amplified resist comprises a base resin, a photoacid generator and a salt exhibiting buffer effect in the base resin. | 2009-03-19 |
20090075483 | ULTRA LIGHTWEIGHT PHOTOVOLTAIC DEVICE AND METHOD FOR ITS MANUFACTURE - An ultra lightweight semiconductor device such as a photovoltaic device is fabricated on a non-etchable barrier layer which is disposed upon an etchable substrate. The device is contacted with an appropriate etchant for a period of time sufficient to remove at least a portion of the thickness of the substrate. The barrier layer prevents damage to the photovoltaic material during the etching process. Photovoltaic devices fabricated by this method have specific power levels in excess of 300 w/kg. | 2009-03-19 |
20090075484 | Method of Processing A Substrate, Spin Unit for Supplying Processing Materials to A Substrate, and Apparatus for Processing A Substrate Having the Same - In a spin unit for rotating a substrate and a method of processing the substrate, the substrate is secured on a support and is rotated on the support. Processing materials including drying gases, etching solutions and cleaning solutions are selectively supplied onto a bottom surface of the rotating substrate. The same processing materials are also selectively supplied onto a top surface of the substrate. The top and bottom surfaces of the substrate are simultaneously processed by simultaneous supply of the processing materials through the first and second sub-injectors. | 2009-03-19 |
20090075485 | METHOD FOR FORMING PATTERN OF SEMICONDUCTOR DEVICE - A method for forming a fine pattern of a semiconductor device comprises: forming a first hard mask film and an etch barrier film over a semiconductor substrate; forming a sacrificial pattern over the etch barrier film; forming a spacer on sidewalls of the sacrificial pattern; removing the sacrificial pattern; etching the etch barrier film and the hard mask film with the spacer as an etch mask to form an etch barrier pattern and a hard mask pattern; and removing the spacer and the etch barrier pattern, thereby improving yield and reliability of the device. | 2009-03-19 |
20090075486 | SURFACE TREATMENT SOLUTION FOR THE FINE SURFACE PROCESSING OF A GLASS SUBSTRATE CONTAINING MULTIPLE INGREDIENTS - A surface treatment solution for finely processing a glass substrate containing multiple ingredients is used for the construction of liquid crystal-based or organic electroluminescence-based flat panel display devices without invoking crystal precipitation and/or increasing surface roughness. An etching solution of the invention contains, in addition to hydrofluoric acid (HF) and ammonium fluoride (NH | 2009-03-19 |
20090075487 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a method of manufacturing a semiconductor device, which includes forming an insulating film above a semiconductor substrate having a recess and stopper film formed above the semiconductor substrate excluding the recess, thereby filling the recess with the insulating film, performing a first polishing by polishing the insulating film by means of a chemical mechanical polishing method using a first polishing liquid containing cerium oxide and first anionic surfactant, thereby obtaining a flattened surface, and performing a second polishing by polishing the flattened insulating film using a second polishing liquid containing cerium oxide and a second anionic surfactant having a smaller molecular weight than that of the first anionic surfactant under a polishing condition which differs from that of the first polishing, thereby exposing the stopper film. | 2009-03-19 |
20090075488 | BETA-DIKETIMINATE LIGAND SOURCES AND METAL-CONTAINING COMPOUNDS THEREOF, AND SYSTEMS AND METHODS INCLUDING SAME - The present invention provides metal-containing compounds that include at least one β-diketiminate ligand, and methods of making and using the same. In certain embodiments, the metal-containing compounds include at least one β-diketiminate ligand with at least one fluorine-containing organic group as substituent. In other certain embodiments, the metal-containing compounds include at least one β-diketiminate ligand with at least one aliphatic group as a substituent selected to have greater degrees of freedom than the corresponding substituent in the β-diketiminate ligands of certain metal-containing compounds known in the art. The compounds can be used to deposit metal-containing layers using vapor deposition methods. Vapor deposition systems including the compounds are also provided. Sources for β-diketiminate ligands are also provided. | 2009-03-19 |
20090075489 | REDUCTION OF ETCH-RATE DRIFT IN HDP PROCESSES - A processing chamber is seasoned by providing a flow of season precursors to the processing chamber. A high-density plasma is formed from the season precursors by applying at least 7500 W of source power distributed with greater than 70% of the source power at a top of the processing chamber. A season layer having a thickness of at least 5000 Å is deposited at one point using the high-density plasma. Each of multiple substrates is transferred sequentially into the processing chamber to perform a process that includes etching. The processing chamber is cleaned between sequential transfers of the substrates. | 2009-03-19 |
20090075490 | METHOD OF FORMING SILICON-CONTAINING FILMS - A method of forming a silicon-containing film comprising providing a substrate in a reaction chamber, injecting into the reaction chamber at least one silicon-containing compound; injecting into the reaction chamber at least one co-reactant in the gaseous form; and reacting the substrate, silicon-containing compound, and co-reactant in the gaseous form at a temperature equal to or less than 550° C. to obtain a silicon-containing film deposited onto the substrate. A method of preparing a silicon nitride film comprising introducing a silicon wafer to a reaction chamber; introducing a silicon-containing compound to the reaction chamber; purging the reaction chamber with an inert gas; and introducing a nitrogen-containing co-reactant in gaseous form to the reaction chamber under conditions suitable for the formation of a monomolecular layer of a silicon nitride film on the silicon wafer. | 2009-03-19 |
20090075491 | Method for curing a dielectric film - A method of curing a low dielectric constant (low-k) dielectric film on a substrate is described, wherein the dielectric constant of the low-k dielectric film is less than a value of approximately 4. The method comprises exposing the low-k dielectric film to ultraviolet (UV) radiation. Following the UV exposure, the dielectric film is exposed to IR radiation. | 2009-03-19 |
20090075492 | DISTRIBUTOR CONNECTION MODULE - The invention relates to a distributor connection module used in the telecommunication and data technology field. Said distributor connection module comprises a housing which comprises a cavity wherein at least two conductor plates are arranged, and the housing comprises at least one opening in a front side wherein two connector modules can be inserted. A pivotable protection frame is arranged on the housing, which can adopt at least two positions. In a first pivoted position, the connector module is free and in a second position, the protection frame is arranged in a parallel manner in relation to the front side. | 2009-03-19 |
20090075493 | Electrical connector with fastening structure - An electrical connector ( | 2009-03-19 |
20090075494 | BACK-TO-BACK MOUNTED ELECTRICAL CONNECTORS - An electrical connector assembly is provided that includes a pair of connectors configured to be mounted onto a midplane circuit board in a back-to-back orientation. Each connector includes offset engagement members that mate with corresponding engagement members on the midplane circuit board. | 2009-03-19 |
20090075495 | Socket of semiconductor module - A socket of a semiconductor module is provided. The socket of the semiconductor module comprises a pin in the form of a wire having at least one flat plane and at least two round portion. | 2009-03-19 |
20090075496 | Connector which can be reduced in warpage - In a connector for connecting first and second connection objects faced to each other, a conductive contact includes a holding portion held by an insulator, a first spring portion, and a second spring portion connected to the first spring portion. The first spring portion extends from the holding portion in one direction and has a first contacting portion to be connected to the first connection object. The second spring portion extends in the other direction opposite to the one direction and has a free end provided with a second contacting portion to be connected to the second connection object. | 2009-03-19 |
20090075497 | SEMICONDUCTOR ELECTROMECHANICAL CONTACT - A compliant electrical contact assembly for interconnecting a lead or terminal of an integrated circuit having two cantilever beams positioned within a slot in a housing arranged such that a portion of the beams slide along a portion of one another and within the housing as the beams are deformed elastically in order to allow more travel and compliance without yielding or totally deforming the beam. The sliding action during deformation effectively multiplies the total compliance in the assembly above and beyond the compliance otherwise available to elastic compression of the cantilever beams. | 2009-03-19 |
20090075498 | Electrical connector - An electrical connector is disclosed. Connection targets have edges, respectively, on which conductive portions are formed. The electrical connector serves to electrically connect the conductive portions of connection targets with the edges facing each other. The electrical connector comprises an electrode sheet, a press member and a connection keeper. The electrode sheet comprises an insulation sheet and an electrode pattern formed on the insulation sheet. The press member is made of elastic material distinct from the electrode sheet. The press member is arranged to press the electrode pattern against the conductive portions of the connection targets when the press member is compressed, so that the conductive portions of the connection targets are connected to each other by the electrode pattern. The connection keeper is configured to keep the connection between the conductive portions of the connection targets with the press member compressed. | 2009-03-19 |
20090075499 | IC socket - An IC socket comprises an insulative housing having a plurality of periphery walls and a cover pivotally assembled to one end of the insulative housing and adapted to be locked to the insulative housing at the other end. The cover includes a plurality of peripheral edges. The cover also has a plurality of spring arms upwardly extending therefrom and disposed at the edges. | 2009-03-19 |
20090075500 | Connector with dual compression polymer and flexible contact array - A socket connector includes an insulative carrier having opposite first and second sides and a plurality of vias extending between the first and second sides. A plurality of polymer columns is held by the carrier. Each polymer column includes a first end extending from the first side of the carrier and a second end extending from the second side of the carrier. A contact array is disposed on each first and second side of the carrier. Each contact array comprises a flexible sheet having a plurality of conductive elements having contact tips proximate corresponding first and second ends of the polymer columns. The conductive elements on the first side of the carrier are electrically connected to corresponding conductive elements on the second side of the carrier through the vias in the carrier to establish electrical paths between corresponding contact tips on the first and second sides of the carrier. | 2009-03-19 |
20090075501 | Electronic device including printed circuit board, connector and case - An electronic device includes a printed circuit board, a connector mounted on the printed circuit board, and a case housing the printed circuit board. The connector includes a housing and a plurality of terminals arranged in the housing. The case has an opening portion on one side thereof and the housing covers the opening portion. The case includes a wall having a case-side fixing part and a case-side engaging part at a portion adjacent to the opening portion. The housing has a housing-side fixing part and a housing-side engaging part. The case-side fixing part engages with the housing-side fixing part for fixing the housing to the case. The case-side engaging part engages with the housing-side engaging part for restricting the portion of the case adjacent to the opening portion from separating from the housing. | 2009-03-19 |
20090075502 | Planar Array Contact Memory Cards - A Planar Memory Module (PAMM) device comprising a generally planar card comprising a first side and a second side, the first side having a plurality of couplings and the second side having a plurality of connectors, a plurality of memory devices coupled to the card via a first portion of the plurality of couplings, and at least one hub chip coupled to the card via a second portion of the plurality of couplings. Each of the plurality of couplings is connected to an associated one of the plurality of connectors. | 2009-03-19 |
20090075503 | Single use security module mezannine connector - An electrical connector assembly includes an electrical connector and a tool. The electrical connector includes a contact having a compliant jog section disposed between first and second ends of the contact. The tool is required to press-fit the connector to an electrical device without deforming the compliant jog section of the contact. | 2009-03-19 |
20090075504 | Electrical Plug-In Connection System - An electrical plug-in connection system has a first electrical plug-in connection element and a second electric plug-in connection element complementary thereto. Pertaining first and a second housings having a number of contact elements corresponding to the number of the wires in the one housing and a corresponding number of opposite contact elements in the other housing are provided. An electrical plug-in connection between the contact elements and their respective opposite contact elements can be established and released again respectively by a relative movement of the two housings. A locking connection occurs between the two housings, which can be established and detached again. A two-step operating mechanism is provided, where, during the relative movement of the two housings in a first step, a locking of the two housings takes place essentially without providing contact between the contact elements and their respective opposite contact elements, and where, during the transition into an end position as the second step, the actual providing of contact between the contact elements and their respective opposite contact elements takes place with a position-dependent increase of the contact force. | 2009-03-19 |
20090075505 | Electrical switch and outlet design that can be safely replaced with the power on and without tools - An electrical switch and outlet design which includes a modular electrical component system having a universal connector which can receive replacement switches, sockets and other electrical components. The connection between these switches, sockets or other components and the universal connector is controlled by a lifting system in which the entirety of the replacement module is inserted into a receptacle or removed therefrom without the user touching any electrical wiring. Essentially, components are changed by plugging a component into and unplugging one from a universal grounded connector. | 2009-03-19 |
20090075506 | Lever lock type connector - A lever lock type connector includes a pair of outer housings including connecting terminals for an electrical connection, the pair of outer housings being joined each other by a rotating operation of a rotating lever in a state that the rotating lever rotatably supported by one of the pair of outer housings is engaged with an engaging portion of an other of the pair of outer housings, and a locking member that is provided on the one of the pair of outer housings and movable towards a sidewall of the other of the pair of outer housings. The locking member is adapted to move towards the sidewall of the other of the pair of outer housings in conjunction with the rotating operation of the rotating lever so as to contact the sidewall of the other of the pair of outer housings. | 2009-03-19 |
20090075507 | SLIDER UNIT AND CARD CONNECTOR - A slider unit and a card connector having a slider that is arranged in a housing so as to be capable of moving along the insertion/ejection directions of a card and whose position is capable of being switched by a heart cam mechanism between a first position and a second position that is farther from an opening than the first position. A coil spring that biases the slider in the card ejection direction; an abutting portion that is integrally formed in the slider and is capable of abutting the insertion direction side of the card; and a pipe that is provided in the slider and retains the coil spring by being inserted in the coil spring, where both ends of the shaft that protrude from the coil spring becoming enlarged diameter portions and that are partially widened compared to the middle potion on which the coil spring is fitted. | 2009-03-19 |
20090075508 | ELECTRICAL CONNECTORS AND COUPLING DEVICE FOR SUCH A CONNECTOR - An electrical connector with a first coupling device with a first connection for a first electrical cable and a second coupling device with a second connection for a second electrical cable and wherein both coupling devices are interlocking for electrical contact. The second coupling device includes a first component to contact the first coupling device by interlocking, a second component that includes the second connection, and a coupling device for electrical coupling of the first component with the second component, wherein both components are flexible relative to each other in radial and/or axial direction. | 2009-03-19 |
20090075509 | Socket connector having leading-and-positioning arrangement within a passageway and method for mating with the same - An electrical connector ( | 2009-03-19 |
20090075510 | Socket - The present invention provides a socket for an element with an element electrode. The socket comprises a base shell, a cover shell and a contact member. The cover shell is engaged with the base shell so that the base shell and the cover shell define a cavity. Each of the base shell and the cover shell is made of a high thermal-conductive material. The contact member comprises an elastic member and a contact electrode provided on the elastic member and are designed and arranged so that the element is mountable on the contact member within the cavity with the element electrode connected to the contact electrode. | 2009-03-19 |
20090075511 | SOCKET AND ELECTRICAL ASSEMBLY INCLUDING THE SOCKET - A socket that electrically connects a memory drive unit to a circuit board includes a socket housing including a base portion having a slot disposed in a central portion therein, sidewalls extending upward from the base portion, and end walls extending upward from the base portion and between the sidewalls, and a locking member arranged to engage a locking structure of a memory drive unit when a memory drive unit is inserted into the memory drive socket. The slot includes a plurality of contacts disposed therein which are arranged to engage corresponding contact pads of the memory drive unit. A bottom surface of the base portion includes at least one pin arranged to engage a through hole of a circuit board. The locking member includes at least one pin disposed at a lower end portion thereof and arranged to be secured to the circuit board. | 2009-03-19 |
20090075512 | Socket connector having retaining tabs arranged on edges of sidewalls thereon - A socket connector is provided for securely mounting an IC package ( | 2009-03-19 |