11th week of 2010 patent applcation highlights part 45 |
Patent application number | Title | Published |
20100068807 | INTERFERON-alpha REGULATOR - An object of the present invention is to elucidate the role of IKKα in TLR signaling and provide an agent and a method for controlling interferon-α. The present invention provides an agent for suppressing interferon-α production which comprises an agent for inhibiting IKKα. | 2010-03-18 |
20100068808 | Tubular nanostructure targeted to cell membrane - Devices, compositions, and methods are described which provide a tubular nanostructure or a composite tubular nanostructure targeted to a lipid bilayer membrane. The tubular nanostructure includes a hydrophobic surface region flanked by two hydrophilic surface regions. The tubular nanostructure is configured to interact with a lipid bilayer membrane and form a pore in the lipid bilayer membrane. The tubular nanostructure may be targeted by including at least one ligand configured to bind to one or more cognates on the lipid bilayer membrane of a target cell. | 2010-03-18 |
20100068809 | Reproductive cell function preservation system - Compositions or extracts (2)(15)(24)(25)(16)(23)(31)(36)(41) obtained from the fruit (4) or leaves (26) of plants of the genus | 2010-03-18 |
20100068810 | METHODS AND COMPOSITIONS FOR GROWTH OF EMBRYONIC STEM CELLS - The present invention provides methods and compositions for establishing and maintaining growth of undifferentiated stem cells. In particular, the present invention provides synthetic growth matrices for stem cells, wherein said cells are capable of going through multiple passages while remaining in an undifferentiated state. | 2010-03-18 |
20100068811 | Cardiac Stem Cells - Human cardiac stem cells can be isolated from endomyocardial biopsies. Such cells mediate cardiac regeneration and improve heart function in a mouse infarct model. The cells can be used for autologous, allogeneic, syngeneic, or xenogeneic therapeutic applications in patients. The stem cells can be genetically modified to enhance their therapeutic activity. | 2010-03-18 |
20100068812 | METHOD FOR INCREASING TRANSFORMATION EFFICIENCY IN PLANTS, COMPRISING COCULTURE STEP FOR CULTURING PLANT TISSUE WITH COCULTURE MEDIUM CONTAINING 3, 6-DICHLORO-O-ANISIC ACID - The present invention aims to provide a method for increasing transformation efficiency in plants when compared to conventionally known | 2010-03-18 |
20100068813 | APOPTOTIC CELL-MEDIATED TRANSFECTION OF MAMMALIAN CELLS WITH INTERFERING RNA - Mammalian host cells for use in a cell-mediated tranfection process, which contain an RNAi molecule and an expression vector for a pro-apoptotic protein. The method includes inducing apoptotic cell (AC) death in mammalian cells that contain an RNAi molecule capable of downregulating a chosen target gene. Living cells expressing the target gene are then exposed to the ACs. The ACs are processed by the living cells, and the RNAi molecule in the ACs downregulates the expression of the target gene in living cells. | 2010-03-18 |
20100068814 | MULTI-MICRORNA METHODS AND COMPOSITIONS - Provided are DNAs comprising a polynucleotide that encodes at least a first modified miR-30 precursor and a second modified miR-30 precursor. Also provided are vectors comprising the the DNAs, where the vector can replicate in a host cell. Additionally, specific lentiviral vectors comprising the above-described DNA are provided, as are methods of inhibiting expression of a target gene in a eukaryotic cell. | 2010-03-18 |
20100068815 | SITE-SPECIFIC RECOMBINATION SYSTEMS FOR USE IN EUKARYOTIC CELLS - Prokaryotic recombination systems have been adapted to function in eukaryotes in order to achieve one or more of the following: DNA site specific excision, translocation, integration and inversion. These recombination systems are identified as seven members of the small serine resolvase subfamily: CinH, ParA, Tn1721, Tn5053, Tn21, Tn402, and Tn501 and three members of the large serine resolvase subfamily: Bxb1, U153, and TP901-1. These recombination systems represent new tools for the genetic manipulation of eukaryotic genomes. | 2010-03-18 |
20100068816 | Genetically engineered herbicide resistance for maintaining axenic cultures - This disclosure provides herbicide resistant algae and cyanobacteria. This disclosure also provides a method to cultivate algae and cyanobacteria in axenic cultures without contaminating species. Moreover, this disclosure provides transgenic algal and cyanobacterial cells that are capable of high production in high light intensities as typically applied in cultivation. Furthermore, a novel transformation method is provided for algal cells. | 2010-03-18 |
20100068817 | COLORIMETRIC DETECTION OF METALLIC IONS IN AQUEOUS MEDIA USING FUNCTIONALIZED NANOPARTICLES - Disclosed herein are methods of detecting metal ions in a sample using functionalized nanoparticles. More specifically, functionalized nanoparticles are used to selectively detect metal ions in a sample using changes in melting temperature of hybridized oligonucleotides on functionalized nanoparticles. The melting temperature can be detected using absorbance, color change, or both. In some cases, the concentration of the metal ion in the sample can be determined. Concentrations of metal ion of as little as 20 ppb (about 100 nM) can be detected using the disclosed methods. | 2010-03-18 |
20100068818 | ALGORITHMS FOR MULTIVARIANT MODELS TO COMBINE A PANEL OF BIOMARKERS FOR ASSESSING THE RISK OF DEVELOPING OVARIAN CANCER - The present invention provides methods for assessing a patient's risk of having and/or developing ovarian cancer. Also, methods for evaluating the ovarian cancer state of a patient are described herein. These methods involve the detection, analysis, and classification of biological patterns in biological samples. The biological patterns are obtained using, for example, mass spectrometry systems and other techniques. The present invention also includes therapeutic and prophylactic agents that target the biomarkers described herein. Also, the present invention provides methods for the treatment of ovarian cancer using the markers described herein or agents that mimic the properties of these markers. | 2010-03-18 |
20100068819 | COMPOUNDS AND METHODS FOR DOUBLE LABELLING OF POLYPEPTIDES TO ALLOW MULTIPLEXING IN MASS SPECTROMETRIC ANALYSIS - The present invention describes double labelling reagents with both an isotopic and isobaric label component suitable for differentially labelling different—protein samples. After labelling of the individual protein samples, all samples are pooled. Peptides from the pooled samples are isolated and analysed by mass spectrometry for determining the relative concentration of each differentially double-labelled polypeptide. | 2010-03-18 |
20100068820 | MOLECULARLY IMPRINTED POLYMER AND USE THEREOF IN DIAGNOSTIC DEVICES - An adhesive is provided containing at least one synthetic polymer with receptor sites that enable the selective capture or release of a target molecule. A polymer is synthesized by polymerizing and cross-linking a functional monomer or functional copolymers in the presence of a target or template molecule allowing for reversible interactions between the polymer and the target molecule. The target molecule may be extracted from the polymer creating receptor sites complimentary to the target molecule. Alternatively, the target molecule may remain in the polymer network and be controllably released. The molecularly imprinted polymer is formulated into an adhesive. The adhesive can be used as a component in an in-vitro diagnostic device to release template molecules or to capture target molecules in vacated receptor sites in the synthetic polymer. | 2010-03-18 |
20100068821 | METHOD FOR DETECTION AND ANALYSIS OF AROMATIC HYDROCARBONS FROM WATER - Methods for analyzing aromatic hydrocarbons dissolved in water are discussed. The methods include providing a substrate coated with a thin film layer of a material, wherein the material has a high affinity for at least one aromatic hydrocarbon, the material is substantially optically transparent, and the material has near-zero auto fluorescence, inserting the coated substrate directly into an environmental location including water, waiting for an exposure time permitting at least one aromatic hydrocarbon to absorb into the thin film layer, retrieving the coated substrate from the environmental location, removing any non-absorbed matter from the coated substrate, and performing fluorescence analysis on the coated substrate to detect aromatic hydrocarbons present in the thin film layer. Also methods for analyzing aromatic hydrocarbons dissolved in water contained in coated vessels are provided. | 2010-03-18 |
20100068822 | Device For Carrying Out Tests On And Analyzing Biological Samples With Temperature-Controlled Biological Reactions - The invention relates to a device for carrying out tests on and analyzing biological samples with temperature-controlled biological reactions. It comprises: A reaction chamber ( | 2010-03-18 |
20100068823 | Carrier Material, Method for the Production and Use Thereof - An embodiment of the present invention relates to a carrier material which is used in a method of diagnosis and which comprises a base material which is provided with a surface which is equipped with at least two different affinity ligands. | 2010-03-18 |
20100068824 | SENSING METHOD, SENSING DEVICE, INSPECTION CHIP, AND INSPECTION KIT - A sensing method comprises the steps of: allowing a liquid sample containing an analyte to flow through a channel, applying a force oriented in a given direction normal to a direction in which the liquid sample flows in the channel upon the analyte in a given position of the channel to move the analyte in the given direction so that the analyte is concentrated, causing the liquid sample to flow to a sensing surface forming a part of a wall surface of the channel located downstream of the given position and in the given direction against the channel, the sensing surface securing thereon a binding substance specifically reacting with the analyte, to allow the concentrated analyte to bind to the binding substance, and detecting a quantity of the analyte bound to the binding substance. | 2010-03-18 |
20100068825 | Method and Device for Detecting at Least One Property of at Least One Object with a Microchip - The present invention relates to a method and a device for the detection of at least one property of at least one object. The detection is effected by means of a microchip. The microchip has at least one readable detection pixel. In order to reduce the technical equipment outlay during object detection, the method according to the invention is characterized by the fact that the at least one object is arranged at the microchip in a spatially predetermineable position. The at least one object is exposed to illumination light in order to detect the illumination light that interacts with the at least one object or the light that is induced by the illumination light and emerges from the at least one object by means of the at least one readable detection pixel of the microchip. | 2010-03-18 |
20100068826 | HYBRID PHASE LATERAL FLOW ASSAY - The invention relates to devices for performing single step assays for the determination of the presence or absence of an analyte in a liquid sample, and methods of determining the presence or absence of such analytes using such devices. Devices disclosed comprise a labeled analyte-binding reagent reversibly-immobilized on a non-porous solid material, which solid material is in physical contact with a dry porous carrier bearing an immobilized analyte-binding reagent. Also provided are quantitative assay devices. | 2010-03-18 |
20100068827 | Stabilized Standards for Busulfan Immunoassay - Use of busulfan amide as stabilized standards in immunoassays for quantifying the amount of busulfan in samples of human biological fluids, methods for carrying out said immunoassay and kits for use in said immunoassay. | 2010-03-18 |
20100068828 | METHOD OF FORMING A STRUCTURE HAVING A GIANT RESISTANCE ANISOTROPY OR LOW-K DIELECTRIC - A method is provided involving the growth of carbon nanotubes to provide giant resistance anisotropy or a low-k dielectric. The method comprises growing a plurality of one-dimensional nanostructures ( | 2010-03-18 |
20100068829 | MANUFACTURE METHOD FOR SEMICONDUCTOR DEVICE CAPABLE OF PREVENTING REDUCTION OF FERROELECTRIC FILM - A ferroelectric capacitor is formed on a semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a ferroelectric film and an upper electrode stacked in an order recited. A first capacitor protective film of aluminum oxide having a thickness equal to or thicker than 30 nm is formed covering the ferroelectric capacitor. A first insulating film of silicon oxide is formed on the first capacitor protective film by chemical vapor deposition using high density plasma. | 2010-03-18 |
20100068830 | MARKER STRUCTURE AND METHOD FOR CONTROLLING ALIGNMENT OF LAYERS OF A MULTI-LAYERED SUBSTRATE - The invention includes a lithographic system having a first source for generating radiation with a first wavelength and an alignment system with a second source for generating radiation with a second wavelength. The second wavelength is larger than the first wavelength. A marker structure is provided having a first layer and a second layer. The second layer is present either directly or indirectly on top of said first layer. The first layer has a first periodic structure and the second layer has a second periodic structure. At least one of the periodic structures has a plurality of features in at least one direction with a dimension smaller than 400 nm. Additionally, a combination of the first and second periodic structure forms a diffractive structure arranged to be illuminated by radiation with the second wavelength. | 2010-03-18 |
20100068831 | Method for wafer trimming for increased device yield - According to an exemplary embodiment, a method for site-specific trimming of a wafer to provide a target parameter value for a plurality of devices on the wafer includes performing a first measurement of a parameter at a subset of the number of devices on the wafer. The method further includes forming a top layer over the wafer after performing the first measurement. The method further includes performing a second measurement of the parameter at the subset of the devices on the wafer after forming the top layer. The method further includes determining an amount of the top layer to remove across the wafer to provide the target parameter value for the devices by utilizing the first and second measurements of the parameter. The method can be utilized to, for example, achieve a more uniform characteristic frequency for bulk acoustic wave (BAW) filters. | 2010-03-18 |
20100068832 | METHOD FOR THE PROTECTION OF INFORMATION IN MULTI-PROJECT WAFERS - A method for the protection of the information in a multi-project wafer (MPW) is provided. First, a substrate is provided. There are a first die and a second die on the substrate. Second, a first wafer process is performed on the substrate. The first wafer process includes performing a wafer procedure by using a non-destructive energy source and destroying the first die by using a destructive energy source. Later, a second wafer process is performed to finish the second die. | 2010-03-18 |
20100068833 | System of testing semiconductor devices, a method for testing semiconductor devices, and a method for manufacturing semiconductor devices - A system of testing semiconductor devices includes a classification module configured to classify a plurality of lots into a plurality of groups; an apparatus assignment module configured to assign a plurality of testing apparatuses to each of the groups; and a test recipe creation module configured to create a test recipe to test defects in a second group other than a first group specified in the groups, the test recipe including a definition of testing positions in the second group defined by a rule different from the first group. | 2010-03-18 |
20100068834 | DAMAGE EVALUATION METHOD OF COMPOUND SEMICONDUCTOR MEMBER, PRODUCTION METHOD OF COMPOUND SEMICONDUCTOR MEMBER, GALLIUM NITRIDE COMPOUND SEMICONDUCTOR MEMBER, AND GALLIUM NITRIDE COMPOUND SEMICONDUCTOR MEMBRANE - A method of evaluating damage of a compound semiconductor member, comprising: a step of performing spectroscopic ellipsometry measurement on a surface of the compound semiconductor member; and a step of evaluating damage on the surface of the compound semiconductor member, using a spectrum in a wavelength band containing a wavelength corresponding to a bandgap of the compound semiconductor member, in a spectrum of an optical constant obtained by the spectroscopic ellipsometry measurement. | 2010-03-18 |
20100068835 | THIN FILM SCRIBE PROCESS - A method and apparatus for improving a thin film scribing procedure is presented. Embodiments of the invention include a method and apparatus for determining a scribe setting for removal of an absorber layer of a photovoltaic device that improves contact resistance between a back contact layer and a front contact layer of the device. | 2010-03-18 |
20100068836 | METHOD OF MEASURING RESISTIVITY OF SIDEWALL OF CONTACT HOLE - A method of measuring a resistivity of a sidewall of a contact hole formed in a semiconductor device, wherein said semiconductor device includes a first electrode formed on a substrate; a second electrode formed on the first electrode with an insulating film in between; a resist pattern formed on the first electrode and the second electrode; a contact hole formed in the first electrode and the second electrode; and an organic film deposited on the sidewall of the contact hole, includes the steps of: placing a probe needle on the first electrode and the second electrode so that the probe needle contacts with the first electrode and the second electrode several times; establishing electrical conductivity of the probe needle relative to the first electrode and the second electrode; and measuring the resistivity of the organic film between the first electrode and the second electrode. | 2010-03-18 |
20100068837 | Structures and Methods for Wafer Packages, and Probes - This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of semiconductor devices. In some embodiments, such structures are shown to be useful for simultaneously testing multiple devices on a semiconductor wafer, or for assembling multiple substrates on to a wafer, to accomplish both testing and packaging of the dies on the wafer. In yet another embodiment of the invention, single or multilevel ceramic interconnect structures with thick film metal conductors, are fabricated right on the product wafer to facilitate economical testing and packaging of the dies on the wafer. | 2010-03-18 |
20100068838 | Method of Manufacturing a Light Emitting, Photovoltaic or Other Electronic Apparatus and System - The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes forming at least one first conductor coupled to a base; coupling a plurality of substantially spherical substrate particles to the at least one first conductor; converting the substrate particles into a plurality of substantially spherical diodes; forming at least one second conductor coupled to the substantially spherical diodes; and depositing or attaching a plurality of substantially spherical lenses suspended in a first polymer. The lenses and the suspending polymer have different indices of refraction. In some embodiments, the lenses and diodes have a ratio of mean diameters or lengths between about 10:1 and 2:1. In various embodiments, the forming, coupling and converting steps are performed by or through a printing process. | 2010-03-18 |
20100068839 | Method of Manufacturing a Light Emitting, Photovoltaic or Other Electronic Apparatus and System - The present invention provides a method of manufacturing an electronic apparatus, such as a lighting device having light emitting diodes (LEDs) or a power generating device having photovoltaic diodes. The exemplary method includes forming at least one first conductor coupled to a base; coupling a plurality of substrate particles to the at least one first conductor; converting the plurality of substrate particles into a plurality of diodes; forming at least one second conductor coupled to the plurality of spherical diodes; and depositing or attaching a plurality of substantially spherical lenses suspended in a first polymer, with the lenses and the suspending polymer having different indices of refraction. In some embodiments, the lenses and diodes have a ratio of mean diameters or lengths between about 10:1 and 2:1. In various embodiments, the forming, coupling and converting steps are performed by or through a printing process. | 2010-03-18 |
20100068840 | ORGANIC LIGHT EMITTING APPARATUS AND METHOD OF PRODUCING THE SAME - Provided are an organic light emitting apparatus for use in, for example, a flat device display, and a method of producing the apparatus. The organic light emitting apparatus has sides formed by division at ends of its substrate. Three-dimensional portions are formed on the surface of the substrate along the sides. An inorganic sealing layer is formed to extend toward the three-dimensional portions. | 2010-03-18 |
20100068841 | Thin Film Transistor Array Panel and Method of Manufacturing the Same - A method of manufacturing a thin film transistor array panel is provided, which includes: forming a semiconductor layer of polysilicon on an insulating substrate; forming a gate insulating layer on the semiconductor layer; forming a gate electrode on the gate insulating layer; forming a source region and a drain region by doping conductive impurities in the semiconductor layer; forming an interlayer insulating layer covering the gate electrode; forming a source electrode and a drain electrode respectively connected to the source and the drain regions; forming a passivation layer covering the source and the drain electrodes; forming a pixel electrode connected to the drain electrode; and forming a first alignment key when forming one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode, wherein one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode is at least formed by photolithography process using a photoresist pattern as an etch mask, and a second alignment key completely covering the first alignment key is formed at the same layer as the photoresist pattern. | 2010-03-18 |
20100068842 | LONG-WAVELENGTH RESONANT-CAVITY LIGHT-EMITTING DIODE - An efficient long-wavelength light-emitting diode has a resonant-cavity design. The light-emitting diode preferably has self-organized (In,Ga)As or (In,Ga)(As,N) quantum dots in the light-emitting active region, deposited on a GaAs substrate. The light-emitting diode is capable of emitting in a long-wavelength spectral range of preferably 1.15-1.35 μm. The light-emitting diode also has a high efficiency of preferably at least 6 mW and more preferably at least 8 mW at an operating current of less than 100 mA and a low operating voltage of preferably less than | 2010-03-18 |
20100068843 | DISTRIBUTED BRAGG'S REFLECTOR OF DIGITAL-ALLOY MULTINARY COMPOUND SEMICONDUCTOR - There is provided a distributed Bragg's reflector (DBR) comprising a substrate and an unit distributed Bragg's reflector (DBR) layer, wherein a multi-layer is laminated on the substrate. The unit DBR layer is composed of a multi-layer laminated structure of unit digital-alloy multinary compound semiconductor layer/multinary compound semiconductor layer or unit digital-alloy multinary compound semiconductor layer/unit digital-alloy multinary compound semiconductor layer. The unit digital-alloy multinary compound semiconductor layer is composed of the multi-layer laminated structure of the first layer of multinary compound semiconductor and the second layer of a different multinary compound semiconductor on said first layer. The digital-alloy distributed Bragg's reflector of the present invention has a uniform quality on the substance area and the filter and reflector having uniformly high quality can be mass produced by using the reflector. | 2010-03-18 |
20100068844 | Microcap Wafer Bonding Method and Apparatus - A method of fabricating an apparatus including a sealed cavity and an apparatus embodying the method are disclosed. To fabricate the apparatus, a device chip including a substrate and at least one circuit element on the substrate is fabricated. Also, a cap is fabricated. Next, the device chip and the cap are bonded such that a sealed cavity is formed by the device chip and the cap. The bond is accomplished using thermo compression technique. Gold or other suitable metal can be used as a bonding agent. Then or at the same time, caulking agent is reflowed over the bonding agent, over portions of the cap, or both to further seal the cavity. In the resultant device, the sealed cavity is sealed by the bonding agent, the caulking agent, or both. The caulking agent increases hermeticity of the cavity and provides for even higher level of protection of the cavity against adverse environmental conditions. | 2010-03-18 |
20100068845 | PHOTODETECTOR USING NANOPARTICLES - The present invention relates to a photodetector using nanoparticles, and more particularly, to a novel photodetector wherein surfaces of nanoparticles synthesized by a wet colloidal process are capped with organic materials which then serve as channels for electron migration, or nanoparticles, from which organic materials capped on the surfaces of nanoparticles are removed to form a close-packed particle structure, directly serve to transport electrons. In accordance with specific embodiments of the present invention, it is possible to improve performance of the photodetector and simplify the manufacturing process thereof. | 2010-03-18 |
20100068846 | Package structure and fabrication method thereof - A package structure and fabrication method thereof. The structure includes a substrate having a terminal, a chip overlying the substrate, the chip having an active surface, having a center region and periphery region, the periphery region having an electrode thereon, a patterned cover plate overlying the chip and exposing the electrode, a conductive material electrically connecting the electrode and terminal, and an encapsulant covering the terminal, conductive material, and electrode, but exposing the cover plate overlying the center region of the chip. | 2010-03-18 |
20100068847 | METHOD FOR MANUFACTURING AN IMAGE SENSOR - A method for fabricating an image sensor die includes providing a wafer having a plurality of die, each die having a raised portion adjacent to an image area onto which a glass cover will be adhered; and thereafter dicing the wafer so that the plurality of die are separated into individual die. | 2010-03-18 |
20100068848 | ONE-STEP DIFFUSION METHOD FOR FABRICATING A DIFFERENTIAL DOPED SOLAR CELL - A one-step diffusion method for fabricating a differential doped solar cell is described. The one-step diffusion method includes the following step. First, a substrate is provided. A doping control layer is formed on the substrate. The doping control layer includes a plurality of openings therein. A doping process is conducted on the substrate to form heavy doping regions under the openings of the doping control layer and light doping regions on the other portion of the substrate | 2010-03-18 |
20100068849 | MANUFACTURING METHOD OF TRANSLUCENT SOLAR CELL - A translucent solar cell and a manufacturing method thereof are provided. The translucent solar cell at least includes a substrate, a front electrode layer, a photoconductive layer, and a back electrode layer stacked in order. Therein, a plurality of apertures are formed on the front electrode layer. In addition, a plurality of light-transmissive regions are formed on the back electrode layer and further extended in a depth direction so as to reach the plurality of apertures on the front electrode layer. Thus, the projected area of each light-transmissive region is within and smaller than that of the corresponding aperture. | 2010-03-18 |
20100068850 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A technique for mounting two semiconductor chips over a wiring substrate including mounting a first chip having first bonding pads over a surface of the wiring substrate having electrodes and stacking the second chip having second bonding pads over the first chip; connecting each of the first bonding pads to an associated one of the electrodes of the wiring substrate via an associated first wire; and connecting each of the second bonding pads to an associated one of the electrodes of the wiring substrate via an associated second wire. The bondings being carried out using a reverse bonding method in which at least one of the first and second wires are first bonded to an associated one of the electrodes of the wiring substrate followed by the bonding thereof to an associated one of the bonding pads of the first or second semiconductor chip. | 2010-03-18 |
20100068851 | CASTELLATION WAFER LEVEL PACKAGING OF INTEGRATED CIRCUIT CHIPS - Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts. | 2010-03-18 |
20100068852 | Method of Manufacturing A Semiconductor Device - The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding. Accordingly, when cutting the suspending leads, corner portions of the back surface of the sealing body can be supported by a flat portion of a holder portion in a cutting die which flat portion has an area sufficiently wider than a cutting allowance of the suspending leads, whereby it is possible to prevent chipping of the resin and improve the quality of the semiconductor device (QFN). | 2010-03-18 |
20100068853 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a substrate having first electrodes on a main surface thereof and a semiconductor chip having second electrodes on a first main surface thereof are arranged such that the main surface of the substrate and the first main surface of the semiconductor chip oppose to each other, and the first electrodes and the second electrodes are connected so as to electrically connect the substrate and the semiconductor chip. The semiconductor chip is made thin by grinding a second main surface opposing to the first main surface of the semiconductor chip which is connected with the substrate. Side surfaces and the second main surface of the semiconductor chip made thin are sealed with resin. | 2010-03-18 |
20100068854 | MEMS Switch Capping and Passivation Method - A MEMS switch with a platinum-series contact is capped through a process that also passivates the contact by controlling, over time, the amount of oxygen in the environment, pressures and temperatures. Some embodiments passivate a contact in an oxygenated atmosphere at a first temperature and pressure, before hermetically sealing the cap at a higher temperature and pressure. Some embodiments hermetically seal the cap at a temperature below which passivating dioxides will form, thus trapping oxygen within the volume defined by the cap, and later passivate the contact with the trapped oxygen at a higher temperature. | 2010-03-18 |
20100068855 | Group III nitride semiconductor devices with silicon nitride layers and methods of manufacturing such devices - Methods of fabricating transistor in which a first Group III nitride layer is formed on a substrate in a reactor, and a second Group III nitride layer is formed on the first Group III nitride layer. An insulating layer such as, for example, a silicon nitride layer is formed on the second Group III nitride layer in-situ in the reactor. The substrate including the first Group III nitride layer, the second group III nitride layer and the silicon nitride layer is removed from the reactor, and the silicon nitride layer is patterned to form a first contact hole that exposes a first contact region of the second Group III nitride layer. A metal contact is formed on the first contact region of the second Group III nitride layer. | 2010-03-18 |
20100068856 | CHARGE MAPPING MEMORY ARRAY FORMED OF MATERIALS WITH MUTABLE ELECTRICAL CHARACTERISTICS - A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. | 2010-03-18 |
20100068857 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME - A semiconductor device in which a channel region of MOS transistor is provided not to include a non-flat active region end portion and a manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor device comprising a semiconductor substrate, a device isolation separating active region, wherein at least a portion of the device isolation is provided in the semiconductor substrate, and a memory cell including a memory cell transistor that comprises a channel region separated by a slit and constituted of a flat active region alone, a charge storage layer provided on a gate dielectric on the channel region, and a first gate electrode provided on an inter-electrode dielectric so as to cover the charge storage layer, and a select transistor that comprises a second gate electrode provided on the gate dielectric on the active region and electrically connected to a wiring. | 2010-03-18 |
20100068858 | DOUBLE GATE FET AND FABRICATION PROCESS - A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulating material, an active layer of crystalline semiconductor material, an upper gate insulating layer of crystalline rare earth insulating material, and an upper gate layer of crystalline rare earth conductive material. The upper gate layer and the upper gate electrically insulating layer are etched and a contact is deposited on the upper gate layer to define an upper gate structure. An impurity is implanted into the lower gate layer to define a lower gate area aligned with the upper gate structure. A source and drain are formed in the active layer and contacts are deposited on the source and drain, respectively. | 2010-03-18 |
20100068859 | METHOD OF MANUFACTURING A FET GATE - A method of manufacturing a FET gate with a plurality of materials includes depositing a dummy region | 2010-03-18 |
20100068860 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF - There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region. | 2010-03-18 |
20100068861 | METHOD OF DEFINING GATE STRUCTURE HEIGHT FOR SEMICONDUCTOR DEVICES - Provided is a method of semiconductor fabrication including process steps allowing for defining and/or modifying a gate structure height during the fabrication process. The gate structure height may be modified (e.g., decreased) at one or more stages during the fabrication by etching a portion of a polysilicon layer included in the gate structure. The method includes forming a coating layer on the substrate and overlying the gate structure. The coating layer is etched back to expose a portion of the gate structure. The gate structure (e.g., polysilicon) is etched back to decrease the height of the gate structure. | 2010-03-18 |
20100068862 | SEMICONDUCTOR DEVICE HAVING A ROUND-SHAPED NANO-WIRE TRANSISTOR CHANNEL AND METHOD OF MANUFACTURING SAME - A field-effect transistor (FET) with a round-shaped nano-wire channel and a method of manufacturing the FET are provided. According to the method, source and drain regions are formed on a semiconductor substrate. A plurality of preliminary channel regions is coupled between the source and drain regions. The preliminary channel regions are etched, and the etched preliminary channel regions are annealed to form FET channel regions, the FET channel regions having a substantially circular cross-sectional shape. | 2010-03-18 |
20100068863 | Method of Manufacturing a Bipolar Transistor and Bipolar Transistor Obtained Therewith - The invention relates to a method of manufacturing a semiconductor device ( | 2010-03-18 |
20100068864 | APPARATUS AND METHOD FOR WAFER LEVEL FABRICATION OF HIGH VALUE INDUCTORS ON SEMICONDUCTOR INTEGRATED CIRCUITS - Methods for forming multiple inductors on a semiconductor wafer are described. A plating layer and a photoresist layer are applied over a semiconductor wafer. Recess regions are etched in the photoresist layer using photolithographic techniques, which exposes portions of the underlying plating layer. Metal is electroplated into the recess regions in the photoresist layer to form multiple magnetic core inductor members. A dielectric insulating layer is applied over the magnetic core inductor members. Additional plating and photoresist layers are applied over the dielectric insulating layer. Recess regions are formed in the newly applied photoresist layer. Electroplating is used to form inductor windings in the recess regions. Optionally, a magnetic paste can be applied over the inductor coils. | 2010-03-18 |
20100068865 | METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION LAYER OF SEMICONDUCTOR DEVICE - An electrical device, such as a semiconductor device, and methods of manufacturing the same. A semiconductor device having a shallow trench isolation (STI) layer may include a pad oxide layer formed over a semiconductor substrate, a trench formed over the substrate, a liner insulating layer formed over the trench, a gap-fill insulating layer formed over the liner insulating layer and a gate layer formed over the substrate. The gap-fill insulating layer may have a relatively and/or substantially planar polished surface. Methods of fabricating a semiconductor device having a shallow trench isolation (STI) layer may include performing a first chemical mechanical polishing over a gap-fill insulating layer to expose and/or target a portion of a liner insulating layer and performing a second chemical mechanical polishing over a gap-fill insulating layer to remove a portion of a liner insulating layer. | 2010-03-18 |
20100068866 | III-V Compound Semiconductor Epitaxy From a Non-III-V Substrate - A method of forming a circuit structure includes providing a substrate; forming recesses in the substrate; forming a mask layer over the substrate, wherein the mask layer covers non-recessed portions of the substrate, with the recesses exposed through openings in the mask layer; forming a buffer/nucleation layer on exposed portions of the substrate in the recesses; and growing a group-III group-V (III-V) compound semiconductor material from the recesses until portions of the III-V compound semiconductor material grown from the recesses join each other to form a continuous III-V compound semiconductor layer. | 2010-03-18 |
20100068867 | METHOD FOR PRODUCING BONDED SILICON WAFER - A bonded silicon wafer is produced by a method comprising an oxygen ion implantation step on a silicon wafer for active layer having the specified wafer face; a step of bonding the silicon wafer for active layer to a silicon wafer for support; a first heat treatment step; an inner SiO | 2010-03-18 |
20100068868 | Wafer temporary bonding method using silicon direct bonding - A wafer temporary bonding method using silicon direct bonding (SDB) may include preparing a carrier wafer and a device wafer, adjusting roughness of a surface of the carrier wafer, and combining the carrier wafer and the device wafer using the SDB. Because the method uses SDB, instead of an adhesive layer, for a temporary bonding process, a module or process to generate and remove an adhesive is unnecessary. Also, a defect in a subsequent process, for example, a back-grinding process, due to irregularity of the adhesive may be prevented. | 2010-03-18 |
20100068869 | METHOD FOR FABRICATING A MICRO-ELECTRONIC DEVICE EQUIPPED WITH SEMI-CONDUCTOR ZONES ON AN INSULATOR WITH A HORIZONTAL GE CONCENTRATION GRADIENT - A method for the realization of a microelectronic device which includes at least one semi-conductor zone which rests on a support and which exhibits a Germanium concentration gradient in a direction parallel to the principal plane of the support,
| 2010-03-18 |
20100068870 | High Speed Thin Film Deposition via Pre-Selected Intermediate - A method and apparatus for the unusually high rate deposition of thin film materials on a stationary or continuous substrate. The method includes delivery of a pre-selected precursor intermediate to a deposition chamber and formation of a thin film material from the intermediate. The intermediate is formed outside of the deposition chamber and includes a metastable species such as a free radical. The intermediate is pre-selected to include a metastable species conducive to the formation of a thin film material having a low defect concentration. By forming a low defect concentration material, deposition rate is decoupled from material quality and heretofore unprecedented deposition rates are achieved. In one embodiment, the pre-selected precursor intermediate is SiH | 2010-03-18 |
20100068871 | Microwave Heating for Semiconductor Nanostructure Fabrication - The present invention grows nanostructures using a microwave heating-based sublimation-sandwich SiC polytype growth method comprising: creating a sandwich cell by placing a source wafer parallel to a substrate wafer, leaving a small gap between the source wafer and the substrate wafer; placing a microwave heating head around the sandwich cell to selectively heat the source wafer to a source wafer temperature and the substrate wafer to a substrate wafer temperature; creating a temperature gradient between the source wafer temperature and the substrate wafer temperature; sublimating Si- and C-containing species from the source wafer, producing Si- and C-containing vapor species; converting the Si- and C-containing vapor species into liquid metallic alloy nanodroplets by allowing the metalized substrate wafer to absorb the Si- and C-containing vapor species; and growing nanostructures on the substrate wafer once the alloy droplets reach a saturation point for SiC. The substrate wafer may be coated with a thin metallic film, metal nanoparticles, and/or a catalyst. | 2010-03-18 |
20100068872 | Method for Fabricating Single-Crystalline Substrate Containing Gallium Nitride - The present invention provides a method for fabricating a single-crystalline substrate containing gallium nitride (GaN) comprising the following steps. First, form a plurality of island containing GaN on a host substrate. Next, use the plurality of islands containing GaN as a mask to etch the substrate and form an uneven host substrate. Then, perform epitaxy on the uneven host substrate to make the islands containing GaN grow in size and merge into a continuous single-crystalline film containing GaN. Finally, separate the single-crystalline film containing GaN from the uneven host substrate to obtain the single-crystalline substrate containing GaN. According to the present invention, process time can be saved and yield can be improved. | 2010-03-18 |
20100068873 | Depletion-Free MOS using Atomic-Layer Doping - A semiconductor device and a method of manufacturing are provided. A dielectric layer is formed over a substrate, and a first silicon-containing layer, undoped, is formed over the dielectric layer. Atomic-layer doping is used to dope the undoped silicon-containing layer. A second silicon-containing layer is formed over first silicon-containing layer. The process may be expanded to include forming a PMOS and NMOS device on the same wafer. For example, the first silicon-containing layer may be thinned in the PMOS region prior to the atomic-layer doping. In the NMOS region, the doped portion of the first silicon-containing layer is removed such that the remaining portion of the first silicon-containing layer in the NMOS is undoped. Thereafter, another atomic-layer doping process may be used to dope the first silicon-containing layer in the NMOS region to a different conductivity type. A third silicon-containing layer may be formed doped to the respective conductivity type. | 2010-03-18 |
20100068874 | METHOD FOR FORMING A SACRIFICIAL SANDWICH STRUCTURE - The present disclosure provides a method for making a semiconductor device. The method includes forming a first material layer on a substrate; forming a second material layer on the first material layer; forming a sacrificial layer on the second material layer; forming a patterned resist layer on the sacrificial layer; applying a first wet etching process using a first etch solution to the substrate to pattern the sacrificial layer using the patterned resist layer as a mask, resulting in a patterned sacrificial layer; applying an ammonia hydroxide-hydrogen peroxide-water mixture (APM) solution to the substrate to pattern the second material layer, resulting in a patterned second material layer; applying a second wet etching process using a second etch solution to the substrate to pattern the first material layer; and applying a third wet etching process using a third etch solution to remove the patterned sacrificial layer. | 2010-03-18 |
20100068875 | DOUBLE TREATMENT ON HARD MASK FOR GATE N/P PATTERNING - The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region, forming first and second gate stacks over the first and second regions, respectively, the first and second gate stacks each including a dummy gate electrode, removing the dummy gate electrodes from the first and second gate stacks, respectively, thereby forming trenches, forming a metal layer to partially fill the trenches, forming an oxide layer over the metal layer filling a remaining portion of the trenches, applying a first treatment to the oxide layer, forming a patterned photoresist layer on the oxide layer overlying the first region, applying a second treatment to the oxide layer overlying the second region, etching the oxide layer overlying the second region, etching the first metal layer overlying the second region, removing the patterned photoresist layer, and removing the oxide layer overlying the first region. | 2010-03-18 |
20100068876 | METHODS OF FABRICATING HIGH-K METAL GATE DEVICES - Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate. | 2010-03-18 |
20100068877 | METHOD FOR TUNING A WORK FUNCTION OF HIGH-K METAL GATE DEVICES - The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming first and second transistors in the substrate, the first transistor having a first gate structure that includes a first dummy gate, the second transistor having a second gate structure that includes a second dummy gate, removing the first and second dummy gates thereby forming a first trench and a second trench, respectively, forming a first metal layer to partially fill in the first and second trenches, removing the first metal layer within the first trench, forming a second metal layer to partially fill in the first and second trenches, forming a third metal layer to partially fill in the first and second trenches, reflowing the second metal layer and the third metal layer, and forming a fourth metal layer to fill in the remainder of the first and second trenches. | 2010-03-18 |
20100068878 | THIN FILM FUSE PHASE CHANGE CELL WITH THERMAL ISOLATION PAD AND MANUFACTURING METHOD - A memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode and the top side of the second electrode extends outwardly from the top sides of the first and second electrodes defining a wall of insulating material having top side. A bridge of memory material crosses the insulating member over the top of the wall, and defines an inter-electrode path between the first and second electrodes across the insulating member. An array of such memory cells is provided. The bridge comprises an active layer of memory material on the top side of the wall, having at least two solid phases and a layer of thermal insulating material overlying the memory material having thermal conductivity less than a thermal conductivity of the first and second electrodes. | 2010-03-18 |
20100068879 | CONTACT FOR MEMORY CELL - A contact for memory cells and integrated circuits having a conductive layer supported by the sidewall of a dielectric mesa, memory cells incorporating such a contact, and methods of forming such structures. | 2010-03-18 |
20100068880 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS - A method for manufacturing a semiconductor device that improves the reliability of a metal cap layer and productivity. The method includes an insulation layer step of superimposing an insulation layer ( | 2010-03-18 |
20100068881 | Method of forming metallization in a semiconductor device using selective plasma treatment - A method of forming metallization in a semiconductor device, including forming an interlayer insulation layer on a semiconductor layer, forming a hole in the interlayer insulation layer by removing a portion of the interlayer insulation layer, forming a metal seed layer in the hole and on an upper surface of the interlayer insulation layer, such that the metal seed layer includes a first portion on the upper surface of the interlayer insulation layer, a second portion on an upper side surface of the hole, and a third portion on central and lower side surfaces of the hole, selectively plasma-treating a portion of the metal seed layer, forming a metal layer on the metal seed layer to fill the hole, and forming metallization by polishing the metal layer. | 2010-03-18 |
20100068882 | Semiconductor Device and Method for Manufacturing the Same - The present method for manufacturing a semiconductor device comprises the steps of forming an aluminum wiring layer on a substrate; sequentially forming a hard mask, a polysilicon layer, and a bottom anti-reflective coating over the aluminum wiring layer; etching the polysilicon layer using a photoresist pattern formed over the bottom anti-reflective coating as mask; etching the hard mask to a predetermined thickness; and etching the hard mask to expose the aluminum wiring layer. The method for manufacturing a semiconductor device according to the present invention may prevent byproducts and polymer residue from when patterning the hard mask. As a result, the presently disclosed methods may avoid the need for a conventional cleaning process prior to etching the aluminum wiring layer to form aluminum lines. | 2010-03-18 |
20100068883 | CMP SLURRY COMPOSITION FOR FORMING METAL WIRING LINE - Disclosed is CMP slurry, which includes a pyridine-based compound including at least two pyridinyl groups, and minimizes the occurrence of dishing and erosion of a wiring line. | 2010-03-18 |
20100068884 | METHOD OF ETCHING A LAYER OF A SEMICONDUCTOR DEVICE USING AN ETCHANT LAYER - A method of semiconductor fabrication including an etching process is provided. The method includes providing a substrate and forming a target layer on the substrate. An etchant layer is formed on the target layer. The etchant layer reacts with the target layer and etches a portion of the target layer. In an embodiment, an atomic layer of the target layer is etched. The etchant layer is then removed from the substrate. The process may be iterated any number of times to remove a desired amount of the target layer. In an embodiment, the method provides for decreased lateral etching. The etchant layer may provide for improved control in forming patterns in thin target layers such as, capping layers or high-k dielectric layers of a gate structure. | 2010-03-18 |
20100068885 | SIDEWALL FORMING PROCESSES - An etch layer underlying a patterned photoresist mask is provided. A plurality of sidewall forming processes are performed. Each sidewall forming process comprises depositing a protective layer on the patterned photoresist mask by performing multiple cyclical depositions. Each cyclical deposition involves at least a depositing phase for depositing a deposition layer over surfaces of the patterned photoresist mask and a profile shaping phase for shaping vertical surfaces in the deposition layer. Each sidewall forming process further comprises a breakthrough etch for selectively etching horizontal surfaces of the protective layer with respect to vertical surfaces of the protective layer. Afterwards, the etch layer is etched to form a feature having a critical dimension that is less than the critical dimension of the features in the patterned photoresist mask. | 2010-03-18 |
20100068886 | METHOD OF FABRICATING A DIFFERENTIAL DOPED SOLAR CELL - A method of fabricating a differential doped solar cell is described. The method includes the following steps. First, a substrate is provided. A doping process is conducted thereon to form a doped layer. A heavy doping portion of the doped layer is partially or fully removed. Subsequently, an anti-reflection coating layer is formed thereon. A metal conducting paste is printed on the anti-reflection coating layer and is fired to form the metal electrodes for the solar cell. | 2010-03-18 |
20100068887 | PLASMA REACTOR WITH ADJUSTABLE PLASMA ELECTRODES AND ASSOCIATED METHODS - Plasma reactors with adjustable plasma electrodes and associated methods of operation are disclosed herein. The plasma reactors can include a chamber, a workpiece support for holding a microfeature workpiece, and a plasma electrode in the chamber and spaced apart from the workpiece support. The plasma electrode has a first portion and a second portion configured to move relative to the first portion. The first and second portions are configured to electrically generate a plasma between the workpiece support and the plasma electrode. | 2010-03-18 |
20100068888 | DRY ETCHING METHOD - A dry etching method includes: mounting a silicon substrate on an electrode arranged in a processing chamber; generating a plasma by discharging an etching gas in the processing chamber; supplying to the electrode a radio frequency power for attracting ions from the plasma; and etching the silicon substrate by the plasma by using an inorganic mask containing silicon as an etching mask. An absolute value of a self-bias voltage generated in the electrode is equal to or smaller than about 280 V, and wherein the etching is carried out while satisfying the following equation: y≦0.0114x+0.171, where x is a pressure inside the processing chamber and y is a power density of the radio frequency power per unit area of the electrode. | 2010-03-18 |
20100068889 | PARTICLE-CONTAINING ETCHING PASTES FOR SILICON SURFACES AND LAYERS - The present invention relates to particle-containing etching media in the form of etching pastes which are suitable for the full-area or selective etching of extremely fine lines or structures in silicon surfaces and layers and in glass-like surfaces formed from suitable silicon compounds. The present invention also relates to the use of the pastes according to the invention in processes for etching surfaces of this type. | 2010-03-18 |
20100068890 | PRINTABLE MEDIUM FOR ETCHING OXIDIC, TRANSPARENT AND CONDUCTIVE LAYERS - The present invention relates to novel printable etching media having improved properties for use in the process for the production of solar cells. These are corresponding particle-containing compositions by means of which extremely fine lines and structures can be etched very selectively without damaging or attacking adjacent areas. | 2010-03-18 |
20100068891 | METHOD OF FORMING BARRIER FILM - A barrier film made of a ZrB | 2010-03-18 |
20100068892 | SUBSTRATE PROCESSING METHOD - In a substrate processing method of processing a substrate in which a processing target layer, an intermediate layer, and a mask layer are stacked one on top of another, the mask layer having an opening that partially exposes the intermediate layer, a thickness of the mask layer is increased by depositing deposits on an upper surface of the mask layer with plasma generated from a mixed gas of SF | 2010-03-18 |
20100068893 | FILM DEPOSITION APPARATUS, FILM DEPOSITION METHOD, AND COMPUTER READABLE STORAGE MEDIUM - A film deposition apparatus includes a reaction chamber evacuatable to a reduced pressure; a substrate holding portion rotatably provided in the reaction chamber and configured to hold a substrate; a first reaction gas supplying portion configured to flow a first reaction gas from an outer edge portion toward a center portion of the substrate holding portion; a second reaction gas supplying portion configured to flow a second reaction gas from an outer edge portion toward a center portion of the substrate holding portion; a separation gas supplying portion configured to flow a separation gas from an outer edge portion toward a center portion of the substrate holding portion, the separation gas supplying portion being arranged between the first and the second gas supplying portions; and an evacuation portion located in the center portion of the substrate holding portion in order to evacuate the first, the second, and the separation gases. | 2010-03-18 |
20100068894 | COMPOSITION AND METHOD FOR LOW TEMPERATURE CHEMICAL VAPOR DEPOSITION OF SILICON-CONTAINING FILMS INCLUDING SILICON CARBONITRIDE AND SILICON OXYCARBONITRIDE FILMS - Silicon precursors for forming silicon-containing films in the manufacture of semiconductor devices, such as films including silicon carbonitride, silicon oxycarbonitride, and silicon nitride (Si | 2010-03-18 |
20100068895 | Substrate processing apparatus and substrate processing method - A substrate processing apparatus includes a processing chamber that processes a substrate, and a substrate placing base enclosed in the processing chamber, and a substrate transporting member that allows the substrate to wait temporarily on the substrate placing base, and exhaust holes provided so as to surround the substrate placing base, and a retracting space that allows the substrate transporting member to move in between lines each connecting the exhaust hole and an upper end of the substrate placing base and the substrate placing base. | 2010-03-18 |
20100068896 | METHOD OF PROCESSING SUBSTRATE - A method of processing a substrate to form a thin film into which an impurity is introduced, the method including forming a thin film on the substrate; and introducing the impurity to the thin film by irradiating a gas cluster ion beam, which is generated by ionizing and accelerating a gas cluster of the impurity, onto the thin film. | 2010-03-18 |
20100068897 | DIELECTRIC TREATMENT PLATFORM FOR DIELECTRIC FILM DEPOSITION AND CURING - A system for curing a low dielectric constant (low-k) dielectric film on a substrate is described, wherein the dielectric constant of the low-k dielectric film is less than a value of approximately 4. The system comprises one or more process modules configured for exposing the low-k dielectric film to electromagnetic (EM) radiation, such as infrared (IR) radiation and ultraviolet (UV) radiation. | 2010-03-18 |
20100068898 | MANAGING THERMAL BUDGET IN ANNEALING OF SUBSTRATES - A method and apparatus are provided for treating a substrate. The substrate is positioned on a support in a thermal treatment chamber. Electromagnetic radiation is directed toward the substrate to anneal a portion of the substrate. Other electromagnetic radiation is directed toward the substrate to preheat a portion of the substrate. The preheating reduces thermal stresses at the boundary between the preheat region and the anneal region. Any number of anneal and preheat regions are contemplated, with varying shapes and temperature profiles, as needed for specific embodiments. Any convenient source of electromagnetic radiation may be used, such as lasers, heat lamps, white light lamps, or flash lamps. | 2010-03-18 |
20100068899 | Lighting System - A lighting system comprising a socket, a light fixture and a magnetic holding mechanism. The magnetic holding mechanism may be removably or integrally attached to the socket. The magnetic holding mechanism may be situated at the inner walls of the cavity created by the socket close to the socket's opening; and the light fixture comprises at least one magnetic coupler enabling to magnetically couple to the magnetic holding mechanism's coupler, once the mechanism is attached to the socket and the light fixture is inserted into the socket and couples to the magnetic holding mechanism. The socket may hold the light fixture's weight by the magnetic force attracting the couplers. | 2010-03-18 |
20100068900 | Electrical connector with low profile contacts - An electrical connector includes: an insulating housing having a plurality of passageways; a plurality of contacts retained in the passageways of the insulating housing, the contact having a retaining beam engaged with the insulating housing, a first contacting beam extending from the retaining beam, a second contacting beam opposite to the first contacting beam and a connecting portion connected with the first and second contacting beam. The second contacting beam and the connecting portion define an acute angle between 10° to 40° to make the contact in a low profile. The insulating housing has a blocking portion with a large thickness protruding into the passageway to downwardly block the second contacting beam from upwardly moving. | 2010-03-18 |
20100068901 | SURFACE MOUNT CONTACT - A surface mount contact interposes between a mounted conductor and a pressing conductive member to make the mounted conductor conductive to the pressing conductive member when the mounted conductor and the pressing conductive member are proximate to each other. The surface mount contact includes: a base portion solderable to the mounted conductor; a movable portion elastically deformable according to a distance between the mounted conductor and the pressing conductive member, at least a part of the movable portion being closer to the base portion when the movable portion elastically deforms; and an insulating coating film provided in a region where the movable portion is closer to the base portion and inhibiting electric contact between the movable portion and the base portion. | 2010-03-18 |
20100068902 | ELECTRICAL CONNECTOR WITH MATCHED COUPLING - An electrical connector includes a housing having a mating end and a mounting end. The electrical connector also includes a plurality of contact modules each having a web with opposed contact faces and flanges extending from ends of the web. Each contact module holds a pair of signal contacts with the signal contacts being arranged along the contact faces. The flanges and the web forming channels that expose the contact faces and signal contacts. The electrical connector includes a plurality of ground contacts each being coupled to at least one of the housing and a corresponding contact module. Each ground contact being arranged along one of the flanges of the corresponding contact module | 2010-03-18 |
20100068903 | Electrical connector - An electrical connector includes a housing, a plurality of terminals fixed in the housing and a shell encircling the housing. The shell has two opposing sidewalls each having a holding portion extending and bending outward therefrom and being spaced a distance from a bottom of the shell. An inserting portion extends downward from a place of the holding portion. The electrical connector is adapted for being mounted to a printed circuit board which defines a receiving space and two fixing holes with the inserting portions inserted into the fixing holes and the holding portions placed on the printed circuit board. Therefore, the electrical connector has a portion below the holding portions sunk in the receiving space and the total height thereof is reduced. | 2010-03-18 |
20100068904 | MODULAR ELECTRICAL CONNECTOR WITH OPPOSING CONTACT SUPPORT MEMBERS - A contact sub-assembly is provided for an electrical connector. The contact sub-assembly includes a base configured for mounting to a mating component. The base includes a pair of opposite side surfaces. A pair of separate contact support members are mounted on the base. Each contact support member holds a separate set of electrical contacts. Each contact support member includes a mounting portion engaged with a corresponding one of the side surfaces of the base such that a portion of the base extends between the mounting portions of the contact support members. The sets of electrical contacts held by the contact support members cooperate to define a mating interface for a mating connector. | 2010-03-18 |
20100068905 | EXTENSION-TYPE SPARK PLUG - An extension-type spark plug includes an upper terminal stud and a lower terminal stud axially spaced from one another in electrical communication with one another. An upper tubular insulator having a through cavity surrounds at least a portion of the upper terminal stud. A lower insulator constructed of a separate piece of material from the upper insulator has a through cavity surrounding at least a portion of the lower terminal stud. A spring member is disposed between the upper terminal stud and the lower terminal stud and biases the upper terminal stud and the lower member away from one another. The spring member allows the upper terminal stud to move axially under an externally applied force sufficient to overcome the bias imparted by the spring member and maintains electrical communication between said upper terminal stud and said lower terminal stud. | 2010-03-18 |
20100068906 | LEVER ENGAGEMENT TYPE CONNECTOR - A lever type engagement connector includes a first connector; a second connector to be engaged with the first connector; and a lever including a connection portion at which the lever is jointed to the first connector, and an end portion at which the lever is jointed to the second connector so as to rotate from a first position to a second position, an operation portion which is provided at an opposite side of the end portion respective to the connection portion, and a lock portion which is provided between the operation portion and the first connector when the lever is at the first position and is engaged with the second connector when the lever is at a second position. Preferably, the operation portion defines a touching surface and the lock portion is provided below the touching surface. | 2010-03-18 |