| 11th week of 2011 patent applcation highlights part 56 |
| Patent application number | Title | Published |
|---|
| 20110066771 | LANE TO LANE DESKEWING VIA NON-DATA SYMBOL PROCESSING FOR A SERIAL POINT TO POINT LINK - Multiple symbol sequences that have been transmitted in parallel using the same transmit clock over a serial point to point link are received. Each symbol sequence includes an instance of a first, non-data symbol. The multiple symbol sequences are buffered and the number of times an instance of a second, non-data symbol that occurs in one of the symbol sequences is changed. A first deskew process is performed, followed by a second deskew process. The first deskew process aligns an instance of the first non-data symbol in every one of the buffered symbol sequences. The second deskew process equalizes the number of instances of the second non-data symbol that follow an instance of the first non-data symbol in every one of the symbol sequences. Other embodiments are also described and claimed. | 2011-03-17 |
| 20110066772 | CONTROLLING ACCESS TO DIGITAL CONTENT - Method for utilizing digital content is provided. The method includes controlling a throughput rate for utilizing the digital content by an accessing system, where the throughput rate is associated with information related to the digital content and is stored as a file. The throughput rate is controlled by a storage system that is operationally coupled to the accessing system. | 2011-03-17 |
| 20110066773 | REDIRECTING INPUT AND OUTPUT FOR MULTIPLE COMPUTERS - Apparatus, methods, and systems provide for remote management of a set of local computers by transferring screen frames produced by the local computer for viewing at a remote computer. A redirection module captures and transmits video signals from a local computer through over a network, such as the Internet, to a remote computer where the remote computer produces a display that contains the screen frames being transferred. The module is configured for use with and installation within a keyboard, video, and mouse switch configured for receiving the module. The redirection module is further configured for use with and installation on a server-blade to allow remote management of the server-blade. | 2011-03-17 |
| 20110066774 | PROCESSING SYSTEM WITH RF DATA BUS AND METHOD FOR USE THEREWITH - A processing system includes a plurality of first circuit modules. A plurality of second circuit modules are coupled to an RF data bus via a 60 GHz communications. The RF data bus receives first data from at least one of the plurality of first circuit modules, and transmits the first data via 60 GHz communications to at least one of the plurality of second circuit modules. | 2011-03-17 |
| 20110066775 | Communication Between a Media Player and an Accessory with an Extended Interface Mode - An interface and protocol allow a media player to communicate with external accessories over a transport link. The protocol includes a core protocol functionality and a number of accessory lingoes. Examples of accessory lingoes include a microphone lingo, a simple remote lingo, a display remote lingo, an RF transmitter lingo, and an extended interface lingo. | 2011-03-17 |
| 20110066776 | Communication Between a Media Player and an Accessory with an Extended Interface Mode - An interface and protocol allow a media player to communicate with external accessories over a transport link. The protocol includes a core protocol functionality and a number of accessory lingoes. Examples of accessory lingoes include a microphone lingo, a simple remote lingo, a display remote lingo, an RF transmitter lingo, and an extended interface lingo. | 2011-03-17 |
| 20110066777 | WIRELESS MEMORY CARD AND METHOD THEREOF - A wireless memory card device includes a casing having a width, a length, and a thickness for supporting an integrated power supply. The device has one or more solar cell modules spatially disposed on a first portion of the casing. The device further includes a power supply control circuitry coupled to the one or more solar cell modules for providing regulated voltages to the device. In addition, the device includes a flash memory module provided in a second portion of the casing and a wireless communication module provided on a third portion of the casing. The device further includes one or more antennas coupled to the wireless communication module for transmitting and receiving data packets to and from a host system. The device additionally includes a power-on switch and an indicator signal for indicating the wireless data transfer between the device and the host system. | 2011-03-17 |
| 20110066778 | METHOD AND APPARATUS FOR TRANSPORTING AND INTEROPERATING TRANSITION MINIMIZED DIFFERENTIAL SIGNALING OVER DIFFERENTIAL SERIAL COMMUNICATION TRANSMITTERS - A differential serial communication transmitter (i.e. PCI Express or other suitable type of transmitter) can be used to transport and interoperate transition minimized differential signaling. The differential serial communication transmitter control logic receives display configuration control data and in response configures at least one differential serial communication transmitter of a plurality of differential serial communication transmitters in an integrated circuit for communication with a display (i.e. visual digital display) employing transition minimized differential signaling. For example, the integrated circuit, such as a graphics processor, may include the plurality of differential serial communication transmitters for communication with devices, such as a northbridge circuit and a display within a computer system. The differential serial communication transmitter control logic may configure at least one of the plurality of differential serial communication transmitters for communication with the display via a differential serial communication display link (i.e. DVI or other suitable type of link). The plurality of differential serial communication transmitters may also be configured for communication with one or more other devices, such as with a bridge circuit such as a northbridge. | 2011-03-17 |
| 20110066779 | DATA PROCESSING SYSTEM, DATA PROCESSING METHOD, AND APPARATUS - A data processing system may include a first data path and a second data path. A set of components may include a system component and a partner component, each having a communication interface for communicating data. The components are operable in a synchronized mode and a non-synchronized mode with respect to each other. The set may further include a configuration control system connected to the system component and the partner component, for controlling the set to be in a synchronized mode configuration or a non-synchronized mode configuration. The configuration control system may include a first path selector module connecting the communication interface of the system component to the first data path and the second data path and a partner path selector module connecting the communication interface of the partner component to the first data path and the second data path. The path selector modules may be arranged to enable, depending on the configuration, communication of data to the respective component via one or more selected data path, selected from the first data path and the second data path, and to inhibit communication via the not selected data paths. | 2011-03-17 |
| 20110066780 | Data processing apparatus and method for measuring a value of a predetermined property of transactions - A data processing apparatus and method for measuring a value of a predetermined property of transactions are provided. The data processing apparatus has initiator circuitry for initiating transactions, recipient circuitry for handling each transaction initiator by the initiator circuitry, and a communication path interconnecting the initiator circuitry and the recipient circuitry via which the transactions are propagated between the initiator circuitry and the recipient circuitry. Measurement circuitry is coupled to the communication path for measuring a value of a predetermined property of the transactions, such as the latency of those transactions. The measurement circuitry has active transaction count circuitry for maintaining an indication of the number of transactions in progress, and accumulator circuitry for maintaining an accumulator value which is increased dependent on the number of transactions in progress. Further, a value register is provided for maintaining an estimate of the value of the predetermined property. Each time a transaction in progress reaches a predetermined point, for example a transaction end point, the accumulator value is decreased dependent on the estimate currently stored in the value register, and further the estimate stored in the value register is updated dependent on the accumulator value. Via this feedback mechanism, the estimate stored in the value register quickly settles to the actual value of the predetermined property being measured, and accordingly such measurement circuitry provides a simple, low cost and flexible mechanism for measuring the value of a predetermined property of transactions. | 2011-03-17 |
| 20110066781 | METHOD FOR ASSIGNING ADRESSES TO INJECTORS - A method for assigning addresses to injectors of an internal combustion machine, wherein, prior to the starting procedure, an electronic motor control device selects a first injector by activating the first injector by a first control line from the electronic motor control device. The electronic motor control device is arranged on a data bus to which the electronic motor control device and all injectors are connected. A first address value is placed on the motor control device and the first injector assumes the first address value as the address assigned to it. | 2011-03-17 |
| 20110066782 | PARTITION BUS - A method and system are provided for integrating partitions in a virtual machine environment. Specifically, a partition bus is provided, where the partition bus operatively connects partitions in such a way that it functions as a data transport mechanism allowing for data transfer and device sharing between partitions. The partition bus relies on virtualizing software in order to establish itself and to establish channels of communication between partitions and to inject interrupts to partitions where it is appropriate to do so. Furthermore, the partition bus employs such mechanisms ring buffers, transfer pages, and memory map changes to transfer information (requests and data). Furthermore, it uses policy agents to decide when information should be transferred or when devices should be shared among partitions. Lastly, it employs various mechanisms to ensure smooth integration between partitions, which includes remote services that have proxy devices and device versioning functionalities. | 2011-03-17 |
| 20110066783 | Secure Handling and Routing of Message-Signaled Interrupts - Encryption of interrupt vectors and authentication of device drivers prevents unauthorized modules from interfering with an interrupt handler. An operating system may encrypt an interrupt vector for a PCI device, initializing a Local Interrupt Controller of a CPU with the key to enable decryption of the interrupt vector, initializing a redirection table on an I/O Interrupt Controller of the CPU with the encrypted interrupt vector, and initializing the PCI device with an encrypted MSI vector for subsequent use in an interrupt request. The PCI device may raise an interrupt that can only be decrypted by the Local Interrupt Controller and used be used by the processor to handle the interrupt. The operating system may also authenticate a driver before executing a request to register, deregister or change an interrupt handler. An authentication code is sent from the OS to the device driver for use in any request. The request is executed only if the operating system determines that the authentication code in the request matches the authentication code stored by the operating system for that device driver. | 2011-03-17 |
| 20110066784 | Adaptive USB extender - An adaptive USB extender is installed in a computer and includes a USB host controller mounted on a computer motherboard, a USB receptacle mounted on an I/O board, a USB cable interconnecting the I/O board and the USB host controller for transmitting USB-compliant signals, and an active signal driver mounted on the I/O board and connected between the USB receptacle and the USB cable for amplifying and buffering the USB-compliant signals, thereby maintaining the signal integrity of the USB-compliant signals. | 2011-03-17 |
| 20110066785 | Memory Management System and Method Thereof - A memory management system and method include and use a cache buffer (such as a table look-aside buffer, TLB), a memory mapping table, a scratchpad cache, and a memory controller. The cache buffer is configured to store a plurality of data structures. The memory mapping table is configured to store a plurality of addresses of the data structures. The scratchpad cache is configured to store the base address of the data structures. The memory controller is configured to control reading and writing in the cache buffer and the scratchpad cache. The components are operable together under control of the memory controller to facilitate effective searching of the data structures in the memory management system. | 2011-03-17 |
| 20110066786 | Method of Suspending and Resuming Virtual Machines - A virtual machine is suspended and quickly restarted while maintaining the VM's state. The method is quick enough so that network connections are maintained across the restart and the guest operating system and guest applications running in the VM are not aware of the restart. As a result, users and clients connected to the VM do not notice any downtime or disruption to the VM. After suspension and before the restart, VM configuration changes that would not be possible or be very difficult through code changes alone while the VM was running can be made. | 2011-03-17 |
| 20110066787 | METHOD AND SYSTEM FOR SECURELY PROGRAMMING OTP MEMORY - A semiconductor chip may be operable to receive and copy an OTP programming vector presented by the semiconductor chip programming device into its memory after it boots up from the boot read-only memory (ROM). The OTP programming vector which is a computer program may comprise an encrypted data to be programmed into the one-time programmable (OTP) memory in the semiconductor chip and may be signed with an electronic signature. The semiconductor chip may be operable to authenticate the OTP programming vector in the memory. The authenticated OTP programming vector in the memory may be executed to decrypt the data and program the data in a random data format into the OTP memory and then report the status via one or more general purpose input/output (GPIO) pins on the semiconductor chip. | 2011-03-17 |
| 20110066788 | CONTAINER MARKER SCHEME FOR REDUCING WRITE AMPLIFICATION IN SOLID STATE DEVICES - A solid state storage device and method are provided. Multiple blocks are configured as storage memory for a solid state storage device, and each block includes multiple pages. A controller is configured to operate the solid state storage device. A free block of the multiple blocks is assigned a marker level by the controller. For a particular page of the multiple pages, each particular page of data is written to a block of the multiple blocks with a marker level corresponding to a level of dynamicity calculated by the controller for that particular page. | 2011-03-17 |
| 20110066789 | FILE SYSTEM DERIVED METADATA FOR MANAGEMENT OF NON-VOLATILE MEMORY - A file system programs metadata on a non-volatile memory device. The metadata can include data associating files with ranges of logical block addresses. During a garbage collection process, the data can be used to determine portions of physical blocks of the non-volatile memory device that are associated with files that have been deleted. Using the programmed metadata during garbage collection results in erasure of larger portions of blocks and improved wear leveling. | 2011-03-17 |
| 20110066790 | MAIN MEMORY WITH NON-VOLATILE MEMORY AND DRAM - One embodiment is main memory that includes a combination of non-volatile memory (NVM) and dynamic random access memory (DRAM). An operating system migrates data between the NVM and the DRAM. | 2011-03-17 |
| 20110066791 | CACHING DATA BETWEEN A DATABASE SERVER AND A STORAGE SYSTEM - Techniques are provided for using an intermediate cache between the shared cache of a database server and the non-volatile storage of a storage system. The intermediate cache may be local to the machine upon which the database server is executing, or may be implemented within the storage system. In one embodiment, the database system includes both a DB server-side intermediate cache, and a storage-side intermediate cache. The caching policies used to populate the intermediate cache are intelligent, taking into account factors that may include which database object an item belongs to, the item type of the item, a characteristic of the item; or the database operation in which the item is involved. | 2011-03-17 |
| 20110066792 | Segmentation Of Flash Memory For Partial Volatile Storage - This disclosure provides a method and system that segment flash memory to have differently managed regions. More particularly, flash memory is segmented into a “non-volatile” region, where program counts are restricted to preserve baseline retention assumptions, and a “volatile” region, where program counts are unrestricted. Contrary to conventional wisdom, wear leveling is not performed on all flash memory, as the volatile region is regarded as degraded, and as the non-volatile region has program counts restricted to promote long-term retention. More than two regions may also be created; each of these may be associated with intermediate program counts and volatility expectations, and wear leveling may be applied to each of these on an independent basis if desired. Refresh procedures may optionally be applied to the region of flash memory which is treated as volatile memory. | 2011-03-17 |
| 20110066793 | Implementing RAID In Solid State Memory - The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving data to be stored, dividing data into logical data blocks, assigning the blocks to a logical block grouping comprising at least one physical data storage block from two or more of multiple solid state physical memory devices, storing the blocks in physical data storage blocks, determining a code that corresponds to the persisted data, and storing the code that corresponds to the data stored in the logical block grouping. Blocks of damaged stored data may be recovered by identifying the logical data block and logical block grouping corresponding to the damaged physical data storage block, reading the data and the code stored in the identified grouping, and comparing the code to the read data other than the data stored in the damaged block. | 2011-03-17 |
| 20110066794 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor device comprises a board, a first semiconductor storage device placed on the board, and a second semiconductor storage device placed on the board. Each of the first and second semiconductor storage devices has a first pad for inputting a chip enable signal, a second pad for inputting a write enable signal, a third pad for inputting an output enable signal, a fourth pad for inputting an address signal, and a fifth pad for inputting data. The first semiconductor storage device has a sixth pad which is electrically connected to the first pad of the second semiconductor device, and the second semiconductor storage device has a seventh pad which is electrically connected to the first pad of the first semiconductor device. | 2011-03-17 |
| 20110066795 | STREAM CONTEXT CACHE SYSTEM - The present invention is directed to a stream context cache system, which primarily includes a cache and a mapping table. The cache stores plural stream contexts, and the mapping table stores associated stream context addresses in a system memory. Consequently, a host may, according to the content of the mapping table, directly retrieve the stream context that is pre-fetched and stored in the cache, rather than read the stream context from the system memory. | 2011-03-17 |
| 20110066796 | AUTONOMOUS SUBSYSTEM ARCHITECTURE - An autonomous sub-system receives a database downloaded from a host controller. A controller monitors bus traffic and/or allocated resources in the subsystem and re-allocates resources based on the monitored results to dynamically improve system performance. | 2011-03-17 |
| 20110066797 | MEMORY SYSTEM - A memory system according to the present invention includes a bus connected to process units, a first DRAM which has a first storage area and a second storage area and which is controlled in operation by a DRAM control signal, a second DRAM which has the same bit width as that of the first DRAM, which has a third storage area having the same address space as that of the first storage area and having a capacity equal to that of the first storage area, and which is controlled in operation by the DRAM control signal, and a controller which is provided with a read command and a logical address from the process units via the bus, which controls operation of the first DRAM and the second DRAM according to the read command and the logical address, and thereby outputs data read from the first DRAM or the second DRAM to the process units via the bus. | 2011-03-17 |
| 20110066798 | Semiconductor device having calibration circuit that adjusts an impedance of output buffer and data processing system including the same - A calibration operation can be performed automatically at a semiconductor device without issuing a calibration command from a controller. Because a calibration operation is performed in response to a fact that the auto refresh command has been issued for a predetermined number of times, a periodical calibration operation can be secured and a read operation or a write operation is not requested from a controller during a calibration operation. | 2011-03-17 |
| 20110066799 | Enhanced virtual storage replication - Systems and methods of enhanced virtual storage replication are disclosed. An exemplary method comprises moving a virtual tape from a local virtual library to a remote virtual library. The method also comprises ejecting the virtual tape moved to the remote virtual library. The method also comprises recycling the ejected virtual tape at the local virtual library based on a remote retention policy. | 2011-03-17 |
| 20110066800 | DATA STORAGE SYSTEM INCLUDING RESPECTIVE BUFFERS FOR NON-VOLATILE MEMORY AND DISC RECORDING MEDIUM, AND DATA ACCESS METHOD THEREOF - A data storage system includes a non-volatile memory, a disc recording medium, a non-volatile memory buffer, operatively disposed between a host interface and the non-volatile memory, which stores a portion of data stored in the non-volatile memory, and a disc buffer, operatively disposed between the host interface and the disc recording medium, which stores a portion of data stored in the disc recording medium. The data storage system may be configured to receive an access address from a host operatively connected to the host interface, and sequentially determine whether the access address exists in one of the non-volatile memory buffer, the non-volatile memory, the disc buffer, and the disc recording medium, in that order. | 2011-03-17 |
| 20110066801 | STORAGE SYSTEM AND METHOD FOR CONTROLLING THE SAME - A storage system in accordance with the present invention creates a virtual volume based on a remote copy pair and provides the virtual volume to a host. A first storage device and a second storage device share a locked disk in a third storage device. The information for controlling a usage of the virtual volume is stored into the locked disk. The virtual volume is created based on a remote copy pair composed of a primary volume and a secondary volume. A user can create and delete a virtual volume and a locked disk by issuing an instruction from a management server. | 2011-03-17 |
| 20110066802 | DYNAMIC PAGE REALLOCATION STORAGE SYSTEM MANAGEMENT - In one embodiment, a storage system for storage management in a tiered storage environment comprises a plurality of storage volumes in a pool which are divided into a plurality of tiers having different tier levels, the tiers being organized according to a tier configuration rule, the plurality of storage volumes provided by a plurality of physical storage devices in the storage system; and a controller controlling the plurality of physical storage devices, the controller including a processor and a memory. The controller changes tier configurations of the tiers of storage volumes when the tier configuration rule is changed, the tier configurations including the tier levels. The controller allocates the pool to a plurality of virtual volumes based on a change of tier levels against the physical storage devices which occurs when the pool does not meet the tier configuration rule that was in effect. | 2011-03-17 |
| 20110066803 | METHOD AND APPARATUS TO UTILIZE LARGE CAPACITY DISK DRIVES - A method of utilizing storage in a storage system comprises prioritizing a plurality of storage areas in the storage system for data recovery with different priorities; and performing data recovery of the storage system at an occurrence of a failure involving one or more of the storage areas in the storage system based on the priorities. Data recovery for one storage area having a higher priority is to occur before data recovery for another storage area having a lower priority in the storage system. In various embodiments, the prioritization is achieved by monitoring the access characteristics, or the priority is specified by the host or management computer based on the usage and/or importance of data stored in the storage system, or the priority is determined by the storage system based on the area assignment/release (i.e., usage) of thin provisioned volumes. | 2011-03-17 |
| 20110066804 | STORAGE DEVICE AND INFORMATION MANAGEMENT SYSTEM - Using a snapshot function, a remote copy is efficiently created. Data for a snapshot is converted into a first bitmap of differential data for a remote copy. The conversion is performed in advance at appropriate chronological intervals. Furthermore, when the snapshot function splits, a second bitmap of cascade differential data, which is new differential data, is created simultaneously with creation of the data for the snapshot. This second bitmap of cascade differential data is created in the same format as the first bitmap of differential data for the remote copy. Then, when the snapshot function shifts from split status to pair status, the second bitmap of cascade differential data is added to the first bitmap of differential data for the remote copy (to produce a logical sum), and a remote copy is created based on this bitmap that was added. | 2011-03-17 |
| 20110066805 | Process For The Management Of Data Of Analysis Devices, Analysis Device And System Comprising Analysis Devices - A process for the management of data of an analysis device, which data serve for the operation of a further analysis device which is designed so as to be equivalent to the first analysis device, is disclosed. The analysis device newly creates or modifies data on an internal memory medium of the analysis device and the first analysis device, during its operation, continuously stores the newly created or modified data in a redundant manner in a non-volatile removable storage medium, with the removable storage medium being independent of the internal memory medium. | 2011-03-17 |
| 20110066806 | System and method for memory bandwidth friendly sorting on multi-core architectures - In some embodiments, the invention involves utilizing a tree merge sort in a platform to minimize cache reads/writes when sorting large amounts of data. An embodiment uses blocks of pre-sorted data residing in “leaf nodes” residing in memory storage. A pre-sorted block of data from each leaf node is read from memory and stored in faster cache memory. A tree merge sort is performed on the nodes that are cache resident until a block of data migrates to a root node. Sorted blocks reaching the root node are written to memory storage in an output list until all pre-sorted data blocks have been moved to cache and merged upward to the root. The completed output list in memory storage is a list of the fully sorted data. Other embodiments are described and claimed. | 2011-03-17 |
| 20110066807 | Protection Against Cache Poisoning - Protecting computers against cache poisoning, including a cache-entity table configured to maintain a plurality of associations between a plurality of data caches and a plurality of entities, where each of the caches is associated with a different one of the entities, and a cache manager configured to receive data that is associated with any of the entities and store the received data in any of the caches that the cache-entity table indicates is associated with the entity, and receive a data request that is associated with any of the entities and retrieve the requested data from any of the caches that the cache-entity table indicates is associated with the requesting entity, where any of the cache-entity table and cache manager are implemented in either of computer hardware and computer software embodied in a computer-readable medium. | 2011-03-17 |
| 20110066808 | Apparatus, System, and Method for Caching Data on a Solid-State Storage Device - An apparatus, system, and method are disclosed for caching data on a solid-state storage device. The solid-state storage device maintains metadata pertaining to cache operations performed on the solid-state storage device, as well as storage operations of the solid-state storage device. The metadata indicates what data in the cache is valid, as well as information about what data in the nonvolatile cache has been stored in a backing store. A backup engine works through units in the nonvolatile cache device and backs up the valid data to the backing store. During grooming operations, the groomer determines whether the data is valid and whether the data is discardable. Data that is both valid and discardable may be removed during the grooming operation. The groomer may also determine whether the data is cold in determining whether to remove the data from the cache device. The cache device may present to clients a logical space that is the same size as the backing store. The cache device may be transparent to the clients. | 2011-03-17 |
| 20110066809 | XML PROCESSING DEVICE, XML PROCESSING METHOD, AND XML PROCESSING PROGRAM - Provided is an XML processing device capable of describing, using conventional XML processing language, a method of processing also an asynchronously inputted XML. The XML processing device converts, according to a predetermined rule, the XML inputted asynchronously from outside and outputs the XML. The XML processing device is characterized by including an XML conversion module which performs XML conversion of the XML inputted according to the rule, an output destination interpretation module which interprets an output destination described in the converted XML, and an output distribution module which allows the XML to be outputted to the output destination interpreted by the output destination interpretation module. | 2011-03-17 |
| 20110066810 | PERSISTENT CACHEABLE HIGH VOLUME MANUFACTURING (HVM) INITIALIZATION CODE - A persistent cacheable high volume manufacturing (HVM) initialization code is generally presented. In this regard, an apparatus is introduced comprising a processing unit, a unified cache, a unified cache controller, and a control register to selectively mask off access by the unified cache controller to portions of the unified cache. Other embodiments are also described and claimed. | 2011-03-17 |
| 20110066811 | STORE AWARE PREFETCHING FOR A DATASTREAM - A system and method for efficient data prefetching. A data stream stored in lower-level memory comprises a contiguous block of data used in a computer program. A prefetch unit in a processor detects a data stream by identifying a sequence of storage accesses referencing a contiguous blocks of data in a monotonically increasing or decreasing manner. After a predetermined training period for a given data stream, the prefetch unit prefetches a portion of the given data stream from memory without write permission, in response to an access that does not request write permission. Also, after the training period, the prefetch unit prefetches a portion of the given data stream from lower-level memory with write permission, in response to determining there has been a prior access to the given data stream that requests write permission subsequent to a number of cache misses reaching a predetermined threshold. | 2011-03-17 |
| 20110066812 | TRANSFER REQUEST BLOCK CACHE SYSTEM AND METHOD - The present invention is directed to a transfer request block (TRB) cache system and method. A cache is used to store plural TRBs, and a mapping table is utilized to store corresponding TRB addresses in a system memory. A cache controller pre-fetches the TRBs and stores them in the cache according to the content of the mapping table. | 2011-03-17 |
| 20110066813 | Method And System For Local Data Sharing - Embodiments for a local data share (LDS) unit are described herein. Embodiments include a co-operative set of threads to load data into shared memory so that the threads can have repeated memory access allowing higher memory bandwidth. In this way, data can be shared between related threads in a cooperative manner by providing a re-use of a locality of data from shared registers. Furthermore, embodiments of the invention allow a cooperative set of threads to fetch data in a partitioned manner so that it is only fetched once into a shared memory that can be repeatedly accessed via a separate low latency path. | 2011-03-17 |
| 20110066814 | CONTROL SOFTWARE FOR DISTRIBUTED CONTROL, AND ELECTRONIC CONTROL DEVICE - The control software which can improve the development efficiency of a control system using a plurality of processing units by absorbing the difference due to the data exchange through a shared storage area is provided. | 2011-03-17 |
| 20110066815 | MEMORY ACCESS CONTROL DEVICE AND MEMORY ACCESS CONTROL METHOD - A memory access control device includes an input data control unit, a processing unit, and an output data control unit. The input data control unit inputs image data from a memory. The processing unit subjects the input image data to a preset process. The output data control unit outputs the processed image data to the memory. | 2011-03-17 |
| 20110066816 | NON-VOLATILE MEMORY DEVICE ADAPTED TO IDENTIFY ITSELF AS A BOOT MEMORY - Non-volatile memory devices and methods of their operation are provided. One such non-volatile memory device has an interface and a control circuit. The non-volatile memory device is adapted to identify itself as a boot memory in response to receiving an interrogation request on the interface. | 2011-03-17 |
| 20110066817 | HIERARCHICAL SYSTEMS AND METHODS FOR PERFORMING STORAGE OPERATIONS IN A COMPUTER NETWORK - A system for performing storage operations using hierarchically configured storage operation cells. The system includes a first storage manager component and a first storage operation cell. The first storage operation cell has a second storage manager component directed to performing storage operations in the first storage operation cell. Moreover, the first storage manager component is programmed to instruct the second storage manager regarding performance of storage operations in the first storage operation cell. | 2011-03-17 |
| 20110066818 | STORAGE DEVICE, MEMORY CONTROLLER, AND DATA PROTECTION METHOD - A storage device, a memory controller, and a data protection method are provided. The method includes when receiving a read command sent by a host, adopting a corresponding output flow rate limit to determine an operation that is executed on read data corresponding to the read command by the host according to location information included in the read command or a type of a transmission interface between the host and the storage device. The method also includes executing an interference procedure by the storage device to prevent the read data from being copied to the host or slow down the speed of copying the read data to the host when identifying that the operation is a copy operation. | 2011-03-17 |
| 20110066819 | Method and System for Optimizing Live Migration of Persistent Data of Virtual Machine Using Disk I/O Heuristics - Techniques for migrating persistent data of virtual machines between and across data stores are optimized using special tracking data structures and monitoring methods. Special tracking data structures include an incremental change block tracking bitmap that indicate what blocks have been modified during a copy operation. The determination of whether any one block has been modified during the copy operation is based on whether or not the copy operation has progressed past that block. Another special tracking data structure is a Bloom filter, which provides a space-efficient data structure for keeping track of dirtied blocks. In addition, heat-based optimization techniques are applied so that blocks that are frequently updated are filtered and not transferred to the destination data store until the last iteration of the migration process. | 2011-03-17 |
| 20110066820 | OVERFLOW HANDLING OF SPECULATIVE STORE BUFFERS - A method, a system and a computer program product for handling speculative stores. The system determines when a speculative store buffer is not full. An indicator is generated when the speculative store buffer is not full, and the speculative stores are input into the speculative store buffer. When the speculative store buffer is full, a full buffer indicator is generated. Speculative stores prevented from entering the speculative store buffer are overflow stores. The overflow list is searched to determine whether one or more addresses of the overflow stores are present in the overflow list. When one or more addresses of the overflow stores are not present in the overflow list, the overflow stores are stored in the overflow list. | 2011-03-17 |
| 20110066821 | DATA HANDLING SYSTEM COMPRISING A REARRANGEMENT NETWORK - A data handling system wherein the system is configured for receiving at an input a first plurality of commands, the plurality of commands comprising a plurality of read commands, and for producing at an output a second plurality of data objects; the system comprises: a plurality of memory banks, a distributor ( | 2011-03-17 |
| 20110066822 | DATA TRANSFER APPARATUS, DATA TRANSFER DEVICE, AND DATA TRANSFER METHOD IN A DATA TRANSFER DEVICE - A data transfer apparatus includes: a first port and a second port that communicate data; a memory unit that stores the data; and a securing unit that secures, when a first time period starting from transmission of data up to reception of a response to transmitted data at the first port is longer than a second time period starting from transmission of data up to reception of a response to transmitted data at the second port, a first memory space that is used in data transfer in the first port so as for the first memory space to have a larger size than a size of a second memory space used in data transfer in the second port. | 2011-03-17 |
| 20110066823 | COMPUTER SYSTEM PERFORMING CAPACITY VIRTUALIZATION BASED ON THIN PROVISIONING TECHNOLOGY IN BOTH STORAGE SYSTEM AND SERVER COMPUTER - The management system identifies a server level virtual volume corresponding to a storage level pool on the basis of storage management information and server management information, and displays information relating to the correspondence between the storage level pool and the server level virtual volume. The storage management information represents correspondence between a storage level virtual volume to which a portion of an area is allocated from the storage level pool by thin provisioning technology at the storage level, and the storage level pool. The server management information represents correspondence between a server level virtual volume to which a portion of an area is allocated from the storage level virtual volume belonging to a server level pool by thin provisioning technology at the server level, and the storage level virtual volume. | 2011-03-17 |
| 20110066824 | Method and System for Combining Page Buffer List Entries to Optimize Caching of Translated Addresses - Certain aspects of a method and system for combining page buffer list entries (PBLEs) to optimize caching of translated addresses are disclosed. Aspects of a method may include encoding at least two page buffer list entries in a remote direct memory access (RDMA) memory map into at least two contiguous memory locations by utilizing a remainder of a physical address corresponding to the two page buffer list entries. The first memory location of the two contiguous memory locations may comprise a base address and a contiguous length of the first page buffer list entry. The second memory location of the two contiguous memory locations may comprise a virtual address and a contiguous length of the second page buffer list entry. | 2011-03-17 |
| 20110066825 | MESSAGE ROUTING SCHEME - Each possessor node in an array of nodes has a respective local node address, and each local node address comprises a plurality of components having an order of addressing significance from most to least significant. Each node comprises: mapping means configured to map each component of the local node address onto a respective routing direction, and a switch arranged to receive a message having a destination node address identifying a destination node. The switch comprises: means for comparing the local node address to the destination node address to identify a the most significant non-matching component; and means for routing the message to another node, on the condition that the local node address does not match the destination node address, in the direction mapped to the most significant non-matching component. | 2011-03-17 |
| 20110066826 | IMAGE DATA PROCESSING APPARATUS - An image data processing apparatus includes: a plurality of operational processing circuits each of which is configured to have a variable circuit configuration and to execute operational processing on image data; and a control section that controls each of the operational processing circuits such that each of the operational processing circuits executes one of a plurality of types of operational processing performed on image data in a predetermined order. The control section controls each of the operational processing circuits so that when image data to be newly given to one of the operational processing circuits is interrupted, said one of the operational processing circuits and another one of the operational processing circuits execute operational processing by taking partial charge of the operational processing. | 2011-03-17 |
| 20110066827 | MULTIPROCESSOR - A multiprocessor of a single processor, including a pipeline processing unit which successively fetches an instruction sequence to be independently processed on each of the multiprocessor with a shifted phase in one cycle. | 2011-03-17 |
| 20110066828 | MAPPING OF COMPUTER THREADS ONTO HETEROGENEOUS RESOURCES - Techniques are generally described for mapping a thread onto heterogeneous processor cores. Example techniques may include associating the thread with one or more predefined execution characteristic(s), assigning the thread to one or more heterogeneous processor core(s) based on the one or more predefined execution characteristic(s), and/or executing the thread by the respective assigned heterogeneous processor core(s). | 2011-03-17 |
| 20110066829 | Selecting Regions Of Hot Code In A Dynamic Binary Rewriter - An approach to region selection which extends beyond traces and selects super-regions. A super-region (SR) contains arbitrary control flow, such as interprocedural nested loops, that provides a larger scope for transformation (e.g. optimization) than traces. Hardware samples are used to identify SRs that contain the hot code of a client process without requiring any static program information. | 2011-03-17 |
| 20110066830 | CACHE PREFILL ON THREAD MIGRATION - Techniques for pre-filling a cache associated with a second core prior to migration of a thread from a first core to the second core are generally disclosed. The present disclosure contemplates that some computer systems may include a plurality of processor cores, and that some cores may have hardware capabilities different from other cores. In order to assign threads to appropriate cores, thread/core mapping may be utilized and, in some cases, a thread may be reassigned from one core to another core. In a probabilistic anticipation that a thread may be migrated from a first core to a second core, a cache associated with the second core may be pre-filled (e.g., may become filled with some data before the thread is rescheduled on the second core). Such a cache may be a local cache to the second core and/or an associated buffer cache, for example. | 2011-03-17 |
| 20110066831 | SYSTEM AND METHOD FOR SOFTWARE INITIATED CHECKPOINT OPERATIONS - A method, system and computer program product for issuing one or more software initiated operations for creating a checkpoint of a register file and memory, and for restoring a register file and memory to the checkpointed state. At the execution of a checkpoint operation, the system returns a condition code indicating success or failure. When the condition code is set equal to one, one or more checkpoints are initiated. Contents of the register file and gated store buffer are stored each time the one or more checkpoints are initiated. When the checkpoint is created, the system notifies software when a hardware checkpoint capacity has been reached. One or more of the software checkpoint, hardware checkpoint, and handler checkpoint are utilized to provide a more precise point of restoration. During software execution, the register file and gated store buffer can be restored as defined by the one or more previous checkpoints. | 2011-03-17 |
| 20110066832 | Configurable Processor Module Accelerator Using A Programmable Logic Device - A configurable processor module accelerator using a programmable logic device is described. According to one embodiment, the accelerator module includes a circuit board having coupled thereto a first programmable logic device, a controller, and a first memory. The first programmable logic device has access to a bitstream which is stored in the first memory. Access to the bitstream by the first programmable logic device is controlled by the controller. The bitstream is capable of being instantiated in the first programmable logic device using programmable logic thereof to provide at least a transport interface for communication between the first programmable logic device and one or more other devices associated with the motherboard using the microprocessor interface. | 2011-03-17 |
| 20110066833 | CHURCH-TURING THESIS: THE TURING IMMORTALITY PROBLEM SOLVED WITH A DYNAMIC REGISTER MACHINE - A new computing machine and new methods of executing and solving heretofore unknown computational problems are presented here. The computing system demonstrated here can be implemented with a program composed of instructions such that instructions may be added or removed while the instructions are being executed. The computing machine is called a Dynamic Register Machine. The methods demonstrated apply to new hardware and software technology. The new machine and methods enable advances in machine learning, new and more powerful programming languages, and more powerful and flexible compilers and interpreters. | 2011-03-17 |
| 20110066834 | CONCURRENT EXCEPTION HANDLING - Various technologies and techniques are disclosed for providing concurrent exception handling. When one or more exceptions are received from concurrent workers, one or more exception handler functions are supplied. For each respective exception in the exception results, determine if the respective exception is one of a kind of exceptions handled by the one or more exception handler functions. If the respective exception is one of a kind handled by the exception handler functions, then run a particular handler of the exception handler functions and mark the respective exception as handled. Any unhandled exceptions are then processed appropriately. In one implementation, a collection of input data is processed to produce a collection of output results, with the exceptions being interleaved with other output results. In another implementation, a particular exception is selected that represents the multiple exceptions. The selected one particular exception is then thrown. | 2011-03-17 |
| 20110066835 | METHOD AND SYSTEM FOR SECURELY PROTECTING A SEMICONDUCTOR CHIP WITHOUT COMPROMISING TEST AND DEBUG CAPABILITIES - A semiconductor chip may be operable to block the debug interfaces when the semiconductor chip boots up from the boot read-only memory (ROM). The semiconductor chip may be operable to authenticate a debug certificate received by the semiconductor chip and enable one or more debug interfaces in the semiconductor chip based on the information resulting from the authentication of the debug certificate. The debug certificate may be in a form of a cryptographic public key certificate. A unique device ID which may be generated at boot and stored in the memory may be used by the semiconductor chip to authenticate the debug certificate. The device ID may be generated using the cryptographic public key that is stored in the one-time programmable (OTP) memory in the semiconductor chip and a cryptographic hash algorithm. | 2011-03-17 |
| 20110066836 | OPERATING SYSTEM BOOTING METHOD, COMPUTER, AND COMPUTER PROGRAM PRODUCT - According to one embodiment, a CPU boots a small OS having a function of executing a target application, boots the target application on the booted small OS, and boots a CPU dispatcher for switching an execution OS. The CPU boots a rich OS capable of executing applications larger in number than applications executed by the small OS by using the CPU dispatcher, in a background of the small OS, while causing the target application booted on the small OS to run. After the rich OS is booted, the CPU boots the target application on the booted OS separately from the target application running on the small OS. The CPU passes an execution state of the target application running on the small OS to the target application booted on the rich OS and shifting the execution OS from the small OS to the rich OS. | 2011-03-17 |
| 20110066837 | Single-Chip Flash Device with Boot Code Transfer Capability - A Multi-Media Card (MMC) Single-Chip Flash Device (SCFD) contains a MMC flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. An initial boot loader is read from the first page of flash by a state machine and written to a small RAM. A central processing unit (CPU) in the microcontroller reads instructions from the small RAM, executing the initial boot loader, which reads more pages from flash. These pages are buffered by the small RAM and written to a larger DRAM. Once an extended boot sequence is written to DRAM, the CPU toggles a RAM_BASE bit to cause instruction fetching from DRAM. Then the extended boot sequence is executed from DRAM, copying an OS image from flash to DRAM. Boot code and control code are selectively overwritten during a code updating operation to eliminate stocking issues. | 2011-03-17 |
| 20110066838 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND COMPUTER PROGRAM AND INTEGRATED CIRCUIT FOR THE REALIZATION THEREOF - The present invention provides an information processing apparatus that is capable of continuously performing secure boot between module groups in the case where software of a terminal device consists of module groups provided by a plurality of providers, while keeping independence between the providers. The information processing apparatus is provided with a linkage certificate that contains a first configuration comparison value | 2011-03-17 |
| 20110066839 | System And Method For Providing A System Management Command - Exemplary embodiments of the present invention disclosed herein relate to a method of providing a system management command. The method comprises receiving from an authorized requestor information identifying the electronic device and a request to issue a system management command to the electronic device. The method additionally comprises providing, in response to the request, a system management command, information identifying a source of the command as a trusted source and the information identifying the electronic device. Also disclosed are an electronic device and a computer system according to the invention. | 2011-03-17 |
| 20110066840 | SYSTEM AND METHOD FOR REDUCING SUBSYSTEM ENERGY COSTS - Power supply to system resources is managed by implementing a hardware hook. System resources that should be reconfigured for an application workload are identified. A present power profile in a non-volatile memory is then updated. The present power profile is updated according to the application workload. During a system restart, the present power profile is retrieved from the non-volatile memory. Power is applied to system resources through the hardware hook based on the present power profile. | 2011-03-17 |
| 20110066841 | PLATFORM FOR POLICY-DRIVEN COMMUNICATION AND MANAGEMENT INFRASTRUCTURE - A policy-driven communication and management infrastructure may include components such as Agent, Server and Console, policy messages, and Relays to deliver security and system management to networked devices. An Agent resides on a Client, acting as a universal policy engine for delivering multiple management services. Relays, Clients additionally configured to each behave as though they were a root Server, Relaying information to and from other Clients, permit Clients to interact with the root Server through the Relay, enabling information exchange between Client and Server. Such information exchange allows Clients to gather information, such as new policy messages, from the Server, to pass status messages to the Server and to register their network address so that they can be readily located. Automatic Relay selection enables Clients and Relays to select their own parent Relays, thus allowing Clients and Relays to discover new routing paths through the network without administrator input. | 2011-03-17 |
| 20110066842 | SYSTEM AND METHOD FOR PLATFORM ACTIVATION - A platform discrimination indication register is stored in a wireless network card. This register holds a platform discrimination indication that indicates whether the wireless network card can be used to transfer data with notebook computers or whether the wireless network card is restricted to transferring data from a personal digital assistant or defined set of restricted devices. The platform discrimination indication can be upgraded using a key value obtained from an Internet site. This key value is limited to a specific wireless network card because of the use of a unique electronic I.D. An Internet site encrypts the electronic I.D. to produce the first key, such as a platform activation key (PAK). This first key is then decrypted at the personal data device in order to obtain a unique calculated I.D. value. If the calculated I.D. value matches the electronic I.D. value on the wireless network card, then the platform discrimination indication is altered (upgraded), allowing the operation of the wireless network card with notebook computers. | 2011-03-17 |
| 20110066843 | MOBILE MEDIA PLAY SYSTEM AND METHOD - A mobile play device rights-managed media system and method are provided herein. | 2011-03-17 |
| 20110066844 | METHOD AND SYSTEM FOR DIGITAL RIGHTS MANAGEMENT BROKERING AND DIGITAL ASSET SECURITY TRANSCODING - A computer-implemented method and system for DRM brokering and digital asset security transcoding comprising utilizing a broker for converting content from one format into one or more alternative DRM-protected formats for distribution to end-users. The broker operates an escrow system for securing and tracking the content and information about the content and encryption keys associated with a plurality of DRM content formats. The broker further provides a common inter-DRM log format for receiving usage transaction logs and payment logs associated with transcoding and distribution the content in one or more DRM-protected content formats. | 2011-03-17 |
| 20110066845 | TRANSMISSION OF SECURE ELECTRONIC MAIL FORMATS - A method and system for providing e-mail messages to a receiving e-mail application. The e-mail messages as sent from a sending e-mail application being secure and in opaque signed format. The opaque signed e-mail messages being converted to clear signed e-mail messages by decoding extracting message content and digital signatures. The clear signed e-mails being sent to a receiving e-mail application. | 2011-03-17 |
| 20110066846 | METHOD AND A SYSTEM OF HEALTHCARE DATA HANDLING - This invention relates to a method of healthcare data handling by a trusted agent possessing or having an access to decryption keys for accessing healthcare data. A request is received from a requestor requesting accessing healthcare data. A log is generated containing data relating to the request or the requestor or both. Finally, the requestor is provided with an access to the healthcare data. | 2011-03-17 |
| 20110066847 | Just In Time Trust Establishment and Propagation - Trust relationships in an online service system are established at a domain level, and propagated to components of domains as they attempt cross domain communication. In attempting to communicate across domains, a first component in a first domain attempts to validate a certificate of a second component in a second domain. Where the attempt to validate the certificate indicates that a trust relationship does not exist between the first component and the second domain, the first component determines whether a domain level trust relationship exists between the two domains. The first component propagates the trust status between the first and second domains to itself. If there is an existing trust relationship between the first and second domains, the first component validates the certificate of the second component in response. The second component executes the same process to complete the connection. | 2011-03-17 |
| 20110066848 | REMOTE CERTIFICATE MANAGEMENT - A system for managing security certificates on a plurality of remote computers comprises a certificate manager that can determine in accordance with at least one preestablished criterion whether a security certificate on a remote computer is to be managed. The system also includes an installer module that can access an account of the remote computer to manage the security certificate. Methods of using the system are also provided. | 2011-03-17 |
| 20110066849 | METHOD AND SYSTEM FOR VERIFYING THE IDENTITY OF A COMMUNICATION PARTNER - A method for verifying the identity of a communication partner, in particular in real-time communications, wherein a caller (A) sends a message towards a callee (B), and wherein the caller (A) attaches a self-signed certificate to the message, characterized in that the caller (A) and the callee (B) are part of a web-of-trust, wherein certificates of users within the web-of-trust are stored by one or more key-servers ( | 2011-03-17 |
| 20110066850 | COMMUNICATION USING MULTIPLE APPARATUS IDENTITIES - A system for broadcasting multiple public identities corresponding to the same apparatus. For example, each public identity may correspond to different operational environments, while none of the public identities disclose a private identity that uniquely and permanently identifies the apparatus. This allows apparatuses to keep their unique identity a secret while still being able to communicate with other apparatuses in various environments. | 2011-03-17 |
| 20110066851 | Secure Route Discovery Node and Policing Mechanism - A computer implemented method and computer program product for obtaining a secure route. A trusted host sets a node security association for a trusted host. The trusted host receives, at the trusted host, a client communication request directed to a destination host. The trusted host builds a secure route query comprising a trusted host address, a destination host address, and at least one security level, to form at least one secure route. The trusted host sends packets from the trusted host to the destination host based on the at least one secure route. The packets are responsive to the client communication request, and the packets each have a security label that matches the security level. | 2011-03-17 |
| 20110066852 | DOCUMENT MANAGEMENT SYSTEM, DOCUMENT MANIPULATION APPARATUS, AND COMPUTER READABLE MEDIUM - According to an aspect of the invention, a document management system includes a protection policy storage unit, a correspondence storage unit, an embedding unit, a portable identification unit, a storage control unit, and a document manipulation unit. The document manipulation unit executes a user manipulation specified by the certain user based on a communication between the portable identification unit and the document manipulation unit. | 2011-03-17 |
| 20110066853 | SYSTEM AND METHOD FOR SECURELY IDENTIFYING AND AUTHENTICATING DEVICES IN A SYMMETRIC ENCRYPTION SYSTEM - The present invention describes a system and method for securely identifying and authenticating devices in a symmetric encryption system. An RFID tag can generate indicators using encryption state variables and a symmetric key. An RFID reader, after receiving the encryption state variables from the tag, may identify the tag by performing an exhaustive key search in a key database. Each key in the database may be tested by using the key and encryption state variables to perform an encryption operation similar to that performed by the tag. The result is then compared with the received tag indicators to determine if the tag has been identified. A rotor-based encryption scheme provides for a low cost key search while providing resilience against cloning, tracking, tampering and replay attacks. | 2011-03-17 |
| 20110066854 | METHOD FOR SECURE DYNAMIC BANDWIDTH ALLOCATION IN A TT ETHERNET - A communication method for transmitting TT Ethernet messages is a distributed real-time system, including a plurality of node computers. Each node computer has an Ethernet controller, which by way of a data line is directly connected to a port of a TTE star coupler, said port being uniquely associated with the node computer. A plurality of TTE star couplers are connected among each other by way of one or more data lines to form a TTE network. A TTE message scheduler dynamically calculates the conflict-free schedules for a number of time-controlled messages and signs the schedule provided for each node with a secret part of a public-key signature before it transmits said schedule to the corresponding node computer. Each node computer integrates the signed periodic schedule, which is transmitted to the node computer in the form of a TTE message header of an ETE message, into each dynamically calculated TTE message. The TTE star couplers check whether each dynamically calculated TTE message contains an authentically signed schedule. | 2011-03-17 |
| 20110066855 | AUTHENTICATION FOR DEVICES LOCATED IN CABLE NETWORKS - An extensible authentication framework is used in cable networks such as Data Over Cable Service Interface Specification (DOCSIS) cable networks. The authentication scheme allows for centralized authentication of cable modems, as well as authentication of the cable network by cable modems. Additionally, the authentication scheme allows a Cable Modem Termination System (CMTS) to authenticate devices downstream from cable modems, such as Customer Premise Equipment (CPE) devices. | 2011-03-17 |
| 20110066856 | Communication data freshness confirmation system - A receiving device sends challenge information to a transmitting device. The transmitting device initializes a time varying parameter and transmits communication data together with data derived from the challenge information to the receiving device. Subsequent communication data, if any, are then transmitted together with data derived from the time varying parameter. The receiving device uses the challenge information to verify the freshness of the communication data transmitted first, and uses the time varying parameter to verify the freshness of the subsequent communication data. Freshness can be verified without having to maintain any type of verification data during sleep periods, and without having to send a separate challenge for each data transmission. | 2011-03-17 |
| 20110066857 | Method for secure delivery of digital content - Methods and apparatus for the secure and copy-proof distribution of digital content are disclosed. In a preferred embodiment of the invention cryptographic primitives (encryption algorithms, message-authentication codes, hash functions, random-number generators, etc.) are used in a novel security protocol. The invention may be utilized to protect a first-run movie that has been digitized in accordance with one of the current or forthcoming MPEG standards (e.g., MPEG-7). Content receivers or users first register their boxes. This registration information is stored in a secure database. When a subscriber registers, he then receives a box (interface to his player) that has been initialized to contain a number of tamper-proof secrets that are shared between the station and that particular box. The station stores an encrypted version of the digital content. This encrypted version ultimately arrives at some unprotected storage medium local to the player. Upon demand, the station delivers to the box the use-once computational ability to decrypt the content and display it on the player or terminal. | 2011-03-17 |
| 20110066858 | SYSTEM AND METHOD FOR IPSec LINK CONFIGURATION - A method for configuring Internet Protocol Security (IPsec) protocol. The method includes configuring IPsec phase 1 Security Associations (SA) lifetimes and soft phase 2 SA lifetimes in a manner enabling efficient Dead Peer Detection recovery of secure communication between client and server in the event of a communication disruption and thereby preventing undesirable sustained periods of non-communication between client and server. | 2011-03-17 |
| 20110066859 | FLEXIBLE BROADCAST AUTHENTICATION IN RESOURCE-CONSTRAINED SYSTEMS: PROVIDING A TRADEOFF BETWEEN COMMUNICATION AND COMPUTATIONAL OVERHEADS - A method for authenticating a message that is transmitted wirelessly. The method includes providing a set of private key values that define a private key and performing a key pair generation process that provides a key pair including the private key and a public key, where performing the key pair generation process includes applying one or more hash functions to the private key values, where a succeeding hash function provides a hash of a previous hash function. The scheme uses a signature generation process that generates a message digest by applying a hash function on the message to be signed and then separates the message digest into two parts including signing bits and selection bits and using the private key to sign the message. A receiver verifies the authenticity of the received message using the public key and a signature verification algorithm. | 2011-03-17 |
| 20110066860 | Virtual World Embedded Security Watermarking - A method, apparatus, and program product are provided for using watermarks to embed security features on avatars in a virtual world. A watermark engine receives security information for an avatar in a virtual world. The watermark engine creates a watermark for the avatar using the security information and associates the watermark with the avatar. The watermark may comprise at least one of: security preferences for the avatar, contact information for an owner of the avatar, and graphical information to cause alteration of the avatar when the avatar is recorded. | 2011-03-17 |
| 20110066861 | DIGITAL CONTENT MANAGEMENT AND DELIVERY - Methods, systems, and apparatus for digital content management and distribution are provided. In an example, a plurality of unique keys can be provide, wherein each unique key corresponding to one or more docks for accessing digital content. A selection of at least one item of digital content can be received from a user and an indication of a dock corresponding to the user can also be received. A unique key can be selected from the plurality of unique keys corresponding to the dock of the user, and the at least one item of digital content can be encrypted based on the selected unique key. | 2011-03-17 |
| 20110066862 | METHOD FOR OUTPUTTING IMAGE DATA, IMAGE PROCESSING APPARATUS, AND COMPUTER-READABLE STORAGE MEDIUM FOR COMPUTER PROGRAM - A method for outputting image data generated by an image processing apparatus to a portable storage medium connected to an interface is provided. The method includes the following steps of: issuing an identifier of the image data; writing the identifier into the storage medium without waiting for the image data to be generated completely; after generating the image data, associating the image data with the identifier and storing the image data in a storage portion; reading out the identifier from the storage medium when the storage medium is connected to the interface again; and writing, into the storage medium, the image data stored in the storage portion in association with the identifier thus read out. | 2011-03-17 |
| 20110066863 | IDENTITY-BASED ENCRYPTION OF DATA ITEMS FOR SECURE ACCESS THERETO - The invention uses the concept of identity-based encryption in the context of data-centric protection of electronic health records, where each data item is encrypted by using its own identifier as a public key. The corresponding decryption keys are managed by special trusted entities, which distribute the keys to authorized parties and provide logging facilities. This approach has the particular advantage that emergency access mechanisms can 5 be implemented in a secure and extremely efficient way. In contrast to previous approaches, it requires no large-scale distribution of secret decryption keys. Furthermore, the scheme allows limiting the impact of a compromised decryption key, as one key can only be used to decrypt one single document. | 2011-03-17 |
| 20110066864 | Methods And Apparatus For Use In Transferring User Data Between Two Different Mobile Communication Devices Using A Removable Memory Card - Methods and apparatus for use in transferring user data from a first (“source”) mobile communication device to a second (“target”) mobile communication device using a removable memory card are disclosed. The source and target devices may be possessed and/or owned by the same end user. The source device is initially enabled to maintain data synchronization with a host server over a wireless communication network via a first wireless transceiver for user data of an application program associated with the user account. To enable the target device for the communications associated with the user account, the source device is operative to establish a programming session with the target device via a second wireless transceiver. During the programming session, the source device causes user account data (e.g. at least one encryption/decryption key for the data-synchronized communications) for the user account to be transmitted to the target device via the second wireless transceiver. Preferably, the user account data is encrypted based on a passkey for the programming session. The user data associated with the application program may then be transferred from the source device to the target device via a removable memory card such as a secure digital (SD) card. | 2011-03-17 |
| 20110066865 | Nameplate Power Capping - A nameplate for power capping a computer including a mounting surface; a module integrated in the mounting surface for providing a machine-readable designation of a power cap for a particular computer; a human readable designation of a power cap for the particular computer integrated in the mounting surface; and a mount for attaching the mounting surface to a chassis of the particular computer such that the human readable designation of a power cap is exposed. | 2011-03-17 |
| 20110066866 | POWER SUPPLY CONTROL CIRCUIT AND ELECTRONIC DEVICE USING THE SAME - A power supply control circuit used to control a power supply to supply a MCU includes a first transistor switch, a RC circuit, a power switch control circuit, and an input signal control circuit. When the power switch control circuit is grounded via the MCU, the RC circuit is discharged to ground and the first transistor switch is switched on, such that the power supply supplies power to the MCU. When the MCU outputs a control signal to the input signal control circuit, the RC circuit is discharged to ground and the first transistor switch is switched on, such that the power supply supplies power to the MCU. When the MCU stops outputting the control signal to the input signal control circuit, the RC circuit is charged and the first transistor switch is switched off, such that the power supply does not supply power to the MCU. | 2011-03-17 |
| 20110066867 | METHOD AND SYSTEM FOR MONITORING MODULE POWER INFORMATION IN A COMMUNICATION DEVICE - A method for communication is disclosed and includes, in a single chip including a plurality of on-chip devices, acquiring, from at least one of the plurality of on-chip devices, power information for the at least one of the plurality of on-chip devices. The acquiring may be in response to a query signal received by the at least one of the plurality of on-chip devices. An output signal indicative of power status of the at least one of the plurality of on-chip devices may be generated from within the chip, based on the acquired power information. The acquired power information may be communicated to the off-chip device. The acquired power information may be wirelessly communicated to the off-chip device via an antenna or an infrared transmitter on the single chip. The acquired power information may be communicated to an off-chip device via a wired connection on the single chip. | 2011-03-17 |
| 20110066868 | Variably Delayed Wakeup Transition - A computing system includes a controller configured to undergo a variably delayed wakeup transition. The controller is configured to transition a processing module from an idle state to an active state in response to successive assertions of a wakeup interrupt command. The system includes a variable delay module configured to vary delay lengths between assertion and execution of each of the successive wakeup interrupt commands during the wakeup transition to substantially cause power supply components to vibrate in a non-periodic manner. | 2011-03-17 |
| 20110066869 | Memory Array Power Cycling - In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both. | 2011-03-17 |
| 20110066870 | PERIPHERAL CAPABLE OF CONNECTING WITH A HOST AND POWER CONTROL METHOD THEREOF - A peripheral connected with a host via a transmission interface, and a power control method applied to the peripheral includes the steps of: receiving signal data from the host via the transmission interface; generating a power control signal when determining that the host and the peripheral are indifferent statuses; and selectively switching on or switching off an input power of the peripheral according to the power control signal, so as to make the peripheral change its status. | 2011-03-17 |
