11th week of 2011 patent applcation highlights part 27 |
Patent application number | Title | Published |
20110063873 | TRANSREFLECTORS, TRANSREFLECTOR SYSTEMS AND DISPLAYS AND METHODS OF MAKING TRANSREFLECTORS - Optical assembly comprises a light emitting assembly comprising a light emitting panel and an LED light source, and a transreflector film or sheet attached to the light emitting panel. The light emitting panel has a first pattern of optical deformities, and the transreflector sheet or film has a second pattern of optical deformities. The optical deformities of the second pattern are smaller in length and width than the transreflector film or sheet, and the optical deformities of the first pattern are aligned with the optical deformities of the second pattern. | 2011-03-17 |
20110063874 | PROJECTION LENS FOR LIGHTING EQUIPMENT AND LIGHTING EQUIPMENT USING PROJECTION LENS FOR LIGHTING EQUIPMENT - A projection lens for lighting equipment of an aspect of the present invention is characterized by formed in a shape where N of sector-shaped lens parts each of which corresponds to a central angle 2α degrees (α=180/N, N is an integer more than or equal to 3) and is bilaterally symmetric in a rotationally asymmetric elliptical collimator lens are circumferentially disposed. The projection lens for lighting equipment of such aspect is formed in the shape where N of the sector-shaped lens parts each of which corresponds to a central angle 2α degrees (α=180/N, N is an integer more than or equal to 3) and is bilaterally symmetric in the rotationally asymmetric elliptical collimator lens are circumferentially disposed. Accordingly, the projection lens for lighting equipment with a novel design which has a shape of a N-sided polygon (e.g. quadrilateral) in planar view or a shape similar to the N-sided polygon and has common edges (N edges) formed on a surface without impairment in function as a collimator lens can be configured. | 2011-03-17 |
20110063875 | BACKLIGHT MODULE - A backlight module includes at least one light emitting device capable of emitting a light beam, a light guide plate, and a thermal insulation light guide element. The light guide plate has two surfaces opposite to each other and a side surface connecting the two surfaces. The light emitting device is disposed beside the side surface. The light beam enters the light guide plate through the side surface. The thermal insulation light guide element has a light incident surface and a light emitting surface. The light incident surface having at least one first recess is located in a transmission path of the light beam and between the light emitting device and the side surface. The light emitting surface is disposed between the light incident surface and the side surface. The glass transition temperature of the thermal insulation light guide element is higher than that of the light guide plate. | 2011-03-17 |
20110063876 | OVERVOLTAGE LIMITATION IN A SWITCH-MODE CONVERTER - A switch-mode converter including an inductive transformer having a secondary winding associated with at least one first switch, including, in parallel with the first switch, at least one first diode in series with a capacitive element; and in parallel with the capacitive element, an active circuit for limiting the voltage thereacross. | 2011-03-17 |
20110063877 | Synchronous rectifying circuit with primary-side swithching current detection for offline power converters - A synchronous rectifying circuit is provided for offline power converter. A pulse signal generator is utilized to generate a pulse signal in response to a switching current of the power transformer. An isolation device is coupled to the pulse signal generator for transferring the pulse signal through an isolation barrier of the power transformer. A synchronous rectifier includes a power switch and a control circuit. The power switch is coupled between the secondary side of the power transformer and the output of the power converter for the rectifying. The control circuit is operated to receive the pulse signal for turning on/off the power switch. The pulse signal is generated to turn on the power switch once the switching current is higher than a threshold. | 2011-03-17 |
20110063878 | POWER-SUPPLY CONTROLLER - An embodiment of a controller for a power supply includes circuitry that is operable to allow the power supply to operate as follows. During a first portion of a supply period, a first current flows through a first winding of the power supply, through a second winding of the power supply, and to an output node of the power supply. And during a second portion of the supply period, a second current flows through the first winding, through a third winding of the power supply, and to the output node. Each of the first, second, and third windings may be non-electrically isolated from one or more of the other windings during one or more portions of the supply period. Furthermore, the first, second, and third windings may be magnetically coupled to one another. For example, in an embodiment, such a controller may be part of a DC-DC converter that may be more efficient, and that may have reduced interdependence between output-signal ripple and transient response, than a conventional buck converter. | 2011-03-17 |
20110063879 | SWITCHING POWER SUPPLY DEVICE AND SEMICONDUCTOR DEVICE - The switching power supply device includes: an input unit which receives an input voltage; a transformer which includes a primary winding and a secondary winding; an output unit which provides an output voltage; a switching element; and a control circuit. The control circuit includes: a T | 2011-03-17 |
20110063880 | FORWARD CONVERTER TRANSFORMER SATURATION PREVENTION - A control circuit for use in a power converter in one aspect limits the magnetic flux in a transformer. Controlled current sources produce a first current that is proportional to an input voltage of the power converter and a second current that is proportional to a reset voltage of the transformer. An integrating capacitor is charged with the first current and discharged with the second current, where a voltage on the capacitor is representative of the magnetic flux in the transformer. A logic circuit is adapted to turn off the switch when the voltage on the integrating capacitor is greater than or equal to a first threshold voltage, and to allow the switch to turn on and off in accordance with a pulse width modulation signal after a delay time that begins when the integrating capacitor discharges to a second threshold voltage. | 2011-03-17 |
20110063881 | SYSTEM AND METHOD FOR AUTOMATICALLY TUNING A VOLTAGE CONVERTER - A power converter system is provided, comprising a plant having a plant input and a plant output; and a plant identification filter that receives the plant input and the plant output, and estimates the values of poles and zeros of the plant, wherein the plant identification filter updates the estimates of the poles and zeros, based upon the plant input and the plant output, beginning from an initial state; and a rate at which the plant identification filter updates the estimates of the values of the poles and zeros is slower than a rate at which the plant input and the plant output are received by the plant identification filter. | 2011-03-17 |
20110063882 | ACCURACY OF A VOLT-SECOND CLAMP IN AN ISOLATED DC/DC CONVERTER - A novel system and methodology for providing a volt-second clamp. A DC/DC conversion system configured for producing an output voltage in response to an input voltage has a transformer with a primary winding responsive to the input voltage and a secondary winding for producing the output voltage. The conversion system has a power switch coupled to the primary winding of the transformer and controlled with a converter control signal, such as a PWM control signal. The power switch is further controlled by a comparator that compares an input value supplied to its input with a variable reference value so as to prevent magnetic flux density of the transformer from increasing to an undesired level. The input value of the comparator is produced by a comparator input circuit as a function of the input voltage and an on-time of the power switch. A reference circuit produces the reference value that varies as a function of the input voltage. | 2011-03-17 |
20110063883 | INVERTER CONTROL CIRCUIT AND INTERCONNECTION INVERTER SYSTEM HAVING THAT INVERTER CONTROL CIRCUIT - An inverter control circuit ( | 2011-03-17 |
20110063884 | STRUCTURE AND METHOD FOR BACKING UP AND RESTITUTION OF DATA - A structure and a method for backing up and restitution of data allowing management of a memory space. The backup and restitution structure includes a matrix of connectors distributed in line and in column, on said matrix. Each connector of one line is connected to its two adjacent connectors. Each connector of one column is connected to its two adjacent connectors. Each line of connectors is connected to a memory of the first-in, first-out type, by a connector situated at one end of the line. Each column of connectors is connected to an input and, or output port of a data stream of the structure by a connector situated at one end of the column. Each connector propagates a data stream. An embodiment is suitable for an onboard computing system including a component, associating a computing structure and a memory space produced for example on one electronic circuit board. | 2011-03-17 |
20110063885 | Information storage devices including vertical nano wires - A memory cell includes: a memory cell array unit having a plurality of nano wires arranged vertically on a substrate, each of the plurality of nano wires having a plurality of domains for storing information; a nano wire selection unit formed on the substrate and configured to select at least one of the plurality of nano wires; a domain movement control unit formed on the substrate and configured to control a domain movement operation with respect to at least one of the plurality of nano wires; and a read/write control unit formed on the substrate and configured to control at least one of a read operation and a write operation with respect to at least one of the plurality of nano wires. | 2011-03-17 |
20110063886 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD OF THE SAME - A memory includes a cell region; a spare region including a spare block; a fuse region storing remedy information necessary for an access to the spare block instead of a remedy target block, the fuse region comprising non-defective cells in the remedy target block, or including cells in a first block of the spare region; an initial reading fuse storing a block address for identifying the remedy target block or the first block allocated as the fuse region, and a selection address for selecting a region in the remedy target block or a region in the first block allocated as the fuse region; and a controller configured to acquire the remedy information from the fuse region based on the block address and the selection address, and to change the access to the remedy target block to the access to the spare block based on the remedy information. | 2011-03-17 |
20110063887 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE CAPABLE OF TESTING DIODES AND MANUFACTURING METHOD THEREOF - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array, and a control circuit. The memory cell array includes plural memory cells arranged in rows and columns and each including a diode and resistance-change element. The control circuit tests the diodes for the respective memory cells. The control circuit tests the diode at least at one of times before and after one of a write operation, erase operation and read operation with respect to the memory cell is performed. | 2011-03-17 |
20110063888 | Green Transistor for Resistive Random Access Memory and Method of Operating the Same - A random access memory includes a plurality of memory cells arrayed in bit-lines and word-lines. Each memory cell comprises a green transistor (gFET) including a gate, a source, and a drain; a switching resistor including a first terminal and a second terminal; and a reference resistor including a third terminal and a fourth terminal. The first terminal of the switching resistor and the third terminal is connected to a bit-line, the second terminal of the switching resistor is connected to the first source of the gFET, the fourth terminal of the reference resistor is connected to the second source of the gFET, and the gate of the gFET is connected to a word-line. The method of operating the RRAM includes a write operation and a read operation The write operation comprises steps of: applying a first voltage to the bit-line to perform a large voltage difference across the bit-line and the drain of the gFET, applying a second voltage to the gate of the gFET to turn on the gFET transiently, and a large current pulse flowing through the switching resistor for changing the resistance state. The read operation comprises steps of: applying a third voltage to the bit-line to perform a small voltage difference across the bit-line and the drain of the gFET, applying a second voltage to the word-line to turn on the gFET, and comparing the current through the switching resistor with the current through the reference resistor so as to read the data stored in the memory cell. | 2011-03-17 |
20110063889 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes memory cells including serially-connected variable-resistance layer and diode. A memory cell array includes the memory cells arranged on a plane including a first and second axes and has a first region lying along an edge of the array and a second region lying opposite to the edge with respect to the first region. A first wiring is continuous along the first axis between both ends of the array, partly lies in the second region, and is connected to the first ends of the memory cells. A second wiring lies along the first axis only in the first region, is connected to the first ends of the memory cells, and is divided between adjacent memory cells. A third wiring is continuous along the second axis between both ends of the array, and connected to the second ends of the memory cells. | 2011-03-17 |
20110063890 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a phase change element (RP) and a memory cell transistor (MN | 2011-03-17 |
20110063891 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING SYSTEM COMPRISING SEMICONDUCTOR SYSTEM - A semiconductor device comprises a memory cell, a bit line, a sense amplifier operating between a first voltage and a second voltage higher than the first voltage, a transfer control circuit including a transfer transistor, and a write circuit writing data into the memory cell through the bit line based on the first voltage and a third voltage. The sense amplifier receives and amplifiers the signal voltage at a sense node when the transfer transistor controls the connection between the bit line and the sense node in response to a transfer control voltage. The third voltage is set to a voltage lower than the second voltage and higher than the transfer control voltage, and the sense node is set to a voltage higher than the transfer control voltage in an initial period of a read operation before the data of the memory cell is read out to the bit line. | 2011-03-17 |
20110063892 | SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR DEVICE - A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes. | 2011-03-17 |
20110063893 | SYSTEMS AND METHODS FOR REDUCING MEMORY ARRAY LEAKAGE IN HIGH CAPACITY MEMORIES BY SELECTIVE BIASING - A source-biasing mechanism for leakage reduction in SRAM in which SRAM cells are arranged into a plurality of sectors. In standby mode, the SRAM cells in a sector in the plurality of sectors are deselected and a source-biasing potential is provided to the SRAM cells of the plurality sectors. In working mode, the source-biasing potential provided to the SRAM cells of a selected sector in the plurality of sectors is deactivated and the SRAM cells in a physical row within the selected sector are read while the remaining SRAM cells in the unselected sectors continue to be source-biased. The source-biasing potential provided to the SRAM cells that are in standby mode can be set to different voltages based on the logical state of control signals. | 2011-03-17 |
20110063894 | SRAM CELLS, MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A third transistor is coupled with the first node. The third transistor has a threshold voltage that is higher than that of a fourth transistor of the pair of cross-coupled inverters by about 10% or more. A fifth transistor is coupled between the third transistor and a third bit line | 2011-03-17 |
20110063895 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SYSTEM - A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line. | 2011-03-17 |
20110063896 | Semiconductor memory device - A semiconductor device according to the present invention includes a first memory cell array in which a plurality of first memory cells are arranged as a matrix, data being read from or written to the first memory cells, and a second memory cell array in which a plurality of second memory cells amplifying and storing the data of one of the plurality of the first memory cells arranged in a corresponding column are arranged as a matrix. The first memory cell array and the second memory cell array are arranged face to face in the column direction. An area of the second memory cell is larger than that of the first memory cell. An area of the first memory cell array is twice or more as large as that of the second memory cell array. | 2011-03-17 |
20110063897 | DIFFERENTIAL READ AND WRITE ARCHITECTURE - A memory cell includes a pair of magnetic tunnel junctions and a pair of associated transistors. The magnetic tunnel junctions of the pair are differentially disposed so that in response to the applied voltages, when one them stores a logic one, the other one stores a logic zero. Accordingly, the read operation margin is increased by a factor of two. The true and complementary bit lines of the differential memory cell are coupled to a sense amplifier. Consequently, the need for using reference bit lines is eliminated. | 2011-03-17 |
20110063898 | METHOD AND SYSTEM FOR PROVIDING A HIERARCHICAL DATA PATH FOR SPIN TRANSFER TORQUE RANDOM ACCESS MEMORY - A method and system for providing a magnetic memory are described. The method and system include providing memory array tiles (MATs), intermediate circuitry, global bit lines, global word lines, and global circuitry. Each MAT includes magnetic storage cells, bit lines, and word lines. Each of the magnetic storage cells includes at least one magnetic element and at least one selection device. The magnetic element(s) are programmable using write current(s) driven through the magnetic element(s). The bit lines and the word lines correspond to the magnetic storage cells. The intermediate circuitry controls read and write operations within the MATs. Each global bit line corresponds to a first portion of the plurality of MATs. Each global word line corresponds to a second portion of the MATs. The global circuitry selects and drives part of the global bit lines and part of the global word lines for the read and write operations. | 2011-03-17 |
20110063899 | MAGNETIC MEMORY ELEMENT, METHOD OF DRIVING SAME, AND NONVOLATILE STORAGE DEVICE - In order to obtain a memory cell of size 4 F | 2011-03-17 |
20110063900 | MAGNETIC MEMORY - According to one embodiment, a magnetic memory includes a magnetoresistive element includes a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is variable and a nonmagnetic layer disposed between the fixed layer and the recording layer. A direction of a read current is set to a first direction in a case where an expression of MR ratio ≧|I | 2011-03-17 |
20110063901 | STATIC SOURCE PLANE IN STRAM - A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A first word line is electrically coupled to a gate of first set of two of the transistors and a second word line is electrically coupled to a gate of a second set of two of the transistors. The source line is a common source line for the plurality of magnetic tunnel junctions. | 2011-03-17 |
20110063902 | 2T2R-1T1R MIX MODE PHASE CHANGE MEMORY ARRAY - A memory device as described herein includes an array of programmable resistance memory cells. The memory device further includes sense circuitry having a dual memory cell (2T-2R) mode to read a data value stored in a pair of memory cells in the array based on a difference in resistance between a first memory cell in the pair and a second memory cell in the pair. The sense circuitry also has a single memory cell (1T-1R) mode to read a data value in a particular memory cell in the array based on the resistance of the particular memory cell. | 2011-03-17 |
20110063903 | NONVOLATILE MEMORY DEVICES, SYSTEMS HAVING THE SAME, AND WRITE CURRENT CONTROL METHODS THEREOF - Provided is a nonvolatile memory device, a memory system having the same, and a write current control method thereof. The memory system includes a nonvolatile memory device and a memory controller. The nonvolatile memory device has a plurality of write modes. The memory controller includes a sensor configured to sense environment information of the memory system. The memory controller is configured to select one of the write modes according to the sensed environment information and control the nonvolatile memory device according to the selected write mode. Accordingly, the nonvolatile memory device provides a write current for appropriate current consumption in a write operation. | 2011-03-17 |
20110063904 | PHASE CHANGE MEMORY DEVICE, MEMORY SYSTEM, AND PROGRAMMING METHOD - A method of programming a phase change memory device is disclosed. Write data is programmed in a plurality of phase change memory cells by applying write pulses to each of the plurality of phase change memory cells. Whether each of the phase change memory cells is programmed is verified by applying at least one verification pulse to each of the phase-change memory cells. A number of applications for the at least one verification pulse and the intervals between respective applications of the at least one verification pulse are varied in accordance with a verification result for each of the phase-change memory cells. | 2011-03-17 |
20110063905 | MULTI-VALUED ROM USING CARBON-NANOTUBE AND NANOWIRE FET - A multivalued memory device which includes a first multivalued memory transistor and a second multivalued memory transistor, wherein each transistor has a channel made from at least one carbon nanotube or nanowire, wherein data is stored by varying the number of carbon nanotubes or nanowires used in the channel, wherein the channel is the at least one carbon nanotube or nanowire which allows current to flow through it. | 2011-03-17 |
20110063906 | MEMORY ADAPTED TO PROGRAM A NUMBER OF BITS TO A MEMORY CELL AND READ A DIFFERENT NUMBER OF BITS FROM THE MEMORY CELL - A memory has a memory array with a memory cell. The memory is adapted to program a first number of bits into the memory cell. The memory is adapted to sense a second number of bits, different from the first number of bits, from the memory cell. | 2011-03-17 |
20110063907 | FRACTIONAL BITS IN MEMORY CELLS - Methods, devices, modules, and systems for programming memory cells can include storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. Programming memory cells can include storing a charge in a cell of the set, where the charge corresponds to a programmed state, where the programmed state represents a fractional number of bits, and where the programmed state denotes a digit of the data state as expressed by a number in base N, where N is equal to 2 | 2011-03-17 |
20110063908 | Nonvolatile Memory, Verify Method Therefor, and Semiconductor Device Using the Nonvolatile Memory - Provided is a nonvolatile memory that realizes a high-speed verify operation. During verify writing/erasing, the writing/erasing and reading are performed at the same time. As to a circuit that performs a verify operation, for instance, there is obtained a construction where the output from a sense amplifier ( | 2011-03-17 |
20110063909 | NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD OF TESTING THE SAME - A memory cell array and a peripheral circuit are provided. The memory cell array has a plurality of blocks which are erasing units respectively. Each of the blocks includes a plurality of memory cells. A block control unit operates according to input signals from outside and controls operation of the blocks. A ready/busy control circuit outputs a busy signal during a period of operation implementation for a block selected from the blocks, in response to an output from the block control unit. The ready/busy control circuit outputs a ready signal out of the period of the operation implementation for the selected block. A registration control unit registers the selected block as a bad block, in the case that the ready/busy control circuit outputs a busy signal when the registration control unit receives a bad block identification command. | 2011-03-17 |
20110063910 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one. | 2011-03-17 |
20110063911 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array including a plurality of blocks each including a memory cell unit, and a selection transistor which selects the memory cell unit, and a row decoder including a first block selector and a second block selector each of which includes a plurality of transfer transistors which are formed to correspond to the plurality of blocks and arranged adjacent to each other in a word-line direction wherein the diffusion layers are formed to oppose each other in the first block selector and the second block selector, and a width between the diffusion layers of the first block selector and the second block selector adjacent to each other in the word-line direction is made larger than a width between the diffusion layers in each of the first block selector and the second block selector adjacent to each other in the word-line direction. | 2011-03-17 |
20110063912 | METHODS AND STRUCTURES FOR READING OUT NON-VOLATILE MEMORY USING NVM CELLS AS A LOAD ELEMENT - A Non-Volatile Memory (NVM) cell in an NVM array is read out using other NVM cells in the array as a load element. Conventional load elements such as MOS transistors or resistors used to vary the bitline potential for the NVM cell readout in conventional NVM arrays are replaced with NVM cell(s) in the array. The omission of the extra MOS transistors or resistors for the load elements not only saves silicon area but also simplifies the bitline sensing circuitry design in the NVM array. | 2011-03-17 |
20110063913 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - In a three dimensional stacked nonvolatile semiconductor memory according to the present invention, a first block has a selected first cell unit including a memory cell to be read and a non-selected second cell unit not including a memory cell to be read. A read potential or a transfer potential higher than the read potential is applied to the word line in the first block in a state that a ground potential is applied to a channel of a memory cell existing nearer to the bit line side than a memory cell in the second cell unit to which the read potential is applied, after which all the memory cells in the second cell unit are cut off from the bit line, the bit line is set to a precharge potential, and read is performed to the a memory cell to be read in the first cell unit. | 2011-03-17 |
20110063914 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: a multilayer structure including electrode films and interelectrode insulating films alternately stacked; a semiconductor pillar piercing the multilayer structure; insulating films and a memory layer provided between the electrode films and the semiconductor pillar; and a wiring connected to the semiconductor pillar. In an erase operation, the control unit performs: a first operation setting the wiring at a first potential and the electrode film at a second potential lower than the first potential during a first period; and a second operation setting the wiring at a third potential and the electrode film at a fourth potential lower than the third potential during a second period after the first operation. A length of the second period is shorter than the first period, and/or a difference between the third and fourth potentials is smaller than a difference between the first and second potentials. | 2011-03-17 |
20110063915 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells capable electrically rewriting data, bit lines and source lines. A driver circuit is coupled with the source lines of the memory cell array to output a voltage higher than a power source voltage or a programming voltage for writing data in the memory cell by switching over, and the driver circuit discharges the source lines to ground. A sense amplifier circuit is coupled with the bit line and reads out the data in the memory cell. The sense amplifier includes a sense node and a capacitor having first and second terminals, and the first terminal is coupled with the sense node. The sense node is boosted by a plurality of voltages applied to the second terminal of the capacitor. | 2011-03-17 |
20110063916 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - At least some of the memory transistors included in a first memory string are commonly connected to first conductive layers that are connected to at least some of the memory transistors included in a second memory string connected to the same third and fourth conductive layers as the first memory string. At least one of either the memory transistors or the back-gate transistor in the first memory string and at least one of either the memory transistors or the back-gate transistor in the second memory string are connected to the independent first or fifth conductive layers, respectively. | 2011-03-17 |
20110063917 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line. | 2011-03-17 |
20110063918 | IDENTIFYING AT-RISK DATA IN NON-VOLATILE STORAGE - The non-volatile storage system predicts which blocks (or other units of storage) will become bad based on performance data. User data in those blocks predicted to become bad can be re-programmed to other blocks, and the blocks predicted to become bad can be removed from further use. | 2011-03-17 |
20110063919 | MEMORY KINK CHECKING - This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell. | 2011-03-17 |
20110063920 | SENSING FOR ALL BIT LINE ARCHITECTURE IN A MEMORY DEVICE - Methods for sensing, memory devices, and memory systems are disclosed. One such method for sensing includes charging bit lines of an all bit line architecture to a precharge voltage, selecting a word line, and performing a sense operation on the bit lines. After the sense operation on the memory cells of the first selected word line is complete, the precharge voltage is maintained on the bit lines while a second word line is selected. | 2011-03-17 |
20110063921 | Circuit Arrangement with a Column Latch and Method for Operating a Column Latch - In one embodiment, a circuit arrangement with a column latch has a first terminal (A | 2011-03-17 |
20110063922 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Nonvolatile semiconductor memory device according to one embodiment includes: a plurality of planes; a memory cell array provided in the plurality of planes respectively; bit lines; and a control circuit. Each memory cell array is configured as an array of NAND cell units each including a memory string. The memory string includes a plurality of nonvolatile memory cells connected in series. The bit lines are connected to a first end of the NAND cell units, respectively. The control circuit controls a write operation of charging the bit lines up to a certain voltage value, and then setting data in the nonvolatile memory cells to a certain threshold voltage distribution state. The control circuit is configured to be capable of executing an operation of charging the bit lines in a write operation by varying timings of starting charging the bit lines among the plurality of planes. | 2011-03-17 |
20110063923 | TRENCH MEMORY STRUCTURE OPERATION - Memory cells utilizing dielectric charge carrier trapping sites formed in trenches provide for non-volatile storage of data. The memory cells of the various embodiments have two control gates. One control gate is formed adjacent the trench containing the charge carrier trap. The other control gate has a portion formed over the trench, and, for certain embodiments, this control gate may extend into the trench. The charge carrier trapping sites may be discrete formations on a sidewall of a trench, a continuous layer extending from one sidewall to the other, or plugs extending between sidewalls. | 2011-03-17 |
20110063924 | METHOD OF FLASH MEMORY DESIGN WITH DIFFERENTIAL CELL FOR BETTER ENDURANCE - A flash memory system includes a first flash memory cell having a first floating gate, a first source region, and a first control gate. The first control gate is connected to a word line. The first flash memory cell includes a first oxide layer separating the first control gate from the first floating gate and a first drain region connecting to a first bit line. The flash memory system also includes a second flash memory cell having a second floating gate, a second source region, and a second control gate. The second control gate is connected to the word line. The second flash memory cell includes a second oxide layer separating the second control gate from the second floating gate and a second drain region connecting to a second bit line. A comparator processes a first and second input signals received from the respective first and second bit lines. | 2011-03-17 |
20110063925 | Semiconductor device and semiconductor package including the same - To include a plurality of pad groups each including a first data I/O pad, a first power supply pad, a second data I/O pad, and a second power supply pad arranged in order in an X direction. The first data I/O pad is connected to a first data I/O buffer, and the second data I/O pad is connected to a second data I/O buffer. The first power supply pad supplies a first power supply potential to the first and second data I/O buffers, and the second power supply pad supplies a second power supply potential to the first and second data I/O buffers. The first data I/O pad included in each of the pad groups is adjacent to the second power supply pad included in other pad group or any one of a plurality of power supply pads not included in any one of the pad groups. | 2011-03-17 |
20110063926 | Write Through Speed Up for Memory Circuit - A method of performing a write-through operation with a memory circuit having a write enable line, a write address line, a data in line, a read address line, a data out line, a bit array, a comparator, and a mux. A write address is received on the write address line, a read address is received on the read address line, data is received on the data in line. The comparator determines as a first condition whether the write address is identical to the read address, and determines as a second condition whether the write enable line is enabled. When both the first condition and the second condition are met, the comparator signals the mux to directly output the data receiving on the data in line on the data out line without writing the data to the bit array. In this manner, the memory circuit checks to determine whether a write-through operation is called for. If it is, then the mux sends the data on the data in line directly to the data out line, instead of retrieving data from the bit array of the memory, such as through the read decoder, which would take much longer. | 2011-03-17 |
20110063927 | Semiconductor device using plural internal operation voltages and data processing system using the same - A semiconductor device includes an input buffer that receives an address signal having a first amplitude, a level shifter that converts an amplitude of the address signal output from the input buffer to a second amplitude that is smaller than the first amplitude, an address controller that receives the address signal output from the level shifter, address decoders that generate a decode signal by decoding the address signal output from the address controller, and level shifters that convert an amplitude of the address signal or of the decode signal from the second amplitude to the first amplitude such that at least an amplitude level of the decode signal becomes the first amplitude. | 2011-03-17 |
20110063928 | SEMICONDUCTOR MEMORY DEVICE - A dummy cell array is provided in a memory cell array, and an intermediate buffer is provided between input/output circuits, whereby control signals to the input/output circuits can be operated at high speed and with a high frequency while the area increasing effect is reduced even in a memory with a large bit width. | 2011-03-17 |
20110063929 | DELAY LINE THAT TRACKS SETUP TIME OF A LATCHING ELEMENT OVER PVT - A latching element latches incoming data into an integrated circuit. The latching element (for example, a latch or flip-flop) can be considered to include a data path portion, a clock path portion, and an ideal latching element. In one embodiment, an open-loop replica of the data path portion is disposed in a clock signal path between a clock input terminal of the integrated circuit and a clock input lead of the latching element. In a second embodiment, an additional replica of the clock path portion is disposed in a data signal path between a data terminal of the integrated circuit and a data input lead of the latching element. The replica circuits help prevent changes in skew between a data path propagation time to the ideal latching element and clock path propagation time to the ideal latching element. Setup times remain substantially constant over PVT (process, supply voltage, temperature). | 2011-03-17 |
20110063930 | SUBTRACTION CIRCUITS AND DIGITAL-TO-ANALOG CONVERTERS FOR SEMICONDUCTOR DEVICES - A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output and an analog input, which may be connected to the bit-line. In some embodiments, the delta-sigma modulator includes a circuit with first and second inputs and an output. The circuit is configured to combined (add or subtract) input signals. The first input may be connected to the analog input. The delta-sigma modulator may also include an integrator connected to the output of the circuit, an analog-to-digital converter with an input connected to an output of the integrator and an output connected to the digital output, and a digital-to-analog converter with an input connected to the output of the analog-to-digital converter and an output connected to the second input of the circuit. | 2011-03-17 |
20110063931 | INTERFACES, CIRCUITS, AND METHODS FOR COMMUNICATING WITH A DOUBLE DATA RATE MEMORY DEVICE - An input/output interface reads data from and writes data to a DDR memory. The interface includes data and strobe circuits. The strobe circuit includes preamble logic, a first counter operating with a strobe clock, a second counter operating with an ASIC-generated clock, a strobe park circuit and a first synchronizer. The preamble logic receives strobe signals from the DDR memory and generates a preamble signal. The first counter generates a first input of the strobe park circuit. The second counter generates a second input of the strobe park circuit. The strobe park circuit controllably replaces the strobe signals from the DDR memory with respective non-transitioning signals when data is not being read. The data circuit includes a FIFO buffer and a second synchronizer. The FIFO buffer receives data with the strobe clock. The second synchronizer generates a representation of the data in response to the ASIC-generated clock. | 2011-03-17 |
20110063932 | Boosting voltage levels applied to an access control line when accessing storage cells in a memory - A semiconductor memory storage device is disclosed, the memory comprises: a plurality of storage cells for storing data; at least two access control lines each for controlling access to a respective at least one of the plurality of storage cells; at least two access control circuits each for controlling a voltage level supplied to a corresponding one of the at least two access control lines in response to an access request, the at least two access control circuits each comprising a capacitor and switching circuitry; routing circuitry for routing the access request and a boost signal to a selected one of the at least two access control circuits in dependence upon an address associated with the access request; wherein the at least two access control circuits are each responsive to: receipt of the access request from the routing circuitry to connect the selected access control line to a supply voltage; and receipt of the boost signal from the routing circuitry to disconnect the supply voltage from the access control line and to couple the boost signal to the access control line through the capacitor of the access control circuit to provide a boost to a voltage level on the access control line. | 2011-03-17 |
20110063933 | Semiconductor device, relief-address-information writing device, and relief-address-information writing method - To provided a relief-address generating circuit that generates relief address information based on plural data bits supplied in time sequence via a first terminal from outside and a programming circuit that writes into any one of fuse sets the relief address information generated by the relief-address generating circuit. With this configuration, repetition of a programming operation by the total number of the fuse sets at the maximum completes a series of write processing on relief address information. Therefore, it is possible to reduce the time required for a series of write processing on relief address information. | 2011-03-17 |
20110063934 | MEMORY CIRCUIT WITH MULTI-SIZED SENSE AMPLIFIER REDUNDANCY - A memory circuit with multi-sized sense amplifier redundancy is disclosed. In one aspect, the circuit includes sense amplifiers connected to differential bit-lines and configured to amplify a voltage difference sensed on the differential bit-lines. The sense amplifiers include a first set of smaller sense amplifiers and a second set of larger sense amplifiers redundantly arranged to the first set to form redundant groups which each contain one smaller sense amplifiers and one larger sense amplifiers. The larger sense amplifiers have a failure rate lower than the smaller sense amplifiers. The circuit also includes calibration circuitry connected to enable and disable nodes of each of the sense amplifiers and configured to select for each redundant group either the smaller sense amplifier of the first set or, if the smaller sense amplifier fails, the larger sense amplifier of the second set. | 2011-03-17 |
20110063935 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM COMPRISING SEMICONDUCTOR DEVICE - A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof. | 2011-03-17 |
20110063936 | SEMICONDUCTOR DEVICE INCLUDING PLURAL ELECTRODE PADS - A semiconductor device includes a pad for sense amplifier ground potential as an electrode pad supplying ground potential voltage to a sense amplifier, a first conductive line connected to the pad for sense amplifier ground potential, and a second conductive line connected to an electrode pad closest to the pad for sense amplifier ground potential among plural electrode pads included in a pad row. The second conductive line extends to the opposite side of the first conductive line with the pad row as a reference. | 2011-03-17 |
20110063937 | SYSTEM AND METHOD TO COMPENSATE FOR PROCESS AND ENVIRONMENTAL VARIATIONS IN SEMICONDUCTOR DEVICES - An integrated circuit (IC) including a controller integrally formed on a shared die with the IC and method of operating the same to compensate for process and environmental variations in the IC are provided. In one embodiment the IC is comprised of device and sub-circuits, and the method includes: receiving in the IC electrical power and information on at least one of one or more operational parameters of the IC; and adjusting one or more operating characteristics of at least one of the devices and sub-circuits in the IC based on the received information using a controller integrally formed on a shared die with the IC. Other embodiments are also disclosed. | 2011-03-17 |
20110063938 | CONCRETE DISCHARGE BOOT ACCESSORY DEVICE AND METHOD OF USE THEREOF - A cabling system and accessory for attachment to the rubber boot surrounding the metal chute area of either a front or rear loader concrete truck for improving and enhancing the function and purpose of the rubber boot and chute area of a ready mix concrete truck, and for increasing the safety, health, and environmental aspects of cleaning thereof, wherein physical exertion and risk of injury to the truck operator is minimized, wherein the quantity of water utilized for cleaning is reduced, wherein the overall cleanliness of the truck is improved, and wherein the functional life span of the boot, chute, mechanical parts, and the truck itself is increased. | 2011-03-17 |
20110063939 | BARREL COOLING AND HEATING SYSTEM FOR SCREW EXTRUDER - An extruder barrel section is disclosed. The extruder barrel section comprises of a first barrel pad and a second barrel pad. The first and second barrel pad co-operating to define a recess configured to receive an extruder liner. The length of the first and second barrel pad is less than the length of the extruder liner such that the extruder liner defines an end surface that projects beyond the extruder barrel section on at least one side. The end surface is configured to abut the end surface of another extruder liner. The extruder barrel section further comprises of a locking structure configured to lock the first barrel pad to the second barrel pad with the extruder liner therebetween. | 2011-03-17 |
20110063940 | METHOD OF EXTRUDER OPERATION - An extruder capable of improved mixing is disclosed. The extruder comprises of a housing having at least two cylindrical housing bores, each housing bore having an axis disposed parallel to the other axis. The extruder further comprises of at least a first screw shaft and a second screw shaft being disposed in the first and second housing bores. The first and second screw shaft being provided with extruder processing elements that defines a mixing zone. The first and second screw each having extruder D and a screw root diameter d. The first and second screw shaft each having a volumetric ratio of at least 1.4 wherein the volumetric ratio is defined by the extruder diameter D divided by the screw inner diameter d. | 2011-03-17 |
20110063941 | STAND MIXER ARRANGEMENT - A stand mixer ( | 2011-03-17 |
20110063942 | Methods and Systems for Integral Blending and Storage of Materials - Methods and systems for integral storage and blending of the materials used in oilfield operations are disclosed. An integrated material blending and storage system is disclosed with a storage unit, a blender located under the storage unit, a liquid additive storage module having a pump to maintain constant pressure at an outlet of the liquid additive storage module and a pre gel blender. Gravity directs a first input from the storage unit, a second input from the liquid additive storage module and a third input from the pre-gel blender to the blender. | 2011-03-17 |
20110063943 | CHANNEL CROSS-SECTION GEOMETRY TO MANIPULATE DISPERSION RATES - The present invention provides novel methods for controlling/manipulating materials flowing in a fluidic device. In particular, the methods of the invention create and utilize differences between dispersion rates and/or average velocity of materials in order to manipulate the materials. | 2011-03-17 |
20110063944 | BLENDER SYSTEM HAVING A CONTAINER - A blender system ( | 2011-03-17 |
20110063945 | APPARATUS AND METHOD FOR PROCESSING AN ULTRASOUND SPECTRUM IMAGE - There is provided a method of processing an ultrasound spectrum image. According to such method, a spectrum image is formed based on ultrasound data and then the noise is removed from the spectrum image. The noise-removed spectrum image is matched with one or more spectrum models representing specific spectrum types. Then, whether or not the noise-removed spectrum image contains an aliasing is checked. If the noise-removed spectrum image contains the aliasing, then the aliasing is removed from the noise-removed spectrum image to provide a noise-removed spectrum image without the aliasing. Thereafter, contour tracing is performed on the noise-removed spectrum image without the aliasing to detect contour points. Further, peak tracing is performed on the noise-removed spectrum image without the aliasing to detect peaks. | 2011-03-17 |
20110063946 | MARINE SEISMIC ACQUISITION SYSTEM - A marine cable for seismic surveys is described with a plurality of ceramic pressure sensors arranged in groups of at least two pressure sensors with a group output being representative of the vertical pressure gradient at the group location, and an inclinometric system including one or more transducers for determining the orientation of the sensors of the group in order to determine their true vertical separation. | 2011-03-17 |
20110063947 | ZERO OFFSET PROFILE FROM NEAR-FIELD HYDROPHONES - Method for acquiring zero offset data from a marine seismic survey. Seismic data are recorded using source signature monitor receivers located very near the air guns or other sources ( | 2011-03-17 |
20110063948 | Method for combining signals of pressure and particle motion sensors in marine seismic streamers - A cross-line slowness is determined for each sample in the signals in towed marine seismic streamers. A range of assumed cross-line slownesses is selected. Vertical wavenumbers are determined using the range of assumed cross-line slowness determined for samples in the signals of pressure sensors and particle motion sensors in the towed marine seismic streamers. The determined vertical wavenumbers are used to correct the particle motion sensor signals for angle of incidence along the direction of the seismic streamers and transverse thereto to generate a corrected particle motion sensor signal. The corrected particle motion sensor signals are combined based on the determined cross-line slowness for the samples. The corrected particle motion sensor signal and the pressure sensor signal are used to determine at least one of upgoing and downgoing pressure components and upgoing and downgoing particle motion components of the particle motion sensor and pressure sensor seismic signals. | 2011-03-17 |
20110063949 | TDEM FORWARD FOCUSING SYSTEM FOR DOWNHOLE USE - A method and apparatus for estimating a parameter of interest of an earth formation ahead of a carrier within borehole. The method including estimating one or more functions based on received signals that may reduce the sum of the signals received by a first receiver, and estimating the parameter of interest based on signals received by one or more additional receivers by applying the one or more functions and, if necessary, a defocusing factor, such that reception of information from downhole of a selected downhole location is enhanced relative to reception of information uphole from the selected location. The apparatus including two or more transmitters, two or more receivers, and a processor to estimate one or more functions, and, based on these functions, the parameter of interest. | 2011-03-17 |
20110063950 | VIBRATION GENERATION AND DETECTION IN SHEAR WAVE DISPERSION ULTRASOUND VIBROMETRY WITH LARGE BACKGROUND MOTIONS - A method for measuring a mechanical property of a subject includes using an ultrasonic transducer to apply ultrasonic vibration pulses to a vibration origin in the subject in an on-off time sequence in order to impart a harmonic motion at a prescribed frequency to the subject, and when the vibration pulses are off, preferably using the same transducer to apply ultrasonic detection pulses to a motion detection point and to receive echo signals therefrom in order to sense the harmonic motion on the subject at the motion detection point The ultrasonic detection pulses are interspersed with the vibration pulses and can be applied in a non-uniform manner From the received ultrasonic echo signals, a harmonic signal is detected and a characteristic such as amplitude or phase of the detected harmonic signal is calculated using a Kalman filter or interpolation. | 2011-03-17 |
20110063951 | Active sonar system - An active sonar system includes at least one transmitter to transmit an acoustic signal, at least one receiver to receive a reflected acoustic signal, and an electronic cabinet to control the at least one transmitter to transmit the acoustic signal and the receiver to receive the reflected acoustic signal. At least one transmitter includes at least one carbon nanotube transmitting transducer. At least one carbon nanotube transmitting transducer includes at least one first electrode, at least one second electrode, and an acoustic element. The acoustic element includes a carbon nanotube structure that is electrically connected to at least one first electrode and at least one second electrode. | 2011-03-17 |
20110063952 | Electronic Timepiece And Time Adjustment Method For An Electronic Timepiece - An electronic timepiece wherein, when the week number indicates an n-th cycle from a specific reference date as a cycle number, a date determination information setting unit sets the date determination information using a partial unit that is a different number in each date corresponding to the same week number in a plurality of consecutive cycle numbers, and the date determination unit acquires the date in each cycle number identified by the week number and time of week based on week number cycle information correlating week numbers, cycle numbers, and dates, and determines in which of these dates the partial unit matches the date determination information. | 2011-03-17 |
20110063953 | ANALOG ELECTRONIC TIMEPIECE AND STEPPING MOTOR DRIVING METHOD - An analog electronic timepiece including, a plurality of hands, a plurality of stepping motors, a maximum speed of at least one stepping motor being different from that of another stepping motor, and a fast-forward control section to simultaneously drive at least two of the plurality of stepping motors, the fast-forward control section composed of, a speed judging section to judge the slowest speed among maximum speeds of stepping motors, a drive control section to simultaneously drive the stepping motors at the speed judged by the speed judging section, an end judging section to judge whether a further hand to be moved remains when drive of the stepping motors at the speed judged by the speed judging section ends, and a control section to make the speed judging section, the drive control section, and the end judging section operate again when the hand to be moved remains. | 2011-03-17 |
20110063954 | Near-field optical recording apparatus, method and medium - An apparatus, a method and a recording medium for optical near-field recording are proposed. The apparatus includes a light source for generating a reading light beam, which is illuminated onto a near-field optical recording medium. The apparatus further includes a detector for generating a gap error signal from a light beam returning from the near-field optical recording medium. A data signal is derived from an output signal of the detector by a signal processor. | 2011-03-17 |
20110063955 | Standalone Duplication System with Network Connection - A standalone duplication system with network connection has a casing, multiple recording devices, a control module, a bridge unit, a storage device and a network module, wherein the bridge unit connects between the control module, the storage device and the network module. When the bridge unit confirms that the control module has disconnected from the storage device and the network module receives a data transfer command, the storage device can receive data via the network module and store data for duplication. Therefore, the standalone duplication system is capable of receiving data from different computers over a network without using a high-end central processing unit (CPU). The standalone duplication system need not be moved to different places and connected to and disconnected from different personal computers again and again. Users operate their own personal computers to send required data to the standalone duplication system via the network. | 2011-03-17 |
20110063956 | OPTICAL PICKUP DEVICE AND OPTICAL DISC APPARATUS - An optical pickup device includes a polarization diffraction grating to diverge an optical beam reflected from an optical disc and an optical detector to receive the optical beam diverged by the polarization diffraction grating, a polarization of 0 order diffracted light diffracted through the polarization diffraction grating is substantially perpendicular to that of a +1 order diffracted light diffracted therethrough, and a polarization filter having a plurality of domains is mounted between the polarization diffraction grating and the optical detector. | 2011-03-17 |
20110063957 | OPTICAL DISK APPARATUS - In an optical disk apparatus, an optical pickup includes an actuator for driving an object lens, and a sensed signal output part for making it possible to generate a tracking error signal and a lens error signal by addition/subtraction, and a signal processor includes a servo signal generator for generating a tracking error signal and a lens error signal on the basis of a signal supplied from the sensed signal output part, and a tracking offset correction quantity signal generator supplied with the lens error signal to output a tracking offset correction quantity signal. DC (direct current) offset correction is conducted by conducting addition/subtraction between the tracking error signal and both the lens error signal and the tracking offset correction quantity signal. | 2011-03-17 |
20110063958 | Servo Processor Receiving Photodetector Signals - A servo processor for an optical disk drive is provided that includes: an analog-to-digital converter for converting versions of photodetector output signals into digital signals; and a digital signal processor configured to receive the digital signals, the digital signal processor being further configured to determine a focus error signal (FES) and a tracking error signal (TES) from the digital signals, the digital signal processor being further configured to process TES and FES through servo algorithms to produce tracking and focus control signals. | 2011-03-17 |
20110063959 | LOADER MODULE OF AN OPTICAL ACCESS APPARATUS - A loader module of an optical access apparatus is provided. The optical access apparatus has a main control printed circuit board (PCB). The loader module comprises an optical pick-up head, a drive unit, a first signal line, a second signal line and a non-volatile memory (NVM). The first signal line is configured to electrically connect the optical pick-up head, the drive unit and the main control PCB. The second signal line is configured to electrically connect the NVM and the main control PCB. The NVM is configured to store control information. The control information is transmitted to the main control PCB via the second signal line so that the main control PCB can control the loader module. | 2011-03-17 |
20110063960 | OPTICAL DISC APPARATUS - An optical disc apparatus, being improved in a random access speed thereof and superior in a usability thereof, comprises: a virtual disc for memorizing data of at least one (1) pieces of an optical disc; a recording/reproducing means for executing reproduction of data from the optical disc and recording of data onto the optical disc; and a system controller means for controlling the virtual disc and the recording/reproducing means. | 2011-03-17 |
20110063961 | OPTICAL DISC APPARATUS AND OPTICAL DISC RECORDING/REPRODUCING METHOD - An optical disc apparatus includes an optical pickup including: a light source; an objective lens for converging a light flux emitted from the light source and forming an optical spot on an information recording plane of an optical disc; and an optical modulation unit divided into a plurality of areas for modulating an area containing a main beam of the light flux to change a shape of the optical spot, wherein data is reproduced by converting a reproduction signal read from the optical disc with the optical pickup into an NRZI signal of a predetermined modulation rule by a PRML method. An optical spot shape, laser power setting and PRML setting are changed with each optical disc and each drive operation state. | 2011-03-17 |
20110063962 | REPRODUCING DEVICE AND REPRODUCING METHOD - A reproducing device includes: a laser light irradiating section; a correction coefficient information retaining section; a correction coefficient obtaining section; a laser power setting section; and a driving signal outputting section. | 2011-03-17 |
20110063963 | METHOD AND DEVICE FOR OPTICAL RECORDING ONTO OPTICAL DISC MEDIUM - There is provided an optical recording method for directing a recording pulse train to an optical disc medium to form marks thereon and for recording information as information about the edge positions of said marks and the spaces between marks, the recording pulse train having been created by modulating laser light into plural power levels. The method includes: coding to-be-recorded data into coded data consisting of the combination of marks and spaces; classifying said marks within said coded data on the basis of the mark length and the preceding or succeeding space lengths of the marks; shifting the position of the second pulse edge counted from the end portion of the recording pulse train for forming said marks, depending on the result of said classification, to adjust said recording pulse train; and directing said recording pulse train to the optical disc medium to form said marks thereon. | 2011-03-17 |
20110063964 | METHOD OF MANUFACTURING A DISK DRIVE DEVICE HAVING BASE MEMBER, BEARING UNIT, DRIVE UNIT AND HUB, AND DISK DRIVE DEVICE MANUFACTURED BY THE MANUFACTURING METHOD - A method of manufacturing a disk drive device including: assembling a subassembly by fixing at least a bearing unit, a drive unit and a hub to a base member in a first clean room; cleaning the subassembly in a second clean room; and sealing the subassembly by a sealing member. The first clean room and the second clean room are communicated with each other by a communicating opening for transferring the subassembly, and an atmospheric pressure in the second clean room is equal to or higher than that in the first clean room. | 2011-03-17 |
20110063965 | MULTIPLEXED DATA STORAGE METHOD - The core of the present invention is a method and an apparatus for transformation of matter parameters through optical way. In course of said method, a multilateral pattern inside a sample matter is created by means of a specific imaging beam emitted by a light emitting device. The most significant application of the suggested method is for writing on optic data storage media. Further application concerns the analysis of the above-mentioned optical parameters, i.e. reading data from the storage media. | 2011-03-17 |
20110063966 | COMPOUND, POLYMERIZABLE LIQUID CRYSTAL COMPOSITION, OPTICAL ELEMENT AND OPTICAL INFORMATION WRITING/READING DEVICE - A compound having a good durability against light and capable of producing desired liquid crystallinity after polymerization, and a polymerizable liquid crystal composition containing such a compound, are provided. Further, an optical element having a good durability against light, and an optical information writing/reading device employing such an element, are provided. | 2011-03-17 |
20110063967 | OPTICAL PICKUP DEVICE AND OPTICAL DISC APPARATUS USING THE SAME - A diffractive optical element having a diffraction region for diffracting a part of a luminous flux is mounted and an unwanted luminous flux generated in a multi-layer optical disc is suppressed from entering a photodetector surface. Using the above-described structure, fluctuation of a tracking error signal can be suppressed from being caused by the unwanted luminous flux and preferable recording or reproduction quality can be obtained also in the multi-layer optical disc. | 2011-03-17 |
20110063968 | OPTICAL PICKUP APPARATUS HAVING MULTI-SECTIONAL POLARIZER - An optical pickup apparatus includes a light generating unit to generate a light to record or reproduce information, an objective lens to focus the light generated from the light generating unit onto a disk, and a multi-sectional polarizer disposed on a light path between the light generating unit and the objective lens and divided into a plurality of sectors having their individual optical axes. | 2011-03-17 |
20110063969 | SEMICONDUCTOR INTEGRATED CIRCUIT - The semiconductor integrated circuit incorporates a PLL circuit including a phase-frequency comparator | 2011-03-17 |
20110063970 | MOVING APPARATUS AND INFORMATION RECORDING/REPRODUCING APPARATUS | 2011-03-17 |
20110063971 | Data relay apparatus, and ring-type communication system - A data relay apparatus for data relay in a ring-type network for data including a path identifier which is transferred according to the path identifier, receives the data; stores the path identifier that is used to determine a data path in which the data is transferred in the ring-type communication network in association with a reception direction and a transmission direction of the data; compares the path identifier included in the received data and the path identifier stored by an information storing part to determine a path for receiving and transmitting the data and switches the transmission direction of the data based on a reception direction of a failure notification message notified when a communication failure occurs and whether a switching inhibition message transmitted concerning the communication failure is received; and transmits the data in the switched transmission direction. | 2011-03-17 |
20110063972 | Duplicate traffic avoidance in a point to multi-point network - Provided is a method for avoiding traffic duplication in a point to multi-point network, the method including monitoring a status of first interconnection links in a first data path from a source to a destination, the first data path including an ingress node, an egress node, and one or more intermediate nodes. The method further includes establishing a second data path if a link of the first interconnecting links is determined to be an inoperable link, the second data path including the ingress node, the egress node, at least one of the one or more intermediate nodes and second interconnecting links, the second interconnecting links including new interconnecting links and a subset of the first interconnecting links, the subset not including the inoperable link in the first interconnecting links. | 2011-03-17 |