11th week of 2011 patent applcation highlights part 13 |
Patent application number | Title | Published |
20110062473 | LIGHT EMITTING DEVICE - A light emitting device includes a light emitting element, a wire connected to the light emitting element, and a substrate supporting the light emitting element. The substrate is formed with a first recess and a second recess that are open in a common surface of the substrate. The first recess includes a first bottom surface and a first side surface connected to the first bottom surface, and the light emitting element is disposed on the first bottom surface. The second recess includes a second bottom surface and a second side surface connected to the second bottom surface, and the wire is bonded to the second bottom surface. Both of the first side surface and the second side surface reach the common surface. The first side surface is connected to both of the second bottom surface and the second side surface. The opening area of the first recess is larger than the opening area of the second recess. | 2011-03-17 |
20110062474 | LIGHT-EMITTING DIODE DEVICE AND FABRICATION METHOD THEREOF - A light-emitting diode device includes a frame, a light-emitting diode die, a fluorescent layer, a reflector, and a lens. The light-emitting diode die is disposed on the frame. The fluorescent layer is directly molded to cover the light-emitting diode die. The reflector is directly molded on the frame, surrounding the light-emitting diode die, and configured to direct light from the light-emitting die in a predetermined direction. The lens is directly molded within the reflector, covering the fluorescent layer. | 2011-03-17 |
20110062475 | ORGANIC LIGHT EMITTING DISPLAY DEVICE - An organic light emitting display device includes a substrate and a plurality of pixels on the substrate. The pixels include a plurality of first electrodes, a second electrode, a white light emitting layer, and a first thin film layer between the first electrodes and the second electrode. White light emitted from the white light emitting layer causes resonance to occur between the first electrodes and the second electrode. | 2011-03-17 |
20110062476 | LIGHT-EXTRACTION MEMBER, ORGANIC EL ELEMENT, AND METHOD FOR PRODUCING THE ORGANIC EL ELEMENT - A light-extraction member for use in a light-emitting display device, the light-extraction member including a light-extracting substrate which is disposed on the light-extraction side of the light-emitting display device, a color filter layer formed over the light-extracting substrate, and a lens member formed over the color filter layer, wherein the color filter layer is bonded via an adhesive portion to a convex top portion of the lens member. | 2011-03-17 |
20110062477 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed are a semiconductor light emitting device. The semiconductor light emitting device comprises a light emitting structure comprising a plurality of compound semiconductor layers, a passivation layer at the outside of the light emitting structure, a first electrode layer on the light emitting structure, and a second electrode layer under the light emitting structure. | 2011-03-17 |
20110062478 | SEMICONDUCTOR LIGHT EMITTING DEVICES INCLUDING FLEXIBLE UNITARY FILM HAVING AN OPTICAL ELEMENT THEREIN - A semiconductor light emitting device includes a substrate having a face, a flexible unitary film that includes an optical element therein on the face, and a semiconductor light emitting element between the substrate and the flexible film that is configured to emit light through the optical element. The flexible unitary film extends conformally on the face of the substrate outside the semiconductor light emitting element and also extends on the semiconductor light emitting element. | 2011-03-17 |
20110062479 | METHOD OF MANUFACTURING GROUP-III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND GROUP-III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND LAMP - Provided are a method of manufacturing a group-III nitride semiconductor light-emitting device in which a light-emitting device excellent in the internal quantum efficiency and the light extraction efficiency can be obtained, a group-III nitride semiconductor light-emitting device and a lamp. Included are an epitaxial step of forming a semiconductor layer ( | 2011-03-17 |
20110062480 | SEMI-CONDUCTOR LIGHT-EMITTING DEVICE - Disclosed is a semiconductor light emitting device. The semiconductor light emitting device includes a first conductive semiconductor layer, an active layer under the first conductive semiconductor layer, a second conductive semiconductor layer under the active layer, a second electrode layer under the second conductive semiconductor layer; and an insulating layer on an outer peripheral surface of at least two layers of the first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer. | 2011-03-17 |
20110062481 | ORGANIC LIGHT-EMITTING DEVICE - An organic light-emitting device cutting off ambient light while keeping emission intensity includes a pair of first and second electrodes opposed to each other; and a plurality of organic semiconductor layers layered and disposed between the first and second electrodes, wherein the organic semiconductor layers include an organic light-emitting layer, the organic semiconductor device further comprising a light-scattering layer layered and disposed between the organic light-emitting layer and at least one of the first and second electrodes. The light-scattering layer includes: organic materials having carrier injection and transport characteristics of transporting electrons and/or holes; and plural particles dispersed among the organic materials so that light emitted from the organic light-emitting layer is passed therethrough. | 2011-03-17 |
20110062482 | Apparatus And Method For Enhancing Connectability In LED Array Using Metal Traces - A light-emitting device having multiple light-emitting diode (“LED”) dice organized in an array capable of configuring LED dice in series, parallel, and/or a combination of series and parallel via metal traces is disclosed. In one aspect, the light-emitting device includes a substrate, a dielectric layer, an LED array, and a metal trace. The dielectric layer, which is disposed over the substrate, provides electric insulation. The LED array capable of generating light is able to enhance flexibility of LED connections using a metal trace. The metal trace has a predefined shape configured to travel through the LED array for facilitating electric connections. | 2011-03-17 |
20110062483 | LIGHT-EMITTING DIODE - This invention provides a light-emitting diode (LED). The LED is electrically connected with a circuit board. The LED includes a light-emitting chip, an encapsulating element, a lead, and a heat insulating element. The encapsulating element encapsulates the light-emitting chip. The lead is coupled with the light-emitting chip and the circuit board. The lead and the encapsulating element form a first connecting place. The lead and the circuit board form a second connecting place. The heat insulating element is disposed between the first connecting place and the second connecting place. | 2011-03-17 |
20110062484 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light-emitting device which includes a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; and a light emitting layer provided between the first and second semiconductor layers, the device comprises a first electrode formed on the first semiconductor layer; a second electrode formed on the second semiconductor layer; and a light-transmissive electrode covering the second semiconductor layer and the second electrode, wherein contact between the second electrode and the second semiconductor layer is non-ohmic, and the second electrode has a stacked structure including a lower layer and an upper layer whose contact resistance with the light-transmissive electrode is lower than that of the lower layer, part of the second electrode being exposed through an opening formed in the light-transmissive electrode. | 2011-03-17 |
20110062485 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT, METHOD FOR MANUFACTURING THE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND LAMP THAT USES THE SEMICONDUCTOR LIGHT-EMITTING ELEMENT - Provided are a semiconductor light-emitting element that is capable of efficiently outputting blue color or ultraviolet light, and a lamp using the semiconductor light-emitting element. | 2011-03-17 |
20110062486 | FABRICATION FOR ELECTROPLATING THICK METAL PADS - A method of electroplating includes forming a seed region to be electroplated on a first portion of a substrate, forming a ground plane on a second portion of a substrate, electrically isolating the ground plane from the seed region, electroplating the region, wherein electroplating includes causing the ground plane and the region to make electrical connection, and then removing the ground plane region on the second portion of the substrate, but not removing the electrical isolation. This creates a structure having a substrate, a passivation layer on the substrate, and at least one electroplated, metal region on the substrate such that there is contiguous contact between the metal region and the passivation layer. And, after an additional flip-chip assembly to a bond pad/heat sinking chip, results in a device having a bond pad chip having bond pads, solder beads formed on the bond pads, and a component connected to the bond pads by the solder beads. Wherein, the component has a substrate, a passivation layer on the substrate, and at least one electroplated, metal region on the substrate such that there is contiguous contact between the metal region and the passivation layer. | 2011-03-17 |
20110062487 | SEMICONDUCTOR LIGHT EMITTING DEVICE - The present disclosure relates to a semiconductor light emitting device, the semiconductor light emitting device comprising: a plurality of openings positioned between first electrode and second electrode, the plurality of openings defining a first opening region for suppressing current flow between the first electrode and the second electrode and a second opening region for relatively less suppressing current flow than the first opening region. | 2011-03-17 |
20110062488 | Group III nitride semiconductor light-emitting device - A Group III nitride semiconductor light-emitting device includes an electrically conductive support; a p-electrode provided on the support; a p-type layer, an active layer, and an n-type layer, which are formed of a Group III nitride semiconductor and are sequentially provided on the p-electrode; an n-electrode which is connected to the n-type layer; a first trench extending from the surface of the p-type layer on the p-electrode's side to reach the n-type layer; an auxiliary electrode which is in contact with the surface of the n-type layer serving as the bottom of the first trench, but is not in contact with the side walls of the first trench; and an insulating film which exhibits light permeability and covers the auxiliary electrode and the bottom and side walls of the first trench. | 2011-03-17 |
20110062489 | POWER DEVICE WITH SELF-ALIGNED SILICIDE CONTACT - An improved power device with a self-aligned suicide and a method for fabricating the device are disclosed. An example power device is a vertical power device that includes contacts formed on gate and body contact regions by an at least substantially self-aligned silicidation (e.g., salicide) process. The example device may also include one or more sidewall spacers that are each at least substantially aligned between edges of the gate region and the body contact region. The body contact region may also be implanted into the device in at least substantial self-alignment to the sidewall spacer. The method may also include an at least substantially self-aligned silicon etch. | 2011-03-17 |
20110062490 | MOS GATE POWER SEMICONDUCTOR DEVICE - A MOS-gate power semiconductor device includes: a main device area including an active area and an edge termination area; and an auxiliary device area horizontally formed outside the main device area so as to include one or more diodes. Accordingly, it is possible to protect a circuit from an overcurrent and thus to prevent deterioration and/or destruction of a device due to the overcurrent. | 2011-03-17 |
20110062491 | POWER SEMICONDUCTOR MODULE - A power semiconductor module ( | 2011-03-17 |
20110062492 | High-Quality Hetero-Epitaxy by Using Nano-Scale Epitaxy Technology - An integrated circuit structure includes a semiconductor substrate formed of a first semiconductor material; two insulators in the semiconductor substrate; and a semiconductor region between and adjoining sidewalls of the two insulators. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material, and has a width less than about 50 nm. | 2011-03-17 |
20110062493 | EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR DEVICE, SCHOTTKY JUNCTION STRUCTURE, AND LEAKAGE CURRENT SUPPRESSION METHOD FOR SCHOTTKY JUNCTION STRUCTURE - Provided is an epitaxial substrate for semiconductor device that is capable of achieving a semiconductor device having high reliability in reverse characteristics of schottky junction. An epitaxial substrate for semiconductor device obtained by forming, on a base substrate, a group of group III nitride layers by lamination such that a (0001) crystal plane of each layer is approximately parallel to a substrate surface includes: a channel layer formed of a first group III nitride having a composition of In | 2011-03-17 |
20110062494 | STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS - A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench. | 2011-03-17 |
20110062495 | Field Effect Transistor with Access Region Recharge - The current invention provides the design of the field effect transistor with lateral channel suitable for high voltage switching. In such a transistor, the electrical charge stored in the high electric field region has to vary as the transistor switches from ON to OFF state and back. The invention provides the method of calculating the necessary recharging path parameters based on the material parameters of the FET and desired blocking voltage, ON state resistance and switching speed. The invention can be used in power electronics by providing circuits and parts, for example, for electrical power distribution between power plant customers, for automotive, craft and space applications and many other applications where high voltage in excess of 400-600 V is involved. | 2011-03-17 |
20110062496 | Methods and Compositions for Preparing Ge/Si Semiconductor Substrates - The present disclosure describes methods for preparing semiconductor structures, comprising forming a Ge layer on a semiconductor substrate using an admixture of (a) (GeH | 2011-03-17 |
20110062497 | SEMICONDUCTOR DEVICE STRUCTURE WITH STRAIN LAYER AND METHOD OF FABRICATING THE SEMICONDUCTOR DEVICE STRUCTURE - A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and gate dummies not to overlap each other, the area of active dummy on which a strain layer dummy will be formed can be secured, thereby reducing the loading effect. | 2011-03-17 |
20110062498 | EMBEDDED SILICON GERMANIUM SOURCE DRAIN STRUCTURE WITH REDUCED SILICIDE ENCROACHMENT AND CONTACT RESISTANCE AND ENHANCED CHANNEL MOBILITY - Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 Å to 28 about 800 Å, and the first and second layers at a thickness of about 30 Å to about 70 Å. | 2011-03-17 |
20110062499 | Electronic Shutter With Photogenerated Charge Extinguishment Capability for Back-Illuminated Image Sensors - An electronic image sensor includes a semiconductor substrate having a first surface configured for accepting illumination to a pixel array disposed in the substrate. An electrically-doped channel region for each pixel is disposed at a second substrate surface opposite the first substrate surface. The channel regions are for collecting photogenerated charge in the substrate. An electrically-doped channel stop region is at the second substrate surface between each channel region. An electrically-doped shutter buried layer, disposed in the substrate at a depth from the second substrate surface that is greater than that of the pixel channel regions, extends across the pixel array. An electrically-doped photogenerated-charge-extinguishment layer, at the first substrate surface, extends across the pixel array. A substrate bulk region between the shutter buried layer and the photogenerated-charge-extinguishment layer is characterized by an electrical resistivity enabling independent electrical bias of the photogenerated-charge-extinguishment layer from electrically-doped regions of the substrate. | 2011-03-17 |
20110062500 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode. | 2011-03-17 |
20110062501 | METHOD FOR SELF-ALIGNING A STOP LAYER TO A REPLACEMENT GATE FOR SELF-ALIGNED CONTACT INTEGRATION - Semiconductor devices with replacement gate electrodes and integrated self aligned contacts are formed with enhanced gate dielectric layers and improved electrical isolation properties between the gate line and a contact. Embodiments include forming a removable gate electrode on a substrate, forming a self aligned contact stop layer over the removable gate electrode and the substrate, removing a portion of the self aligned contact stop layer over the removable gate electrode and the electrode itself leaving an opening, forming a replacement gate electrode of metal, in the opening, transforming an upper portion of the metal into a dielectric layer, and forming a self aligned contact. Embodiments include forming the contact stop layer of a dielectric material, e.g., a hafnium oxide, an aluminum oxide, or a silicon carbide and transforming the upper portion of the metal into a dielectric layer by oxidation, fluorination, or nitridation. Embodiments also include forming a hardmask layer over the removable gate electrode to protect the electrode during silicidation in source/drain regions of the semiconductor device. | 2011-03-17 |
20110062502 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention proposes a method of forming a dual contact hole, comprising steps of: forming a source/drain region and a replacement gate structure on a semiconductor substrate, the replacement gate structure including a replacement gate; depositing a first inter-layer dielectric layer; planarizing the first inter-layer dielectric layer to expose the replacement gate in the replacement gate structure; removing the replacement gate and depositing to form a metal gate; etching to form a first source/drain contact opening in the first inter-layer dielectric layer; sequentially depositing a liner and filling conductive metal in the first source/drain contact opening to form a first source/drain contact hole; depositing a second inter-layer dielectric layer on the first inter-layer dielectric layer; etching to form a second source/drain contact opening and a gate contact opening in the second inter-layer dielectric layer; and sequentially depositing a liner and filling conductive metal in the second source/drain contact opening and the gate contact opening to form a second source/drain contact hole and a gate contact hole. The present invention also proposes a semiconductor device manufactured by the above process. | 2011-03-17 |
20110062503 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of transistors on a semiconductor substrate; a first interlayer dielectric film on the transistors; a plurality of ferroelectric capacitors on the first interlayer dielectric film; a first hydrogen barrier film covering an upper surface and a side surface of each of the ferroelectric capacitors; a second interlayer dielectric film above the ferroelectric capacitors, the second interlayer dielectric film being buried to have a void or hole between two adjacent ferroelectric capacitors out of the ferroelectric capacitors; a cover dielectric film covering the second interlayer dielectric film to close an opening of the void or hole; and a second hydrogen barrier film covering the cover dielectric film. | 2011-03-17 |
20110062504 | SEMICONDUCTOR MEMORY DEVICE INCLUDING FERROELECTRIC CAPACITOR - An aspect of the present disclosure, there is provided semiconductor memory device including a ferroelectric capacitor and a field effect transistor as a memory cell, the ferroelectric capacitor including a lower electrode connected to one of the pair of the impurity diffusion layers, a bit line formed below the lower electrode, wherein each of the memory cells shares the bit line contact with an adjacent memory cell at one side in the first direction to connect to the bit line, and three of the word lines are formed between the bit line contacts in the first direction. | 2011-03-17 |
20110062505 | SEMICONDUCTOR DEVICE WITH CAPACITOR AND FUSE AND ITS MANUFACTURE - An upper electrode of a capacitor has a two-layer structure of first and second upper electrodes. A gate electrode of a MOS field effect transistor and a fuse are formed by patterning conductive layers used to form the lower electrode, first upper electrode and second upper electrode of the capacitor. In forming a capacitor and a fuse on a semiconductor substrate by a conventional method, at least three etching masks are selectively used to pattern respective layers to form the capacitor and fuse before wiring connection. The number of etching masks can be reduced in manufacturing a semiconductor device having capacitors, fuses and MOS field effect transistors so that the number of processes can be reduced and it becomes easy to improve the productivity and reduce the manufacture cost. | 2011-03-17 |
20110062506 | Metal Oxide Semiconductor Field Effect Transistor Integrating a Capacitor - A bypass capacitor is directly integrated on top of a MOSFET chip. The capacitor comprises multi layers of conductive material and dielectric material staking on top of each other with connection vias through dielectric layer for connecting different conductive layers. The method of integrating the bypass capacitor comprises repeating steps of depositing a dielectric layer, forming connection vias through the dielectric layer, depositing a conductive layer and patterning the conductive layer. | 2011-03-17 |
20110062507 | SEMICONDUCTOR DEVICE AND A METHOD OF FABRICATING THE SAME - A semiconductor device is provided. The semiconductor device includes a memory device, and the memory device includes a substrate, two stacked gates, two spacers, an insulating layer, and a dielectric layer. The stacked gates having a gap therebetween are located on the substrate. The spacers having a pipe or a seam therebetween are respectively located at sidewalls of each of the stacked gates in the gap. The pipe or the seam is filled with the insulating layer. The dielectric layer is located on the substrate and covers the insulating layer and the stacked gates. | 2011-03-17 |
20110062508 | SEMICONDUCTOR DEVICE INCLUDING RESISTOR AND METHOD OF FABRICATING THE SAME - Embodiments of a semiconductor device including a resistor and a method of fabricating the same are provided. The semiconductor device includes a mold pattern disposed on a semiconductor substrate to define a trench, a resistance pattern including a body region and first and second contact regions, wherein the body region covers the bottom and sidewalls of the trench, the first and second contact regions extend from the extending from the body region over upper surfaces of the mold pattern, respectively; and first and second lines contacting the first and second contact regions, respectively. | 2011-03-17 |
20110062509 | SEMICONDUCTOR DEVICE HAVING UPPER LAYER PORTION OF SEMICONDUCTOR SUBSTRATE DIVIDED INTO A PLURALITY OF ACTIVE AREAS - A semiconductor memory device includes: a semiconductor substrate; a plurality of element isolation insulators disposed in parts of an upper layer portion of the semiconductor substrate and dividing the upper layer portion into a plurality of active areas extended in one direction; tunnel insulating films provided on the active areas: charge storage members provided on the tunnel insulating films; and control gate electrodes provided on the charge storage members. A width of a middle portion of one of the active areas in the up-to-down direction being smaller than a width of a portion of the active areas upper of the middle portion and a width of a portion of the active areas below the middle portion. | 2011-03-17 |
20110062510 | 3D NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device having a string of a plurality of memory cells that are serially coupled, wherein the string of memory cells includes a plurality of second channels of a pillar type, a first channel coupling lower end portions of the plurality of the second channels with each other, and a plurality of control gate electrodes surrounding the plurality of the second channels. | 2011-03-17 |
20110062511 | DEVICE HAVING COMPLEX OXIDE NANODOTS - Devices are disclosed, such as those having a memory cell. The memory cell includes an active area formed of a semiconductor material; a first dielectric over the semiconductor material; a second dielectric comprising a material having a perovskite structure over the first dielectric; a third dielectric over the second dielectric; and a gate electrode over the third dielectric. | 2011-03-17 |
20110062512 | NONPLANAR DEVICE WITH THINNED LOWER BODY PORTION AND METHOD OF FABRICATION - A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode. | 2011-03-17 |
20110062513 | OVERLAPPING TRENCH GATE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An overlapping trench gate semiconductor device includes a semiconductor substrate, a plurality of shallow trenches disposed on the semiconductor substrate, a first conductive layer disposed in the shallow trenches, a plurality of deep trenches respectively disposed in each shallow trench, a second conductive layer disposed in the deep trenches, a source metal layer and a gate metal layer. Each of the deep trenches extends into the semiconductor substrate under each shallow trench. The source metal layer is electrically connected to the second conductive layer, and the gate metal layer is electrically connected to the first conductive layer. | 2011-03-17 |
20110062514 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first semiconductor element portion for switching a first current includes a first channel surface having a first plane orientation. A first region of a semiconductor layer includes a first trench having the first channel surface. A first gate insulating film covers the first channel surface with a first thickness. A second semiconductor element portion for switching a second current smaller than the first current includes a second channel surface having a second plane orientation different from the first plane orientation. A second region of the semiconductor layer includes a second trench having the second channel surface. A second gate insulating film covers the second channel surface with a second thickness larger than the first thickness. | 2011-03-17 |
20110062515 | SEMICONDUCTOR DEVICE - A first gate electrode surrounding the periphery of the first gate insulating film, a second gate insulating film surrounding the periphery of the first gate electrode, a first columnar silicon layer surrounding the periphery of the second gate insulating film, a first upper part high concentration semiconductor layer of the first conductivity type formed in the upper part of the first island-shaped silicon layer, a second lower part high concentration semiconductor layer of the first conductivity type formed in the lower part of the first island-shaped silicon layer, a first upper part high concentration semiconductor layer of the second conductivity type formed in the upper part of the first columnar silicon layer, and a second lower part high concentration semiconductor layer of the second conductivity type formed in the lower part of the first columnar silicon layer. | 2011-03-17 |
20110062516 | Semiconductor device - Provided is a LOCOS offset MOS field-effect transistor in which a first lightly-doped N-type drain offset region with a LOCOS oxide film and a second lightly-doped N-type drain offset region without a LOCOS oxide film are formed in a drain-side offset region, and both the regions are covered with a gate electrode. Provision of the first lightly-doped N-type drain offset region mitigates an electric field applied to the first lightly-doped N-type drain offset region to increase a breakdown voltage. Provision of the second lightly-doped N-type drain offset region increases carriers within the second lightly-doped N-type drain offset region to obtain a high current drivability. | 2011-03-17 |
20110062517 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes: a semiconductor substrate of a first conductivity type; a source region; a drain region of a second conductivity type; a gate electrode formed via a gate insulating film on the semiconductor substrate between the source region and the drain region; and a drift region of the second conductivity type formed adjacent to the drain region from the drain region to a lower part of the gate electrode. The upper surface of the gate electrode is formed such that the height of a side on the source region side of a stack of the gate electrode and the gate insulating film is larger than the height of a side on the drain region side of the stack. | 2011-03-17 |
20110062518 | finFETS AND METHODS OF MAKING SAME - A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates. | 2011-03-17 |
20110062519 | FABRICATION OF SEMICONDUCTORS WITH HIGH-K/METAL GATE ELECTRODES - Semiconductor devices with high-K/metal gates are formed with spacers that are substantially resistant to subsequent etching to remove an overlying spacer, thereby avoiding replacement and increasing manufacturing throughput. Embodiments include forming a high-K/metal gate, having an upper surface and side surfaces, over a substrate, e.g., a SOI substrate, and sequentially forming, on the side surfaces of the high-K/metal gate, a first spacer of a non-oxide material, a second spacer, of a material different from that of the first spacer, and a third spacer, of a material different from that of the second spacer. After formation of source and drain regions, e.g., epitaxially grown silicon-germanium, the third spacer is etched with an etchant, such as hot phosphoric acid, to which the second spacer is substantially resistant, thereby avoiding replacement. | 2011-03-17 |
20110062520 | METHOD FOR FABRICATING TRANSISTOR WITH THINNED CHANNEL - A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process. | 2011-03-17 |
20110062521 | SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention comprises a first transistor and a second transistor, and functions as an inverter. The first transistor includes an island semiconductor layer, a first gate insulating film surrounding the periphery of the island semiconductor layer, a gate electrode surrounding the periphery of the first gate insulating film, p+-type semiconductor layers formed in the upper and lower part of the island semiconductor layer, respectively. The second transistor includes the gate electrode, a second gate insulating film surrounding a part of the periphery of the gate electrode, an arcuate semiconductor layer contacting a part of the periphery of the second gate insulating film, n+-type semiconductor layers formed in the upper and lower part of the arcuate semiconductor layer, respectively. A first contact electrically connects the p+-type semiconductor layer in the first transistor and the n+-type semiconductor layer in the second transistor. | 2011-03-17 |
20110062522 | SEMICONDUCTOR DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION - Provided is a semiconductor device for electrostatic discharge protection capable of protecting an inner circuit from both noises of an overcurrent noise of an ESD and an overcurrent noise of a latch-up test while achieving size reduction, by sharing a guard ring formed in a periphery of an ESD protection element with a cathode of a latch-up protection diode for protecting the inner circuit from the overcurrent noise of the latch-up test. | 2011-03-17 |
20110062523 | SEMICONDUCTOR MEMORY DEVICE AND PRODUCTION METHOD THEREOF - In a static memory cell composed of four MOS transistors, the transistors composing a memory cell are formed on a substrate and have a drain, gate, and source arranged vertically with the gate surrounding a columnar semiconductor layer. In this memory cell, the first diffusion layers (second diffusion layers) functioning as a first memory node (second memory node) are connected via a first silicide layer (second silicide layer) formed on their surfaces, whereby an SRAM cell having a small area is realized. Furthermore, a first anti-leak diffusion layer (second anti-leak diffusion layer) having the conductivity type opposite to the first well is formed between the first well and the first diffusion layer (second diffusion layer) having the same conductivity type as the first well so as to prevent leak to the substrate. | 2011-03-17 |
20110062524 | GATE STRUCTURES OF CMOS DEVICE AND METHOD FOR MANUFACTURING THE SAME - Gate structures of CMOS device and the method for manufacturing the same are provided. A substrate having an NMOS region, a PMOS region, and a work function modulation layer disposed on the NMOS region and the PMOS region is provided. A nitrogen doping process is performed to dope nitrogen into a portion of the work function modulation layer disposed on the PMOS region so as to form an N-rich work function modulation layer disposed on the PMOS region. A nonmetallic conductive layer is formed blanketly covering the work function modulation layer and the N-rich work function modulation layer. A portion of the nonmetallic conductive layer, the work function modulation layer, and the N-rich work function modulation layer is removed to form a first gate in the NMOS region and a second gate in the PMOS region. | 2011-03-17 |
20110062525 | METHOD AND STRUCTURE FOR DIFFERENTIAL SILICIDE AND RECESSED OR RAISED SOURCE/DRAIN TO IMPROVE FIELD EFFECT TRANSISTOR - A method forms an integrated circuit structure. The method patterns a protective layer over a first-type field effect transistor and removes a stress liner from above a second-type field effect transistors. Then, the method removes a first-type silicide layer from source and drain regions of the second-type field effect transistor, but leaves at least a portion of the first-type silicide layer on the gate conductor of the second-type field effect transistor. The method forms a second-type silicide layer on the gate conductor and the source and drain regions of the second-type field effect transistor. The second-type silicide layer that is formed is different than the first-type silicide layer. For example, the first-type silicide layer and the second-type silicide layer can comprise different materials, different thicknesses, different crystal orientations, and/or different chemical phases, etc. | 2011-03-17 |
20110062526 | METAL GATE TRANSISTOR, INTEGRATED CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer. | 2011-03-17 |
20110062527 | SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SAME - In one embodiment, a semiconductor apparatus is disclosed. The apparatus includes: an element-isolation insulating film formed on a major surface of a semiconductor layer, the element-isolation insulating film having a first opening and a second opening; an n-type MOSFET provided in the first opening; and a p-type MOSFET provided in the first opening. An upper face of a portion of the element-isolation insulating film adjacent to a source/drain region of the n-type MOSFET is positioned below an upper face of the source/drain region of the n-type MOSFET. An upper face of a portion of the element-isolation insulating film adjacent to a source/drain region of the p-type MOSFET is positioned above an upper face of the source/drain region of the p-type MOSFET. | 2011-03-17 |
20110062528 | Semiconductor device and semiconductor device manufacturing method - A semiconductor device includes a semiconductor substrate; a gate insulation film formed on the semiconductor substrate; a silicide gate electrode of an n-type MISFET formed on the gate insulation film; and a silicide gate electrode of a p-type MISFET formed on the gate insulation film and having a thickness smaller than that of the silicide gate electrode of the n-type MISFET, the silicide gate electrode of the p-type MISFET having a ratio of metal content higher than that of the silicide gate electrode of the n-type MISFET. | 2011-03-17 |
20110062529 | SEMICONDUCTOR MEMORY DEVICE - In a static memory cell configured using four MOS transistors and two load resistance elements, the MOS transistors are formed on diffusion layers formed on a substrate. The diffusion layers serve as memory nodes. The drain, gate and source of the MOS transistors are arranged in the direction orthogonal to the substrate, and the gate surrounds a columnar semiconductor layer. In addition, the load resistance elements are formed by contact plugs. In this way, it is possible to form a SRAM cell with a small area. | 2011-03-17 |
20110062530 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a semiconductor substrate; an interface layer formed on the semiconductor substrate; a high-k gate dielectric film formed on the interface layer; and a gate electrode formed on the high-k gate dielectric film. The high-k gate dielectric film contains La. The high-k gate dielectric film has the higher La concentration in an interface with the gate electrode than in an interface with the interface layer. | 2011-03-17 |
20110062531 | SENSOR ARRAY AND A METHOD OF MANUFACTURING THE SAME - A sensor array ( | 2011-03-17 |
20110062532 | MEMS Chip And Package Method Thereof - The present invention proposes a MEMS chip and a package method thereof. The package method comprises; making a capping wafer by: providing a first substrate and forming an etch stop layer on the first substrate; making a device wafer by: providing a second substrate and forming a MEMS device and a material layer surrounding the MEMS device on the second substrate; bonding the capping wafer and the device wafer; after bonding, etching the first substrate to form at least one via; etching the etch stop layer through the via; etch the material layer; and forming a sealing layer on the first substrate. | 2011-03-17 |
20110062533 | Device package substrate and method of manufacturing the same - A device package substrate includes: a substrate having a cavity formed on a top surface thereof, the cavity having a chip mounting region; a first interconnection layer formed to extend to the inside of the cavity; a second interconnection layer formed to be spaced apart from the first interconnection layer; a chip positioned in the chip mounting region so as to be connected to the first and second interconnection layers; an insulating layer formed to cover the first and second interconnection layers and the chip and having a contact hole exposing a part of the second interconnection layer; and a bump pad formed in the contact hole so as to be connected to external elements. | 2011-03-17 |
20110062534 | ELECTRONIC COMPONENT - An electronic component includes: a first substrate having a through-hole; a second substrate opposite the first substrate; a sealing member surrounding a sealing space formed between the first substrate and the second substrate; a functional element having at least a part thereof disposed in the sealing space, and a through-electrode filling the through-hole, the through-hole penetrating the first substrate. The sealing member includes an elastic core part on the first substrate. A metal film is on a surface of the core part and is bonded to the second substrate. | 2011-03-17 |
20110062535 | MEMS TRANSDUCERS - A MEMS device comprises a substrate having at least a first transducer optimized for transmitting pressure waves, and at least a second transducer optimized for detecting pressure waves. The transducers can be optimised for transmitting or receiving by varying the diameter, thickness or mass of the membrane and/or electrode of each respective transducer. Various embodiments are described showing arrays of transducers, with different configurations of transmitting and receiving transducers. Embodiments are also disclosed having an array of transmitting transducers and an array of receiving transducers, wherein elements in the array of transmitting and/or receiving transducers are arranged to have different resonant frequencies. At least one of said first and second transducers may comprise an internal cavity that is sealed from the outside of the transducer. | 2011-03-17 |
20110062536 | Design and fabrication methods of partial cladded write line to enhance write margin for magnetic random access memory - A cladding structure for a conductive line used to switch a free layer in a MTJ is disclosed and includes two cladding sidewalls on two sides of the conductive line, a top cladding portion on a side of the conductive line facing away from the MTJ, and a highly conductive, non-magnetic spacing control layer formed between the MTJ and conductive line. The spacing control layer has a thickness of 0.02 to 0.12 microns to maintain the distance separating free layer and conductive line between 0.03 and 0.15 microns. The spacing control layer is aligned parallel to the conductive line and contacts a plurality of MTJ elements in a row of MRAM cells. Half-select error problems are avoided while maintaining high write efficiency. A spacing control layer may be formed between a word line and a bottom electrode in a top pinned layer or dual pinned layer configuration. | 2011-03-17 |
20110062537 | Magnetic Memory Devices - A magnetic memory device may include a first vertical magnetic layer, a non-magnetic layer on the first vertical magnetic layer, and a first junction magnetic layer on the non-magnetic layer, with the non-magnetic layer being between the first vertical magnetic layer and the first junction magnetic layer. A tunnel barrier may be on the first junction magnetic layer, with the first junction magnetic layer being between the non-magnetic layer and the tunnel barrier. A second junction magnetic layer may be on the tunnel barrier with the tunnel barrier being between the first and second junction magnetic layers, and a second vertical magnetic layer may be on the second junction magnetic layer with the second junction magnetic layer being between the tunnel barrier and the second vertical magnetic layer. | 2011-03-17 |
20110062538 | MAGNETIC ELEMENT HAVING REDUCED CURRENT DENSITY - A memory device includes a fixed magnetic layer, a tunnel barrier layer over the fixed magnetic layer, and a free magnetic structure formed over the tunnel barrier layer, wherein the free magnetic structure has layers or sub-layers that are weakly magnetically coupled. Thus, a low programming voltage can be used to avoid tunnel barrier breakdown, and a small pass transistor can be used to save die real estate. | 2011-03-17 |
20110062539 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a semiconductor device in which the deterioration of the rewrite property is suppressed. In a memory cell region, magnetoresistive elements in a semiconductor magnetic-storage device are formed in an array shape in a mode that the magnetoresistive elements are arranged at portions where digit lines extending in one direction intersect bit lines extending in the direction approximately orthogonal to the digit lines. The digit line and the bit line have such a wiring structure constituted by covering a copper film to be a wiring main body with a cladding layer. One end side of the magnetoresistive element is electrically coupled to the bit line via a top via formed from a non-magnetic material. | 2011-03-17 |
20110062540 | SOLID-STATE IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a solid-state image sensor includes a semiconductor substrate including a first surface on which light enters, and a second surface opposite to the first surface, a pixel region formed in the semiconductor substrate, and including a photoelectric conversion element which converts the incident light into an electrical signal, a peripheral region formed in the semiconductor substrate, and including a circuit which controls an operation of the element in the pixel region, a plurality of interconnects which are formed in a plurality of interlayer insulating films stacked on the second surface, and are connected to the circuit, and a support substrate formed on the stacked interlayer insulating films and the interconnects. An uppermost one of the interconnects formed in an uppermost one of the interlayer insulating films is buried in a first trench formed in the uppermost interlayer insulating film. | 2011-03-17 |
20110062541 | HIGH MOLECULAR EXTINCTION COEFFICIENT METAL DYES - The present invention relates to novel compounds that are useful as ligands in organometallic dyes. More particularly, the invention relates to dyes comprising the compounds, said dyes being sensitizing dyes useful in solar cell technology. According to an embodiment, the present invention discloses new ruthenium dyes and their application in dye-sensitized solar cells (DSC). The referred ruthenium dyes with new structural features can be easily synthesized, show more than 85% light-to-electricity conversion efficiency and a higher than 9% cell efficiency. | 2011-03-17 |
20110062542 | STRUCTURES, DESIGN STRUCTURES AND METHODS OF FABRICATING GLOBAL SHUTTER PIXEL SENSOR CELLS - Pixel sensor cells, method of fabricating pixel sensor cells and design structure for pixel sensor cells. The pixel sensor cells including: a photodiode body in a first region of a semiconductor layer; a floating diffusion node in a second region of the semiconductor layer, a third region of the semiconductor layer between and abutting the first and second regions; and dielectric isolation in the semiconductor layer, the dielectric isolation surrounding the first, second and third regions, the dielectric isolation abutting the first, second and third regions and the photodiode body, the dielectric isolation not abutting the floating diffusion node, portions of the second region intervening between the dielectric isolation and the floating diffusion node. | 2011-03-17 |
20110062543 | SEMICONDUCTOR DEVICE - The present invention provides a photoelectric conversion device capable of detecting light from weak light to strong light and relates to a photoelectric conversion device having a photodiode having a photoelectric conversion layer; an amplifier circuit including a transistor; and a switch, where the photodiode and the amplifier circuit are electrically connected to each other by the switch when intensity of entering light is lower than predetermined intensity so that a photoelectric current is amplified by the amplifier circuit to be outputted, and the photodiode and part or all of the amplifier circuits are electrically disconnected by the switch so that a photoelectric current is reduced in an amplification factor to be outputted. According to such a photoelectric conversion device, light from weak light to strong light can be detected. | 2011-03-17 |
20110062544 | OPTICAL SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An optical semiconductor device is provided with a low concentration p-type silicon substrate ( | 2011-03-17 |
20110062545 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - A semiconductor device in accordance with the present invention includes a diode | 2011-03-17 |
20110062546 | STRUCTURE AND METHOD TO MINIMIZE REGROWTH AND WORK FUNCTION SHIFT IN HIGH-K GATE STACKS - The present invention provides a semiconductor structure comprising high-k material portions that are self-aligned with respect to the active areas in the semiconductor substrate and a method of fabricating the same. The high-k material is protected from oxidation during the fabrication of the semiconductor structure and regrowth of the high-k material and shifting of the high-k material work function is prevented. | 2011-03-17 |
20110062547 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film. | 2011-03-17 |
20110062548 | BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC SELF-ALIGNED BASE USING SELECTIVE EPITAXIAL GROWTH FOR BICMOS INTEGRATION - High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces. | 2011-03-17 |
20110062549 | Semiconductor Device and Method of Forming Integrated Passive Device - An IPD semiconductor device has a capacitor formed over and electrically connected to a semiconductor die. An encapsulant is deposited over the capacitor and around the semiconductor die. A first interconnect structure is formed over a first surface of the encapsulant by forming a first conductive layer, forming a first insulating layer over the first conductive layer, and forming a second conductive layer over the first insulating layer. The second conductive layer has a portion formed over the encapsulant at least 50 micrometer away from a footprint of the semiconductor die and wound to operate as an inductor. The portion of the second conductive layer is electrically connected to the capacitor by the first conductive layer. A second interconnect structure is formed over a second surface of the encapsulant. A conductive pillar is formed within the encapsulant between the first and second interconnect structures. | 2011-03-17 |
20110062550 | HYDROGEN BARRIER FOR FERROELECTRIC CAPACITORS - An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate. | 2011-03-17 |
20110062551 | MULTILAYER OXIDE ON NITRIDE ON OXIDE STRUCTURE AND METHOD FOR THE MANUFACTURE OF SEMICONDUCTOR DEVICES - An integrated circuit device having a capacitor structure and methods of manufacture are disclosed. The device has a substrate, e.g., silicon wafer, silicon on insulator, epitaxial wafer. The device has a dielectric layer overlying the substrate and a polysilicon layer overlying the dielectric layer. The device has a tungsten silicide layer overlying the polysilicon layer and a first oxide layer overlying the tungsten silicide layer. A nitride layer overlies the oxide layer. A second oxide layer is overlying the nitride layer to form a sandwiched oxide on nitride on oxide structure to form a capacitor dielectric. The device also has an upper capacitor plate formed overlying the second oxide layer. | 2011-03-17 |
20110062552 | SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to a first electrode upwardly extending, and a second electrode upwardly extending along the first electrode. The first electrode includes a lower portion and an upper portion. The second electrode covers a bottom surface and an outer side surface of the lower portion of the first electrode. The upper portion of the first electrode is positioned higher than the second electrode. | 2011-03-17 |
20110062553 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - The semiconductor device ( | 2011-03-17 |
20110062554 | HIGH VOLTAGE FLOATING WELL IN A SILICON DIE - In one embodiment, a graded n-doped region surrounding a well, and a spiral resistor connected to the well and to a p-doped region surrounding the graded n-doped region. | 2011-03-17 |
20110062555 | SEMICONDUCTOR STRUCTURE HAVING VARACTOR WITH PARALLEL DC PATH ADJACENT THERETO - A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region. | 2011-03-17 |
20110062556 | COMPOUND SEMICONDUCTOR SUBSTRATE - A compound semiconductor substrate which inhibits the generation of a crack or a warp and is preferable for a normally-off type high breakdown voltage device, arranged that a multilayer buffer layer | 2011-03-17 |
20110062557 | 3D POLYSILICON DIODE WITH LOW CONTACT RESISTANCE AND METHOD FOR FORMING SAME - A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array. | 2011-03-17 |
20110062558 | SEMICONDUCTOR WAFER FOR SEMICONDUCTOR COMPONENTS AND PRODUCTION METHOD - A semiconductor wafer for semiconductor components and to a method for its production is disclosed. In one embodiment, the semiconductor wafer includes a front side with an adjoining near-surface active zone as basic material for semiconductor component structures. The rear side of the semiconductor wafer is adjoined by a getter zone for gettering impurity atoms in the semiconductor wafer. The getter zone contains oxygen precipitates. In the near-surface active zone, atoms of doping material are located on lattice vacancies. The atoms of doping material have a higher diffusion coefficient that the oxygen atoms. | 2011-03-17 |
20110062559 | PLANARIZATION STOP LAYER IN PHASE CHANGE MEMORY INTEGRATION - A key hole structure and method for forming a key hole structure to form a pore in a memory cell. The method includes forming a first dielectric layer on a semiconductor substrate having an electrode formed therein, forming an isolation layer on the first dielectric layer, forming a second dielectric layer on the isolation layer, and forming a planarization stop layer on the second dielectric layer. The method further includes forming a via to extend to the first dielectric layer and recessing the isolation layer and the stop layer with respect to the second dielectric layer, depositing a conformal film within via and over the stop layer, forming a key hole within the conformal film at a center region of the via such that a tip of the key hole is disposed at an upper surface of the second dielectric layer, and planarizing the conformal film to the stop layer. | 2011-03-17 |
20110062560 | BPSG FILM DEPOSITION WITH UNDOPED CAPPING - Semiconductor devices containing a CVD BPSG layer and an undoped CVD oxide cap layer are described. The cap layer can be any silicon oxide material with a thickness between about 50 Å and about 350 Å. The cap layer may be formed using a low temperature CVD process that is controlled for density by adjusting the amount of silicon precursor in the gas-phase. In some embodiments, the cap layer is deposited on the BPSG layer followed immediately by the BPSG film deposition prior to any annealing of the BPSG layer. The cap layer may prevent dopant out-diffusion and/or out-gassing during storage and high-temperature annealing, and moisture penetration into the BPSG layer, as well as suppress defect nucleation on the as-deposited BPSG surface and defect formation during high temperature annealing, while still allowing flow ability of the BPSG layer. Other embodiments are also described. | 2011-03-17 |
20110062561 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device comprising: forming a p type region and an n type region in a main surface of a semiconductor substrate, the p type region and the n type region being insulated from each other with an element-isolation region; forming a first insulating film on the p type region and on the n type region, the first insulating film being made of any one of a silicon oxide film and a silicon oxynitride film; forming a lanthanum oxide film on the first insulating film on the p type region; forming a second insulating film both on the lanthanum oxide film on the p type region and on the first insulating film on the n type region, the second insulating film containing any one of hafnium and zirconium; and forming a titanium nitride film on the second insulating film, the titanium nitride film satisfying Ti | 2011-03-17 |
20110062562 | DIELECTRIC LAYER STRUCTURE - A dielectric layer structure includes an interlayer dielectric (ILD) layer covering at least a metal interconnect structure and a single tensile hydrophobic film. The ILD layer further includes a low-k dielectric layer, and the single tensile hydrophobic film is positioned on the low-k dielectric layer for counteracting at least a part of a stress of the low-k dielectric layer. | 2011-03-17 |
20110062563 | NON-VOLATILE MEMORY WITH REDUCED MOBILE ION DIFFUSION - Mobile ion diffusion causes a shift in the threshold voltage of non-volatile storage elements in a memory chip, such as during an assembly process of the memory chip. To reduce or avoid such shifts, a coating can be applied to a printed circuit board substrate or a leader frame to which the memory chip is surface mounted. An acrylic resin coating having a thickness of about 10 μm may be used. A memory chip is attached to the coating using an adhesive film. Stacked chips may be used as well. Another approach provides metal barrier traces over copper traces of the printed circuit board, within a solder mask layer. The metal barrier traces are fabricated in the same pattern as the copper traces but are wider so that they at least partially envelop and surround the copper traces. Corresponding apparatuses and fabrication processes are provided. | 2011-03-17 |
20110062564 | SEMICONDUCTOR DIE CONTAINING LATERAL EDGE SHAPES AND TEXTURES - Methods for singulating a semiconductor wafer into a plurality of individual dies that contain lateral edges or sidewalls and the semiconductor dies formed from these methods are described. The dies are formed from methods that use a front to back photolithography alignment process to form a photo-resist mask and an anisoptropic wet etch in an HNA and/or a TMAH solution on the backside of the wafer through the photoresist mask to form sloped sidewalls and/or textures. The conditions of the TMAH etching process can be controlled to form any desired combination of rough or smooth sidewalls. Thus, the dies formed have a Si front side with an area larger than the Si backside area and sidewalls or lateral edges that are not perpendicular to the front or back surface of the die. Other embodiments are also described. | 2011-03-17 |
20110062565 | METHOD FOR MANUFACTURING A MICROELECTRONIC PACKAGE COMPRISING AT LEAST ONE MICROELECTRONIC DEVICE - A method for manufacturing a microelectronic package ( | 2011-03-17 |
20110062566 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS - A semiconductor device comprising: a substrate; a terminal on the substrate's first surface; a first electrode on the first surface connected to the terminal; an electronic element on the substrate's second surface; a second electrode connected to the electronic element; a groove on the second surface leading to the second electrode; a conductive portion inside the grove connected to the second electrode's rear face; a first wiring on the first surface connected to the first electrode; a second wiring connecting the first wiring and the terminal; a stress-absorbing layer between the substrate and terminal; a land connecting the first wiring and the second wiring, the land opening a part of the stress-absorbing layer and exposing the first wiring, the land being in a region surrounded by terminals, and the land being along a straight line connecting the centers of diagonal terminals, with the region between the terminals. | 2011-03-17 |
20110062567 | LEADFRAME AND CHIP PACKAGE - A leadframe including a die pad, leads, an outer frame, connecting bars and grounding bars is provided. Each of the grounding bars is suspended between two connecting bars by being connected with branches of the two connecting bars, such that the grounding bars are spaced by the die pad. The leadframe and the chip package of the present invention can permit a great design variation. | 2011-03-17 |
20110062568 | FOLDED LANDS AND VIAS FOR MULTICHIP SEMICONDUCTOR PACKAGES - Semiconductor packages and methods for making and using the same are described. The semiconductor packages contain a lead frame that has been folded to create folded leads that form a customized array of land pads and vias. The lead frame contains both longer folded lead and shorter folded leads. The longer leads can be folded so that an upper part of the longer leads form vias, the lower part forms part of a land pad array, and a substantially flat part that is connected to a first die containing an IC. The shorter leads can be folded so that a lower part forms part of a land pad array and the short leads are connected to a second die containing in IC. The folded leads can be routed according to the requirements of each specific IC die to which they are connected and therefore can support multiple dies in the semiconductor package. Other embodiments are also described. | 2011-03-17 |
20110062569 | SEMICONDUCTOR DEVICE PACKAGE WITH DOWN-SET LEADS - A QFP type packaged device includes down-set leads to allow for more I/O's and a smaller foot print. The device includes a die attached to a flag of a lead frame. Die pads are electrically connected to leads of the lead frame with wires. The leads are bent and include indentations so that they are exposed at the bottom side of the package. The leads are also trimmed so that they do not extend out of the sides of the packaged device. | 2011-03-17 |
20110062570 | ISOLATED STACKED DIE SEMICONDUCTOR PACKAGES - Semiconductor packages that contain isolated, stacked dies and methods for making such devices are described. The semiconductor package contains both a first die with a first integrated circuit and a second die with a second integrated circuit that is stacked onto the first die while also being isolated from the first die. The first and second dies are connected using an array of metal connectors containing both a base segment and a beam segment extending over the first die and supporting the second die. This configuration can provide a thinner semiconductor package since wire-bonding is not used. As well, since the integrated circuit devices in the first and second dies are isolated from each other, local heating and/or hot spots are diminished or prevented in the semiconductor package. Other embodiments are also described. | 2011-03-17 |
20110062571 | OPTICAL DEVICE, INTEGRATED CIRCUIT DEVICE AND SYSTEM - An optical device for an integrated circuit device, includes a laminated substrate having a through-passage and a tubular frame in which an optical lens is mounted, the tubular frame having an end part inserted or integrated in the through-passage of the laminated substrate. A integrated circuit device includes an optical device and an integrated circuit die carried by the laminated substrate and having an active optical area placed in front of the optical lens. | 2011-03-17 |
20110062572 | SELF-ALIGNED SILICON CARRIER FOR OPTICAL DEVICE SUPPORTING WAFER SCALE METHODS - Disclosed is a carrier assembly for and a method of manufacturing an optical device. The method comprises providing a silicon substrate; attaching a number of optical dies on the silicon substrate to form an optical device carrier assembly; providing a corresponding number of through holes in the silicon substrate to permit the passage of light therethrough and further providing guide holes in the silicon substrate to present means for passive alignment of an external optical connection; and dicing the optical device carrier assembly to form individual optical devices. Preferably, the step of attaching a number of optical dies comprises using self-alignment of solder bumps using gaseous flux, the through holes are dry etched into the silicon substrate, and/or the volume between the optical die and silicon substrate is filled with a transparent polymer. Preferably, the transparent polymer is silicone rubber or epoxy. Preferably, the optical dies have a polymer mass to assist the heat transfer to the silicon substrate. | 2011-03-17 |