11th week of 2013 patent applcation highlights part 27 |
Patent application number | Title | Published |
20130063964 | Illumination Apparatus with High Conversion Efficiency and Methods of Forming the Same - In various embodiments, an illumination apparatus includes a substantially planar waveguide or a light box, at least one light source emitting light therein, a layer of photoluminescent material for converting a portion of the light to a different wavelength, a reflector for reflecting light back-scattered from the photoluminescent material, and an optically active layer for separating light interacting with the photoluminescent material from light propagating within the waveguide or light box. | 2013-03-14 |
20130063965 | LIGHT GUIDE PLATE AND BACKLIGHT MODULE - A light guide plate is disclosed which comprises a bottom surface and a reflective layer. The bottom surface is formed with a plurality of mesh points, and a density of the mesh points increases with a distance from a light source. The reflective layer is a sputtered film formed on the bottom surface. A corresponding backlight module is further disclosed. The light guide plate and other components of the backlight module can be pushed into the backplate from a side, so they are easy to be assembled, thus improving the yield of the backlight module. | 2013-03-14 |
20130063966 | SADDLE-RIDING TYPE VEHICLE AND LIGHT GUIDE USED IN SAME - A position light and light guide that serve as a light source are disposed on a front cover. The light guide extends in a width direction and receives and reflects light from the position light that is emitted in the width direction of the chassis. The light guide has first and second emission faces. The first emission face emits a first portion of the reflected light and faces upward or downward. The second emission face emits a second portion of the reflected light and faces forward. A length of the light guide in a front and back direction and a length of the light guide in a normal direction of the first emission face that is normal to the first emission face are both shorter than a length of the light guide in the width direction. | 2013-03-14 |
20130063967 | REFLECTIVE TOUCH DISPLAY AND FABRICATION METHOD THEREOF - The present disclosure relates to a display device, and more particularly to a reflective touch display and a fabrication method thereof The reflective touch display comprises a reflective display device, a first bonding layer, a light guiding plate, a second bonding layer, and a touch screen. The light guiding plate is laminated to top surface of the reflective display through the first bonding layer. The touch screen is laminated to top surface of the light guiding plate through the second bonding layer. The first bonding layer and the second bonding layer are formed by a liquid bonding material that transforms from a liquid state to a solid state, wherein refraction index of each of the first and second bonding layer is less than that of the light guiding plate. In accordance with the present disclosure, yield rate can be increased and production cost can be reduced. | 2013-03-14 |
20130063968 | PLANAR FRONT ILLUMINATION SYSTEM HAVING A LIGHT GUIDE WITH MICRO SCATTERING FEATURES FORMED THEREON AND METHOD OF MANUFACTURING THE SAME - A system for illuminating a reflective display or other material from a planar front device and a method of manufacture thereof. The system includes a light guide plate that conducts light from an edge light source across the face of a reflective display. Micro scattering features are formed on an outer surface of the light guide, farthest from the reflective display or material. A stepped index layer is formed on the surface of light guide plate containing the micro scattering features. The stepped index layer has an index of refraction lower than an index of refraction of the light guide plate to assist in the total internal reflection of light injected into the light guide plate. The micro scattering features, light reflecting areas, redirect luminous flux toward the display. In one embodiment, the micro scattering features are formed as white dots on the light guide plate. A black absorbing layer can be added to each white scattering dot in order to improve the apparent contrast when the front light is deactivated. | 2013-03-14 |
20130063969 | PLANAR FRONT ILLUMINATION SYSTEM HAVING A LIGHT GUIDE WITH MICRO LENSES FORMED THEREON AND METHOD OF MANUFACTURING THE SAME - A system for illuminating a reflective display or other material from a planar front device and a method of manufacture thereof. The system includes a light guide plate that conducts light from an edge light source across the face of a reflective display. Micro lenses are formed on the inner or outer surface of the light guide and direct the light conducted in the light guide toward the display. A stepped index layer is formed on the surface of light guide plate containing the micro lenses. The stepped index layer has an index of refraction lower than an index of refraction of the light guide plate to assist in the total internal reflection of light injected into the light guide plate. A top layer protective coat or touch screen can be laminated to the outside of the light guide plate. | 2013-03-14 |
20130063970 | MULTI-SECTIONED, BILLBOARD-MOUNTED LIGHT-EMITTING DEVICE - The present invention relates to a multi-sectioned, billboard-mounted light-emitting device comprising: a mounting frame onto which one or a plurality of partition pieces are joined by being slotted in a detachable fashion, and on the front of which are formed a plurality of billboard housing space parts; a light-emitting-diode module in which a plurality of LEDs are provided at predetermined intervals; a light-guide plate which surface emits due to the LEDs; a back-surface plate devised such that the light generated from the light-guide plate is emitted towards the front surface; and a billboard plate which is provided on the front surface of the light-guide plate while being received in a detachable fashion at a size matched to each of the billboard housing space parts which are section bared by means of the partition pieces. | 2013-03-14 |
20130063971 | BACKLIGHT MODULE - A backlight module includes a light guide plate, a first light source device, and a second light source device. The first light source device is disposed adjacent to a first side surface of the light guide plate and has at least one first polarized light source for emitting a first polarized light beam. The second light source device is disposed adjacent to a second side surface of the light guide plate and has at least one second polarized light source for emitting a second polarized light beam. The light guide plate includes a first polarized light transmitting region adjacent to the second light source device and a second polarized light transmitting region adjacent to the first light source device. | 2013-03-14 |
20130063972 | Microperforation Illumination - Methods and aparatuses disclosed herein relate to backlit visual display elements. A visual display element may include a base layer defining one or more microperforations and a light guide coupled to a light source. The light guide may be positioned adjacent the base layer and include one or more microlenses in alignment with the one or more microperforations along at least one vertical axis. | 2013-03-14 |
20130063973 | LIGHTING FIXTURES HAVING OBSERVABLE ILLUMINATED SPECKLED PATTERN - A lighting fixture includes at least one optic and at least one coherent light source for directing at least one substantially coherent light beam towards the at least one optic. Light provided from the at least one optic comprises an observable illuminated speckle patterned surface resulting from the coherent light beam. | 2013-03-14 |
20130063974 | ASYMMETRIC SERRATED EDGE LIGHT GUIDE FILM HAVING CIRCULAR BASE SEGMENTS - The present invention provides a planar light guide film for a backlight unit having at least one point light source, the light guide film comprising a light input surface for receiving light from the point light source, a light redirecting surface for redirecting light received from the light input surface and a light output surface for outputting at least the light redirected from the light redirecting surface. The light input surface further comprises a composite lens structure having a first and second circular tip segment each circular tip segment with a first contact angle, and a first and second circular base segment each circular base segment with a top and bottom contact angle, the contact angles of the circular base segments being greater than the contact angle of the circular tip segments. Further, the circular tip segments satisfies the following equations: | 2013-03-14 |
20130063975 | ASYMMETRIC SERRATED EDGE LIGHT GUIDE FILM HAVING ELLIPTICAL BASE SEGMENTS - The present invention provides a planar light guide film for a backlight unit having at least one point light source, the light guide film comprising a light input surface for receiving light from the point light source, a light redirecting surface for redirecting light received from the light input surface and a light output surface for outputting at least the light redirected from the light redirecting surface. The light input surface further comprises a composite lens structure having a circular tip segment with a first contact angle, and a first and second elliptical base segments with a second contact angle, the second contact angle being greater than the first contact angle and the second contact angle being equal to each other and wherein the first and second circular tip segments satisfy the following equations respectively: | 2013-03-14 |
20130063976 | ASYMMETRIC SERRATED EDGE LIGHT GUIDE FILM HAVING CIRCULAR BASE SEGMENTS - The present invention provides a planar light guide film for a backlight unit having at least one point light source, the light guide film comprising a light input surface for receiving light from the point light source, a light redirecting surface for redirecting light received from the light input surface and a light output surface for outputting at least the light redirected from the light redirecting surface. The light input surface further comprises a composite lens structure having a first and second circular tip segment each circular tip segment with a first contact angle, and a first and second circular base segment each circular base segment with a top and bottom contact angle, the contact angles of the circular base segments being less than the contact angle of the circular tip segments. Further, the circular tip segment satisfies the following equations: | 2013-03-14 |
20130063977 | ASYMMETRIC SERRATED EDGE LIGHT GUIDE FILM HAVING ELLIPTICAL BASE SEGMENTS - The present invention provides a planar light guide film for a backlight unit having at least one point light source, the light guide film comprising a light input surface for receiving light from the point light source, a light redirecting surface for redirecting light received from the light input surface and a light output surface for outputting at least the light redirected from the light redirecting surface. The light input surface further comprises a composite lens structure having a circular tip segment with a first contact angle, and a first and second elliptical base segments with a second contact angle, the second contact angle being less than the first contact angle and the second contact angle being equal to each other and | 2013-03-14 |
20130063978 | Chassis for Display Backlight - An electronic device may be provided with a display. Backlight structures may be used to provide backlight for the display. The backlight structures may include a light guide plate. A rectangular ring-shaped chassis may have a rectangular opening that receives the light guide plate. One or more edges of the chassis may be provided with an array of notches that receive light-emitting diodes or other light sources. The light sources may launch light into edge portions of the light guide plate. The chassis may include a first plastic structure such as a light reflecting structure formed from a material such as white plastic. The first plastic structure may surround two or more peripheral edges of the light guide plate. The chassis may also include a second plastic structure such as a light blocking structure formed from a material such as black plastic that helps prevent light leakage. | 2013-03-14 |
20130063979 | ELECTRICAL CONNECTOR AND BACKLIGHT MODULE USING THE SAME - The invention provides an electrical connector and a backlight module using that electrical connector. The electrical connector includes a body and two conducting lines. The body is provided with first and second connecting portions, the former of which has a first connecting surface and the latter has a second connecting surface. An invariable relative angle is defined between the first and second connecting surfaces. The conducting lines are coated on the first and second connecting surfaces without crossing each other. The backlight module includes a light guide plate, two LED light bars mounted to two respective light receiving edges of the light guide plate, and an aforesaid electrical connector connecting the LED light bars. The electrical connector is electrically connected with the LED light bars and fixes their relative positions. Besides, it is easy to install the electrical connector to connect the LED light bars firmly. | 2013-03-14 |
20130063980 | LIGHTGUIDES HAVING LIGHT EXTRACTION STRUCTURES PROVIDING REGIONAL CONTROL OF LIGHT OUTPUT - Lightguides, devices incorporating lightguides, and processes for making lightguides are described. A lightguide includes light extractors arranged in a pattern on a surface of the lightguide. The pattern of light extractors is arranged to enhance uniformity of light output across a surface of the lightguide and to provide enhanced defect hiding. The efficiency of the light extractors is controlled by a shape factor. The areal density of the light extractors across the surface of the lightguide may be substantially constant or may decrease along the direction of propagation of light from the light source. | 2013-03-14 |
20130063981 | MULTILEVEL CONVERTER AND A CONTROL METHOD FOR OPERATING A MULTILEVEL CONVERTER - A converter includes an active stage for converting an AC input voltage at an AC input into an intermediate DC voltage, and a DC/DC converter for transforming the intermediate DC voltage into an output DC voltage at a DC output. The DC/DC converter has a resonant transformer formed by a resonant circuit and a transformer. The converter also includes control unit configured to actively operate the active stage only based on an output DC voltage of the DC/DC converter, an input voltage, and an input current of the converter, and to operate the DC/DC converter in an open loop mode. A method for operating such a converter is also provided. | 2013-03-14 |
20130063982 | Soft Transition Apparatus and Method for Switching Power Converters - An embodiment apparatus comprises a secondary synchronous rectifier and a secondary gate drive controller. The secondary gate drive controller coupled to a transformer winding comprises a secondary synchronous rectifier soft start signal generator configured to generate a plurality of soft start pulses, a pulse width modulation generator configured to generate a forward switch drive signal and a freewheeling switch drive signal based upon a signal across the transformer winding and a soft transition generator configured to generate a soft start freewheeling switch drive signal by gradually releasing the freewheeling switch drive signal during a soft start process. | 2013-03-14 |
20130063983 | POWER CONVERTER ENABLING SUPPRESSION OF MAGNETIC FLUX BIAS IN A TRANSFORMER OF THE CONVERTER - In an electrical power converter, an input circuit performs switching for converting a supply voltage of a power source to alternating-polarity voltage pulses which are applied to the primary winding of a transformer. Each voltage pulse is controlled (e.g., pulse width or amplitude is adjusted) based on a detected value of current flow in the primary winding, where the value has been detected an even-numbered plurality of voltage pulses previously. Any DC component of current flow in the primary winding, caused by manufacturing deviations between switching elements in the input circuit, can thereby be suppressed, and DC flux bias in the transformer thereby suppressed. | 2013-03-14 |
20130063984 | DEAD-TIME OPTIMIZATION OF DC-DC CONVERTERS - Representative implementations of devices and techniques determine the timing of switches associated with a dc-dc converter. The determination is based on a body diode conduction of at least one of the switches, which is detected and used to determine a switching delay. | 2013-03-14 |
20130063985 | Adaptive Dead Time Control Apparatus and Method for Switching Power Converters - An embodiment apparatus comprises a secondary synchronous rectifier and a secondary gate drive controller coupled to a transformer winding. The secondary gate drive controller is configured to generate a forward gate drive signal for the forward switch and generate a freewheeling gate drive signal for the freewheeling switch, wherein the secondary gate drive controller generates a dead time between the forward gate drive signal and the freewheeling gate drive signal. | 2013-03-14 |
20130063986 | CONTROL CIRCUIT FOR CONTROLLING THE MAXIMUM OUTPUT CURRENT OF POWER CONVERTER AND METHOD THEREOF - A control circuit of the power converter according to the present invention comprises a feedback circuit, an output circuit and an adaptive clamping circuit. The feedback circuit generates a feedback signal in accordance with an output of the power converter. The output circuit generates a switching signal in accordance with the feedback signal for regulating the output of the power converter. The adaptive clamping circuit limits the level of the feedback signal under a first level for a first load condition. The feedback circuit determines a slew rate of the feedback signal for increasing the level of the feedback signal from the first level to a second level. The adaptive clamping circuit is disabled and the level of the feedback signal can be increased to the second level for a second load condition. | 2013-03-14 |
20130063987 | CONTROL CIRCUIT OF SWITCHING POWER SUPPLY SYSTEM AND SWITCHING POWER SUPPLY SYSTEM - An input voltage detection unit detects whether an AC input voltage is the voltage of a 100V system or of a 200V system. In response, a frequency decreasing gain setting unit switches between frequency decreasing gain characteristics relative to load factors. The frequency decreasing gain characteristics are established so that the initiation of a decrease in a feed back signal in the 100V system is earlier than that in the 200V system. By switching the frequency decreasing gain characteristics based on an AC input signal, the characteristics, in which a decrease in a feed back signal in the 200V system is earlier than that in the 100V system, are cancelled to allow load factors, at each of which a power supply operation frequency reaches the audible region, to be approximately the same to enable a vibration isolating measure to be independent of the AC input voltage. | 2013-03-14 |
20130063988 | POWER CONVERSION WITH ADDED PSEUDO-PHASE - Methods and systems for power conversion. An energy storage capacitor is contained within an H-bridge subcircuit which allows the capacitor to be connected to the link inductor of a Universal Power Converter with reversible polarity. This provides a “pseudo-phase” drive capability which expands the capabilities of the converter to compensate for zero-crossings in a single-phase power supply. | 2013-03-14 |
20130063989 | INTERFACE ARRANGEMENT BETWEEN AC AND DC SYSTEMS USING GROUNDING SWITCH - An interface arrangement for connection between an AC system and a DC system and to a method of disconnecting a DC system from an AC system are disclosed. The arrangement includes a converter for conversion between AC and DC having a DC side for connection to the DC system and an AC side for being coupled to the AC system, a set of circuit breakers coupled between the AC side of the converter and the AC system and a breaker assisting unit including a set of branches connected between the AC side of the converter and ground, where each branch includes a switch in series with an impedance element. | 2013-03-14 |
20130063990 | PROTECTION CIRCUIT FOR POWER CONVERTER - A protection circuit of a power converter without an input capacitor is disclosed. The protection circuit comprises a high voltage switch, a detection circuit and a control circuit. The switch senses an input voltage of the power converter via a resistor for generating a first signal. The detection circuit coupled to a transformer senses the input voltage of the power converter for generating a second signal. The control circuit controls a switching signal in response to the first signal and the second signal. The switching signal is utilized to switching the transformer for regulating the power converter; and the level of the first signal and the second signal is correlated a level of the input voltage of the power converter. | 2013-03-14 |
20130063991 | VOLTAGE CONVERTER CONFIGURATIONS FOR SOLAR ENERGY SYSTEM APPLICATIONS - A system includes a low switching frequency power converter configured to be coupled to a solar cell, wherein the low switching frequency power converter is configured to generate alternating current (AC) power based on low voltage direct current (DC) power transmitted from the solar cell and transmit the converted AC power. The system also include a multi-pulse transformer configured to receive the converted AC power and generate transformed power based on the converted AC power, wherein the transformed power comprises power at a voltage level that differs from the a voltage level of the converted AC power. | 2013-03-14 |
20130063992 | CONNECTION APPARATUS FOR POWER CONVERTER - A power converter apparatus is provided with a lead-in board in which alternating-current power received from power converting units is connected in parallel, and a connection base including frames for installing the power converting units therein. The frames are provided with connection sections for connecting the main, circuits of the power converting units. The lead-in board is provided with breakers for cut off alternating-current power from the power converting units. | 2013-03-14 |
20130063993 | ALTERNATING CURRENT LINE EMULATOR - An alternating current (AC) line emulator includes an AC power supply and an automatic regulating load. The AC power supply is used for providing an AC line frequency and an AC line voltage. The automatic regulating load is coupled between the AC power supply and a grid-connected power generation system for functioning as a test load of the grid-connected power generation system, and preventing current from reversing to the AC power supply and shutting down the AC power supply. When the grid-connected power system is tested, power consumption of the automatic regulating load is equal to a sum of output power of the grid-connected power generation system and output power of the AC power supply. | 2013-03-14 |
20130063994 | POWER CONVERSION WITH ADDED PSEUDO-PHASE - Methods and systems for power conversion. An energy storage capacitor is contained within an H-bridge subcircuit which allows the capacitor to be connected to the link inductor of a Universal Power Converter with reversible polarity. This provides a “pseudo-phase” drive capability which expands the capabilities of the converter to compensate for zero-crossings in a single-phase power supply. | 2013-03-14 |
20130063995 | Converter Cell For Cascaded Converters And A Control System And Method For Operating A Converter Cell - A cascaded electric power converter and a method of operating a cascaded electric power converter are disclosed. The cascaded converter includes: a converter cell including a cell capacitor and at least one phase leg having at least two electric valves, the at least one phase leg being connected in parallel to the cell capacitor; and a control system for controlling the switching of the electric valves of the at least one phase leg. The control system is configured to, upon detection of a need to by-pass the converter cell, control the switching of the electric valves in a manner so that the cell capacitor is short circuited via a phase leg, so as to obtain a current surge through the phase leg, thereby creating a permanent current path through the converter cell. | 2013-03-14 |
20130063996 | POWER SUPPLY APPARATUS - A power supply apparatus includes: an input terminal to which alternating current power is input; a positive terminal and a negative terminal at which direct-current power is output; a rectifier circuit configured to rectify the alternating current power input to the input terminal; an inductor coupled to the rectifier circuit; a capacitor coupled between the positive terminal and the negative terminal; a first rectifying element coupled between an output terminal of the inductor and the positive terminal; a first switching element coupled between an input terminal of the first rectifying element and the negative terminal; a second switching element and a transformer coupled in parallel to the first switching element; a second rectifying element coupled between the positive terminal and a coupling portion of the second switching element and the transformer; and a third rectifying element coupled between the transformer and the positive terminal. | 2013-03-14 |
20130063997 | High-Resolution Readout of Analog Memory Cells - A method includes storing data in an analog memory cell by writing an analog value into the memory cell. After storing the data, the data stored in the memory cell is read by discharging electrical current to flow through the memory cell, during a predefined time interval, while applying a variable voltage to a gate of the memory cell. A fraction of the predefined time interval, during which the variable voltage allows the electrical current to flow through the memory cell, is estimated. The stored data is estimated based on the estimated fraction. | 2013-03-14 |
20130063998 | SYSTEM AND MEMORY MODULE - A system includes: a controller, a first memory module connected to the controller through a first data bus, and a second memory module connected to the controller through a second data bus, wherein the first memory module includes: first and second memory chips; a first data terminal connected to the first data bus, and a first switch unit that electrical connects the first data terminal with either the first memory chip and the second memory chip, and the second module includes: third and fourth memory chips; a second data terminal connected to the second data bus, and a second switch unit that switches over electrical connection of the second data terminal with either the third memory chip or the fourth memory chip. | 2013-03-14 |
20130063999 | ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY STRUCTURE HAVING AN ANTIFUSE COMPONENT AND A PROCESS OF USING THE SAME - An electronic device can include a nonvolatile memory cell, wherein the nonvolatile memory cell can include an antifuse component, a switch, and a read transistor having a control electrode. Within the nonvolatile memory cell, the switch can be coupled to the antifuse component, and the control electrode of the read transistor can be coupled to the antifuse component. The nonvolatile memory cell can be programmed by flowing current through the antifuse component and the switch and bypassing the current away the read transistor. Thus, programming can be performed without flowing current through the read transistor decreasing the likelihood of the read transistor sustaining damage during programming. Further, the antifuse component may not be connected in series with the current electrodes of the read transistor, and thus, during read operations, read current differences between programmed and unprogrammed nonvolatile memory cells can be more readily determined. | 2013-03-14 |
20130064000 | SEMICONDUCTOR STORAGE DEVICE INCLUDING MEMORY CELLS CAPABLE OF HOLDING DATA - According to one embodiment, a semiconductor storage device includes first cells, first bit and first word, and first sense. The first cells are capable of holding 2-level or higher-level data. The first bit and first word are capable of selecting the first cells. The first sense detects a first current. The first sense includes a first supply unit, a first accumulation unit, a detector, and a counter. The first supply unit supplies a second current when the data is read. The first accumulation unit accumulates an amount of charge. The detector detects the potential the amount of charge. The counter counts output from the detector. The counter includes a second supply unit, a second accumulation unit, and a sensing unit. The second supply unit charges a first node. The second accumulation unit accumulates a charge. The sensing unit detects the amount of charge of the second accumulation unit. | 2013-03-14 |
20130064001 | RESISTANCE CHANGE NONVOLATILE MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING RESISTANCE CHANGE NONVOLATILE MEMORY DEVICE - To provide a resistance change nonvolatile memory device performing a stable switching operation at a low cost. The resistance change nonvolatile memory device has a first wiring, an interlayer insulating layer formed thereon, a second wiring formed thereon, and a resistance change element formed between the first wiring and the second wiring. The interlayer insulating layer between the first wiring and the second wiring has a hole having a width not greater than that of the first wiring. The resistance change element is in contact with the first wiring and has a lower electrode at the bottom of the hole, a resistance change layer thereon, and an upper electrode thereon. They are formed inside the hole. The first wiring contains copper and the lower electrode contains at least one metal selected from the group consisting of ruthenium, tungsten, cobalt, platinum, gold, rhodium, iridium, and palladium. | 2013-03-14 |
20130064002 | RESISTANCE CHANGE NONVOLATILE MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF OPERATING RESISTANCE CHANGE NONVOLATILE MEMORY DEVICE - A resistance change nonvolatile memory device includes with a first electrode, a resistance change portion provided on the first electrode, and a second electrode provided on the resistance change portion. The resistance change portion is equipped with a resistance change layer provided on the first electrode and undergoing a change in resistance with an applied voltage and a stable layer provided on the resistance change layer and forming a filament. The resistance change layer and the stable layer are made of metal oxides different from each other. The oxide formation energy of the resistance change layer is higher than that of the stable layer. The resistance change layer has such a film thickness as to permit the resistance of the resistance change portion in an Off state to fall within a range determined by the film thickness. | 2013-03-14 |
20130064003 | DUAL PORT STATIC RANDOM ACCESS MEMORY CELL - An SRAM has at least two sets of pass transistors for coupling at least two sets of bit lines to true and complement data nodes of an SRAM cell based on the assertion of at least two word lines. The cell includes two pull up transistors and two pull down transistors coupled to the true and complement data nodes. None of the pass transistors are implemented in an active area that includes a pull up transistor or a pull down transistor of the cell. | 2013-03-14 |
20130064004 | SRAM CELL WRITABILITY - Systems and methods for detecting and improving writeability of a static random access memory (SRAM) cell. A bias voltage value corresponding to an operating condition, such as, a process, a voltage, or a temperature operation condition that indicates a cell write failure condition of an external SRAM array comprising the SRAM cell is generated. This bias voltage value is applied to word lines of SRAM cells in a model SRAM array. A first delay for a trigger signal rippled through the model SRAM array is detected and compared to a reference delay. A write assist indication is generated if the first delay is greater than or equal to the reference delay. Based on the write assist indication, a write assist is provided to the SRAM cell. | 2013-03-14 |
20130064005 | TUNNEL TRANSISTOR, LOGICAL GATE COMPRISING THE TRANSISTOR, STATIC RANDOM-ACCESS MEMORY USING THE LOGICAL GATE AND METHOD FOR MAKING SUCH A TUNNEL TRANSISTOR - A tunnel transistor is provided comprising a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and the second semiconductor part. | 2013-03-14 |
20130064006 | Apparatus for Selective Word-Line Boost on a Memory Cell - Systems and methods for selectively boosting word-line (WL) voltage in a memory cell array. The method relies several embodiments to minimize energy costs associated with WL boost scheme. One embodiment generates a transient voltage boost rather than supply a DC voltage boost. The transient boost generation may be controlled on a cycle basis and can be disabled when the array is not accessed. Another embodiment allows the system to generate the transient voltage boost locally, near a WL driver and only during the cycles when it is needed. Localized boost voltage generation reduces the load capacitance that needs to be boosted to higher voltage. Another embodiment efficiently distributes the transient boost to the WL drivers. | 2013-03-14 |
20130064007 | DISTURB-FREE STATIC RANDOM ACCESS MEMORY CELL - A solid-state memory in which each memory cell includes a cross-point addressable write element. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and a read buffer for coupling one of the storage nodes to a read bit line for the column containing the cell. The write element of each memory cell includes one or a pair of write select transistors controlled by a write word line for the row containing the cell, and write pass transistors connected to corresponding storage nodes and connected in series with a write select transistor. The write pass transistors are gated by a write bit line for the column containing the cell. In operation, a write reference is coupled to one of the storage nodes of a memory cell in the selected column and the selected row, depending on the data state carried by the complementary write bit lines for that column. | 2013-03-14 |
20130064008 | DATA READ CIRCUIT, NONVOLATILE MEMORY DEVICE COMPRISING DATA READ CIRCUIT, AND METHOD OF READING DATA FROM NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a nonvolatile cell array comprising a memory cell and a reference cell, a clamping circuit electrically connected to the memory cell and configured to clamp a voltage applied to a data sensing line during a read operation, and a clamping voltage generation unit configured to generate a clamping voltage responsive to a first voltage having a level based on the reference cell, and to feed back the clamping voltage to the clamping circuit. | 2013-03-14 |
20130064009 | SIZE-REDUCED MAGNETIC MEMORY CELL - A semiconductor device includes: a first memory cell, a second memory cell adjacent to the first memory cell, first and second write bitlines and a common bitline. The first memory cell includes: a first magnetization fixed layer, a first magnetic recording layer, a first reference layer, a first tunnel barrier film, and a first transistor. The second memory cell includes: a second magnetization fixed layer, a second magnetic recording layer, a second reference layer, a second tunnel barrier layer and a second transistor. Each of the first and second reference layer has a fixed magnetization. A common magnetization fixed layer having a fixed magnetization is coupled to the first and second magnetic recording layers. The common magnetization fixed layer and the common bitline is connected so that the common magnetization fixed layer and the common bitline are unable to be electrically unconnected. | 2013-03-14 |
20130064010 | MEMORY CELL HAVING NONMAGNETIC FILAMENT CONTACT AND METHODS OF OPERATING AND FABRICATING THE SAME - A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the free and pinned layers. The nonmagnetic filament contact is formed from a nonmagnetic source layer, also between the free and pinned layers. The filament contact directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell. | 2013-03-14 |
20130064011 | STT-MRAM CELL STRUCTURE INCORPORATING PIEZOELECTRIC STRESS MATERIAL - A magnetic memory cell including a piezoelectric material, and methods of operating the memory cell are provided. The memory cell includes a stack, and the piezoelectric material may be formed as a layer in the stack or adjacent the layers of the cell stack. The piezoelectric material may be used to induce a transient stress during programming of the memory cell to reduce the critical switching current of the memory cell. | 2013-03-14 |
20130064012 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor, formed in a substrate, that includes a first gate insulating film, a source and a drain region, a first gate electrode, and a first sidewall, and a second transistor that includes a second gate insulating film, a second gate electrode, a source and a drain region, and a second sidewall. The first transistor includes a portion of a logic circuit. The second transistor includes a transistor included in a memory cell of a DRAM, or includes a portion of a peripheral circuit that performs writing and erasing with respect to the DRAM. The first gate insulating film has a same thickness as that of the second gate insulating film. The first gate electrode has the same thickness as that of the second gate electrode. A layer structure of the first sidewall is a same as a layer structure of the second sidewall. | 2013-03-14 |
20130064013 | NON-VOLATILE MULTI-LEVEL MEMORY DEVICE AND DATA READ METHOD - A non-volatile memory device, a data read method thereof and a recording medium are provided. The method includes receiving a data read command for a first word line in a memory cell array, reading data from a second word line adjacent to the first word line, and reading data from the first word line using a different voltage according to a state of the data read from the second word line. The number of read voltages used to distinguish an erased state and a first programmed state is greater than the number of read voltages used to distinguish a second programmed state and a third programmed state. | 2013-03-14 |
20130064014 | EEPROM MEMORY PROTECTED AGAINST BREAKDOWN OF CONTROL GATE TRANSISTORS - The disclosure relates to an electrically erasable and programmable memory comprising at least one word of memory cells with first and second control gate transistors in parallel to apply a control gate voltage to the memory cells of the word. The memory also comprises s first control circuit to supply a first control voltage to a control terminal of the first control gate transistor through a first current limiter, and a second control circuit to supply a second control voltage to a control terminal of the second control gate transistor through second current limiter. | 2013-03-14 |
20130064015 | METHOD OF BURN-IN TEST OF EEPROM OR FLASH MEMORIES - The disclosure relates to a method for testing an integrated circuit, comprising in a burn-in test mode, two steps during which gate oxides of conductive high voltage MOS transistors of the integrated circuit are subjected to a first test voltage, and blocked high voltage MOS transistors of the integrated circuit are subjected to a second test voltage, the first test voltage being set to a value higher than a high supply voltage supplied to the high voltage MOS transistors in a normal operating mode, to make the gate oxides of transistors considered as insufficiently robust break down, the second test voltage being set to a value lower than the first test voltage and which can be supported by the blocked transistors, the states of the transistors being changed between the two steps. | 2013-03-14 |
20130064016 | SEMICONDUCTOR DEVICE AND CONTROL METHOD OF THE SAME - The present invention provides a semiconductor memory and a control method therefor, the semiconductor device including a first current-voltage conversion circuit connected to a core cell provided in a nonvolatile memory cell array, a second current-voltage conversion circuit connected to a reference cell through a reference cell data line, a sense amplifier sensing an output from the first current-voltage conversion circuit and an output from the second current-voltage conversion circuit, a compare circuit comparing a voltage level at the reference cell data line with a predefined voltage level, and a charging circuit charging the reference cell data line, if the voltage level at the reference cell data line is lower than the predefined voltage level during pre-charging the reference cell data line. According to the present invention, the pre-charging period of the reference cell data line can be shortened, and the data read time can be shortened. | 2013-03-14 |
20130064017 | CONCURRENT OPERATION OF PLURAL FLASH MEMORIES - A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed. | 2013-03-14 |
20130064018 | MEMORY ACCESS CIRCUIT FOR DOUBLE DATA/SINGLE DATA RATE APPLICATIONS - A memory access circuit includes a write data circuit and a first write switch circuit. The write data circuit is used for receiving double data rate data or single data rate data, and outputting odd term data and even term data of adjusted double data rate data or adjusted single data rate data. The first write switch circuit is used for outputting the odd term data of the adjusted double data rate data to an odd block of a memory and outputting the even term data of the adjusted double data rate data to an even block of the memory when the write data circuit receives the double data rate data, and outputting the adjusted single data rate data to the even block or the odd block of the memory when the write data circuit receives the single data rate data. | 2013-03-14 |
20130064019 | DATA STORAGE CIRCUIT THAT RETAINS STATE DURING PRECHARGE - A data storage circuit for receiving and holding a data value includes an input stage configured to receive a data value in response to the precharge phase changing to an evaluation phase and to hold the data value during the evaluation phase. An output stage has an output latching element for holding the value, two switching devices for updating the output latching element and an output. The switching devices each being controlled by respective signals from dual data lines, wherein, in response to the data value held in the input stage being a logical one, the first switching device updates the output latching element with a value indicative of the logical one and in response to the data value held in the input stage being a logical zero, the second switching device updates the output latching element with a value indicative of the logical zero. | 2013-03-14 |
20130064020 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a first data input/output line configured to transmit data from a first memory bank; a second data input/output line configured to transmit the data from the first memory bank; a first data output section configured to align and output data transmitted through the first data input/output line based on an input/output mode; and a second data output section configured to align and output either data transmitted through the first input/output line or the second data input/output line based on the input/output mode and an address signal. | 2013-03-14 |
20130064021 | SENSE AMPLIFIER WITH FAST BITLINE PRECHARGE MEANS - The disclosure relates to a sense amplifier comprising a cascode transistor and means for biasing the cascode transistor, supplying a control voltage to a gate terminal of the cascode transistor. The means for biasing the cascode transistor comprise means for isolating the gate terminal of the cascode transistor from the output of the voltage generator during a first period of the precharge phase, so as to boost the bitline voltage, then for linking the gate terminal to the output of the voltage generator during a second period of the precharge phase. Application in particular to sense amplifiers for non-volatile memories. | 2013-03-14 |
20130064022 | Method and Apparatus for Memory Access - An interleaver or deinterleaver comprises a memory having M logical memory units arranged in groups of N memory units such that accesses to memory units within a group are faster after a first access to a memory in that group using first access. An address generator is arranged to write consecutive data items a number of memory units apart that is less than the size of groups N of memory units so that two or more data items are written within groups. The arrangement provides fast interleaving without increasing memory size. | 2013-03-14 |
20130064023 | Memory Systems and Methods for Dynamically Phase Adjusting A Write Strobe and Data to Account for Receive-Clock Drift - A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift. | 2013-03-14 |
20130064024 | SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING - A semiconductor device is disclosed. The semiconductor device includes a plurality of memory cells provided in a matrix and having a charge storage layer, a plurality of word lines provided on the charge storage layer, and an application section. When reading data from a selected memory cell selected from the plurality of memory cells, the application section applies a voltage having an opposite polarity to the voltage applied to a selected word line to non-selected word lines arranged on both adjacent sides of the selected word line. | 2013-03-14 |
20130064025 | DYNAMIC DATA STROBE DETECTION - Techniques are disclosed relating to determining when a data strobe signal is valid for capturing data. In one embodiment, an apparatus is disclosed that includes a memory interface circuit configured to determine an initial time value for capturing data from a memory based on a data strobe signal. In some embodiments, the memory interface circuit may determine this initial time value by reading a known value from memory. In one embodiment, the memory interface circuit further configured to determine an adjusted time value for capturing the data, where the memory interface circuit is configured to determine the adjusted time value by using the initial time value to sample the data strobe signal. | 2013-03-14 |
20130064026 | TECHNOLOGY OF MEMORY REPAIR AFTER STACKING OF THREE-DIMENSIONAL INTEGRATED CIRCUIT - A three-dimensional integrated circuit (3-D IC) includes a controller chip and at least one memory chip, in which, besides an original storage capacity, the memory chip further includes multiple spare memory cells and an address translation circuit with an external activation/enablement function. After the memory chip and the controller chip are stacked, the controller chip may still activate/enable a spare in the memory chip to repair a damaged or deteriorated memory cell in the memory chip through at least one vertical interconnect (for example, through-silicon via (TSV)), regardless of whether the damaged or deteriorated memory cell has been repaired or not before the controller chip and the memory chip are stacked. | 2013-03-14 |
20130064027 | Memory and Method of Adjusting Operating Voltage thereof - By adjusting an operating voltage of a memory cell in a memory according to a measured capacitance result indicating capacitance of an under-test capacitor of the memory cell, an appropriate operating voltage for the memory cell can always be determined according to the measured capacitance result. The measured capacitance result indicates whether the capacitance of the under-test capacitor indicating the characteristic of the gate dielectric of the memory cell is higher or lower than a reference capacitor, and is generated by amplifying a difference between two voltages indicating capacitance of the reference capacitor and the capacitance of the under-test capacitor. | 2013-03-14 |
20130064028 | SEMICONDUCTOR MEMORY DEVICE AND SENSE AMPLIFIER - A semiconductor memory device comprises a memory cell; a first bit line and a second bit line connected to the memory cell; and a sense amplifier operative to amplify the voltage between the first and second bit lines. The sense amplifier includes a first and a second drive transistor configuring a transistor pair for differential amplification, and a first and a second capacitor connected between the sources of the first and second drive transistors and a source control terminal, respectively. The sense amplifier precharges the first and second drive transistors on the drain side prior to sensing, thereby holding the threshold information on the first and second drive transistors in the first and second capacitors, and compensates for the source voltages on the first and second drive transistors by the threshold information held in the first and second capacitors at the time of sensing. | 2013-03-14 |
20130064029 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - An operating method of a semiconductor memory device includes precharging a channel region of a program-inhibited cell of first memory cells coupled to a first word line, selected from a first one of word line groups between a drain select line and a source select line, to a first level based on first data; performing a first program operation for storing the first data in the first memory cells; precharging the channel region of a program-inhibited cell of second memory cells coupled to a second word line, selected from a second one of the word line groups, to a second level based on second data to be stored in the second memory cells; and performing a second program operation for storing the second data in the second memory cells. | 2013-03-14 |
20130064030 | SEMICONDUCTOR DEVICES, METHODS OF OPERATING SEMICONDUCTOR DEVICES, AND SYSTEMS HAVING THE SAME - A semiconductor device includes a selection circuit and a phase detector. The selection circuit, in response to a first selection signal output from a controller, outputs as a timing signal a first clock signal output from the controller or an output signal of a PLL using the first clock signal as a first input. The phase detector generates a voltage signal indicating a phase difference between a second clock signal output from the controller and the timing signal output from the selection circuit. The semiconductor device further includes a data port, a memory core storing data, and a serializer, in response to the timing signal output from the selection circuit, serializing data output from the memory core and outputting serialized data to the controller via the data port. The controller generates the first selection signal based on at least one of the voltage signal and the serialized data. | 2013-03-14 |
20130064031 | Adaptive Read Wordline Voltage Boosting Apparatus and Method for Multi-Port SRAM - Embodiments of the invention are directed to systems and methods for adaptively boosting the supply voltage to an SRAM (Static Random Access Memory) in response to process-voltage-temperature variations when needed. Embodiments include a critical path that simulates a typical memory cell and read-out circuit in the SRAM. Applying a trigger signal to a word-line input port of the critical path, and comparing the output of the critical path to a reference-latch signal, provides an indication of when to boost the supply voltage to the read-out circuits of the SRAM. | 2013-03-14 |
20130064032 | SEMICONDUCTOR STORAGE DEVICE AND ELECTRONIC APPARATUS - A semiconductor storage device includes a plurality of memory macros including a plurality of memory cell arrays; a low-potential power supply boosting circuit coupling the low-potential power supply to the ground in a normal mode and coupling the low-potential power supply to a voltage higher than a ground voltage in a sleep mode; a virtual power control circuits including a plurality of switches which is turned on when switching from the sleep mode to the normal mode and is turned off when switching from the normal mode to the sleep mode; and a sleep cancellation detecting circuit outputting, when the mode control signal supplied to the plurality of switches in one of the plurality of memory macros indicates to switch form the sleep mode to the normal mode, the mode control signal to a subsequent memory macro subsequent to the one of the plurality of memory macros. | 2013-03-14 |
20130064033 | DEVICE FOR PRODUCING A HARDENABLE MASS - The present invention relates to a device for producing a hardenable mass, preferably bone substitute and/or bone reinforcing material or bone cement or similar material. A mixing container may include a mixing space in which at least one powder and at least one liquid component are mixed to provide the hardenable mass. A piston may be provided in the mixing space of the mixing container. A screw device may be connectable to the mixing container such that the screw device may be configured to impart by screw movements a discharge movement to the piston to discharge the hardenable mass from the mixing space. | 2013-03-14 |
20130064034 | CYLINDRICAL PISTON ASSISTED BLENDING VESSEL - A system for blending and dispensing a frozen mixture includes a blending chamber to receive the ingredients to be blended and a blending mechanism that includes a rotating blade for blending and a motor to drive the blade. A piston is located within the blending chamber, and a dispensing mechanism dispenses a blended mixture from the blending chamber. A discharge mechanism discharges a cleaning fluid from the blending chamber. The piston is moved to a first position with respect to the blending mechanism during a blending cycle and moved to a second position during a dispensing cycle, the second position being closer to the blending mechanism than the first position. The piston is moved to a third position with respect to the blending mechanism during an introduction of a cleaning fluid into the blending chamber, the third position being farther away from the blending mechanism than the first position. The piston is moved to a fourth position with respect to the blending mechanism during a discharging of the cleaning fluid cycle. | 2013-03-14 |
20130064035 | ELECTROMECHANICAL TRANSDUCER - An electromechanical transducer according to an embodiment of the present invention is capable of selectively performing a transmitting and receiving operation by using elements of different shapes. The electromechanical transducer has a plurality of cells, each of which has a vibrating film including two electrodes provided with a gap therebetween, two driving and detecting units, a potential difference setter, and a switch. Each of the driving and detecting units implements a transmitting and/or a receiving function. A first or second element includes first or second electrodes which are electrically connected and further connected to the common first or second driving and detecting unit, respectively. The potential difference setter sets a predetermined potential difference between the reference potentials of the first and second driving and detecting units, respectively, and the switch switches between the first and second driving and detecting units to perform the transmitting and receiving operation. | 2013-03-14 |
20130064036 | ULTRASOUND SYSTEM AND SIGNAL PROCESSING UNIT CONFIGURED FOR TIME GAIN AND LATERAL GAIN COMPENSATION - The present invention provides an ultrasound system, which comprises: a signal acquiring unit to transmit an ultrasound signal to an object and acquire an echo signal reflected from the object; a signal processing unit to control TGC (Time Gain Compensation) and LGC (Lateral Gain Compensation) of the echo signal; a TGC/LGC setup unit adapted to set TGC and LGC values based on TGC and LGC curves inputted by a user; and an image producing unit adapted to produce an ultrasound image of the object based on the echo signal. The signal processing unit is further adapted to control the TGC and the LGC of the echo signal based on the TGC and LGC values set by the TGC/LGC setup unit. | 2013-03-14 |
20130064037 | Method and apparatus for ultrasound image acquisition - Apparatus for ultrasound image acquisition is integrated into the casing of an ultrasound probe that includes an array of electro-acoustic transducers, which transmit and receive ultrasound pulses. The array communicate with a processing unit, to which reception signals are fed, and are connected to a unit generating signals for exciting the transmission of ultrasound waves. In one aspect of the invention, at least the processing unit is fitted into the probe casing and is configured to convert the reception signals into an image, and to generate video signals for generating an image on a display unit. The transmission between the probe and a remote unit displaying and possibly storing the images as video signals may be operated wirelessly. | 2013-03-14 |
20130064038 | DUAL AXIS GEOPHONES FOR PRESSURE/VELOCITY SENSING STREAMERS FORMING A TRIPLE COMPONENT STREAMER - A seismic streamer includes a sensor comprises an axially oriented body including a plurality of axially oriented channels arranged in opposing pairs; a plurality of hydrophones arranged in opposing pairs in the channels; a pair of orthogonally oriented acoustic particle motion sensors; and a tilt sensor adjacent or associated with the particle motion sensors. The streamer has a plurality of hydrophones, as previously described, aligned with a plurality of accelerometers which detect movement of the streamer in the horizontal and vertical directions, all coupled with a tilt sensor, so that the marine seismic system can detect whether a detected seismic signal is a reflection from a geologic structure beneath the streamer or a downward traveling reflection from the air/seawater interface. | 2013-03-14 |
20130064039 | ACOUSTIC LOGGING WHILE DRILLING TOOL WITH ACTIVE CONTROL OF SOURCE ORIENTATION - The subject disclosure relates to sonic logging while drilling. A transmitter and at least one receiver are mounted on a drill collar for performing sonic investigations of the formation traversing a borehole. | 2013-03-14 |
20130064040 | METHOD FOR SEISMIC HYDROCARBON SYSTEM ANALYSIS - Method for analyzing seismic data representing a subsurface region for presence of a hydrocarbon system or a particular play. Seismic attributes are computed, the attributes being selected to relate to the classical elements of a hydrocarbon system, namely reservoir, seal, trap, source, maturation, and migration. Preferably, the attributes are computed along structural fabrics ( | 2013-03-14 |
20130064041 | OSCILLATOR AND ELECTRONIC DEVICE - In an oscillator ( | 2013-03-14 |
20130064042 | DISTANCE ESTIMATION USING SOUND SIGNALS - An apparatus comprises a test signal generator ( | 2013-03-14 |
20130064043 | COMPACT, ENERGY-EFFICIENT ULTRASOUND IMAGING PROBES USING CMUT ARRAYS WITH INTEGRATED ELECTRONICS - A CMUT on CMOS imaging chip is disclosed. The imaging chip can use direct connection, CMOS architecture to minimize both internal and external connection complexity. Intelligent power management can enable the chip to be used for various imaging applications with strict power constraints, including forward-looking intra-vascular ultrasound imaging. The chip can use digital logic to control transmit and receive events to minimize power consumption and maximize image resolution. The chip can be integrated into a probe, or catheter, and requires minimal external connections. The chip can comprise integrated temperature control to prevent overheating. | 2013-03-14 |
20130064044 | ACOUSTIC MODEM FOR FLUID MONITORING IN MEDICAL AND INDUSTRIAL APPLICATIONS - The various embodiments provide systems, devices, and methods which include an acoustic tag configured to transmit an acoustic signal through a contact medium that may be received by an acoustic modem, with the acoustic signal configured to transmit information. By modulating sound traveling through an acoustic connection between the fluid container and a pump, meter or valve, information such as an identifier of the fluid or container may be transmitted without risk of confusion with other fluid containers in the vicinity. In a medical embodiment, IV fluid and the IV drip tube provide a fluid and plastic acoustic connection to an IV pumping or metering device and an IV bag through which sound may be transmitted. The transmission of identification information through this physical connection may insure that the pumping or metering device only communicates with the IV bag coupled to the pump. Acoustic tags may be active or passive. | 2013-03-14 |
20130064045 | Wearable Electronic Device - An analog wearable electronic device that is operationally coupleable to a transmitting device. The transmitting device includes means for viewing a simulation of a display provided on the wearable electronic device, changing information displayable on the simulated display and transmitting the changed information and/or information from which the changed information is derivable to the wearable electronic device. The wearable electronic device includes a receiver for receiving from the transmitting device the changed information and/or the information from which the changed information is derivable. A controller assembly processes the changed information and/or derives the changed information, and an actuation mechanism moves a display indicator based at least in part on the changed information. The changed information is thereafter reflected on the display of the wearable electronic device by the display indicator. | 2013-03-14 |
20130064046 | BALANCE SPRING WITH TWO HAIRSPRINGS - The invention relates to a balance spring ( | 2013-03-14 |
20130064047 | TIMEPIECE MOVEMENT OF REDUCED HEIGHT WITH A LARGE POWER RESERVE - Timepiece gear train device ( | 2013-03-14 |
20130064048 | TIMEPIECE DIAL, AND TIMEPIECE - To provide a timepiece dial that presents a rich stereoscopic effect, and to provide a timepiece including the timepiece dial, a timepiece dial of the invention has a microlens layer in which a plurality of microlenses are arranged in an orderly fashion when viewed from above, and a decorative layer provided with a design, in which the microlens layer and the decorative layer are superimposed when viewed from above, and the decorative layer has a plurality of regions that are different in the design from each other. Preferably, the decorative layer is provided with a design having a plurality of lines and/or a repeating design having the same arrangement as the microlenses and a pitch that differs from that of the microlenses as the design. | 2013-03-14 |
20130064049 | WATCH WITH SHAPEABLE STRAP - There is described a watch ( | 2013-03-14 |
20130064050 | WATCH WITH EASILY REPLACEABLE COMPONENTS - A watch with easily replaceable components, comprising a case, a bezel which is contoured so as to surround the glass of the case, and a strap. The bezel is fixed reversibly to the case with snap-acting quick engagement/release elements. The bezel has, on opposite perimetric portions, pairs of symmetrical grooves which are open on the inner part of the bezel and are closed on the outer part of the bezel and are each adapted to receive by insertion one end of a pin for the engagement of the strap, each pin remaining closed between the two grooves that accommodate its ends and the case. | 2013-03-14 |
20130064051 | Plasmonic Transducer Having Two Metal Elements with a Gap Disposed Therebetween - An apparatus includes a waveguide configured to deliver light to a transducer region. The apparatus also includes a plasmonic transducer that has two metal elements configured as side-by-side plates on a substrate-parallel plane with a gap therebetween. The gap is disposed along the substrate-parallel plane and has an input end disposed proximate the transducer region and an output end. The transducer is configured to provide a surface plasmon-enhanced near-field radiation pattern proximate the output end in response to the light received by the waveguide. | 2013-03-14 |
20130064052 | EFFICIENT ACCESS TO STORAGE DEVICES WITH USAGE BITMAPS - Upon receiving a request to allocate a storage region, a storage device may initialize the contents of the storage device to default values (e.g., zero) in order to avoid problems arising from unknown data stored in the locations of the storage region (e.g., upon writing a data set to a location involved in a mirroring relationship, uninitialized data in the corresponding mirror location may result in a mismatch that jeopardizes the written data). However, initializing the storage device may be time-consuming and inefficient. Instead, a usage bitmap may be generated that, for respective location sets of the storage region, indicates whether values exist in the location. A read request may be fulfilled by examining the usage bitmap to determine whether values exist in the specified location, and if not, the default value may be returned without accessing the storage device. Other efficiencies may also be achieved using the usage bitmap. | 2013-03-14 |
20130064053 | INFORMATION RECORDING MEDIUM, AND RECORDING METHOD AND REPRODUCING METHOD THEREOF - An information recording medium in which bottoms of a guide groove and a pit array formed on a disc substrate are allocated on a same flat plane and shaped in flat. Further, in a transition area from a pit array to a guide groove or from a guide groove to a pit array, the information recording medium is provided with an intermediate area composed of a pit array of which height changes from a height between a bottom and a side of a groove to another height between the bottom and a side of the pit array. | 2013-03-14 |
20130064054 | INFORMATION RECORDING MEDIUM, AND RECORDING METHOD AND REPRODUCING METHOD THEREOF - An information recording medium in which bottoms of a guide groove and a pit array formed on a disc substrate are allocated on a same flat plane and shaped in flat. Further, in a transition area from a pit array to a guide groove or from a guide groove to a pit array, the information recording medium is provided with an intermediate area composed of a pit array of which height changes from a height between a bottom and a side of a groove to another height between the bottom and a side of the pit array. | 2013-03-14 |
20130064055 | Copy Protection System for Data Carriers - A copy-protected compact disc includes, within a single session, a table of contents (TOC) and a Video CD index (VI). Each track (T) is prefaced by unrecoverable data (UD) at a track start position (ATOC) indicated by the table of contents (TOC). However, the Video CD index (VI) indicates the actual position (AP) of the tracks. DVD players use the Video CD index (VI) to locate the tracks, while the CD-ROM drives use the table of contents (TOC) and read the unrecoverable data (UD), which prevents them from reading the subsequent track (T). The unrecoverable data (UD) may be prefaced by data pointers (DP) which cause the CD-ROM drive to load a player program in response to the error condition. The player program can be used to play the tracks (T), but restricts copying. Subchannel data (P; DX) causes audio CD players to ignore the Video CD index (VI) and the unrecoverable data (UD), and to play the tracks (T) at their actual start positions (AP). | 2013-03-14 |
20130064056 | METHOD APPLYING A PULSED LASER BEAM FOR READING OF AN OPTICAL DISC AND RESPECTIVE APPARATUS - Method for reading data from an optical disc comprising a substrate layer, a read-only data layer, and a nonlinear layer with a super-resolution structure disposed on the data layer, the read-only data layer including diffractive pits and lands having a length larger than the diffraction limit of the pickup and super-resolution pits and lands having a length smaller than the diffraction limit of the pickup, the method comprising the steps of using a pickup including a laser for providing a HF signal for retrieving of the data of the data layer, providing a constant laser power for retrieving of the data, and pulsing the laser at the end of a diffractive pit or land. The Apparatus comprises a pickup with a laser and a comparator responsive to a threshold level and to the HF signal, for providing a trigger signal for pulsing of the lamer. | 2013-03-14 |
20130064057 | OBJECTIVE LENS, OPTICAL HEAD, OPTICAL DISK DEVICE, AND INFORMATION PROCESSING DEVICE - A disclosed objective lens includes: a lens having an entrance surface and an emission surface; and an anti-reflection coat formed on the emission surface, wherein a transmittance T | 2013-03-14 |
20130064058 | OPTICAL DISC APPARATUS - An optical disc apparatus includes a focus controller including a first digital filter, tracking controller including a second filter, focus actuator driver, tracking actuator driver, defect detector for detecting a defect on an optical disc, and a system controller for controlling the focus controller, the tracking controller and the defect detector. The system controller holds an input and output of at least one of either the focus controller or the tracking controller on the basis of the output of the defect detector, and sets an initial value in a delay memory of the digital filter of the controller held upon awake of the hold state. | 2013-03-14 |
20130064059 | OPTICAL DISK LIBRARY DEVICE AND OPTICAL DISK DEVICE SELECTING METHOD - In an optical disk library device using a plurality of optical disk devices, before optical disk devices execute recording or reproduction of information to or from optical disks, self-monitoring information is acquired from an optical disk monitor, use preferential orders of the optical disk devices are evaluated on the basis of use frequency information or deterioration information included in the self-monitoring information and an optical disk device to be used for recording or reproduction of information is selected on the basis of the use preferential orders. | 2013-03-14 |
20130064060 | METHOD AND APPARATUS FOR DETERMINING A LOCATION OF A FEATURE ON A STORAGE MEDIUM - A change in a property of a signal is detected, the signal having been sensed from a storage medium by a disk drive. A count is determined, the count corresponding to a first location on the storage medium at which the change in the property of the signal sensed from the storage medium is detected. The count is used to predict a second location on the storage medium corresponding to the change in the property of the signal sensed from the storage medium. Relative to the first location on the storage medium, the second location on the storage medium is closer to an actual location of a feature on the storage medium that causes the change in the property of the signal sensed from the storage medium. | 2013-03-14 |
20130064061 | MARK FORMING APPARATUS AND MARK FORMING METHOD - Provided is a mark forming apparatus including a head unit that forms a mark on a recording medium through laser beam irradiation based on a laser driving pulse, a control signal generation unit that generates a control signal at a start timing of the laser driving pulse supplied to the head unit, a multiplier that multiples a synchronization reference signal used to synchronize with the process of forming the mark on the recording medium in the head unit to generate a multiple signal, and a laser driving pulse generation unit that generates the laser driving pulse by setting the start timing of the laser driving pulse at resolution based on the multiple signal in accordance with the control signal. | 2013-03-14 |
20130064062 | STORAGE DEVICE - A storage device includes a storage medium and a plurality of probes. The probes each have a recording/reproducing portion. The probes include a first probe, a second probe spaced from the first probe in a first direction, and a third probe spaced from the first probe in the first direction and in a second direction different from the first direction. A distance X | 2013-03-14 |
20130064063 | MASTER DISC HAVING A PTM LATER AND A NICKEL UNDERCOAT - The invention provides a master disc comprising a stack of a substrate, a phase transition material layer, a heat absorption layer provided between the substrate and the phase transition layer, and an anisotropic heat sink layer provided between the substrate and the absorption layer. Further, a method of manufacturing a master disc is provided. A stack having an upper side and a lower side is provided, wherein the stack comprises a substrate provided at the lower side of the stack, a phase transition material layer, a heat absorption layer provided between the substrate and the phase transition layer, and an anisotropic heat sink layer provided between the substrate and the absorption layer. The upper side of the stack is exposed to a laser beam and developed. | 2013-03-14 |