11th week of 2009 patent applcation highlights part 62 |
Patent application number | Title | Published |
20090070500 | Sharing of data between devices - The invention relates to the sharing of data between a first and a second device. A data transmission connection is set up between the devices to adapt the devices and to share data between the devices. The second device comprises an adapter program which adapts the first device to the second device on the basis of the setting data of the first device. The setting data of the first device are arranged in the first device, wherein the setting data are transmitted to the second device to implement the adaptation. | 2009-03-12 |
20090070501 | DATA PROCESSOR - A format converter includes a first input buffer for storing input data, an output buffer for storing output data, a converter connected between the first input buffer and the output buffer, and a register that the converter refers to. The register allows plural kinds of conversion patterns to be defined in conformity with a desired data format conversion. The converter generates the output data based on the input data, in accordance with the conversion pattern defined in the register. | 2009-03-12 |
20090070502 | Data Modification Module - The present invention relates to a microcontroller including a central processing unit, a storage location, a bus coupling the storage location to the central processing unit, and a data modification module for modifying data in the storage location. The data modification module includes a first interface being coupled to the bus for transferring data to the storage location over the bus, and a second interface being adapted to be coupled to an external device for receiving the data, wherein the data modification module is adapted to operate as a bus master and to transfer data received from the external device over the bus to the storage location. | 2009-03-12 |
20090070503 | CAPACITIVE MULTIDROP BUS COMPENSATION - The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate. | 2009-03-12 |
20090070504 | Multi-Protocol Bus Device - In one general aspect, methods and devices for use with multiple communications protocols automatically determine which communications protocol to use when connected to a system bus. Signals transmitted on the system bus are monitored to determine what communications protocol the system bus is using. After determining which communications protocol the system is using, a compatible communications protocol is selected from one of several communications protocols stored in a device's memory. As a result, a user may connect a device to the system bus without having to determine which communications protocol is used by the system bus. Furthermore, suppliers may stock a single type of device that is compatible with multiple communications protocols reducing overhead associated with stocking devices. In addition, a device may be switched between systems without regard to the communications protocol of the device or system. | 2009-03-12 |
20090070505 | Method For Exchanging Information Between Devices Connected Via A Communication Link - A method for exchanging information between a first device and a second device connected via a communication link, the communication link supporting a query command and at least a further command, where each command includes a specific command code is described. The method comprises transmitting a query command code and data from the first device via the communication link, the data identifying a specific command, receiving the query command code and the data at the second device, transmitting reply data from the second device via the communication link, the reply data including at least a first segment and a second segment, and receiving the reply data at the first device, wherein the first segment includes information whether the specific command is supported, wherein, if the specific command is not supported, the second segment includes information identifying an alternative command to the specific command. | 2009-03-12 |
20090070506 | ELECTRONIC SYSTEM AND METHOD - A method operating an electronic system including sending or receiving a signal is disclosed. One embodiment includes changing a parameter of a signal from a first value to a second value after a first time duration if a logic zero is to be transmitted, and changing the parameter of the signal from the first value to the second value after a second time duration if a logic one is to be transmitted. | 2009-03-12 |
20090070507 | Back-Off Timing Mechanism - Systems and methods for implementing back-off timing for retries of commands sent from a master device to a slave device over a split-transaction bus. One embodiment includes a buffer having entries for storing each pending command and associated information, including a number of retries of the command and a static pseudorandom timer expiration value. The timer expiration value of each entry is compared to a running counter according to a mask associated with the number of retries of the command corresponding to the entry. When the unmasked bits of the two values match, the command is retried. In one embodiment, the same portion of the buffer entry that is used to store the number of retries and the timer expiration value is alternately used to store a slave-generated tag that is received with an acknowledgment response. | 2009-03-12 |
20090070508 | COMMUNICATION DEVICE AND METHOD FOR SETTING DEVICE RESOURCES - A communication device including a memory configured to store a plurality of device resource profiles, wherein each device resource profile specifies device resources of the communication device and is associated with a respective communication connection state of a plurality of communication connection states; a determining circuit configured to determine a communication connection state of a communication connection of the communication device; and a control circuit configured to set device resources of the communication device in accordance with the device resource profile associated with the communication connection state of the communication connection. | 2009-03-12 |
20090070509 | Method of detecting and protecting falling portable computer hard disk through software monitoring driver - In a method of detecting and protecting a hard disk of a falling portable computer, a falling sensor detects a falling state of a portable computer and sends an interrupt signal to a keyboard controller of the computer, and a falling state signal is responded at a default signal port of the keyboard controller. A software monitoring driver executes polling via an I/O driver about the falling state signal at the default signal port of the keyboard controller, and determines based on the falling state signal whether to actuate a hard disk protection mechanism, in which the software monitoring driver interrupts hard disk data access on the computer via a hard disk driver, and causes a system BIOS of the computer to send a parking control signal to the hard disk. | 2009-03-12 |
20090070510 | PROCESSOR SELECTION FOR AN INTERRUPT BASED ON WILLINGNESS TO ACCEPT THE INTERRUPT AND ON PRIORITY - In some embodiments, an apparatus includes processors, signal storage circuitry, and processor selection logic. The signal storage circuitry is to hold willingness indication signals each indicative of a willingness level of an associated one of the processors to receive an interrupt and to hold priority indication signals each indicative of a processor priority level of an associated one of the processors, wherein there are multiple possible willingness levels and multiple possible processor priority levels. The processor selection logic is to select one of the processors to receive an interrupt based at least on the willingness indication signals. Other embodiments are described. | 2009-03-12 |
20090070511 | PROCESSOR SELECTION FOR AN INTERRUPT IDENTIFYING A PROCESSOR CLUSTER - In some embodiments, an apparatus includes processor selection logic to receive logical destination identification numbers that are associated with interrupts each having a processor cluster identification number to identify a cluster of processors to which the interrupts are directed. The logical destination identification numbers are each to identify which processors within the identified cluster of processors are available to receive the corresponding one of interrupts. The processor selection logic is to select one of the available processors to receive the interrupt, and the selected one of the available processors is identified through a relative position of a corresponding bit in the logical destination identification numbers. Other embodiments are described. | 2009-03-12 |
20090070512 | Apparatus for determining compatibility between devices - Embodiments are generally directed to an apparatus for determining compatibility between devices. In one embodiment, a table including a module's parameters and rules associated therewith is obtained from a module. The rules are applied to a slot's parameters to determine the module's compatibility with the slot upon coupling to the slot. | 2009-03-12 |
20090070513 | Method and Apparatus for Distributed Direct Memory Access for Systems on Chip - A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory. | 2009-03-12 |
20090070514 | PROGRAMMABLE CONTROLLER - In a programmable controller including a special unit, a special-purpose integrated circuit element can be readily utilized for multiple purposes to extend the range of applications to reduce a manufacture cost. A special unit ( | 2009-03-12 |
20090070515 | PHY-LESS ULPI AND UTMI BRIDGES - Embodiments of the present invention provide a unique capability of implementing a pair of pseudo-PHY interfaces using a bridge. From the host and device perspectives, the host and device communicate through a PHY interface. The bridge, however, avoids actually using a USB PHY interface. This PHY-less bridge allows communication between a host and a device at high speeds without high-power transceivers associated with a USB PHY interface. In accordance with the present invention, a host and a device may be coupled together using a PHY-less bridge using the same interface or translating between different interfaces by using a wrapper. Such PHY-less bridges include a UTMI-to-UTMI bridge, a UTMI-to-ULPI bridge, a ULPI-to-UTMI bridge and a ULPI-to-ULPI bridge, each avoiding the need for a USB PHY interface. | 2009-03-12 |
20090070516 | INTEGRATED MEMORY CONTROL APPARATUS - An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory. | 2009-03-12 |
20090070517 | MEMORY APPARATUS, MEMORY CONTROL METHOD, AND PROGRAM - Disclosed herein is a memory apparatus comprising: a nonvolatile memory configured to allow data to be written thereto and read therefrom in units of a cluster and to permit data to be deleted therefrom in units of a block made up of a plurality of sectors; a control circuit configured to control access operations to said nonvolatile memory; a management area; a user data area; and a cache area; said management area includes a logical/physical table, and the addresses of physical blocks in said cache area. | 2009-03-12 |
20090070518 | Adaptive Block List Management - In a nonvolatile memory array, selected blocks are maintained as open blocks that are available to store additional data without being erased first. Nonsequential open blocks are selected from two lists, one list based on recency of the last write operation, and the other list based on frequency of writes to the block. Sequential open blocks are divided into blocks expected to remain sequential and blocks that are not expected to remain sequential. | 2009-03-12 |
20090070519 | SYSTEM AND METHOD FOR SECURE DOCUMENT PROCESSING USING REMOVABLE DATA STORAGE - The subject application is directed to a system and method for secure document processing. A removable storage, such as a flash drive, magnetic storage, IC card, is installed in document processing device. A selected document processing operation, such as copying, scanning, and the like, is then performed. Data files resultant from the selected document processing operations are directed to the removable storage for being stored temporary, instead of being sent to the storage inherent to the document processing device. Data files temporary stored in the removable storage are then deleted. | 2009-03-12 |
20090070520 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR STORAGE DEVICE - In a semiconductor storage device, a memory controller divides each of blocks in each of chips into a first page set composed of pages and a second page set composed of pages, divides a logical address space into groups, and divides each group into lines. Block units are created each of which is obtained by assembling a predetermined number of blocks from the blocks in each chip. A predetermined number of block units from the block units are managed as standard block units, and the other block units are managed as spare block units. Each standard block unit is made to correspond to one group. The corresponding group data is stored in the pages in the first page set in each block constituting the standard block unit, and unwritten pages for recording update data for the group data are provided to be included in the second page set. | 2009-03-12 |
20090070521 | WRITE ABORT AND ERASE ABORT HANDLING - A portion of a nonvolatile memory array that is likely to contain, partially programmed data may be identified from a high sensitivity read, by applying stricter than usual ECC requirements, or using pointers to programmed sectors. The last programmed data may be treated as likely to be partially programmed data. Data in the identified portion may be copied to another location, or left where it is with an indicator to prohibit further programming to the same cells. To avoid compromising previously stored data during subsequent programming, previously stored data may be backed up. Backing up may be done selectively, for example, only for nonsequential data, or only when the previously stored data contains an earlier version of data being programmed. If a backup copy already exists, another backup copy is not created. Sequential commands are treated as a single command if received within a predetermined time period. | 2009-03-12 |
20090070522 | METHOD AND APPARATUS FOR CASCADE MEMORY - A system and method of operating a cascade of a plurality of memory devices connected in series is disclosed. In one aspect, there is a memory controller operatively connected to the memory cell and a cascade circuit configured to enable a subsequent memory device in a cascade of memory devices. | 2009-03-12 |
20090070523 | Flash memory device storing data with multi-bit and single-bit forms and programming method thereof - A flash memory device may include a memory cell array including a plurality of memory blocks and a partition information block, the partition information block storing partition information that indicates a boundary between multi-bit memory blocks and single-bit memory blocks among the memory blocks. The memory device may include a control logic configured to determining whether a memory block that a block address from the outside indicates has a multi-bit form or a single-bit form based on the partition information and to control program and read operations in a multi-bit form or a single-bit form based on a determination result. The control logic automatically programs data in the partition information block according to whether a fuse connected to the control logic fuse is cut or not, the data being used for preventing the partition information block from being programmed or erased. | 2009-03-12 |
20090070524 | NON-SNOOP READ/WRITE OPERATIONS IN A SYSTEM SUPPORTING SNOOPING - Techniques that may utilize generic tracker structures to provide data coherency in a multi-node system that supports non-snoop read and write operations. The trackers may be organized as a two-dimensional queue structure that may be utilized to resolve conflicting read and/or write operations. Multiple queues having differing associated priorities may be utilized. | 2009-03-12 |
20090070525 | SEMICONDUCTOR MEMORY DEVICE - A CAM (Content Addressable Memory) cell includes first and second data storage portions storing data, horizontal port write gates for storing data applied through a match line pair in the data storage portions in a data write through a horizontal port, and search/read gates for driving the match lines of the match line pair in accordance with the data stored in the data storage portions in a search operation and in a data read through the horizontal port. The match lines are used as horizontal bit line pair, or signal lines for accessing the horizontal port. As the first and second data storage portions are used, it becomes possible to store ternary data, and accordingly, a write mask function of inhibiting a data write at a destination of data transfer is realized. Further, as the CAM cell is used, an arithmetic/logic operation following a search process can be executed selectively, and high speed data writing/reading becomes possible. | 2009-03-12 |
20090070526 | USING EXPLICIT DISK BLOCK CACHEABILITY ATTRIBUTES TO ENHANCE I/O CACHING EFFICIENCY - A data caching method comprising identifying whether data stored in a first data block on a storage medium is cacheable; setting a first cacheability attribute associated with the first data block in a data structure to identify whether the data in the first data block is cacheable; monitoring I/O requests submitted for accessing target data in the first data block; determining whether the target data is cacheable based on the first cacheability attribute; and applying algorithms that implement cache policy to the target data, in response to determining that the target data is cacheable. | 2009-03-12 |
20090070527 | USING INTER-ARRIVAL TIMES OF DATA REQUESTS TO CACHE DATA IN A COMPUTING ENVIRONMENT - A data caching method comprising monitoring read and write requests submitted for accessing target data in a first data block on a storage medium; identifying a sequence of access requests for target data as a first stream; and determining whether the first stream is suitable for direct disk access based on inter-arrival times of the read or write requests in the stream. | 2009-03-12 |
20090070528 | APPARATUS, SYSTEM, AND METHOD FOR INCREMENTAL RESYNCHRONIZATION IN A DATA STORAGE SYSTEM - An apparatus, system, and method are disclosed for performing an incremental resynchronization between two unrelated volumes when a third volume fails. The apparatus, system, and method include initiating registration of changed tracks; keeping track of bytes in flight activities between a local volume and an intermediate volume; recording the changed tracks in bitmaps at the local volume; stopping the recording of the changed tracks; and starting a resynchronization process by sending the changed tracks to a recovery volume. | 2009-03-12 |
20090070529 | DATA PROTECTION AFTER POSSIBLE WRITE ABORT OR ERASE ABORT - A portion of a nonvolatile memory array that is likely to contain, partially programmed data may be identified from a high sensitivity read, by applying stricter than usual ECC requirements, or using pointers to programmed sectors. The last programmed data may be treated as likely to be partially programmed data. Data in the identified portion may be copied to another location, or left where it is with an indicator to prohibit further programming to the same cells. To avoid compromising previously stored data during subsequent programming, previously stored data may be backed up. Backing up may be done selectively, for example, only for nonsequential data, or only when the previously stored data contains an earlier version of data being programmed. If a backup copy already exists, another backup copy is not created. Sequential commands are treated as a single command if received within a predetermined time period. | 2009-03-12 |
20090070530 | STORAGE SYSTEM AND REPLICATION CREATION METHOD THEREOF - In a storage system having a plurality of control units each connected with a plurality of disk units, it is provided that a replication is created in the volume of the disk units connected to different control units. The replication creation unit of a given control unit creates a replication in the volume of the disk unit connected to other control units in such a manner that the original volume information, the replication volume information in the control unit and information on the other control units are registered as volume pair information. Based on this volume pair information, a replication creation request is transmitted to the other control units. | 2009-03-12 |
20090070531 | System and Method of Using An N-Way Cache - A system and method of using an n-way cache are disclosed. In an embodiment, a method includes determining a first way of a first instruction stored in a cache and storing the first way in a list of ways. The method also includes determining a second way of a second instruction stored in the cache and storing the second way in the list of ways. In an embodiment, the first way may be used to access a first cache line containing the first instruction and the second way may be used to access a second cache line containing the second instruction. | 2009-03-12 |
20090070532 | System and Method for Efficiently Testing Cache Congruence Classes During Processor Design Verification and Validation - A system and method for using a single test case to test each sector within multiple congruence classes is presented. A test case generator builds a test case for accessing each sector within a congruence class. Since a congruence class spans multiple congruence pages, the test case generator builds the test case over multiple congruence pages in order for the test case to test the entire congruence class. During design verification and validation, a test case executor modifies a congruence class identifier (e.g., patches a base register), which forces the test case to test a specific congruence class. By incrementing the congruence class identifier after each execution of the test case, the test case executor is able to test each congruence class in the cache using a single test case. | 2009-03-12 |
20090070533 | Content network global replacement policy - This invention is related to content delivery systems and methods. In one aspect of the invention, a content provider controls a replacement process operating at an edge server. The edge server services content providers and has a data store for storing content associated with respective ones of the content providers. A content provider sets a replacement policy at the edge server that controls the movement of content associated with the content provider, into and out of the data store. In another aspect of the invention, a content delivery system includes a content server storing content files, an edge server having cache memory for storing content files, and a replacement policy module for managing content stored within the cache memory. The replacement policy module can store portions of the content files at the content server within the cache memory, as a function of a replacement policy set by a content owner. | 2009-03-12 |
20090070534 | MEMORY ACCESS MONITORING APPARATUS AND RELATED METHOD - A memory access controlling apparatus, for monitoring an access of a memory to generate a target watch signal, includes: at least one monitoring circuit, a setting unit and an output circuit. The monitoring circuit corresponds to an address of the memory and holds an access setting value. The monitoring circuit monitors the access of the memory according to the access setting value to generate an initial watch signal. The setting unit holds a setting value for triggering an exception, which is related to a condition for triggering the exception while the memory is accessed. The output circuit is coupled to the monitoring circuit and the setting unit, and is used for generating the target watch signal according to the initial watch signal and the setting value. | 2009-03-12 |
20090070535 | HANDLING TEMPORARY FILES IN A FILE SYSTEM WITH SNAPSHOTS - A temporary file is identified. The temporary file includes a data block containing a first file image. A determination is made whether the temporary block has been included in a previous snapshot. Responsive to receiving a modification of the temporary block that has been included in the previous snapshot, a modified first image is created. The modified image is stored in the original file block, and the original image is copied to a newly allocated block. The original first block is updated to include a reference to the second block. | 2009-03-12 |
20090070536 | Managing snapshots using messages - A method and apparatus for managing snapshots of a file system using messages. A snapshot is a restorable version of a file system created at a predetermined point in time. A message is a persistent data structure supported by a file server. A message may include one or more snapshots, attributes for the message, and/or access control information for the message. The attributes and access control information are applied to all snapshots in the message. The attributes in the message enable users to perform automatic event-based management of the snapshots in the message. The access control information in the message provides granular access control to the snapshots in the message. | 2009-03-12 |
20090070537 | METHOD AND APPARATUS FOR FORMATTING STORAGE MEDIUM - A method for formatting a storage medium. The method includes saving management information associated with data that is to be protected from the formatting, the management information indicating where the data to be protected is stored, formatting a management information area of the storage medium where the management information is stored, and recovering the saved management information to the management information area of the storage medium such that the data to be protected is accessible. | 2009-03-12 |
20090070538 | STORAGE SYSTEM AND METHOD FOR ACQUISITION AND UTILIZATION OF SNAPSHOTS - A computer system including: disk array system to cause a snapshot corresponding to the selected backup time accessible with the specific address to which the computer can access; wherein if the snapshot corresponding to the selected backup time is associated with the specific address to which the computer cannot access, then the disk array system making the snapshot accessible with an address to which the computer can access; and wherein the snapshot relates to differential data between initial backup data and actual backup data at the selected backup time, thereby an acquisition time of the snapshot is different than the selected backup time corresponding to the specific address that can be accessed initially by the computer. | 2009-03-12 |
20090070539 | Automated File Recovery Based on Subsystem Error Detection Results - The present invention provides a method and system for performing file recovery in a computer system coupled to a storage subsystem, wherein a data scrubbing process analyzes said storage subsystem for potential or existing storage errors. The method includes: receiving a report from said data scrubbing process describing said errors, including logical block addresses (LBAs) of storage locations containing errors; interacting with a file system created on logical unit numbers (LUN) provided by said storage subsystem in order to identify file information pertaining to the erroneous LBAs; moving the file pertaining to said erroneous LBAs to a different storage location; updating pointers to said file; in case of an unrecoverable, accessing a backup copy of said file from a backup location; if a predetermined degree of error severity is exceeded, creating an additional copy of said file; and updating the pointers to said file managed by the file system, respectively. | 2009-03-12 |
20090070540 | Receiving Apparatus, Receiving Method, Transmitting Apparatus, Transmitting Method, and Medium - A receiving apparatus has a first memory area accessible by a first provider providing first contents and a second memory area accessible by a second provider providing second contents. A receiving unit receives a first access right file and a second access right file. An output unit outputs the first contents or the second contents. A memory control unit stores first information associated with the first contents in the first memory area and stores second information associated with the second contents in the second memory area. A switching unit switches from outputting the first contents to outputting the second contents. A determining unit determines whether the second provider is permitted to access the first memory area. An output controller reads the first information and outputs the second contents based on the first information to the output unit when the second provider is permitted to access the first memory area. | 2009-03-12 |
20090070541 | Automated information life-cycle management with thin provisioning - A system for managing data includes providing at least one logical device having a table of information that maps sections of the logical device to sections of at least two storage areas. Characteristics of data associated with at least one section of the logical device may be evaluated. The at least one section of the data may moved between the at least two storage areas according to a policy and based on the characteristics of the data. The table of information is updated according to the movement of data between the at least two storage areas. | 2009-03-12 |
20090070542 | METHOD TO DIVIDE A FILE OR MERGE FILES USING FILE ALLOCATION TABLE (FAT) - A method to divide a file or merge files using a file allocation table (FAT) in which the method to divide a file includes storing data of a first cluster, among data intended to be separated from the file, into a second cluster, and generating a first cluster chain and a second cluster chain using a file allocation table (FAT), the first cluster chain containing data remaining in the first cluster, and the second cluster containing data existing in the second cluster. As a result, time delay due to a file copy process and shortening of a lifespan of NAND flash are prevented, and a reserve capacity for editing purposes is minimized. | 2009-03-12 |
20090070543 | DATA COMPRESSION/DECOMPRESSION APPARATUS AND METHOD - A data compression/decompression apparatus and method is provided for improving memory utilization. A data compression/decompression apparatus of the present invention includes a compressor for calculating costs of domain blocks to a range block through forward searching in a search range, for selecting the domain block having the lowest cost to the range block as a reference domain block through backward searching, for generating distance and difference information of the reference domain block, and for encoding the distance and difference information into compressed data of the range block and a decompressor for finding the reference domain block on the basis of the distance and for decoding the compressed data into original data of the range block with reference to the difference information. | 2009-03-12 |
20090070544 | Microcontrollers with instruction sets - A microcontroller includes a plurality of primary registers, a secondary register and a central processing unit (CPU). The primary registers store a plurality of primary data respectively. Each primary data has a first width. The secondary register includes the plurality of primary registers and stores a secondary data having a second width. The secondary data includes a combination of the plurality of primary data. The CPU executes a first instruction in a first mode in which a primary data is fetched for operation and executes a second instruction in a second mode in which the secondary data is fetched for operation. | 2009-03-12 |
20090070545 | PROCESSING SYSTEM IMPLEMENTING VARIABLE PAGE SIZE MEMORY ORGANIZATION USING A MULTIPLE PAGE PER ENTRY TRANSLATION LOOKASIDE BUFFER - A processing system includes memory management software responsive to changes in a page table to consolidate a run of contiguous page table entries into a page table entry having a larger memory page size. The memory management software determines whether the run of contiguous page table entries may be cached using the larger memory page size in an entry of a translation lookaside buffer. The translation lookaside buffer may be a MIPS-like TLB in which multiple page table entries are cached in each TLB entry. | 2009-03-12 |
20090070546 | System and Method for Generating Fast Instruction and Data Interrupts for Processor Design Verification and Validation - A system and method for intentionally invaliding translation entry valid bits in order to provoke storage interrupts when executing a test case is presented. Prior to executing the test case, an interrupt handler pseudo-randomly invalidates a number of translation entries included in a translation lookaside buffer (TLB) by changing particular valid bits in order to provoke initial storage interrupts, such as an instruction storage interrupt (ISI) or a data storage interrupt (DSI). Once the processor executes the test case that, in turn, triggers a storage interrupt, the interrupt handler uses an index counter to validate particular valid bits and invalidate other valid bits, thus provoking subsequent storage interrupts. In one embodiment, the interrupt handler also changes valid bits in a page table when the processor executes in a mode that accesses the page table in addition to the TLB. | 2009-03-12 |
20090070547 | METHOD AND APPARATUS FOR PERFORMING ADDRESS MAPPING IN VIRTUAL FILE SYSTEM OF STORAGE UNIT HAVING A PLURALITY OF NON-VOLATILE DATA STORAGE MEDIA - Provided are a method and apparatus capable of reducing a metadata processing time associated with address mapping performed to input/output burst data at a high speed in a virtual file system of a storage unit having a plurality of non-volatile data storage media. The method includes: determining a block group including a block included in each of a plurality of the non-volatile data storage media; determining an access unit including each page included in the determined block group; and mapping an address of input/output data to the determined block group and the access unit. Therefore, it is possible to significantly reduce an address mapping processing time in the virtual file system that may function as a bottleneck in high-speed input/output in a large-capacity storage unit. | 2009-03-12 |
20090070548 | Programming a Digital Processor with a Single Connection - A digital processor is coupled to a processor programmer through a single programming connection (e.g., terminal, pin, etc.) coupled to the single conductor programming bus. The processor programmer comprises an instruction encoder/decoder, a Manchester encoder, a Manchester decoder, a bus receiver and a bus transmitter. The digital processor comprises an instruction encoder/decoder, a Manchester encoder, a Manchester decoder, a bus receiver, a bus transmitter, a central processing unit (CPU), and a program memory. The instruction encoder/decoder is coupled to the CPU and the program memory. The bus receivers and bus transmitters are coupled to the single conductor programming bus which is coupled to a connection, e.g., terminal, pin, ball, etc., on an integrated circuit package containing the digital processor. The instruction encoder/decoder is coupled to a programming console, e.g., a personal computer, workstation, etc. | 2009-03-12 |
20090070549 | Interconnect architecture in three dimensional network on a chip - The connection architecture of a network on a chip (NoC) is described in which (a) nodes in octahedron sections are connected in an arc Benes network, (b) a hierarchy of node clusters are connected using a globally asynchronous locally asynchronous (GALA) configuration, (c) a double wishbone 2D torus ring is applied to connection between network layers and (d) data is routed using buffer modulation. | 2009-03-12 |
20090070550 | Operational dynamics of three dimensional intelligent system on a chip - The invention pertains to a 3D intelligent SoC. The self-regulating data flow mechanisms of the 3D SoC are elucidated, particularly parallelization of multiple asynchronous 3D IC nodes and reconfigurable components. These behavioral mechanisms are organized into a polymorphous computing architecture with plasticity functionality. Software agents are employed for reprogrammable 3D SoC network operability. Metaheuristic algorithms are applied to solving MOOPs in the 3D SoC for continuous reprogrammability for multiple application environments. | 2009-03-12 |
20090070551 | CREATION OF LOGICAL APIC ID WITH CLUSTER ID AND INTRA-CLUSTER ID - In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described. | 2009-03-12 |
20090070552 | RECONFIGURABLE MULTI-PROCESSING COARSE-GRAIN ARRAY - A signal processing device adapted for simultaneous processing of at least two process threads in a multi-processing manner is disclosed. In one embodiment, the device comprises a plurality of functional units capable of executing word- or subword-level operations on data. The device further comprises means for interconnecting the plurality of functional units, the means for interconnecting supporting a plurality of dynamically switchable interconnect arrangements, and at least one of the interconnect arrangements interconnects the plurality of functional units into at least two non-overlapping processing units each with a pre-determined topology. The device further comprises at least two control modules each assigned to one of the processing units. | 2009-03-12 |
20090070553 | DISPATCH MECHANISM FOR DISPATCHING INSTURCTIONS FROM A HOST PROCESSOR TO A CO-PROCESSOR - A dispatch mechanism is provided for dispatching instructions of an executable from a host processor to a heterogeneous co-processor. According to certain embodiments, cache coherency is maintained between the host processor and the heterogeneous co-processor, and such cache coherency is leveraged for dispatching instructions of an executable that are to be processed by the co-processor. For instance, in certain embodiments, a designated portion of memory (e.g., “UCB”) is utilized, wherein a host processor may place information in such UCB and the co-processor can retrieve information from the UCB (and vice-versa). The UCB may thus be used to dispatch instructions of an executable for processing by the co-processor. In certain embodiments, the co-processor may comprise dynamically reconfigurable logic which enables the co-processor's instruction set to be dynamically changed, and the dispatching operation may identify one of a plurality of predefined instruction sets to be loaded onto the co-processor. | 2009-03-12 |
20090070554 | Register File System and Method for Pipelined Processing - The present disclosure includes a multi-threaded processor that includes a first register file associated with a first thread and a second register file associated with a second thread. At least one hardware resource is shared by the first and second register files. In addition, the first thread may have a pipeline access position that is non-sequential to the second thread. A method of accessing a plurality of register files is also disclosed. The method includes reading data from a first register file while concurrently reading data from a second register file. The first register file is associated with a first instruction stream and the second register file is associated with a second instruction stream. The first instruction stream is sequential to the second instruction stream in an execution pipeline of a processor, and the first register file is in a non-adjacent location with respect to the second register file. | 2009-03-12 |
20090070555 | DEVICE AND METHOD FOR FINDING EXTREME VALUES IN A DATA BLOCK - A method for locating an extreme value data chunk within a data block, the method includes: fetching, by a processor, an instruction; fetching, in response to a content of the instruction, a data unit that comprises multiple data chunks; selectively masking the fetched data chunks in response to a value of a mask; comparing, by a hardware accelerator, between values of valid data chunks to provide a extreme value data chunk; wherein valid data chunks include un-masked data chunks that belong to the data block; updating the value of the mask and jumping to the stage of fetching a new data unit, until the whole data block is fetched. | 2009-03-12 |
20090070556 | STORE STREAM PREFETCHING IN A MICROPROCESSOR - In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The prefetch engine determines whether to allocate an entry in the prefetch queue corresponding to the store instruction by comparing entries in the queue to a window of addresses encompassing multiple cache blocks, where the window of addresses is derived from the received address. The prefetch engine compares entries in the prefetch queue to a window of 2 | 2009-03-12 |
20090070557 | PARALLEL PROGRAM EXECUTION OF COMMAND BLOCKS USING FIXED BACKJUMP ADDRESSES - The invention relates to a method for executing instructions in a processor, according to which an instruction to be executed of a program memory is addressed by a program control unit by means of a program counter reading of a program counter that operates in said unit. The addressed instruction is then read out, decoded and executed by the program control unit. The program control unit additionally stores the current program counter reading and the number of successive instructions when a jump instruction occurs in the form of a block instruction, according to which a specific number of instructions are to be executed successively, thus defining the return address after execution. After the last instruction of the instruction block to be executed, the program counter resumes the counting operation from the stored program counter reading. | 2009-03-12 |
20090070558 | MULTIPLEXING PER-PROBEPOINT INSTRUCTION SLOTS FOR OUT-OF-LINE EXECUTION - The present invention provides a probe system and method for multithreaded user-space programs. The system includes an instrumentation module that enables single stepping out of line processing for multithreaded programs, an establish probepoint module that divides up an area of the probed program's memory into a plurality of instruction slots, an ensure slot assigned module that ensures that an instruction slot is assigned to a probepoint, a slot acquisition module that acquires the instruction slot for the probepoint, stealing a slot from another probepoint as needed, and a free slot module that relinquishes the instruction slot owned by the probepoint when the probepoint is being unregistered. | 2009-03-12 |
20090070559 | DATA PROCESSING CIRCUIT WHEREIN FUNCTIONAL UNITS SHARE READ PORTS - A data processing circuit comprises a register file ( | 2009-03-12 |
20090070560 | Method and Apparatus for Accelerating the Access of a Multi-Core System to Critical Resources - A method accelerates access of a multi-core system to its critical resources, which includes preparing to delete a critical node in a critical resource, separating the critical node from the critical resource, and deleting the critical node if the conditions for deleting the critical node are satisfied. An apparatus includes a confirmation module for the node to be deleted and a deletion module to accelerate access of a multi-core system to its critical resources. | 2009-03-12 |
20090070561 | LINK STACK MISPREDICTION RESOLUTION - Illustrative embodiments provide a method for improved link stack misprediction resolution using a rename structure for tracking the link stack processing, in order to quickly resolve link stack corruption from mispredicted function returns. The method comprises establishing a set of physical data structures forming a common pool and an operation control table. Maintaining, within the common pool, a plurality of entries for a plurality of speculative instructions and a plurality of non-speculative instructions. And determining one speculative instruction to be a bad prediction speculative entry, identifying related entries to form a collection, and discarding the collection. | 2009-03-12 |
20090070562 | METHOD AND APPARATUS FOR ASSIGNING THREAD PRIORITY IN A PROCESSOR OR THE LIKE - In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor. | 2009-03-12 |
20090070563 | CONCURRENT PHYSICAL PROCESSOR REASSIGNMENT - Reassignment of a physical processor backing a logical processor is performed concurrently to the operation of the processor. The operating state of one physical processor is loaded on another physical processor, such that the logical processor is backed by a different physical processor. This reassignment is performed concurrent to processor operation and transparent to the operating system. | 2009-03-12 |
20090070564 | METHOD AND SYSTEM OF ALIGNING EXECUTION POINT OF DUPLICATE COPIES OF A USER PROGRAM BY EXCHANGING INFORMATION ABOUT INSTRUCTIONS EXECUTED - Aligning execution point of duplicate copies of a user program by exchanging information about instructions executed. At least some of the exemplary embodiments may be a method of operating duplicate copies of a user program in a first and second processor, allowing at least one of the user programs to execute until retired instruction counter values in each processor are substantially the same, and then executing a number of instructions of each user program. Of the instructions executed, at least some of the instructions are decoded and the inputs of each decoded instruction determined (the decoding substantially simultaneously with executing in each processor). The method further may include exchanging among the processors addresses of decoded instructions and values indicative of inputs of the decoded instructions, determining that an execution point of the user program in the first processor lags with respect to an execution point of the user program in the second processor using at least the addresses of the decoded instructions, and advancing the first processor until the execution point within each user program is substantially aligned. | 2009-03-12 |
20090070565 | METHODS, SYSTEMS, COMPUTER PROGRAMS AND APPARATUS FOR CHANGING A PROCESSOR STATE - Methods, systems, computer programs and apparatus for changing a processor state. In example embodiments of the invention, software porting onto an operating system calls a library routine, which creates an illegal instruction for special values in parameter registers. An illegal instruction exception handler recognizes the illegal instructions for special values in parameter registers, and, upon detecting the illegal instruction, enables or disables an interrupt state of a CPU associated with the system. | 2009-03-12 |
20090070566 | Electronic Device With CPU and Interrupt Relay Stage - An electronic device with a CPU configured to be switched from a low power mode into a higher power mode in response to an interrupt and an interrupt relay coupled between an interrupt generator and the CPU. A functional stage is coupled to the interrupt relay and functionally linked with the interrupt so as to be used during the second mode of the CPU. The interrupt relay relays the received interrupt to the CPU only after a time needed for the functional stage to settle. Power is saved because the CPU is not powered while waiting for the functional stage to settle. | 2009-03-12 |
20090070567 | EFFICIENT IMPLEMENTATION OF BRANCH INTENSIVE ALGORITHMS IN VLIW AND SUPERSCALAR PROCESSORS - An apparatus for implementing branch intensive algorithms is disclosed. The apparatus includes a processor containing a plurality of ALUs and a plurality of result registers. Each result register has a guard input which allows the ALU to write a result to the register upon receipt of a selection signal at the guard input. A lookup table is dynamically programmed with logic to implement an upcoming branching portion of program code. Upon evaluation of the branch conditions of the branching portion of code, the lookup table outputs a selection signal for writing the correct results of the branching portion of code based on the evaluation of the branch condition statements and the truth table programmed into the lookup table to the result register. | 2009-03-12 |
20090070568 | Computation parallelization in software reconfigurable all digital phase lock loop - A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. A multi-stage data stream based processor incorporates a parallel/pipelined architecture optimized to perform data stream processing efficiently. The multi-stage parallel/pipelined processor provides significantly higher processing speeds by combining multiple RCUs wherein input data samples are input in parallel to all RCUs while computation results from one RCU are used by adjacent downstream RCUs. A register file provides storage for historical values while local storage in each RCU provides storage for temporary results. | 2009-03-12 |
20090070569 | BRANCH PREDICTION DEVICE,BRANCH PREDICTION METHOD, AND MICROPROCESSOR - A branch prediction device predicts a branching probability in which a branch condition of a conditional branch instruction read out from an instruction memory storing an instruction is satisfied. A branch prediction entry part included in the branch prediction device stores prediction information as to whether or not the branch condition of the conditional branch instruction is satisfied. An entry update part included in the branch prediction device predicts the branching probability when the conditional branch instruction is executed next time based on a branch direction and updates the prediction information when the branch condition is satisfied by executing the conditional branch instruction. | 2009-03-12 |
20090070570 | System and Method for Efficiently Handling Interrupts - A system and method for including independent instructions into a test case for intentionally provoking interrupts that may be used in conjunction with an instruction shuffling process is presented. A test case generator builds a test case that includes intentional interrupt instructions, which are constructed to intentionally provoke an interrupt, such as an instruction storage interrupt (ISI), a data storage interrupt (DSI), and alignment interrupt, and/or a program interrupt (PI). When a processor executes the test case and invokes an interrupt to an interrupt handler, the interrupt handler does not resolve the interrupt, but rather increments an instruction address register or a link register and resumes test case execution at an instruction subsequent to the instruction that caused the interrupt. | 2009-03-12 |
20090070571 | NETWORKED PHYSICAL SECURITY ACCESS CONTROL SYSTEM AND METHOD - A distributed networked physical security access control system for controlling a plurality of security access devices comprises a plurality of access server appliances in communication with a primary network. Each access server appliance includes an appliance management module being accessible through a web browser in communication with the primary network. The appliance management module configures the access server appliances to a user specified security configuration. The plurality of access server appliances are in peer-to-peer communication on the primary network to bridge the access server appliances for providing consistency in each of the access server appliances. | 2009-03-12 |
20090070572 | METHOD AND APPARATUS FOR PORTABLE COMPUTING ENVIRONMENT - A method and storage device for enabling a user to carry his or her computing environment with him, including an operating system, GUI preferences, applications, or data. Thus, a user can attach the storage device to a host computer and work on the host computer with its peripherals, while applying the parameters such as operating system and GUI preferences as stored on the device. | 2009-03-12 |
20090070573 | Reliability platform configuration measurement, authentication, attestation and disclosure - A platform configuration measurement device including: a configuration register; means for executing extension processing in which a predetermined operation is performed on a content of the configuration register by using a given additional value, a hash value is obtained by applying a predetermined hash function to a value obtained by the predetermined operation, and the hash value is set for a new content of the configuration register; and measurement extension means for obtaining measured values, corresponding to predetermined components constituting a platform, by sequentially making predetermined measurement on the predetermined components, and for allowing the means for executing extension processing to execute the extension processing using the measured values as the additional values, random extension means is provided for allowing the means for executing extension processing to execute the extension processing using a random value as the additional value. | 2009-03-12 |
20090070574 | Remote diagnostic apparatus - Example apparatus and methods associated with remote diagnostics are described. One apparatus embodiment includes a logic to determine a state of a device associated with a computing platform to which the apparatus is operably connected. The apparatus embodiment may include logic to provide a signal to a remote logic regardless of the state of the computing platform. The apparatus embodiment may also include logic to receive a signal from a remote logic regardless of the state of the computing platform. The apparatus may facilitate actions associated with remote diagnostics including, inventorying add-on devices, controlling add-on device diagnostic execution, and selectively configuring the computing platform based on add-on device diagnostic results. | 2009-03-12 |
20090070575 | MEMORY WITH DATA SYNCHRONIZATION FROM AND FOR A DRIVE CONTROLLER OF A MACHINE - The aim of the invention is to improve the start-up of an electrical machine drive control system comprised of at least one machine ( | 2009-03-12 |
20090070576 | SYSTEM AND METHOD FOR PROVIDING A SECURE COMPUTING ENVIRONMENT - A system and method for providing a secure computing environment to untrusted computer systems is described. A carrier media and an interface are provided, the interface being connectable to a computer to enable communication between the computer and the carrier media. The carrier media encodes a secure computing environment and a boot system, upon connection of the system via the interface to a computer system and booting of the computer system, the boot system is operative to take over the boot process of the computer system and to authenticate the user, wherein upon successful authentication, the boot system is arranged to load the secure computing environment on the computer system, the secure computing environment being configured to prevent predetermined interaction from outside the secure computing environment when it is running. | 2009-03-12 |
20090070577 | SECURING PROPRIETARY FUNCTIONS FROM SCAN ACCESS - An electronic device as described herein implements a scheme to secure a data mapping function from scan access. The protection scheme can be used as a security measure for proprietary lookup tables, secret constants, digitally implemented algorithms, and the like. The electronic device employs a reconfigurable data mapping arrangement that can be reconfigured for a normal operating mode and a scan testing mode. While in the normal operating mode, a normal data mapping arrangement generates valid output data in accordance with the data mapping function. While in the scanning mode, however, a scanning data mapping arrangement generates invalid but testable output data in accordance with a data masking function that conceals, hides, masks, or obfuscates the data mapping function. Using the data masking function in this manner protects the data mapping function against reverse engineering attacks that attempt to derive the data mapping function from scan testing results. | 2009-03-12 |
20090070578 | Methods And Systems For Transmitting Secure Application Input Via A Portable Device - Methods and systems are described for transmitting secure application input via a portable device. In one embodiment, a method includes connecting a portable device to a communication bus of a computing device for exchanging information between the portable device and the computing device. The method further includes connecting the portable device to an input device for exchanging information between the portable device and the input device. The method still further includes transmitting input received from the input device connected to the portable device to the communication bus of the computing device. The input is directed to an application both associated with the portable device and instantiated into a runtime environment of the computing device. The application is further associated with an input component configured for allowing the application to only receive input transmitted via the portable device when the application is instantiated into the runtime environment of the computing device. | 2009-03-12 |
20090070579 | Information processing system and login method - Provided is an information processing system and a login method capable of simplifying login processing and also simplifying the entire configuration of the system. | 2009-03-12 |
20090070580 | Portable electronic file protection system - The portable electronic file protection system includes at least one memory device removably disposed in communicative relation with any one of a plurality of computers. The memory device includes computer readable content contained thereon wherein the content includes electronic file protection software and at least one set of encryption key data. Further, the said electronic file protection software is executable while the memory device is disposed in communicative relation with any one of said plurality of computers. | 2009-03-12 |
20090070581 | SYSTEM AND METHOD FOR CENTRALIZED USER IDENTIFICATION FOR NETWORKED DOCUMENT PROCESSING DEVICES - The subject application is directed to a system and method for centralized user identification for networked document processing devices. A secure communications channel is first established between a document processing device designated as an authentication device and at least one additional document processing device of a plurality of document processing devices. The authentication device then communicates address data to each additional document processing device. Credential data associated with a user of a document processing device is then received. The received credential data is communicated from the document processing device to the authentication device. The user of the document processing is then authenticated in accordance with the received credential data. Authorization data representing the authorization of the user to perform a document processing operation on the document processing device is then communicated to the document processing device from the authentication device according to the completed authentication of the user. | 2009-03-12 |
20090070582 | Secure Network Location Awareness - Secure network location awareness is provided whereby a client is able to use appropriate settings when communicating with an access node of a communications network. In an embodiment a client receives a signed message from the access node, the signed message comprising at least a certificate chain having a public key. In some embodiments the certificate chain may be only a self-signed certificate and in other embodiments the certificate chain is two or more certificates in length. The client validates the certificate chain and verifies the signature of the signed message. If this is successful the client accesses stored settings for use with the access node. The stored settings are accessed at least using information about the public key. In another embodiment the signed message also comprises a location identifier which is, for example, a domain name system (DNS) suffix of the access node. | 2009-03-12 |
20090070583 | SYSTEM AND METHOD FOR SECURE TRANSACTION - Systems and methods for performing a secure transaction provided. In one embodiment, the method includes: reading data on a command token, reading data on a token; encrypting the token data with a key; encrypting an authentication data with a clear text token data; and transmitting the encrypted authentication data with the encrypted token data to a remote device. | 2009-03-12 |
20090070584 | Method for Providing, Distributing and Engraving Digital Data and Associated Distribution Server - The invention relates to a method for engraving digital data received from a remote server. The inventive method consists in acquiring an identifier of a secured disc used for receiving digital data, in transmitting the identifier and a digital data loading instruction to the remote server, in receiving digital date scrambled by at least one second encryption key and second encryption keys by a first encryption key and in engraving scrambled digital data and the second encryption keys on the secured disc. A providing and distributing methods and a distribution server are also disclosed. | 2009-03-12 |
20090070585 | Measurement probe systems for co-ordinate positioning apparatus - A measurement probe, such as a touch trigger measurement probe, is described that comprises a measurement portion for measuring an object and a data transfer portion for receiving data from and/or transmitting data to an associated unit. The measurement device also comprises an authentication module for verifying the authenticity of the associated unit. The authentication module may include a processor for running a one-way hash algorithm. Authenticity may be established using a challenge and response authentication process. | 2009-03-12 |
20090070586 | Method, Device and Computer Program Product for the Encoded Transmission of Media Data Between the Media Server and the Subscriber Terminal - A request is transmitted from a subscriber terminal via a control channel of an access network to an application function for determining a set of encoding parameters. An encoding context is generated by the application function in accordance with the set of encoding parameters. The encoding context is transmitted from the application function to a media server via a control interface of a core network. Either encoded media data are then decoded or unencoded media data are encoded by the media server using the encoding context in such a way that an encoded transmission of media data is carried out between the media server and the subscriber terminal. A network and a computer program are suitable for carrying out the method. | 2009-03-12 |
20090070587 | Advanced Watermarking System and Method - A method, computer program product, and computing device for obtaining an uncompressed digital media data file. One or more default watermarks is inserted into the uncompressed digital media data file to form a watermarked uncompressed digital media data file. The watermarked uncompressed digital media data file is compressed to form a first watermarked compressed digital media data file. The first watermarked compressed media data file is stored on a storage device. The first watermarked compressed media data file is retrieved from the storage device. The first watermarked compressed digital media data file is modified to associate the first watermarked compressed digital media data file with a transaction identifier to form a second watermarked compressed digital media data file. | 2009-03-12 |
20090070588 | RENEWABLE WATERMARK FOR THEATRICAL CONTENT - The present invention relates to a method for a content provider of renewing the watermarking of theatrical content and for updating consumer devices to detect said renewed watermark, wherein a watermark is embedded in said theatrical content using at least a first watermark noise pattern. Renewing is performed by said content provider distributing at least a second watermark noise pattern, which is used for embedding and detecting said watermark in said theatrical content, to said consumer devices using a broadcast encryption technology. The invention further relates to a content provider system adapted to be used for renewing the watermarking of theatrical content and for updating consumer devices to detect said renewed watermark. | 2009-03-12 |
20090070589 | METHOD AND APPARATUS FOR VERIFYING AUTHENTICITY OF DIGITAL DATA USING TRUSTED COMPUTING - A method and apparatus for authenticity and origin of Digital data such as recorded voice samples, video clips or still picture images etc. is provided. The method makes uses of the Trusted Computing principles to provide a secure, tamper detectable solution comprising of both software and hardware such that it can be verified without debate on its authenticity. The method comprises extracting reproduction avoidance key information and log information for captured data from stored information when verification of the captured data is requested, calculating reproduction avoidance key information using the extracted log information, comparing the extracted reproduction avoidance key information with the calculated reproduction avoidance key information and determining that the captured data has not been tampered, if the reproduction avoidance key informations are matched. | 2009-03-12 |
20090070590 | Digital signature and authentication method and apparatus - A signing technique of a disclosed identification/digital signature method hereof uses a mixing system based on multiplication in a ring and reduction modulo an ideal q in that ring, while a disclosed verification technique uses special properties of products of elements whose validity depends on elementary probability theory. The security of the identification/digital signature scheme comes from the interaction of reduction modulo q and the difficulty of forming products with special properties. In an embodiment of the identification/digital signature scheme hereof that employs a quotient ring of polynomials, the security also relies on the experimentally observed fact that for most lattices, it is very difficult to find a vector whose length is only a little bit longer than the shortest vector, and it is also difficult to find a lattice vector that is quite close to a randomly chosen nonlattice vector. | 2009-03-12 |
20090070591 | Grid Mutual Authorization Through Proxy Certificate Generation - A mechanism for mutual authorization of a secondary resource in a grid of resource computers is provided. When a primary resource attempts to offload a grid computing job to a secondary resource, the primary resource sends a proxy certificate request to the user machine. Responsive to a proxy certificate request, the user machine performs authorization with the secondary resource. If authorization with the secondary resource is successful, the user machine generates and returns a valid proxy certificate. The primary resource then performs mutual authentication with the secondary resource. If the authorization with the secondary resource fails, the user machine generates and returns an invalid proxy certificate. Mutual authentication between the primary resource and the secondary resource will fail due to the invalid proxy certificate. The primary resource then selects another secondary resource and repeats the process until a resource is found that passes the mutual authorization with the user machine. | 2009-03-12 |
20090070592 | FINGER SENSING APPARATUS USING ENCRYPTED USER TEMPLATE AND ASSOCIATED METHODS - A finger sensing apparatus may include an integrated circuit (IC) substrate, an array of finger sensing elements on the IC substrate, and encryption circuitry on the IC substrate cooperating with the array of finger sensing elements for encrypting a user template comprising finger template data and at least one user credential. The at least one user credential may enable another device, such as a host platform, to perform at least one protected operation. | 2009-03-12 |
20090070593 | FINGER SENSING APPARATUS USING UNIQUE SESSION KEY AND ASSOCIATED METHODS - A finger sensor apparatus may include a finger sensor having an integrated circuit (IC) substrate, an array of finger sensing elements on the IC substrate, and session key negotiation circuitry on the IC substrate. The finger sensing apparatus may also include a host platform external from the finger sensor and cooperating with the session key negotiation circuitry to negotiate a unique session key for secure communication with the finger sensor during a respective communication session therewith. | 2009-03-12 |
20090070594 | TRANSIENT ON-DEMAND DATA SECURITY CONTROL - The present invention addresses the deficiencies of the art in respect to data security control and provides a method, system and computer program product for securing confidential data through transient on-demand data security control. In one embodiment of the invention, a method of securing confidential data can be provided. The method can include decrypting confidential data in a document, determining a subset of the confidential data specified by an author of the document, rendering a view of the confidential data including the subset, and, in response to detecting when an authorized viewer of the document no longer views the document, concealing the subset of the confidential data while maintaining a view of the confidential data not included in the subset. | 2009-03-12 |
20090070595 | SYSTEM FOR IMPLEMENTING DYNAMIC PSEUDORANDOM KEYBOARD REMAPPING - A system for implementing dynamic pseudorandom keyboard remapping includes a keyboard in communication with an operating system of a computing device; the keyboard configured to encrypt an original keyboard scan code corresponding to each of a plurality of keyboard keys, using a mapping algorithm, wherein the mapping algorithm encrypts the original keyboard scan code by using both the original keyboard scan code and a current one of a sequence of pseudorandom numbers generated using a pseudorandom number generator (PRNG) algorithm and an initial seed value; and the operating system configured to decrypt the original keyboard scan code based on an encrypted scan code generated and transmitted from the keyboard thereto, responsive to a keystroke of the keyboard, wherein the operating system also uses the mapping algorithm, the PRNG algorithm, and the initial seed value. | 2009-03-12 |
20090070596 | Secure Read-Write Storage Device - A method is described for securing a read write storage (RWS) device, the method comprising, providing the RWS device, the RWS device comprising a controller comprising a processor and a bit bucket and employing, in response to a decision making process, a sanction in the RWS device. Related apparatus and methods are also described. | 2009-03-12 |
20090070597 | Method and Apparatus for Store and Replay Functions in a Digital Radio Broadcasting Receiver - A method includes: receiving a plurality of audio frames, assembling groups of the audio frames into logical recording units, storing a plurality of the logical recording units, retrieving the stored logical recording units, and decoding the retrieved logical recording units. An apparatus that performs the method is also provided. | 2009-03-12 |
20090070598 | System and Method for Secure Data Disposal - A system, method, and program product is provided that initializes expected PCRs stored in a TPM by generating and storing a random number, seeding expected PCRs with the random number, inputting a set of startup code processes to a hash algorithm resulting in a set of hash values, updating the expected PCRs using the set of hash values, and saving the expected PCRs in a nonvolatile data area that is secured by the TPM. Upon reboot, the random number is retrieved from the nonvolatile data area, the PCRs are seeded with the retrieved random number, the startup code processes are input to the hash algorithm process resulting in another set of hash values, the PCRs are updated using the resulting set of hash values, and an encrypted data object is decrypted in response to the PCRs being the same as the expected PCRs. | 2009-03-12 |
20090070599 | MEMORY CARD, APPLICATION PROGRAM HOLDING METHOD, AND HOLDING PROGRAM - A memory card of the present invention is a memory card which receives an encrypted application program from a host apparatus, the encrypted application program being downloaded to the host apparatus, the memory card including: an Integrated Circuit (IC) card unit having a tamper resistant function; and a flash memory unit, wherein the IC card unit includes: a tamper resistant storage unit; a program acquisition unit which acquires the encrypted application program from the host apparatus; a storage control unit which stores the acquired encrypted application program in the tamper resistant storage unit or the flash memory unit; and a move control unit which, when the application program stored in the tamper resistant storage unit is to be executed and the size of the to-be-executed application program in the decrypted form exceeds the size of free space of the tamper resistant storage unit, moves an arbitrary encrypted application program stored in the tamper resistant storage unit to the flash memory unit. | 2009-03-12 |