10th week of 2010 patent applcation highlights part 14 |
Patent application number | Title | Published |
20100059811 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - In a nonvolatile semiconductor memory device, a stacked body is provided on a silicon substrate by alternately stacking pluralities of isolation dielectric films and electrode films, a through-hole is formed in the stacked body to extend in the stacking direction, a memory film is formed by stacking a block layer, a charge layer and a tunnel layer in this order at an inner face of the through-hole, and thereby a silicon pillar is buried in the through-hole. At this time, the electrode film is protruded further than the isolation dielectric film toward the silicon pillar at the inner face of the through-hole, and an end face of the isolation dielectric film has a curved shape displacing toward the silicon pillar side as the electrode film is approached. | 2010-03-11 |
20100059812 | FLASH MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are a flash memory device and a method for manufacturing the same. The flash memory device includes a semiconductor substrate having a unit cell defined by an isolation layer, a gate formed over the semiconductor substrate, LDD areas formed at shallow areas of the semiconductor substrate at both sides of the gate, a source and a drain formed at deep areas of the semiconductor substrate while making contact with the LDD areas, and spacers formed at sidewalls of the gate. The spacer includes a first oxide layer pattern, a nitride layer pattern, and a second oxide layer pattern, and the semiconductor substrate includes silicon, so that a silicon-oxide-nitride-oxide-silicon structure for the flash memory device is formed by the silicon of the semiconductor substrate and the spacer at the drain side of the gate. | 2010-03-11 |
20100059813 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR - A gate electrode of a select gate transistor includes a gate insulating film that is formed on a semiconductor substrate, a lower gate electrode that is formed on the gate insulating film and that has a tapered portion in which a side surface on a side of a gate electrode of a memory cell transistor is in a tapered shape, a first oxide film, a silicon nitride film, a second oxide film, and a conductive film that are sequentially formed on the tapered portion, and an upper gate electrode that is connected to the conductive film and the lower gate electrode. | 2010-03-11 |
20100059814 | SEMICONDUCTOR DEVICE HAVING VERTICAL CHARGE-COMPENSATED STRUCTURE AND SUB-SURFACE CONNECTING LAYER AND METHOD - In one embodiment, a semiconductor device is formed having vertical localized charge-compensated trenches, trench control regions, and sub-surface doped layers. The vertical localized charge-compensated trenches include at least a pair of opposite conductivity type semiconductor layers. The trench control regions are configured to provide a generally vertical channel region electrically coupling source regions to the sub-surface doped layers. The sub-surface doped layers are further configured to electrically connect the drain-end of the channel to the vertical localized charge compensation trenches. Body regions are configured to isolate the sub-surface doped layers from the surface of the device. | 2010-03-11 |
20100059815 | SEMICONDUCTOR TRENCH STRUCTURE HAVING A SEALING PLUG AND METHOD - In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core. | 2010-03-11 |
20100059816 | TRENCH GATE TYPE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - The invention provides a trench gate type transistor in which the gate capacitance is reduced, the crystal defect is prevented and the gate breakdown voltage is enhanced. Trenches are formed in an N− type semiconductor layer. A uniformly thick silicon oxide film is formed on the bottom of each of the trenches and near the bottom, being round at corner portions. A silicon oxide film is formed on the upper portion of the sidewall of each of the trenches, which is thinner than the silicon oxide film and round at corner portions. Gate electrodes are formed from inside the trenches onto the outside thereof. The thick silicon oxide film reduces the gate capacitance, and the thin silicon oxide film on the upper portion provides good transistor characteristics. Furthermore, with the round corner portions, the crystal defect does not easily occur, and the gate electric field is dispersed to enhance the gate breakdown voltage. | 2010-03-11 |
20100059817 | POWER MOSFET WITH A GATE STRUCTURE OF DIFFERENT MATERIAL - A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage. | 2010-03-11 |
20100059818 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device includes a first conductive type first semiconductor region, a second semiconductor region, and a second conductive type lateral RESURF region. The first semiconductor region is arranged on a first electrode side. The second semiconductor region includes first conductive type first pillar regions and a terminal part. The second pillar regions are alternately arranged on an element part. The terminal part is formed around the element part along a surface of the first semiconductor region on a second electrode side opposite to the first electrode side of the first semiconductor region. Furthermore, the second conductive type lateral RESURF region is formed in the second semiconductor region on the terminal part. | 2010-03-11 |
20100059819 | POWER TRANSISTOR WITH METAL SOURCE AND METHOD OF MANUFACTURE - A metal source power transistor device and method of manufacture is provided, wherein the metal source power transistor having a source which is comprised of metal and which forms a Schottky barrier with the body region and channel region of the transistor. The metal source power transistor is unconditionally immune from parasitic bipolar action and, therefore, the effects of snap-back and latch-up, without the need for a body contact. The ability to allow the body to float in the metal source power transistor reduces the process complexity and allows for more compact device layout. | 2010-03-11 |
20100059820 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A thin-film transistor (TFT) has a gate insulating film excellent in transparency and flatness. The gate insulating film is formed by a transparent insulating film ( | 2010-03-11 |
20100059821 | Isolated tri-gate transistor fabricated on bulk substrate - A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours. | 2010-03-11 |
20100059822 | METHOD AND SYSTEM FOR MONOLITHIC INTEGRATION OF PHOTONICS AND ELECTRONICS IN CMOS PROCESSES - Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer. | 2010-03-11 |
20100059823 | RESISTIVE DEVICE FOR HIGH-K METAL GATE TECHNOLOGY AND METHOD OF MAKING - A semiconductor device is provided which includes a semiconductor substrate, an isolation structure formed in the substrate for isolating an active region of the substrate, the isolation structure being formed of a first material, an active device formed in the active region of the substrate, the active device having a high-k dielectric and metal gate, and a passive device formed in the isolation structure, the passive device being formed of a second material different from the first material and having a predefined resistivity. | 2010-03-11 |
20100059824 | SYSTEM AND METHOD FOR I/O ESD PROTECTION WITH POLYSILICON REGIONS FABRICATED BY PROCESSES FOR MAKING CORE TRANSISTORS - A system and method for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. A plurality of polysilicon regions are disposed in an proximity of at least one of the plurality of gate regions. The plurality of polysilicon regions are separated from the first substrate a plurality of dielectric layers; | 2010-03-11 |
20100059825 | Integrated circuit and a method of making an integrated circuit to provide a gate contact over a diffusion region - A method of forming an integrated circuit | 2010-03-11 |
20100059826 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - To provide a technique that can maintain uniformity of semiconductor elements and wirings microfabricated, while maintaining the mounting efficiency of circuit cells onto a chip. Respective gate electrodes of an n-channel type MISFET and another n-channel type MISFET forming a NAND circuit cell are coupled to the same node, and simultaneously perform respective on-off operations according to the same input signal. These n-channel type MISFETs are arranged adjacent to each other, and electrically coupled in series. Respective gate electrodes of a p-channel type MISFET and another p-channel type MISFET forming the NAND circuit cell are coupled to the same node, and simultaneously perform respective on-off operations according to the same input signal. These p-channel type MISFETs are arranged adjacent to each other, and electrically coupled in series. | 2010-03-11 |
20100059827 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A first and second gate electrodes are formed on a first and second active regions, respectively. The first and second gate electrodes have a first and second metal-containing conductive films, respectively. The first and second metal-containing conductive films are formed on the isolation region for segmenting the first and second active regions to be spaced apart from each other. A third metal-containing conductive film, which is a part of each of the first and second gate electrodes, is continuously formed from a top of the first metal-containing conductive film through a top of the isolation region to a top of the second metal-containing conductive film. The third metal-containing conductive film is in contact with the first and second metal-containing conductive films. | 2010-03-11 |
20100059828 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device formed by the steps of: forming a dummy electrode | 2010-03-11 |
20100059829 | PROCESS FOR MANUFACTURING A MEMORY DEVICE INCLUDING A VERTICAL BIPOLAR JUNCTION TRANSISTOR AND A CMOS TRANSISTOR WITH SPACERS - A bipolar selection transistor and a circuitry MOS transistor for a memory device are formed in a semiconductor body. The bipolar selection transistor is formed by implanting a buried collector, implanting a base region on the buried collector, forming a silicide protection mask on the semiconductor body, and implanting an emitter region and a control contact region. The circuitry MOS transistor is formed by defining a gate on the semiconductor body, forming lateral spacers on the sides of the gate and implanting source and drain regions on the sides of the lateral spacers. Then, a silicide region is formed on the emitter, base contact, source and drain regions and the gate, in a self-aligned way. The lateral spacers are multilayer structures including at least two different layers, one of which is used to form the silicide protection mask on the bipolar selection transistor. Thereby, the dimensions of the lateral spacers are decoupled from the thickness of the silicide protection mask. | 2010-03-11 |
20100059830 | Semiconductor device - In a semiconductor device, the degree of flatness of 0.3 nm or less in terms of a peak-to-valley (P-V) value is realized by rinsing a silicon surface with hydrogen-added ultrapure water in a light-screened state and in a nitrogen atmosphere and a contact resistance of 10 | 2010-03-11 |
20100059831 | Spacer-less Low-K Dielectric Processes - A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator. | 2010-03-11 |
20100059832 | Semiconductor device - Provided is a semiconductor device including a depletion type MOS transistor and an enhancement type MOS transistor. In the semiconductor device, in order to provide a reference voltage generating circuit having an enhanced temperature characteristic or analog characteristic without increasing an area of the semiconductor device through addition of a circuit, well regions of the depletion type MOS transistor and the enhancement type MOS transistor, which have different concentrations from each other, are formed. | 2010-03-11 |
20100059833 | METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region. | 2010-03-11 |
20100059834 | INTEGRATED ELECTRONIC CIRCUIT INCLUDING A THIN FILM PORTION BASED ON HAFNIUM OXIDE - An integrated electronic circuit has a thin layer portion based on hafnium oxide. This portion additionally contains magnesium atoms, so that the portion is in the form of a hafnium-and-magnesium mixed oxide. Such a portion has a high dielectric constant and a very low leakage current. It is particularly suitable for forming a part of a gate insulation layer of a MOS transistor or a part of a MIM capacitor dielectric. | 2010-03-11 |
20100059835 | Apparatus and Method of Wafer Bonding Using Compatible Alloy - A method of forming an inertial sensor provides 1) a device wafer with a two-dimensional array of inertial sensors and 2) a second wafer, and deposits an alloy of aluminum/germanium onto one or both of the wafers. The alloy is deposited and patterned to form a plurality of closed loops. The method then aligns the device wafer and the second wafer, and then positions the alloy between the wafers. Next, the method melts the alloy, and then solidifies the alloy to form a plurality of conductive hermetic seal rings about the plurality of the inertial sensors. The seal rings bond the device wafer to the second wafer. Finally, the method dices the wafers to form a plurality of individual, hermetically sealed inertial sensors. | 2010-03-11 |
20100059836 | MEMS DEVICE AND METHOD FOR MANUFACTURING THE SAME - A MEMS device, including: a substrate having a first principal plane and a second principal plane opposite to the first principal plane; a through hole formed in the substrate; and a vibrating film formed over the first principal plane so as to cover the through hole. The first principal plane and the second principal plane are both a (110) crystal face; and the through hole has a substantially rhombic shape on the second principal plane. | 2010-03-11 |
20100059837 | Spin Transfer Torque Memory Device Having Common Source Line and Method for Manufacturing the Same - A spin transfer torque memory device and a method for manufacturing the same. The spin transfer torque memory device comprises a MRAM cell using a MTJ and a vertical transistor. A common source line is formed in the bottom of the vertical transistor, thereby obtaining the high-integrated and simplified memory device. | 2010-03-11 |
20100059838 | IMAGE SENSOR MODULE AND METHOD OF MANUFACTURING THE SAME - An image sensor module includes a transparent substrate having recesses defined in a lower face thereof. A light concentration member includes transparent light concentration parts each of which are disposed in a corresponding one of the recesses. Color filters are disposed over each of the light concentration parts and photo diode units having photo diodes are disposed over each of the color filters. An insulation member covers the photo diode units and input/output terminals disposed over the insulation member are each electrically connected to a corresponding photo diode unit. | 2010-03-11 |
20100059839 | LIGHT RECEIVING ELEMENT - A light receiving element comprises: a photodiode including an optical waveguide, an end surface of the optical waveguide being a light receiving surface of the photodiode; a signal electrode and a bias electrode on a common surface of the photodiode, the signal electrode being connected to an anode of the photodiode, the bias electrode being connected to a cathode of the photodiode; an insulating film on the bias electrode; and a metal electrode on the insulating film. | 2010-03-11 |
20100059840 | CMOS IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - A Complementary Metal Oxide Semiconductor (CMOS) image sensor and a method for manufacturing the same are disclosed. The CMOS image sensor includes a photodiode formed in a semiconductor substrate, an inter dielectric layer formed over the semiconductor substrate in which the photodiode is formed, at least one metal line layer formed in the inter dielectric layer, an anti-reflection layer formed over the metal line layer in the inter dielectric layer, a color filter layer formed over the inter dielectric layer, and a micro-lens formed over the color filter layer. | 2010-03-11 |
20100059841 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes an image sensing device on a substrate, an interlayer dielectric layer over the image sensing device, and an aspheric microlens over the interlayer dielectric layer. | 2010-03-11 |
20100059842 | IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - A manufacturing method of an image sensor includes forming a photodiode region by implanting impurity ions in a semiconductor substrate, forming an interlayer dielectric over the semiconductor substrate having the photodiode region, forming a recess in the interlayer dielectric to expose the photodiode region, vapor-depositing a plurality of refractive layers over an inner surface of the recess, each refractive layer having a different refractive index, forming a color filter layer over the interlayer dielectric having the plurality of refractive layers, and forming a micro lens over the color filter layer. | 2010-03-11 |
20100059843 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MAKING THE SAME, AND MANUFACTURING SUBSTRATE FOR SOLID-STATE IMAGING DEVICE - A method for making a solid-state imaging device includes forming a pinning layer, which is a P-type semiconductor layer or an N-type semiconductor layer, on a first substrate by deposition; forming a semiconductor layer on the pinning layer; forming a photoelectric conversion unit in the semiconductor layer, the photoelectric conversion unit being configured to convert incident light into an electrical signal; forming, on the semiconductor layer, a transistor of a pixel unit and a transistor of a peripheral circuit unit disposed in the periphery of the pixel unit, and then forming a wiring section on the semiconductor layer; bonding a second substrate on the wiring section; and removing the first substrate after the second substrate is bonded. | 2010-03-11 |
20100059844 | SOLID-STATE IMAGING DEVICE AND SOLID-STATE IMAGING DEVICE DESIGNING METHOD - A solid-state imaging device includes light receiving sections which are arranged in an image area on a semiconductor substrate at the same pitch and which light exiting from an imaging optical system enters, condensing lenses respectively arranged above the light receiving sections, and light shielding sections each of which is provided at one end of each of the light receiving sections. The condensing lenses are arranged in a peripheral portion in a first direction in the image area at a first pitch, and arranged in a peripheral portion in a second direction opposite the first direction at a second pitch which is smaller than the first pitch. | 2010-03-11 |
20100059845 | IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - An image sensor includes a plurality of unit pixels arranged in a matrix shape, each of which is disposed in a region defined by a gate line extending in a first direction and a data line extending in a second direction that is different from the first direction. Each of the unit pixels includes a switching diode and a sensing diode. The switching diode has a plus terminal electrically connected to the gate line, and a minus terminal electrically connected to a signal node. The sensing diode has a plus terminal electrically connected to the data line, and a minus terminal electrically connected to the signal node. Therefore, a two-dimensional image may be sensed at once without moving of the sensing module so that scan time (image sensing time) may be reduced. | 2010-03-11 |
20100059846 | IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - Provided are image sensors and methods of manufacturing the same. An image sensor includes a metal line and an interlayer insulation layer on a semiconductor substrate including a readout circuit; an image detection unit on the interlayer insulation layer and including stacked first and second doping layers; a pixel separation unit penetrating the image detection unit, separating the image detection unit by pixel; a first metal contact penetrating the image detection unit and the interlayer insulation layer to contact the metal line; a first barrier pattern protecting the first metal contact from contacting the second doping layer, while exposing the first metal contact to the first doping layer; and a second metal contact in a trench above the first metal contact, wherein the second metal contact is electrically connected to the second doping layer while being isolated from the first metal contact by a second barrier pattern. | 2010-03-11 |
20100059847 | STACKED PHOTOELECTRIC CONVERSION DEVICE AND METHOD FOR PRODUCING THE SAME - To provide a stacked photoelectric conversion device and a method for producing the same, in which an interlayer is provided between photoelectric conversion layers to obtain an effect of controlling the amount of incidence light, and carrier recombination at an interface between the interlayer and a semiconductor layer is decreased to enhance photoelectric conversion efficiency. | 2010-03-11 |
20100059848 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - Embodiments provide an image sensor. The image sensor includes readout circuitry, an interlayer dielectric, an interconnection, and an image sensing device. The interconnection includes a lower barrier metal and a nitride barrier formed under the lower barrier metal. A contact plug electrically connecting the lower barrier metal to a lower interconnect is formed passing through the nitride barrier. | 2010-03-11 |
20100059849 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component having a low resistance conduction path and a method for manufacturing the semiconductor component. When the semiconductor component is a Schottky diode, one or more trenches are formed in an epitaxial layer of a first conductivity type that is formed over a semiconductor substrate of the first conductivity type. The trenches may extend into the semiconductor material. Epitaxial semiconductor material of a second conductivity type is selectively grown along the sidewalls of the trenches. An anode contact is formed in contact with the epitaxial layer and the selectively grown epitaxial material and a cathode contact is formed in contact with the semiconductor substrate. | 2010-03-11 |
20100059850 | VARACTOR DIODE WITH DOPED VOLTAGE BLOCKING LAYER - A varactor diode includes a contact layer having a first conductivity type, a voltage blocking layer having the first conductivity and a first net doping concentration on the contact layer, a blocking junction on the voltage blocking layer, and a plurality of discrete doped regions in the voltage blocking layer and spaced apart from the carrier injection junction. The plurality of discrete doped regions have the first conductivity type and a second net doping concentration that is higher than the first net doping concentration, and the plurality of discrete doped regions are configured to modulate the capacitance of the varactor diode as a depletion region of the varactor diode expands in response to a reverse bias voltage applied to the blocking junction. Related methods of forming a varactor diode are also disclosed. | 2010-03-11 |
20100059851 | CMOS CIRCUITS COMBINING HIGH VOLTAGE AND RF TECHNOLOGIES - A CMOS circuit comprises at least one high voltage transistor (having gate and drain operating voltages of greater than 8V) and at least one high frequency capable transistor (having a maximum switching frequency of between 100 MHz and 1000 GHz) wherein said transistors are integrated on the same semiconductor substrate so as to allow the simple integration of high voltage circuits and RF (radio frequency) CMOS circuits on the same integrated circuit. | 2010-03-11 |
20100059852 | SEMICONDUCTOR TRANSISTOR DEVICE WITH IMPROVED ISOLATION ARRANGEMENT, AND RELATED FABRICATION METHODS - A method of fabricating a semiconductor device structure is provided. The method begins by providing a substrate having a layer of semiconductor material, a pad oxide layer overlying the layer of semiconductor material, and a pad nitride layer overlying the pad oxide layer. The method proceeds by selectively removing a portion of the pad nitride layer, a portion of the pad oxide layer, and a portion of the layer of semiconductor material to form an isolation trench. Then, the isolation trench is filled with a lower layer of isolation material, a layer of etch stop material, and an upper layer of isolation material, such that the layer of etch stop material is located between the lower layer of isolation material and the upper layer of isolation material. The layer of etch stop material protects the underlying isolation material during subsequent fabrication steps. | 2010-03-11 |
20100059853 | Semiconductor Device and Method of Forming Shielding Layer over Integrated Passive Device Using Conductive Channels - A semiconductor device is made by providing a substrate, forming a first insulation layer over the substrate, forming a first conductive layer over the first insulation layer, forming a second insulation layer over the first conductive layer, and forming a second conductive layer over the second insulation layer. A portion of the second insulation layer, first conductive layer, and second conductive layer form an integrated passive device (IPD). The IPD can be an inductor, capacitor, or resistor. A plurality of conductive pillars is formed over the second conductive layer. One conductive pillar removes heat from the semiconductor device. A third insulation layer is formed over the IPD and around the plurality of conductive pillars. A shield layer is formed over the IPD, third insulation layer, and conductive pillars. The shield layer is electrically connected to the conductive pillars to shield the IPD from electromagnetic interference. | 2010-03-11 |
20100059854 | Semiconductor Device and Method of Forming an IPD over a High-Resistivity Encapsulant Separated from other IPDS and Baseband Circuit - A semiconductor device has a first conductive layer formed over a sacrificial substrate. A first integrated passive device (IPD) is formed in a first region over the first conductive layer. A conductive pillar is formed over the first conductive layer. A high-resistivity encapsulant greater than 1.0 kohm-cm is formed over the first IPD to a top surface of the conductive pillar. A second IPD is formed over the encapsulant. The first encapsulant has a thickness of at least 50 micrometers to vertically separate the first and second IPDs. An insulating layer is formed over the second IPD. The sacrificial substrate is removed and a second semiconductor die is disposed on the first conductive layer. A first semiconductor die is formed in a second region over the substrate. A second encapsulant is formed over the second semiconductor die and a thermally conductive layer is formed over the second encapsulant. | 2010-03-11 |
20100059855 | Semiconductor Device and Method of Forming a Fan-Out Structure with Integrated Passive Device and Discrete Component - A semiconductor device is made by providing a temporary carrier for supporting the semiconductor device. An integrated passive device (IPD) is mounted to the temporary carrier using an adhesive. The IPD includes a capacitor and a resistor and has a plurality of through-silicon vias (TSVs). A discrete component is mounted to the temporary carrier using the adhesive. The discrete component includes a capacitor. The IPD and the discrete component are encapsulated using a molding compound. A first metal layer is formed over the molding compound. The first metal layer is connected to the TSVs of the IPD and forms an inductor. The temporary carrier and the adhesive are removed, and a second metal layer is formed over the IPD and the discrete component. The second metal layer interconnects the IPD and the discrete component and forms an inductor. An optional interconnect structure is formed over the second metal layer. | 2010-03-11 |
20100059856 | Method of configuring a semiconductor integrated circuit involving capacitors having a width equal to the length of active resistors - A method of configuring a semiconductor integrated circuit (IC) includes arranging a circuit region in the center of a unit cell. Capacitor/resistor regions are arranged along the left and right edge portions of the unit cell. The capacitor/resistor regions include a plurality of active resistors having the same length and a capacitor having a width equal to the length of the plurality of active resistors. In addition, a first conductive layer is arranged longitudinally in each of the capacitor/resistor regions so as to contact the left and right edge portions of the unit cell. | 2010-03-11 |
20100059857 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device. One embodiment provides a metal carrier. A semiconductor chip is provided. A porous layer is produced at a surface of at least one of the carrier and the semiconductor chip. The semiconductor chip is placed on the carrier. The resulting structure is heated until the semiconductor chip is attached to the carrier. | 2010-03-11 |
20100059858 | Integrated capacitors in package-level structures, processes of making same, and systems containing same - An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure. | 2010-03-11 |
20100059859 | VARACTOR STRUCTURE AND METHOD - An improved varactor diode ( | 2010-03-11 |
20100059860 | COUNTER-DOPED VARACTOR STRUCTURE AND METHOD - An improved varactor diode ( | 2010-03-11 |
20100059861 | SEMICONDUCTOR WAFER COMPOSED OF MONOCRYSTALLINE SILICON AND METHOD FOR PRODUCING ITo - Semiconductor wafers composed of monocrystalline silicon and doped with nitrogen contain an OSF region and a PV region, wherein the OSF region extends from the center radially toward the edge of the wafer as far as the P | 2010-03-11 |
20100059862 | THINNED SEMICONDUCTOR WAFER AND METHOD OF THINNING A SEMICONDUCTOR WAFER - A thinned semiconductor wafer and a method for thinning the semiconductor wafer. A semiconductor wafer is thinned from its backside to form a cavity in a central region of the backside of the semiconductor wafer. Forming the cavity also forms a ring support structure in a peripheral region of the semiconductor wafer. The ring support structure has an inner edge and an outer edge. The inner edge may be beveled or have a stepped shape. | 2010-03-11 |
20100059863 | Stretchable Form of Single Crystal Silicon for High Performance Electronics on Rubber Substrates - The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices. | 2010-03-11 |
20100059864 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING ETCHING TO ETCH STOP REGIONS - A method of manufacturing a semiconductor device. The method includes providing a wafer having a first face and a second face opposite the first face, selectively doping the wafer via the first face to selectively form etch stop regions in the wafer and etching the wafer at the second face to the etch stop regions. | 2010-03-11 |
20100059865 | Package with Power and Ground Through Via - A wire bond design integrated circuit with a substrate having a front side and an opposing back side. Circuitry is disposed on the font side. Electrically conductive vias are disposed through the substrate from the front side to the back side, and are electrically connected to the circuitry such that the electrically conductive vias provide power and ground services only for the circuitry. Bonding pads are disposed on the front side, and are electrically connected to the circuitry such that the bonding pads provide signal communication only for the circuitry. | 2010-03-11 |
20100059866 | Semiconductor Device and Method of Forming Vertically Offset Bond on Trace Interconnects on Recessed and Raised Bond Fingers - A semiconductor device has a vertically offset bond on trace (BOT) interconnect structure. The vertical offset is achieved by forming a first conductive layer extending above a surface of a carrier. The first conductive layer is pressed into a surface of a substrate so that the first conductive layer is recessed below the surface of the substrate. The carrier is removed. A second conductive layer is formed above the surface of the substrate to create the vertical offset between the first and second conductive layers. The vertical offset is about 20 micrometers. A conductive via is formed through the substrate. Bond wire bumps are formed on the first and second conductive layers. The bond wire bumps are about 10 micrometers in height. A seed layer is formed over the carrier prior to forming the first conductive layer and removed after forming the second conducive layer. | 2010-03-11 |
20100059867 | INTEGRATED CIRCUIT CHIP WITH SEAL RING STRUCTURE - An integrated circuit chip includes an analog and/or RF circuit block, a digital circuit, and a seal ring structure surrounding and protecting the analog and/or RF circuit block. The seal ring structure comprises a continuous outer seal ring, and a discontinuous inner seal ring divided into at least a first portion and a second portion. The second portion is situated in front of the analog and/or RF circuit block for shielding a noise from interfering the analog and/or RF circuit block. | 2010-03-11 |
20100059868 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING STRUCTURE FOR ELECTRONIC DEVICE - An electronic device including a shielded electronic element, and a method for manufacturing a shielding structure. An oxide film is formed on the surface of a silicon substrate having a [100] face. Part of the oxide film is removed to form a first window region. Silicon substrates are joined together to form an SOI substrate, which includes a buried mask having a second window region. Substrate thinning is then performed, and oxide films are formed on the two surfaces of the SOI substrate so that the first window region has a large area and includes the region above the buried second window region. Then, anisotropic etching is performed to form a cap that includes a step. Wire bonding for shielding is performed on the step. | 2010-03-11 |
20100059869 | Systems and Methods for Enabling ESD Protection on 3-D Stacked Devices - An electrostatic discharge (ESD) protection device is fabricated in a vertical space between active layers of stacked semiconductor dies thereby utilizing space that would otherwise be used only for communication purposes. The vertical surface area of the through silicon vias (TSVs) is used for absorbing large voltages resulting from ESD events. In one embodiment, an ESD diode is created in a vertical TSV between active layers of the semiconductor dies of a stacked device. This ESD diode can be shared by circuitry on both semiconductor dies of the stack thereby saving space and reducing die area required by ESD protection circuitry. | 2010-03-11 |
20100059870 | CHIP PACKAGE STRUCTURE - A chip package structure including a substrate, at least one chip, a plurality of leads, a heat dissipation device, a molding compound, and at least one insulating sheet is provided. The chip is disposed on the substrate. The leads are electrically connected to the substrate. The molding compound having a top surface encapsulates the chip, the substrate, and a portion of the leads. The heat dissipation device is disposed on the top surface of the molding compound. The insulating sheet disposed between the heat dissipation device and at least one of the leads has a bending line dividing the insulating sheet into a main body disposed on the molding compound and a bending portion extending from the main body. | 2010-03-11 |
20100059871 | LEADFRAME - A leadframe including a chip supporting plate, a lead forming plate, and solder points is provided. A notch is formed on an edge of the chip supporting plate. The thickness of the lead forming plate is less than the thickness of the chip supporting plate. The lead forming plate has a main body, inner leads, and a connecting rod. The inner leads and the connecting rod are extended from an edge of the main body. The connecting rod has an end portion fitting the notch. The solder points are located at the boundary between the end portion and the notch for structurally connecting the connecting rod and the chip supporting plate. | 2010-03-11 |
20100059872 | Adhesive Tape, Connected Structure and Semiconductor Package - An adhesive tape | 2010-03-11 |
20100059873 | BALL GRID ARRAY PACKAGE STACKING SYSTEM - A ball grid array package stacking system includes: forming a heat spreader having a centrally located access port; mounting a substrate in the heat spreader for providing a connection pad in the centrally located access port; coupling an integrated circuit die to the substrate; and coupling a system interconnect to the integrated circuit die, the connection pad, or a combination thereof. | 2010-03-11 |
20100059874 | SEMICONDUCTOR CHIP CAPABLE OF INCREASED NUMBER OF PADS IN LIMITED REGION AND SEMICONDUCTOR PACKAGE USING THE SAME - A semiconductor package includes a semiconductor chip including a body unit having one or more circuit units. A first bonding pad is disposed in a first face of the body unit and is connected to a circuit unit. A second bonding pad is disposed in the first face of the body unit in the bonding pad region so as to be positioned in an adjacent surrounding area of the first bonding pad and borders at least one side face of the first bonding pad while being insulated from the first bonding pad. A first connection terminal is attached onto the first bonding pad, and a second connection terminal is attached onto the second bonding pad and is positioned in an adjacent surrounding area of the first connection terminal and borders at least one side face of the first connection terminal while being insulated from the first connection terminal. | 2010-03-11 |
20100059875 | SEMICONDUCTOR DEVICE - The reliability of a semiconductor device is improved. | 2010-03-11 |
20100059876 | ELECTRONIC COMPONENT PACKAGE AND METHOD OF MANUFACTURING THE SAME - There is provided an electronic component package. The electronic component package includes: a core layer including a plurality of insulating layers formed by impregnating a base material with a resin, wherein a hollow portion is formed in the core layer; core wiring layers each disposed between the insulating layers; and an electronic component disposed in the hollow portion. The electronic component and the core wiring layer are electrically connected to each other by a bonding wire. | 2010-03-11 |
20100059877 | Method for packaging electronic devices and integrated circuits - The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits. | 2010-03-11 |
20100059878 | Stack Assemblies Containing Semiconductor Devices - The present invention provides a stack assembly comprising at least one semiconductor device | 2010-03-11 |
20100059879 | Power Amplifier Assembly - The power amplifier module comprises a laminate substrate comprising thermal vias and terminals, as well as a platform device with an interconnection substrate of a semiconductor material. This substrate is provided with electrical interconnects at a first side, and having been mounted on the laminate substrate with an opposite second side. Electrically conducting connections extend from the first to the second side through the substrate. A power amplifier device is attached to the second side of the substrate. One of the electrically conducting connection through the interconnection substrate is a grounding path for the power amplifier, while a thermal path is provided by the semiconductor material. There is an optimum thickness for the interconnection substrate, at which both a proper grounding and a acceptable thermal dissipation is effected. | 2010-03-11 |
20100059880 | SEMICONDUCTOR MODULE AND AN ELECTRONIC SYSTEM INCLUDING THE SAME - A three-dimensional semiconductor module and an electronic system including the same are provided. The semiconductor module includes a module substrate, a logic device formed on a part of the module substrate, and a plurality of memory devices formed on another part of the module substrate, wherein the plurality of memory devices are disposed perpendicular to the logic device, and the module substrate on which the plurality of memory devices are formed is supported by a supporter. The electronic system includes the semiconductor module. | 2010-03-11 |
20100059881 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package and a method of manufacturing the semiconductor package are disclosed. The semiconductor package in accordance with an embodiment of the present invention includes: a substrate, in which a conductive pattern formed on one surface of the substrate; an insulation layer, which is formed on one surface of the substrate, in which a through-hole is formed in the insulation layer such that the conductive pattern is exposed; a metal post, which is formed in the through-hole such that one end of the metal post is in contact with the conductive pattern and the other end of the metal post is protruded from the insulation layer; and a solder bump, which is formed on the other end of the metal post. | 2010-03-11 |
20100059882 | SEMICONDUCTOR DEVICE - Signal lines which provide electric connections from an internal circuit formed on a main surface of a semiconductor chip and including, for example, MIS transistor to protective elements constituted by, for example, diodes are drawn out from outlet ports formed on wiring lines disposed between the protective elements, and a signal line region occupied by the signal lines is provided over the protective elements and under electrode pads. A wiring region on the main surface of the semiconductor chip can be enlarged without increasing the chip area. | 2010-03-11 |
20100059883 | METHOD OF FORMING BALL BOND - A method of forming a ball bond ( | 2010-03-11 |
20100059884 | LEADLESS SEMICONDUCTOR CHIP CARRIER SYSTEM - A semiconductor package system includes: providing a semiconductor die with bonding pad on the semiconductor die; attaching the semiconductor die to an intermediate layer; attaching one end of a bonding wire to the bonding pad; forming a bonding ball at the other end of the bonding wire, the bonding ball being fully or partially embedded in the intermediate layer; encapsulating the semiconductor die, the bonding pad, the bonding wire, and a portion of the bonding ball with a mold compound; removing the intermediate layer, resulting in the bonding ball protruding from the exposed mold compound bottom surface; and conditioning the bonding ball | 2010-03-11 |
20100059885 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION LAYER - An integrated circuit package system includes: providing a base device; attaching a base interconnect to the base device; applying an encapsulant over the base device and the base interconnect; and forming a re-routing film over the encapsulant, the base device, and the base interconnect for connectivity without a substrate. | 2010-03-11 |
20100059886 | Carrier structure of SoC with custom interface - The present invention discloses a carrier structure of a System-on-Chip (SoC) with a custom interface. The carrier structure includes a substrate, at least one common die, at least one custom interface and a molding compound. The common die and the custom interface are disposed on the substrate. The molding compound is used to package the common die which electrically connects to the substrate and the custom interface respectively. The carrier structure which includes the common die can form a complete SoC by connecting to an expansive die through the custom interface. The carrier structure with the common die which can be tested and certified in advance allows reducing and simplifying the developing procedures of the SoC. | 2010-03-11 |
20100059887 | SEMICONDUCTOR DEVICE HAVING INSULATING FILM WITH SURFACE MODIFICATION LAYER AND METHOD FOR MANUFACTURING THE SAME - Provided is a semiconductor device, which includes an interlayer insulating film formed on a semiconductor substrate, a wiring layer filled in a recess formed in the interlayer insulating film, and a cap insulating film. The interlayer insulating film includes a first SiOCH film and a surface modification layer including an SiOCH film formed by modifying a surface layer of the first SiOCH film, the SiOCH film having a lower carbon concentration and a higher oxygen concentration than the first SiOCH film has. The cap insulating film contacts with surfaces of the metal wiring and the surface modification layer. | 2010-03-11 |
20100059888 | Mask ROM and method of fabricating the same - A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes. | 2010-03-11 |
20100059889 | ADHESION OF DIFFUSION BARRIER ON COPPER-CONTAINING INTERCONNECT ELEMENT - The present invention relates to a method for fabricating a semiconductor device. For improving the adhesion between a copper-containing interconnect element and a diffusion barrier on top of it, a first dielectric layer ( | 2010-03-11 |
20100059890 | METAL LINE OF SEMICONDUCTOR DEVICE HAVING A DIFFUSION BARRIER INCLUDING CRxBy AND METHOD FOR FORMING THE SAME - A metal line of a semiconductor device having a diffusion barrier including Cr | 2010-03-11 |
20100059891 | ALTERNATIVE TO DESMEAR FOR BUILD-UP ROUGHENING AND COPPER ADHESION PROMOTION - In some embodiments, an alternative to desmear for build-up roughening and copper adhesion promotion is presented. In this regard, a substrate in introduced having a dielectric layer, a plurality of polyelectrolyte multilayers on the dielectric layer, and a copper plating layer on the polyelectrolyte multilayers. Other embodiments are also disclosed and claimed. | 2010-03-11 |
20100059892 | PRODUCTION METHOD OF SEMICONDUCTOR DEVICE, PRODUCTION METHOD OF DISPLAY DEVICE, SEMICONDUCTOR DEVICE, PRODUCTION METHOD OF SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR ELEMENT - The present invention provides a production method of a semiconductor device, a production method of a display device, a semiconductor device, a production method of a semiconductor element, and a semiconductor element, each capable of providing a lower-resistance semiconductor element which is more finely prepared through more simple steps. The production method of the semiconductor device of the present invention is a production method of a semiconductor device including a semiconductor element on a substrate, wherein the production method includes a metal silicide-forming step of: transferring the semiconductor element onto the substrate, the semiconductor element having a multilayer structure of a silicon layer and a metal layer, and by heating, forming metal silicide from silicon for a metal layer-side part of the silicon layer and metal for a silicon layer-side part of the metal layer. | 2010-03-11 |
20100059893 | Synergy Effect of Alloying Materials in Interconnect Structures - A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line includes an alloying material; and forming an etch stop layer on the copper line. | 2010-03-11 |
20100059894 | METHOD OF MANUFACTURING OPENINGS IN A SUBSTRATE, A VIA IN SUBSTRATE, AND A SEMICONDUCTOR DEVICE COMPRISING SUCH A VIA - The invention relates to a method of manufacturing openings in a substrate ( | 2010-03-11 |
20100059895 | SEMICONDUCTOR DEVICE HAVING AN INTERLAYER INSULATING FILM WIRING LAMINATED STRUCTURE SECTION AND METHOD OF FABRICATING THE SAME - In the manufacture of a semiconductor, in unnecessary semiconductor device formation areas | 2010-03-11 |
20100059896 | Coplaner waveguide and fabrication method thereof - A coplanar waveguide includes a substrate, a signal line formed on the substrate, a pair of ground conductors formed on the substrate on mutually opposite sides of the signal line, a signal line insulating film disposed between the signal line and the substrate, and a ground conductor insulating film disposed between the pair of ground conductors and the substrate. No corresponding insulating film is present on the substrate between the signal line and the ground conductors. Even if a silicon substrate is used, the attenuation characteristics of the coplanar waveguide are comparable to the attenuation characteristics of coplanar waveguides formed on compound semiconductor substrates. | 2010-03-11 |
20100059897 | INTERCONNECT STRUCTURES FOR STACKED DIES, INCLUDING PENETRATING STRUCTURES FOR THROUGH-SILICON VIAS, AND ASSOCIATED SYSTEMS AND METHODS - Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate. | 2010-03-11 |
20100059898 | SIGNAL DELIVERY IN STACKED DEVICE - Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice. | 2010-03-11 |
20100059899 | IC CARD AND MANUFACTURING METHOD THEREOF - This IC card is provided with a module having an inlet, an adhesive layer covering the module, and a first base material and second base material sandwiching the module with interposition of the adhesive layer. The module is disposed on one face of the first base material with interposition of a viscous layer which has a thickness that varies according to the thickness at each area of the module, and its two ends are narrower than its other parts when viewed from the outer face side of the first base material or the outer face side of the second base material. According to this IC card, it is possible to offer the IC card with a flat surface, and without occurrence of strain in the embedded IC chip. | 2010-03-11 |
20100059900 | Translucent, Flame Resistant Composite Materials - A translucent composite material that can be used in various airplane interior applications that allows sufficient light transmissivity while preferably meeting Federal Aviation Administration (FAA) flammability requirements for overhead materials in the cabin of a commercial aircraft. The material also meets FAA standards regarding vertical burn, smoke emissions tests, and toxic fume emissions tests. The composite material is formed by laminating long glass fibers and (PPSU) into a composite sheet under controlled heat and pressure. The composite sheet is then cut, bent or thermoformed to form the desired part. The parts formed are available for a wide variety of uses within the passenger cabin of a commercial aircraft. The long glass fibers may be unidirectional or weaved into a glass cloth like material. While preferably formed for airplane interior applications, these components may also be used in other aerospace or non-aerospace applications. | 2010-03-11 |
20100059901 | OPTICAL FIBER CONNECTING ELEMENT AND MOLDING APPARATUS AND METHOD FOR PRODUCING THE SAME - A method for producing an optical fiber connecting element including a main body having an optical fiber insertion hole and a guide pin insertion hole, the method includes: molding by feeding a material of the optical fiber connecting element with a pin holder having a pin for forming the optical fiber insertion hole and a pin for forming the guide pin insertion hole placed in a certain position of a mold having a cavity having a shape corresponding to a shape in which light exits of the main bodies of a pair of the optical fiber connecting elements face each other, filling the cavity with the material, and then opening the mold; and producing a pair of the optical fiber connecting elements by cutting a molded body formed by the molding. | 2010-03-11 |
20100059902 | PROCESS AND APPARATUS FOR BUFFING GOLF BALLS - A method and apparatus for automatically removing flash along the parting line of a golf ball, especially when the parting line is wavy or corrugated. The apparatus is also effective for removing flash from golf balls that are not completely spherical, or golf balls that are void of tabs or annular ring which are commonly used for alignment. The method removes flash from a golf ball by using a mapping device comprising either a vision orientation system or a laser means incorporating comprises high resolution CCD displacement sensors on a servo controlled vertical axis to properly place the ball in position wherein a cutter and buffer are maneuvered along a mapped contour of the flash that is captured by the coordinated motion logic of a computer. | 2010-03-11 |
20100059903 | CONSTANT SHEAR RATE EXTRUSION DIE - An extrusion die for extruding thermoplastic materials to produce a sheet of substantially uniform thickness, the extrusion die having a manifold width that increases from the centerline toward the die exit or lip. The increasing width manifold arms, with the preland portion, provide a constant shear rate at all areas of the die and a constant residence time, so that every fluid particle path through the die has the same residence time. By having the increasing width manifold arms, the preland area of the extrusion die is decreased, usually by about 30%, often about 40-60%, compared to a Winter die, thus decreasing clam-shelling effect and allowing design and extrusion of wider sheets. | 2010-03-11 |
20100059904 | IMPRINT APPARATUS - An imprint apparatus is configured to mold a resin on a substrate by using a mold and to form a pattern of the resin on the substrate. The imprint apparatus includes a holder configured to hold the substrate, the holder having a groove, an exhaust device configured to exhaust a gas in the groove so that the hold can hold the substrate by setting a pressure in the groove to a negative pressure, a supply device configured to supply the gas to the groove, and a controller configured to control the supply device so as to set the pressure in the groove to a positive pressure during molding. | 2010-03-11 |
20100059905 | Magnetic rubber composition and method for forming molded body from the magnetic rubber composition - The invention provides a magnetic rubber composition prepared by kneading an anisotropic magnetic powder, alkoxysilane represented by the formula below, and a rubber binder: | 2010-03-11 |
20100059906 | HIGH THROUGHPUT ELECTROBLOWING PROCESS - The present invention is a fiber spinning process comprising the steps of providing a polymer solution, which comprises at least one polymer dissolved in at least one solvent with a vapor pressure of at least about 6 kPa at 25° C., to a spinneret, issuing the polymer solution in combination with a blowing gas in a direction away from at least one spinning nozzle in the spinneret and in the presence of an electric field wherein the polymer solution is discharged through the spinning nozzle at a discharge rate between about 6 to about 100 ml/min/hole, forming fibers, and collecting the fibers on a collector. | 2010-03-11 |
20100059907 | FIBER SPINNING PROCESS USING A WEAKLY INTERACTING POLYMER - A fiber spinning process comprising the steps of providing a polymer solution, which comprises at least one weakly interacting polymer dissolved in at least one weakly interacting solvent to a spinneret; issuing the polymer solution in combination with a blowing gas in a direction from at least one spinning nozzle in the spinneret and in the presence of an electric field; forming fibers and collecting the fibers on a collector. | 2010-03-11 |
20100059908 | THERMAL ENERGY MACHINE WITH INTERCHANGEABLE COMPONENTS FOR PROCESSING DIFFERENT SIZED PARTS - A thermal energy machining (“TEM”) machine is designed with interchangeable components for processing different sized parts within a single frame. The frame weldment includes a base, an upper mounting plate and intermediate mounting plates. In one embodiment, a TEM machine for processing short parts includes a ram cylinder directly secured to the base, a chamber spacer directly secured to the upper mounting plate and a thermal chamber directly secured to the chamber spacer. In another embodiment, a TEM machine for processing long parts includes a thermal chamber directly secured to the upper mounting plate, a ram spacer directly secured to the base, and a ram cylinder directly secured to the ram spacer. | 2010-03-11 |
20100059909 | Apparatus for Recycling Noble Metals - The present invention provides an apparatus for recycling noble metals, which comprises a conveyer, one or more carriers, an immersion device, one or more dissolution devices, and one or more rinse devices. The carriers carry objects containing noble metals. The conveyer is used for conveying the carriers to the immersion device, the dissolution devices, and the rinse devices sequentially for recycling noble metals from the objects containing noble metals. The apparatus according to the present invention can recycle noble metals continuously. Thereby, the speed of recycling is enhanced, and the amount of recycled noble metals is increased as well. | 2010-03-11 |
20100059910 | APPARATUS FOR RECYCLING METAL FROM METAL IONS CONTAINING WASTE SOLUTION - An apparatus for recycling metals from metal ions containing waste solution includes a conveying device, a reducing agent supplier and a solution supplier. The conveying device includes a first ferromagnetic conveyor belt, a first roller, and a second roller. The first and second rollers are substantially horizontally arranged, and the second roller is arranged at a lower position relative to the first roller and spaced from the first roller. The ferromagnetic conveyor belt is wrapped around the first and second rollers. The reducing agent supplier is used for supplying a reducing agent onto the first conveyor belt, the ferromagnetic conveyor belt is capable of conveying the reducing agent from the second roller to the first roller. The solution supplier is configured for supplying the waste solution onto the first conveyor belt. | 2010-03-11 |