| 10th week of 2011 patent applcation highlights part 11 |
| Patent application number | Title | Published |
|---|
| 20110057198 | TECHNIQUE FOR DEVELOPMENT OF HIGH CURRENT DENSITY HETEROJUNCTION FIELD EFFECT TRANSISTORS BASED ON (10-10)-PLANE GaN BY DELTA-DOPING - A delta (δ)-doped (10-10)-plane GaN transistor is disclosed. Delta doping can achieve a transistor having at least 10 times higher current density than a conventional (10-10)-plane GaN transistor. | 2011-03-10 |
| 20110057199 | Antistatic Gallium Nitride Based Light Emitting Device and Method for Fabricating the Same - The invention provides an antistatic gallium nitride based light emitting device and a method for fabricating the same. The method includes: growing an n-type GaN-based epitaxial layer, an active layer, a p-type GaN-based epitaxial layer and an undoped GaN-based epitaxial layer sequentially on a substrate; etching to remove parts of the layers above, to expose a part of the n-type GaN-based epitaxial layer, with the unetched part defined as an emitting area; etching to remove a part of the undoped GaN-based epitaxial layer; forming an ohmic contact electrode on an exposed part of p-type GaN-based epitaxial layer, and forming a Schottky contact electrode on another part; forming a p-electrode on a transparent conducting layer such that the p-electrode is electrically connected with the ohmic contact electrode; forming an n-electrode on the exposed n-type GaN-based epitaxial layer; and forming a connecting conductor on an insulation layer such that the connecting conductor is electrically connected with the n-electrode and the Schottky contact electrode. By forming a GaN Schottky diode directly on a p-type GaN-based epitaxial layer, the fabrication process is simplified while providing antistatic ability at the same time, and the emitting area is made the maximum use of so as to avoid the drop in the luminous efficiency of the GaN-based LED. | 2011-03-10 |
| 20110057200 | GROUP III NITRIDE SEMICONDUCTOR DEVICE, EPITAXIAL SUBSTRATE, AND METHOD OF FABRICATING GROUP III NITRIDE SEMICONDUCTOR DEVICE - A group III nitride semiconductor device having a gallium nitride based semiconductor film with an excellent surface morphology is provided. A group III nitride optical semiconductor device | 2011-03-10 |
| 20110057201 | LED Element with a Thin-layer Semiconductor Element Made of Gallium Nitride - An LED module comprising an LED chip, with an active gallium nitride layer and a silicon platform on which the LED chip is arranged, wherein the silicon platform has two electrodes on the side facing away from the LED chip which are electrically connected to the LED chip and wherein the thickness of the gallium nitride layer of the LED chip is between 2 μm and 10 μm, preferably 1 μm to 5 μm. | 2011-03-10 |
| 20110057202 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to the embodiments, a semiconductor device using SiC and having a high breakdown voltage, a low on-resistance, and excellent reliability is provided. The semiconductor device includes a silicon carbide substrate having first and second main surfaces; a first silicon carbide layer of a first conductive type provided on the first main surface of the silicon carbide substrate; first silicon carbide regions of a second conductive type formed on a surface of the first silicon carbide layer; second silicon carbide regions of the first conductive type formed on respective surfaces of the first silicon carbide regions; third silicon carbide regions of the second conductive type formed on the respective surfaces of the first silicon carbide regions; a fourth silicon carbide region of the second conductive type formed between the facing first silicon carbide regions with the first silicon carbide layer therebetween; a gate insulating film formed continuously on surfaces of the first silicon carbide regions, the first silicon carbide layer, and the fourth silicon carbide region; a gate electrode formed on the gate insulating film; an interlayer insulating film which covers the gate electrode; a first electrode which is electrically connected to the second silicon carbide regions and the third silicon carbide regions; and a second electrode formed on the second main surface of the silicon carbide substrate. | 2011-03-10 |
| 20110057203 | PACKAGE CARRIER - A package carrier suitable for carrying at least one light emitting device and at least one light receiving device includes a carrier substrate and a metal sheet. The carrier substrate includes a first carrying area and a second carrying area. The light emitting device is disposed in the first carrying area and the light receiving device is disposed in the second carrying area. The metal sheet is disposed in the carrier substrate and located between the first carrying area and the second carrier area, for blocking optical signal transmission between the light emitting device and the light receiving device. | 2011-03-10 |
| 20110057204 | Optical module - An optical module can reliably provide monitor light and can facilitate manufacturing by reducing the number of lens surfaces. Based on a surface shape of each first lens surface ( | 2011-03-10 |
| 20110057205 | LED WITH PHOSPHOR TILE AND OVERMOLDED PHOSPHOR IN LENS - Overmolded lenses and certain fabrication techniques are described for LED structures. In one embodiment, thin YAG phosphor plates are formed and affixed over blue LEDs mounted on a submount wafer. A clear lens is then molded over each LED structure during a single molding process. The LEDs are then separated from the wafer. The molded lens may include red phosphor to generate a warmer white light. In another embodiment, the phosphor plates are first temporarily mounted on a backplate, and a lens containing a red phosphor is molded over the phosphor plates. The plates with overmolded lenses are removed from the backplate and affixed to the top of an energizing LED. A clear lens is then molded over each LED structure. The shape of the molded phosphor-loaded lenses may be designed to improve the color vs. angle uniformity. Multiple dies may be encapsulated by a single lens. In another embodiment, a prefabricated collimating lens is glued to the flat top of an overmolded lens. | 2011-03-10 |
| 20110057206 | Fast Photoconductor - A photoconductor having a layer stack ( | 2011-03-10 |
| 20110057207 | WHITE-LIGHT EMITTING DEVICE - An white-light emitting device including a carrier, light emitting diode (LED) chips, and a wavelength converting material is provided. The LED chips are disposed on and electrically connected to the carrier. An equivalent wavelength of the first light emitted from the LED chips and divided into groups is λ. A variation of peak wavelengths of the LED chips in one group is smaller than 5 nm. λ meets an equation: | 2011-03-10 |
| 20110057208 | LIGHT EMITTING DISPLAY DEVICE - Provided is an organic light emitting display device sealed maintaining durability by preventing permeation of oxygen and moisture and improving impact resistance. The light emitting display device includes a first substrate; a second substrate disposed facing toward the first substrate; an emission unit disposed between the first substrate and the second substrate and comprising a plurality of light emitting devices; a first sealant disposed between the first substrate and the second substrate, and surrounding the emission unit and combining the first substrate and the second substrate; a first region formed between around a flat portion of the first sealant and a margin of the second substrate; a second region formed between around a corner of the first sealant and a margin of the second substrate; a second sealant disposed in the first region; and a third sealant disposed in the second region. | 2011-03-10 |
| 20110057209 | LIGHT EMITTING DEVICE - Provided are a light emitting device. The light emitting device comprises a package body, an insulating layer on a surface of the package body, first and second electrode layers on the insulating layer, a light emitting diode disposed on the package body and electrically connected to the first and second electrode layers, a resistor layer connected to the first electrode layer, a first element part in a first doping region within the package body, a second element part in a second doping region within the package body, and a third electrode layer connected to the first element part and the second element part. | 2011-03-10 |
| 20110057210 | ORGANIC ELECTROLUMINESCENCE DEVICE AND METHOD FOR PRODUCING THE SAME - To provide an organic electroluminescence device including: a plurality of organic electroluminescence display portions, each of which includes at least an anode, a light-emitting layer and a cathode; a plurality of lenses which are placed over the organic electroluminescence display portions, and each of which controls an optical path of light emitted from the light-emitting layer; and a plurality of filter layers, each of which is formed integrally with each lens and placed so as to cover the optical path in each lens, and transmits the light emitted from the light-emitting layer, wherein the filter layer formed integrally with one lens among the lenses absorbs at least light with a peak wavelength among light which has passed through at least one of lenses that are adjacent to the one lens. | 2011-03-10 |
| 20110057211 | LIGHT EMITTING DIODE DISPLAY AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing LED display is provided. The method provides a sacrificial substrate on which RGB LED device layers are formed, respectively. The method etches and patterns the LED device layer to manufacture RGB LED devices, respectively. The method removes the sacrificial substrate in a lower side of the LED device. The method contacts a stamping processor to the RGB LED devices to separate the RGB LED devices from the sacrificial substrate. The method transfers the LED device, which is attached to the stamping processor, to a receiving substrate. | 2011-03-10 |
| 20110057212 | One-Way Transparent Display Systems - A display system includes a projection screen and a projector. The projection screen includes a retarder plate between a polarizer and a transparent screen. The projector projects an image through the polarizer and the retarder plate onto the transparent screen. The image is visible from a first side of the transparent screen but invisible from a second side of the transparent screen because any light passing twice through the retarder plate is blocked by the polarizer. | 2011-03-10 |
| 20110057213 | III-NITRIDE LIGHT EMITTING DEVICE WITH CURVAT1JRE CONTROL LAYER - A semiconductor structure comprises a III-nitride light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure further comprises a curvature control layer grown on a first layer. The curvature control layer is disposed between the n-type region and the first layer. The curvature control layer has a theoretical a-lattice constant less than the theoretical a-lattice constant of GaN. The first layer is a substantially single crystal layer. | 2011-03-10 |
| 20110057214 | EPITAXIAL WAFER, LIGHT-EMITTING ELEMENT, METHOD OF FABRICATING EPITAXIAL WAFER AND METHOD OF FABRICATING LIGHT-EMITTING ELEMENT - An epitaxial wafer, a light-emitting element, a method of fabricating the epitaxial wafer and a method of fabricating the light-emitting element, which have a high output and a low forward voltage, and can be fabricated without increasing fabricating cost, are provided. The epitaxial wafer is formed with a light-emitting portion, a reflective portion provided between a semiconductor substrate and the light-emitting portion and a current dispersing layer having first and second current dispersing layers, wherein the reflective portion has plural pairs of layers having first and second semiconductor layers wherein the first semiconductor layer has a thickness of T | 2011-03-10 |
| 20110057215 | Light-Emitting Diode Display Module - An LED display module is provided, including a cover element, with the cover element having lenses on one side and the other side having a housing space to house a lighting module, a frame element and the water-proof pad located at the junction of the cover element and the frame element to prevent water from leaking through into the LED display module. | 2011-03-10 |
| 20110057216 | Low profile optoelectronic device package - A low profile optoelectronic device package has a matalized transparent substrate, a chip and a dam ring. The matalized transparent substrate has a transparent board, a window area, and a metal pattern formed on a face of the transparent board and around the window area and having at least one outer contact pad and at least two contact pads. An active face of the chip is mounted to the at least two inner contact pads and aligned to the window area. A bottom face of the chip, that is opposite to the active face is further added a soldering layer. The dam ring is sealed a joint between the chip and the matalized transparent substrate so as to define an air cavity among the chip, the matalized transparent substrate and the dam ring. The matalized transparent substrate is used as a substrate and an optical cover of a conventional device package, so the optoelectronic device package provides low profile, small area outline, low fabricating cost and high lighting efficiency. | 2011-03-10 |
| 20110057217 | Led Package structure for increasing heat-dissipating and light-emitting efficiency and method for manufacturing the same - An LED package structure for increasing heat-dissipating and light-emitting efficiency includes a substrate unit, an alloy unit, a light-emitting unit, a conductive unit and a package unit. The substrate unit has a substrate body, a first conductive pad, a second conductive pad and a chip-placing pad. The alloy unit has a Ni/Pd alloy formed on the chip-placing pad. The light-emitting unit has an LED chip positioned on the Ni/Pd alloy of the alloy unit by solidified solder ball or glue. The conductive unit has two conductive wires, and the LED chip is electrically connected to the first conductive pad and the second conductive pad by the two conductive wires, respectively. The package unit has a light-transmitting package gel body formed on the top surface of the substrate body in order to cover the light-emitting unit and the conductive unit. | 2011-03-10 |
| 20110057218 | RADITION-EMITTIN SEMICONDUCTOR COMPONENT,RECEPTACLE FOR A RADIATION-EMITTING SEMICONDUCTOR COMPONENT,AND METHOD FOR PRODUCING A RADIATION-EMITTING SEMICONDUCTOR COMPONENT - A semiconductor based component with radiation-emitting properties. A glass substrate ( | 2011-03-10 |
| 20110057219 | NITRIDE-BASED SEMICONDUCTOR LIGHT EMITTING DEVICE - An exemplary nitride-based semiconductor light emitting device includes a substrate, a nitride-based multi-layered structure epitaxially formed on the substrate, a first-type electrode and a second-type electrode formed on the nitride-based multi-layered structure and connected with the first-type layer and the second-type layer, respectively. The multi-layered structure includes a first-type layer, an active layer and a second-type layer arranged along a direction away from the substrate in the order written. The second-type layer defines a number of grooves at the top surface. Each groove has a side surface and a bottom surface adjoining the side surface. The side surface and the bottom surface cooperatively form an included angle which is in a range from 140 degree to 160 degree. | 2011-03-10 |
| 20110057220 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE - A nitride semiconductor light-emitting device includes a laminate structure formed of a plurality of nitride semiconductor layers including a light-emitting layer, and having cavity facets facing each other, a first protection film made of AlN, formed over a light-emitting facet of the cavity facets, and a second protection film made of Al | 2011-03-10 |
| 20110057221 | ORGANIC ELECTROLUMINESCENCE DEVICE AND METHOD FOR PRODUCING THE SAME - To provide an organic electroluminescence device including: an organic electroluminescence portion which includes at least an anode, a light-emitting layer and a cathode; a sealing layer which covers a surface of the cathode of the organic electroluminescence portion; a lens which is provided over the sealing layer and controls an optical path of light emitted from the light-emitting layer; and a low-refractive-index layer provided between the sealing layer and the lens, wherein the low-refractive-index layer has a refractive index lower than a refractive index of the sealing layer. | 2011-03-10 |
| 20110057222 | ORGANIC ELECTROLUMINESCENT ELEMENT, AND METHOD FOR PRODUCING THE SAME - The present invention provides a method for producing an organic electroluminescent element, the method including: arranging, on a surface of a substrate having an electrostatic charge, particles provided with a surface electrostatic charge opposite to the electrostatic charge on the surface of the substrate, so that the particles are fixed on the surface of the substrate with an electrostatic force, and forming a thin film on the surface of the substrate on which the particles have been fixed. | 2011-03-10 |
| 20110057223 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM INCLUDING THE SAME - Embodiments relate to a light emitting device, a light emitting device package, and a lighting system including the same. The light emitting device includes a light emitting structure, a second electrode under the light emitting structure and an insulating layer disposed on the at least one of the protrusions. The second electrode includes a bottom member and at least one of protrusions on the bottom member that penetrates the second conductive type semiconductor layer and the active layer. The at least one of the protrusions includes an upper portion and a lower portion having different size. | 2011-03-10 |
| 20110057224 | LIGHT EMITTING DEVICE, SYSTEM AND PACKAGE - A light emitting device includes a light emitting structure formed from an active layer located between two semiconductor layers. An insulator extends through the active layer and at least partially through the semiconductor layers, and the light emitting structure is located between a first electrode and a second electrode layer. The first electrode and insulator overlap one another and may have the same or different widths. | 2011-03-10 |
| 20110057225 | Light Emitting Device - A light emitting device includes a leadframe, a light emitting unit, a transparent encapsulant, and a fluorescent colloid layer. The light emitting unit is disposed on the leadframe. The transparent encapsulant covers the light emitting unit, wherein the transparent encapsulant has a concave on which at least one reflective surface is disposed. The fluorescent colloid layer is disposed outside the transparent encapsulant, wherein a chamber is formed between the fluorescent colloid layer and the transparent encapsulant. The light generated by the light emitting unit is reflected by the reflective surface and guided to a side wall of the fluorescent colloid layer. | 2011-03-10 |
| 20110057226 | LED Module Comprising a Dome-shaped Color Conversion Layer - An LED module comprises at least one LED chip ( | 2011-03-10 |
| 20110057227 | LED Comprising a Multiband Phosphor System - The invention relates to an LED module comprising at least one blue LED and a color conversion layer that is applied thereto and emits a mixed light of the blue light of the LED and the convened spectrum of the color conversion layer. The color conversion layer has at least three different phosphors which at least partially convert the light of the blue LED into red, green, and yellow or yellowish-green light. The phosphor for conversion into red light is a doped nitride compound, preferably a nitridosilicate. | 2011-03-10 |
| 20110057228 | RESIN COMPOSITION FOR OPTICAL SEMICONDUCTOR ELEMENT HOUSING PACKAGE, AND OPTICAL SEMICONDUCTOR LIGHT-EMITTING DEVICE OBTAINED USING THE SAME - The present invention relates to a resin composition for forming an insulating resin layer for optical semiconductor element housing package having a concave portion in which a metal lead frame and an optical semiconductor element mounted thereon are housed, in which the resin composition includes the following ingredients (A) to (D), and the ingredients (C) and (D) are contained in a blend ratio (C)/(D) of 0.3 to 3.0 as a weight ratio thereof: (A) an epoxy resin; (B) an acid anhydride curing agent; (C) a white pigment; and (D) an inorganic filler. | 2011-03-10 |
| 20110057229 | Organic Light Emissive Device - A method of manufacturing an organic light emissive device comprising: depositing an organic light emissive layer over an anode and depositing a cathode over the organic light emissive layer, wherein the cathode comprises a trilayer structure formed by: depositing a first layer comprising an electron injecting material; depositing a second layer over the first layer, the second layer comprising a metallic material having a workfunction greater than 3.5 eV; and depositing a third layer over the second layer, the third layer comprising a metallic material having a workfunction greater than 3.5 eV. | 2011-03-10 |
| 20110057230 | Lateral Insulated Gate Bipolar Transistors (LIGBTS) - This invention generally relates to lateral insulated gate bipolar transistors (LIGBTs), for example in integrated circuits, methods of increasing switching speed of an LIGBT, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT, and methods of fabricating an LIGBT. In particular, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT comprises selecting a current gain αv for a vertical transistor of a parasitic thyristor of the LIGBT such that in at least one predetermined mode of operation of the LIGBT αv<1−αp where αp is a current gain of a parasitic bipolar transistor having a base-emitter junction formed by a Schottky contact between the a semiconductor surface and a metal enriched epoxy die attach. | 2011-03-10 |
| 20110057231 | Semiconductor device and method for manufacturing of the same - The present invention provides a semiconductor device including: a base substrate; a first semiconductor layer disposed on the base substrate; first ohmic electrodes disposed on a central region of the first semiconductor layer; a second ohmic electrode having a ring shape surrounding the first ohmic electrodes, on edge regions of the first semiconductor layer; a second semiconductor layer interposed between the first ohmic electrodes and the first semiconductor layer; and a Schottky electrode part which covers the first ohmic electrodes on the central regions, and is spaced apart from the second ohmic electrode. | 2011-03-10 |
| 20110057232 | SEMICONDUCTOR DEVICES INCLUDING SHALLOW IMPLANTED REGIONS AND METHODS OF FORMING THE SAME - Methods of forming a semiconductor device include forming a dielectric layer on a Group III-nitride semiconductor layer, selectively removing portions of the dielectric layer over spaced apart source and drain regions of the semiconductor layer, implanting ions having a first conductivity type directly into the source and drain regions of the semiconductor layer, annealing the semiconductor layer and the dielectric layer to activate the implanted ions, and forming metal contacts on the source and drain regions of the semiconductor layer. | 2011-03-10 |
| 20110057233 | Semiconductor component and method for manufacturing of the same - The present invention provides a semiconductor component. The semiconductor component in accordance with the present invention includes a lower layer including a low resistance layer and a high resistance layer with higher resistivity than the low resistance layer while surrounding a lateral surface of the low resistance layer; a source electrode disposed on a front surface of the high resistance layer; a gate structure disposed on a front surface of the low resistance layer; a drain structure disposed on a rear surface of the low resistance layer; and a base substrate surrounding the drain structure on a rear surface of the high resistance layer. | 2011-03-10 |
| 20110057234 | Semiconductor device and method for manufacturing of the same - Disclosed is a semiconductor device including: a base substrate; a semiconductor layer disposed on the base substrate; an ohmic electrode part which has ohmic electrode lines disposed in a first direction, on the semiconductor layer; and a Schottky electrode part which is disposed to be spaced apart from the ohmic electrode lines on the semiconductor layer and includes Schottky electrode lines disposed in the first direction, wherein the Schottky electrode lines and the ohmic electrode lines are alternately disposed in parallel, and the ohmic electrode part further includes first ohmic electrodes covered by the Schottky electrode lines on the semiconductor layer. | 2011-03-10 |
| 20110057235 | SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment of the present invention includes a substrate, a compound semiconductor layer, a device region, a drain electrode, a source electrode, a source pad, a gate electrode and a metal. The substrate has a first aperture in a back surface thereof. The compound semiconductor layer is formed on the substrate. The device region is formed on the compound semiconductor layer. The drain electrode is formed transversely to the device region. The source electrode is formed transversely to the device region and with a distance from the drain electrode. The source pad is connected to the source electrode and formed on a non-device region surrounding the device region on the compound semiconductor layer. The gate electrode is formed between the source electrode and the drain electrode, above the first aperture and transversely to the device region. The metal is formed on the back surface of the substrate, including the first aperture and a second aperture penetrating the substrate and the compound semiconductor layer in such a manner as to expose a part of the source pad from the back surface of the substrate. | 2011-03-10 |
| 20110057236 | Inertial sensor having a field effect transistor - An inertial sensor, having a field effect transistor which includes a gate electrode ( | 2011-03-10 |
| 20110057237 | SEMICONDUCTOR DEVICES AND METHODS OF FORMING THEREOF - Provided is a semiconductor device. The semiconductor device includes: a substrate; an active layer on the substrate; a capping layer on the active layer; source/drain electrodes on the capping layer; a gate electrode on the active layer; and a first void region on a first sidewall of the gate electrode and a second void region on a second sidewall facing the first sidewall. | 2011-03-10 |
| 20110057238 | CMOS PIXEL SENSOR WITH DEPLETED PHOTOCOLLECTORS AND A DEPLETED COMMON NODE - An active pixel sensor in a p-type semiconductor body includes an n-type common node formed below a pinning region. A plurality of n-type blue detectors more lightly doped than the common node are disposed below pinning regions and are spaced apart from the common node forming channels below blue color-select gates. A buried green photocollector is coupled to the surface through a first deep contact spaced apart from the common node forming a channel below a green color-select gate. A red photocollector buried deeper than the green photocollector is coupled to the surface through a second deep contact spaced apart from the common node forming a channel below a red color-select gate. A reset-transistor has a source disposed over and in contact with the common node. A source-follower transistor has gate coupled to the common node, a drain coupled to a power-supply node, and a source forming a pixel-sensor output. | 2011-03-10 |
| 20110057239 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device comprises a capacitor in which a lower electrode, an adhesive layer, a capacitance insulating film, and an upper electrode are provided in series. The capacitance insulating film has laminated films in which a first metal oxide film and a second metal oxide film are alternatively laminated so that the first metal oxide film contacts with the adhesive layer. The adhesive layer has thickness of 0.3 nm or more and is an oxide film including at least one element selected from element contained in the lower electrode. | 2011-03-10 |
| 20110057240 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a plurality of conduction plugs disposed on an active region, a bit line connected to a conduction plug of the plurality of conduction plugs which is disposed in a central portion of the active region, and storage nodes connected with conduction plugs of the plurality of conduction plugs which are disposed at both peripherals of the active region and passing over the active region. | 2011-03-10 |
| 20110057241 | FORMING SILICON TRENCH ISOLATION (STI) IN SEMICONDUCTOR DEVICES SELF-ALIGNED TO DIFFUSION - Silicon trench isolation (STI) is formed between adjacent diffusions in a semiconductor device, such as between bitlines in a memory array. The STI may be self-aligned to the diffusions, and may prevent misaligned bitline (BL) contacts from contacting silicon outside of the corresponding bitlines. The bitline contacts may have sufficient overlap of the bitlines to ensure full coverage by the bitlines. Bitline oxides formed over buried bitlines may be used to self-align trenches of the STI to the bitlines. The STI trenches may be lined with a CMOS spacer, salicide blocking layer and/or a contact etch stop layer. STI may be formed after Poly-2 etch or after word line salicidation. The memory cells may be NVM devices such as NROM, SONOS, SANOS, MANOS, TANOS or Floating Gate (FG) devices. | 2011-03-10 |
| 20110057242 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device having a source-side-injected split-gate type of nonvolatile memory cell which can be formed by a one-layer polysilicon CMOS process is provided. A memory cell includes a first memory cell unit including first and second diffusion regions formed on a semiconductor substrate surface, and first and second gate electrodes separately formed through a gate insulation film on a first channel region between the first and second diffusion regions, a second memory cell unit including third and fourth diffusion regions formed on the semiconductor substrate surface, and a third gate electrode formed through a gate insulation film on a second channel region between the third and fourth diffusion regions, and a control terminal. The first to third gate electrodes are formed of the same electrode material layer. The second and third gate electrodes are electrically connected to form a floating gate capacitively coupled to the control terminal. | 2011-03-10 |
| 20110057243 | NON-VOLATILE MEMORY WITH A STABLE THRESHOLD VOLTAGE ON SOI SUBSTRATE - A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate. | 2011-03-10 |
| 20110057244 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device, comprising: forming, on a semiconductor substrate a gate insulating film for a high-voltage transistor of a peripheral circuit; forming on the gate insulating film a gate electrode for the high-voltage transistor; removing the gate insulating film positioned on the semiconductor substrate on both side portions of the gate electrode; forming an impurity diffusion region in a surface of the semiconductor substrate; depositing a first silicon oxide film to extend over surfaces of the gate electrode and the impurity diffusion region; etching the first silicon oxide film to form a spacer such that the spacer is formed on a side wall portion of the gate electrode and also extends over the surface of the semiconductor substrate; and forming a silicon nitride film on a surface of the spacer. | 2011-03-10 |
| 20110057245 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND A MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device according to an exemplary embodiment of the present invention including, a first gate electrode formed above a semiconductor substrate via a first insulating film, having a projecting part which projects in upper direction with a certain width; a second gate electrode formed beside a side surface of the first gate electrode via a second insulating film; two side walls having insulation properties formed on a side surface of the second gate electrode and a side surface of the projecting part respectively; and a silicide layer formed on an upper surface of the projecting part and a part of a surface of the second gate electrode, wherein a width of the projecting part is smaller than a width of the first gate electrode below the projecting part. | 2011-03-10 |
| 20110057246 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a non-volatile memory device includes a stacked structure and a voltage application portion. The stacked structure includes a memory portion, and an electrode stacked with the memory portion and having a surface having a portion facing the memory portion. The voltage application portion applies a voltage to the memory portion to cause a change in a resistance in the memory portion to store information. The surface includes a first region and a second region. The first region contains at least one of a metallic element, Si, Ga, and As. The first region is conductive. The second region contains at least one of the metallic element, Si, Ga, and As, and has a content ratio of nonmetallic element higher than a content ratio of nonmetallic element in the first region. At least one of the first region and the second region has an anisotropic shape on the surface. | 2011-03-10 |
| 20110057247 | FIN-FET Non-Volatile Memory Cell, And An Array And Method Of Manufacturing - A non-volatile memory cell has a substrate layer with a fin shaped semiconductor member of a first conductivity type on the substrate layer. The fin shaped member has a first region of a second conductivity type and a second region of the second conductivity type, spaced apart from the first region with a channel region extending between the first region and the second region. The fin shaped member has a top surface and two side surfaces between the first region and the second region. A word line is adjacent to the first region and is capacitively coupled to the top surface and the two side surfaces of a first portion of the channel region. A floating gate is adjacent to the word line and is insulated from the top surface and is capacitively coupled to the two side surfaces of a second portion of the channel region. A coupling gate is capacitively coupled to the floating gate. An erase gate is insulated from the second region and is adjacent to the floating gate and coupling gate. | 2011-03-10 |
| 20110057248 | VARIED SILICON RICHNESS SILICON NITRIDE FORMATION - A method, in one embodiment, can include forming a tunnel oxide layer on a substrate. In addition, the method can include depositing via atomic layer deposition a first layer of silicon nitride over the tunnel oxide layer. Note that the first layer of silicon nitride includes a first silicon richness. The method can also include depositing via atomic layer deposition a second layer of silicon nitride over the first layer of silicon nitride. The second layer of silicon nitride includes a second silicon richness that is different than the first silicon richness. | 2011-03-10 |
| 20110057249 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked structural body, a semiconductor pillar, and a memory unit. The stacked structural body is provided on a major surface of the substrate. The stacked structural body includes electrode films alternately stacked with inter-electrode insulating films in a direction perpendicular to the major surface. The pillar pierces the body in the direction. The memory unit is provided at an intersection between the pillar and the electrode films. The electrode films include at least one of amorphous silicon and polysilicon. The stacked structural body includes first and second regions. A distance from the second region to the substrate is greater than a distance from the first region to the substrate. A concentration of an additive included in the electrode film in the first region is different from that included in the electrode film in the second region. | 2011-03-10 |
| 20110057250 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A plurality of conductive layers are stacked in a first region and a second region. A semiconductor layer is surrounded by the conductive layers in the first region, includes a columnar portion extending in a perpendicular direction with respect to a substrate. A charge storage layer is formed between the conductive layers and a side surface of the columnar portion. The conductive layers includes first trenches, second trenches, and third trenches. The first trenches are arranged in the first region so as to have a first pitch in a first direction. The second trenches are arranged in the second region so as to have a second pitch in the first direction. The third trenches are arranged in the second region so as to have a third pitch in the first direction and so as to be sandwiched by the second trenches. | 2011-03-10 |
| 20110057251 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device includes a first region having a plurality of electrically rewritable memory cells disposed therein, and a second region adjacent to the first region. The nonvolatile semiconductor memory device includes a plurality of first conductive layers, a semiconductor layer, a charge storage layer, and an insulating columnar layer. The plurality of first conductive layers are stacked in the first region and the second region, and include a stepped portion in the second region, positions of ends of the plurality of first conductive layers being different in the stepped portion. The semiconductor layer is surrounded by the first conductive layers in the first region, includes a first columnar portion extending in a stacking direction. The charge storage layer is formed between the first conductive layers and a side surface of the first columnar portion. The insulating columnar layer is surrounded by the first conductive layers in the stepped portion, and includes a second columnar portion extending in the stacking direction and comprising an insulator. | 2011-03-10 |
| 20110057252 | METHOD FOR FORMING GATE OXIDE OF SEMICONDUCTOR DEVICE - Disclosed herein is a method for forming a triple gate oxide of a semiconductor device. The method for forming a triple gate oxide of a semiconductor device includes the steps of defining a first region where a gate oxide having a first thickness will be formed, a second region where a gate oxide having a second thickness will be formed and a third region where a gate oxide having a third thickness will be formed on a semiconductor substrate, forming a first oxide film through wet oxidation on the semiconductor substrate and forming a second oxide film on the first oxide film, blocking the first region and selectively removing portions the second oxide film and the first oxide film, which are formed on the second region and the third region, forming a third oxide film through thermal oxidation on the semiconductor substrate, blocking the first region and the second region and selectively removing a portion of the third oxide film, which is formed on the third region, and forming a fourth oxide film through thermal oxidation on the semiconductor substrate and then forming a nitride film thereon, wherein a gate oxide having a triple structure of the first oxide film/second oxide film/nitride film is formed in the first region, a gate oxide having a double structure of the third oxide film/nitride film is formed in the second region and a gate oxide having a double structure of the fourth oxide film/nitride film is formed in the third region. | 2011-03-10 |
| 20110057253 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device includes a first transistor including a first source/drain region and a first sidewall spacer, and a second transistor including a second source/drain region and a second sidewall spacer, the first sidewall spacer has a first width and the second sidewall spacer has a second width wider than the first width, and the first source/drain region has a first area and the second source/drain region has a second area larger than the first area. | 2011-03-10 |
| 20110057254 | METAL-OXIDE-SEMICONDUCTOR CHIP AND FABRICATION METHOD THEREOF - A metal-oxide-semiconductor chip having a semiconductor substrate, an epitaxial layer, at least a MOS cell, and a metal pattern layer is provided. The epitaxial layer is located on the semiconductor substrate and has an active region, a termination region, and a scribe line preserving region defined on an upper surface thereof. An etched sidewall of the epitaxial layer is located in the scribe line preserving region. The boundary portion of the upper surface of the semiconductor substrate is thus exposed. The MOS cell is located in the active region. The metal pattern layer is located on the epitaxial layer and has a gate pad coupled to the gate of the MOS cell, a source pad coupled to the source of the MOS cell, and a drain pattern, which is partly located on the upper surface of the semiconductor substrate. | 2011-03-10 |
| 20110057255 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first conductive type semiconductor substrate; a first conductive type semiconductor region provided thereon in which first conductive type first pillar regions and second conductive type second pillar regions alternately arranged; second conductive type second semiconductor regions provided on second pillar regions in an element region to be in contact with first pillar regions therein; gate electrodes each provided on adjacent second semiconductor regions and on one of the first pillar region interposed therebetween; third semiconductor regions functioning as a first conductive type source region provided in parts of the second semiconductor regions located under side portions of the gate electrodes; and a second conductive type resurf region which is a part of a terminal region surrounding the element region and which is provided on first pillar regions and second pillar regions in the part of the terminal regions. | 2011-03-10 |
| 20110057256 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first conductive type semiconductor substrate; a first conductive type semiconductor region provided thereon in which first conductive type first pillar regions and second conductive type second pillar regions alternately arranged; second conductive type second semiconductor regions provided on second pillar regions in an element region to be in contact with first pillar regions therein; gate electrodes each provided on adjacent second semiconductor regions and on one of the first pillar region interposed therebetween; third semiconductor regions functioning as a first conductive type source region provided in parts of the second semiconductor regions located under side portions of the gate electrodes; and a second conductive type resurf region which is a part of a terminal region surrounding the element region and which is provided on first pillar regions and second pillar regions in the part of the terminal regions. | 2011-03-10 |
| 20110057257 | Semiconductor device and method for manufacturing the same - The present invention provides a semiconductor device including: a base substrate; a semiconductor layer which is disposed on the base substrate and has a recess structure formed thereon; a gate structure covering the recess structure; a source electrode and a drain electrode which are disposed to be spaced apart from each other with respect to the gate structure interposed therebetween, on the semiconductor layer, wherein the semiconductor layer having an upper layer whose thickness is increased toward a first direction facing the drain electrode from the gate structure. | 2011-03-10 |
| 20110057258 | DUAL STRESS DEVICE AND METHOD - A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure. | 2011-03-10 |
| 20110057259 | METHOD FOR FORMING A THICK BOTTOM OXIDE (TBO) IN A TRENCH MOSFET - A method for forming a thick bottom oxide in the bottom of a trench used in a vertical MOSFET. Initially, an n-type substrate has an n-type epitaxial layer grown thereon. A top portion of the n-type epitaxial layer is implanted with p-type dopants to provide a p-layer. A trench is then etched into the p- and n-type epitaxial layer. A high density plasma chemical vapor deposition (HDPCVD) process is used to either partially or fully fill the trench. Any oxide on the top surface of the p-layer is then removed, such as by using a chemical mechanical polishing step. Then, an isotropic etching step, such as a wet etch, is used to remove the silicon dioxide from the trench, while leaving a thick bottom oxide at the bottom of the trench. The HDPCVD process utilizes minimal thermal budget to form the thick bottom oxide. | 2011-03-10 |
| 20110057260 | SEMICONDUCTOR DEVICE - A dummy transistor and a field effect transistor are arranged in a second direction. The dummy transistor is located at least at one end in a second direction. | 2011-03-10 |
| 20110057261 | SEMICONDUCTOR DEVICE HAVING RECESS CHANNEL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a recess channel structure includes a semiconductor substrate having a recess formed in a gate forming area in an active area; an insulation layer formed in the semiconductor substrate so as to define the active area and formed so as to apply a tensile stress in a channel width direction; a stressor formed in a surface of the insulation layer and formed so as to apply a compressive stress in a channel height direction; a gate formed over the recess in the active area; and source/drain areas formed in a surface of the active area at both side of the gate. | 2011-03-10 |
| 20110057262 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate, an epitaxial layer, a first sinker, a transistor, a diode unit, a first buried layer, and a second buried layer is provided. When the semiconductor device is operated at the high voltage, the highly large substrate current due to the external load is avoided through the diode unit disposed in the semiconductor device of an embodiment consistent with the invention. Furthermore, according to the design of the semiconductor device, the issue of the narrow input voltage range is improved, and interference of the semiconductor device with the other semiconductor devices is prevented. | 2011-03-10 |
| 20110057263 | ULTRA HIGH VOLTAGE MOS TRANSISTOR DEVICE - An ultra high voltage MOS transistor device includes a substrate having a first conductive type, a first well having a second conductive type and a second well having the first conductive type formed in the substrate, a drain region having the second conductive type formed in the first well, a source region having the second conductive type formed in the second well, a first doped region having the first conductive type formed between the second well and the substrate, an insulating layer formed in a first recess in the first well, a gate formed on the substrate between the source region and the first well, and a recessed channel region formed in the substrate underneath the gate. | 2011-03-10 |
| 20110057264 | METHOD FOR PROTECTING THE GATE OF A TRANSISTOR AND CORRESPONDING INTEGRATED CIRCUIT - A gate of a transistor in an integrated circuit is protected against the production of an interconnection terminal for a source/drain region. The transistor includes a substrate, at least one active zone formed in the substrate, at least one insulating zone formed in the substrate and a gate, the gate being formed above an active zone. A dielectric layer is formed on the transistor, the dielectric layer covering the gate. The dielectric layer is then etched while leaving it remaining at least on the gate so that the gate is electrically insulated from other elements formed above the dielectric layer. This etching is preferably carried out using a mask which was used for fabricating the gate and a mask which was used for fabricating the insulating zone. | 2011-03-10 |
| 20110057265 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Provided is a highly reliable semiconductor device equipped with a plurality of semiconductor elements having desired properties, respectively; and a manufacturing method facilitating the manufacture of the semiconductor device. The semiconductor device is manufactured by forming a gate-electrode metal film having a thickness of from 3 to 30 nm over the entire upper surface of a gate insulating film; forming an n-side cap layer having a thickness of 10 nm or less over the entire upper surface of a portion of the gate-electrode metal film belonging to an nFET region by using a material different from that of the gate-electrode metal film; and carrying out heat treatment over the n-side cap layer to diffuse the material of the n-side cap layer into the gate-electrode metal film immediately below the n-side cap layer and react them to form an n-side gate-electrode metal film in a nFET region. A poly-Si layer is then deposited, followed by gate electrode processing. | 2011-03-10 |
| 20110057266 | BIPOLAR TRANSISTOR INTEGRATED WITH METAL GATE CMOS DEVICES - A high-k gate dielectric layer and a metal gate layer are formed and patterned to expose semiconductor surfaces in a bipolar junction transistor region, while covering a CMOS region. A disposable material portion is formed on a portion of the exposed semiconductor surfaces in the bipolar junction transistor area. A semiconductor layer and a dielectric layer are deposited and patterned to form gate stacks including a semiconductor portion and a dielectric gate cap in the CMOS region and a cavity containing mesa over the disposable material portion in the bipolar junction transistor region. The disposable material portion is selectively removed and a base layer including an epitaxial portion and a polycrystalline portion fills the cavity formed by removal of the disposable material portion. The emitter formed by selective epitaxy fills the cavity in the mesa. | 2011-03-10 |
| 20110057267 | POLYSILICON DESIGN FOR REPLACEMENT GATE TECHNOLOGY - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature. | 2011-03-10 |
| 20110057268 | SEMICONDUCTOR DEVICE AND METHOD FOR FABCRICATING THE SAME - A semiconductor device includes a resistive element and a MISFET. The resistive element includes a first conductive film formed on the semiconductor substrate and containing a metal, a second conductive film formed on the first conductive film and containing silicon, and an insulating film formed between the first conductive film and the second conductive film. | 2011-03-10 |
| 20110057269 | SEMICONDUCTOR STRUCTURES INCLUDING DUAL FINS - Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by thinning shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed. | 2011-03-10 |
| 20110057270 | SEMICONDUCTOR DEVICE - A semiconductor device includes, a gate insulating film, a gate electrode, a source/drain region, and a Si mixed crystal layer in the source/drain region. The Si mixed crystal layer includes a first Si mixed crystal layer that includes impurities with a first concentration, a second Si mixed crystal layer formed over the first Si mixed crystal layer and that includes the impurities with a second concentration higher than the first concentration, and a third Si mixed crystal layer formed over the second Si mixed crystal layer and that includes the impurities with a third concentration lower than the second concentration. | 2011-03-10 |
| 20110057271 | Semiconductor Device with Increased Breakdown Voltage - Optimization of the implantation structure of a metal oxide silicon field effect transistor (MOSFET) device fabricated using conventional complementary metal oxide silicon (CMOS) logic foundry technology to increase the breakdown voltage. The techniques used to optimize the implantation structure involve lightly implanting the gate region, displacing the drain region from the gate region, and implanting P-well and N-well regions adjacent to one another without an isolation region in between. | 2011-03-10 |
| 20110057272 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming an insulating layer over a semiconductor region; forming a multilayer resist composite including a plurality of resist layers over the insulating layer; forming an opening in the resist layers of the multilayer resist composite except in the lowermost resist layer adjacent to the insulating layer; forming a reflow opening in the lowermost resist layer; reflowing part of the lowermost resist layer exposed in the reflow opening by heating to form a slope at the surface of the lowermost resist layer; forming a first gate opening in the lowermost resist layer so as to extend from the slope; and forming a gate electrode having a shape depending on the shapes of the opening in the multilayer resist composite, the slope and the first gate opening. | 2011-03-10 |
| 20110057273 | System with Recessed Sensing or Processing Elements - Backside recesses in a base member host components, such as sensors or circuits, to allow closer proximity and efficient use of the surface space and internal volume of the base member. Recesses may include covers, caps, filters and lenses, and may be in communication with circuits on the frontside of the base member, or with circuits on an active backside cap. An array of recessed components may a form complete, compact sensor system. | 2011-03-10 |
| 20110057274 | ACCELERATION SENSOR, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The acceleration sensor according to the present invention includes a circuit chip having a prescribed circuit built into a front surface thereof; a sensor chip bonded to the front surface of the circuit chip; and a resin package for sealing the circuit chip and the sensor chip, while the sensor chip includes: a membrane arranged to oppose to the front surface of the circuit chip and having a plurality of openings; a piezoresistor formed on a surface of the membrane opposed to the circuit chip; a support section provided on a side opposite to the circuit chip with respect to the membrane and supporting a peripheral edge portion of the membrane; and a weight section provided on the side opposite to the circuit chip with respect to the membrane and integrally held on a central portion of the membrane. | 2011-03-10 |
| 20110057275 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device capable of write operation to a selected magnetoresistive element without causing a malfunction of a non-selected magnetoresistive element and a manufacturing method of this semiconductor device. The semiconductor device includes a magnetic storage element having a magnetization free layer whose magnetization direction is made variable and formed over a lead interconnect and a digit line located below the magnetic storage element, extending in a first direction, and capable of changing the magnetization state of the magnetization free layer by the magnetic field generated. The digit line includes an interconnect body portion and a cladding layer covering therewith the bottom surface and the side surface of the interconnect body portion and opened upward. The cladding layer includes a sidewall portion covering therewith the side surface of the interconnect body portion and a bottom wall portion covering therewith the bottom surface of the interconnect body portion. The thickness of the sidewall portion is made greater than that of the bottom wall portion. | 2011-03-10 |
| 20110057276 | METHOD FOR MANUFACTURING A PHOTOVOLTAIC CELL STRUCTURE - In the frame of manufacturing a photovoltaic cell a layer ( | 2011-03-10 |
| 20110057277 | Image sensor structure and fabricating method therefor - An image sensor structure and a method for making the image sensor structure, for avoiding or mitigating lens shading effect. The image sensor structure includes a substrate, a sensor array disposed at the surface of the substrate, a dielectric layer covering the sensor array, wherein the dielectric layer includes a top surface having a dishing structure, an under layer filled into the dishing structure and having a refraction index greater than that of the dielectric layer, a filter array disposed on the under layer corresponding to the sensor array, and a microlens array disposed above the filter array. A top layer may be additionally disposed to cover the filter array and the microlens array is disposed on the top layer. | 2011-03-10 |
| 20110057278 | X-RAY DETECTOR USING LIQUID CRYSTAL DEVICE - An X-ray detector includes a first substrate having a bottom surface on which a first electrode is formed. A second substrate has a top surface on which a second electrode and a polyimide layer are sequentially formed. A photoconductive layer is formed on a bottom surface of the first electrode and generates electron-hole pairs. A reflective layer is formed on a bottom surface of the photoconductive layer. A liquid crystal polymer layer is formed on a bottom surface of the reflective layer, and peaks and valleys are alternately formed on a bottom surface of the liquid crystal polymer layer. A liquid crystal layer is formed between the liquid crystal polymer layer and the polyimide layer, and liquid crystal molecules are aligned in a direction in which the peaks and valleys on the bottom surface are arranged. | 2011-03-10 |
| 20110057279 | ANTI-REFLECTIVE IMAGE SENSOR - An anti-reflective image sensor and method of fabrication are provided, the sensor including a substrate; first color sensing pixels disposed in the substrate; second color sensing pixels disposed in the substrate; third color sensing pixels disposed in the substrate; a first layer disposed directly on the first, second and third color sensing pixels; a second layer disposed directly on the first layer overlying the first, second and third color sensing pixels; and a third layer disposed directly on portions of the second layer overlying at least one of the first or second color sensing pixels, wherein the first layer has a first refractive index, the second layer has a second refractive index greater than the first refractive index, and the third layer has a third refractive index greater than the second refractive index. | 2011-03-10 |
| 20110057280 | COLOR IMAGING DEVICE AND COLOR IMAGING DEVICE FABRICATING METHOD - In a color imaging device in which a color filter layer is formed respectively for a plurality of photoelectric conversion elements arranged on a substrate, the color filter layer comprises an underlying layer of a transparent resin and a pigment layer. The pigment layer is heat fused on the underlying layer. A heat treatment temperature for heat fusing is at or above a glass transition temperature of the transparent resin constituting the underlying layer. | 2011-03-10 |
| 20110057281 | WAFER LEVEL PACKAGED INTEGRATED CIRCUIT - A wafer level packaged integrated circuit includes an array of contacts, a silicon layer and a glass layer. The silicon and glass layers are bonded together to form a bonding material layer therebetween. The bonding material layer includes gaps between the silicon layer and the glass layer at areas where no bonding material is present. An array of contacts is adjacent the semiconductor layer on a side thereof opposite the bonding layer. The wafer level packaged integrated circuit is provided with additional bonding material layer portions within the gaps and aligned with at least some of the contacts. When the wafer level packaged integrated circuit is configured as an image sensor or display having a pixel array, the additional bonding material layer portions are not used in an area of the pixel array. | 2011-03-10 |
| 20110057282 | PIXEL SENSORS OF MULTIPLE PIXEL SIZE AND METHODS OF IMPLANT DOSE CONTROL - CMOS pixel sensors with multiple pixel sizes and methods of manufacturing the CMOS pixel sensors with implant dose control are provided. The method includes forming a plurality of pixel sensors in a same substrate and forming a masking pattern over at least one of the plurality of pixel sensors that has a pixel size larger than a non-masked pixel sensor of the plurality of pixel sensors. The method further includes providing a single dosage implant to the plurality of pixel sensors. The at least one of the plurality of pixel sensors with the masking pattern receives a lower dosage than the non-masked pixel sensor. | 2011-03-10 |
| 20110057283 | PHOTOELECTRIC CONVERSION ELEMENT, PHOTOELECTRIC CONVERSION ELEMENT ASSEMBLY AND PHOTOELECTRIC CONVERSION MODULE - To provide a photoelectric conversion element that allows connection between adjacent photoelectric conversion elements by use of an inexpensive wiring member. | 2011-03-10 |
| 20110057284 | CMOS IMAGE SENSOR HAVING A CURVED SEMICONDUCTOR CHIP - A digital image sensor includes a planar substrate with one or more bonding pads on one side and a silicon chip with one or more bonding pads. The silicon chip is attached on the planar substrate through the one or more bonding pads. The attachment of the silicon chip to the planar substrate is performed in a manner such that the silicon chip, when attached, has a curved shape. | 2011-03-10 |
| 20110057285 | Sensor for detecting thermal radiation - A sensor having a monolithically integrated structure for detecting thermal radiation includes: a carrier substrate, a cavity, and at least one sensor element for detecting thermal radiation. Incident thermal radiation strikes the sensor element via the carrier substrate. The sensor element is suspended in the cavity by a suspension. | 2011-03-10 |
| 20110057286 | Semiconductor device and method for manufacturing of the same - The present invention provides a semiconductor device including: a base substrate; a first semiconductor layer which is disposed on the base substrate and has a front surface and a rear surface opposite to the front surface; first ohmic electrodes disposed on the front surface of the first semiconductor layer; a second ohmic electrode disposed on the rear surface of the first semiconductor layer; a second semiconductor layer interposed between the first semiconductor layer and the first ohmic electrodes; and a Schottky electrode part which covers the first ohmic electrodes on the front surface of the first semiconductor layer. | 2011-03-10 |
| 20110057287 | SEMICONDUCTOR DEVICE HAVING DUAL-STI AND MANUFACTURING METHOD THEREOF - A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved. | 2011-03-10 |
| 20110057288 | MEMS DEVICE AND METHOD FOR FABRICATING THE SAME - A microelectromechanical system (MEMS) device and a method for fabricating the same are described. The MEMS device includes a first electrode and a second electrode. The first electrode is disposed on a substrate, and includes at least two metal layers, a first protection ring and a dielectric layer. The first protection ring connects two adjacent metal layers, so as to define an enclosed space between two adjacent metal layers. The dielectric layer is disposed in the enclosed space and connects two adjacent metal layers. The second electrode is disposed on the first electrode, wherein a cavity is formed between the first electrode and the second electrode. | 2011-03-10 |
| 20110057289 | Ultrashallow Emitter Formation Using ALD and High Temperature Short Time Annealing - An integrated circuit containing a bipolar transistor including an emitter diffused region with a peak doping density higher than 1·10 | 2011-03-10 |
| 20110057290 | FUSE OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A fuse of a semiconductor device comprises: a fuse pattern formed on a semiconductor substrate; an insulating film covering one side of the fuse pattern and including a trench; a conductive line disposed on the insulating film including the trench. The fuse of the semiconductor device prevents generation of cracks in a fuse box by thermal and physical stress, thereby improving reliability of the semiconductor device. | 2011-03-10 |
| 20110057291 | ULTRA HIGH SPEED SIGNAL TRANSMISSION/RECEPTON - An interconnect for transmitting an electric signal between electronic devices includes a first coupling element electromagnetically coupled to, and immediately juxtaposed to, a second coupling element. The first coupling element is mounted on and is electrically connected to a first electronic device having a first integrated circuit. The second coupling element may be mounted on and electrically connected to the first electronic device, and electrically connected to an interconnect on a second electronic device, or the second coupling element may be mounted on and electrically connected to the second electronic device. | 2011-03-10 |
| 20110057292 | CAPACITORS AND INTERCONNECTS INCLUDING AT LEAST TWO PORTIONS OF A METAL NITRIDE MATERIAL, METHODS OF FORMING SUCH STRUCTURES, AND SEMICONDUCTOR DEVICES INCLUDING SUCH STRUCTURES - Metal-insulator-metal capacitors with a bottom electrode including at least two portions of a metal nitride material. At least one of the portions of the metal nitride material includes a different material than another portion. Interconnects including at least two portions of a metal nitride material are also disclosed, at least one of the portions of the metal nitride material are formed from a different material than another portion of the metal nitride material. Methods for fabricating such MIM capacitors and interconnects are also disclosed, as are semiconductor devices including such MIM capacitors and interconnects. | 2011-03-10 |
| 20110057293 | METAL-OXIDE-METAL CAPACITOR HAVING LOW PARASITIC CAPACITOR - A metal-oxide-metal capacitor including a first metal layer of negative electric charge, a second metal layer of the negative electric charge, and at least a third metal layer formed between the first metal layer and the second metal layer, each of the at least a third metal layer including a plurality of first stripes of the negative electric charge and a plurality of second stripes of positive electric charge, wherein one of the plurality of first stripes is at a side of the third metal layer. | 2011-03-10 |
| 20110057294 | FORMATION OF SUBSTANTIALLY PIT FREE INDIUM GALLIUM NITRIDE - A method of fabricating a device layer structure includes providing a III-nitride semiconductor layer which is bonded to a bonding substrate. A device layer structure is formed on a nitrogen polar surface of the III-nitride semiconductor layer. The device layer structure includes an indium gallium nitride layer with a metal polar surface adjacent to the nitrogen polar surface of the III-nitride semiconductor layer. | 2011-03-10 |
| 20110057295 | EPITAXIAL SUBSTRATE COMPONENT MADE THEREWITH AND CORRESPONDING PRODUCTION METHOD - Proposed is a III-V-semiconductor-containing epitaxial substrate comprising at least one layer of porous III-V semiconductor material, together with a corresponding production method. Also specified is a component, particularly an LED, produced on the proposed epitaxial substrate, and a corresponding production method. | 2011-03-10 |
| 20110057296 | DELAMINATION RESISTANT PACKAGED DIE HAVING SUPPORT AND SHAPED DIE HAVING PROTRUDING LIP ON SUPPORT - A packaged electronic device includes a thickness shaped IC die including a top portion, top surface, active circuitry, bottom portion and bottom surface. A cross sectional area of the bottom surface is ≧5% less than a cross sectional area of the top surface to provide a protruding lip having a bottom lip surface. A package substrate includes a top substrate surface including substrate bonding sites, a bottom substrate surface, and a die support structure on the top substrate surface having a gap region. The bottom lip surface of the IC die is secured to the die support structure and the bottom surface of the IC die extends below the die support structure into the gap region. Coupling connectors couple the bonding features on the IC die to the substrate bonding sites. | 2011-03-10 |
| 20110057297 | SEMICONDUCTOR CHIPS HAVING GUARD RINGS AND METHODS OF FABRICATING THE SAME - Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer. | 2011-03-10 |
