10th week of 2014 patent applcation highlights part 20 |
Patent application number | Title | Published |
20140061632 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A thin film transistor substrate including a base substrate; an active pattern disposed on the base substrate and including a source electrode, a drain electrode, and a channel including an oxide semiconductor disposed between the source electrode and the drain electrode; a gate insulation pattern disposed on the active pattern; a gate electrode disposed on the gate insulation pattern and overlapping with the channel; and a light-blocking pattern disposed between the base substrate and the active pattern. | 2014-03-06 |
20140061633 | OXIDE TFT AND MANUFACTURING METHOD THEREOF - Embodiments of the invention provide an oxide TFT and a manufacturing method thereof. The oxide thin film transistor comprises: a substrate; a gate electrode formed on the substrate; a gate insulation layer covering the gate electrode; an oxide active layer formed on the gate insulation layer and comprising a source region, a drain region, and a channel between the source region and the drain region; an etching barrier layer entirely covering the active layer and the gate insulation layer; and a source electrode and a drain electrode formed on the etching barrier layer and respectively provided on both sides of the channel. The etching barrier layer is a metal layer. The oxide thin film transistor further comprises a channel protective layer, which is a non-conductive oxidation layer converted from the metal layer by performing an oxidation treatment on the metal layer. | 2014-03-06 |
20140061634 | THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE AND DISPLAY DEVICE - According to embodiments of the invention, a thin film transistor (TFT), a manufacturing method of the TFT, an array substrate and a display device are provided. The manufacturing method of the TFT comprises: forming a gate electrode on a substrate; forming a gate insulating layer on the substrate formed with the gate electrode; forming an oxide semiconductor active layer, an etch stop layer and a source/drain electrode on the gate insulating layer, wherein the etch stop layer is obtained by an oxidation treatment. | 2014-03-06 |
20140061635 | Array Substrate, Manufacturing Method And The Display Device Thereof - An array substrate, a manufacturing method thereof and a display device are provided. In the manufacturing method, the needed patterns can be formed by just three photolithography processes, wherein the semiconductor layer and the etch stop layer are formed by just one photolithography process. The method reduces one photolithography process compared to the method of the state of the art, which forms the pattern of the semiconductor layer and the etch stop layer by two photolithography processes respectively, thereby greatly reducing the manufacturing cost and improving the production efficiency. | 2014-03-06 |
20140061636 | SEMICONDUCTOR DEVICE - A semiconductor device having a high aperture ratio, including a capacitor with increased capacitance, and consuming low power is provided. The semiconductor device includes pixels defined by x (x is an integer of 2 or more) scan lines and y (y is an integer of 1 or more) signal lines, and each of the pixels includes a transistor, and a capacitor. The transistor includes a semiconductor film having a light-transmitting property. The capacitor includes a dielectric film between a pair of electrodes. In the capacitor between an (m−1)-th (m is an integer of 2 or more and x or less) scan line and an m-th scan line, a semiconductor film on the same surface as the semiconductor film having a light-transmitting property of the transistor serves as one of the pair of electrodes and is electrically connected to the (m−1)-th scan line. | 2014-03-06 |
20140061637 | Corrosive Resistant Electronic Components - An electronic device of the type wherein a semiconductor stack is functionally supported by interconnects, electrical contacts and dielectric materials. The interconnects and electrical contacts are composed of iridium, ruthenium, zirconium, niobium, tantalum, rhodium, chromium, nickel, palladium, osmium, platinum, titanium, silver and their alloys. The dielectric materials are formed of mixtures of titanium oxide, zirconium oxide, iridium oxide, silver oxide, ruthenium oxide, and niobium oxide. An adhesion layer may be formed of ruthenium, nickel, iridium, zirconium, titanium, chromium, and alloys thereof | 2014-03-06 |
20140061638 | DISPLAY DEVICE - By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included. | 2014-03-06 |
20140061639 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE - To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10 | 2014-03-06 |
20140061640 | SEMICONDUCTOR DEVICE - One object is to provide a new semiconductor device whose standby power is sufficiently reduced. The semiconductor device includes a first power supply terminal, a second power supply terminal, a switching transistor using an oxide semiconductor material and an integrated circuit. The first power supply terminal is electrically connected to one of a source terminal and a drain terminal of the switching transistor. The other of the source terminal and the drain terminal of the switching transistor is electrically connected to one terminal of the integrated circuit. The other terminal of the integrated circuit is electrically connected to the second power supply terminal. | 2014-03-06 |
20140061641 | METROLOGY TEST STRUCTURES IN TEST DIES - Test dies having metrology test structures and methods of manufacture are disclosed. The method includes forming one or more metrology test structures in a test die that are identical to one or more structures formed in an adjacent product chip. | 2014-03-06 |
20140061642 | METHOD AND APPARATUS FOR ROUTING DIE SIGNALS USING EXTERNAL INTERCONNECTS - Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die. | 2014-03-06 |
20140061643 | SEMICONDUCTOR DEVICE - A semiconductor device includes an AC coupling element, and a temperature monitoring unit that outputs a temperature monitor signal, the temperature monitoring unit has a first temperature monitoring element that outputs the temperature monitor signal, and the first temperature monitoring element is arranged in a region immediately below or a region adjacent to the AC coupling element. | 2014-03-06 |
20140061644 | SUPER-JUNCTION SEMICONDUCTOR DEVICE - An SJ-MOSFET can include an active region serving as a main current path and a temperature detection region including a temperature detecting diode. Main SJ cells in which n drift regions and p partition regions are alternately adjacent to each other are arranged in a drift layer in the active region. The temperature detection region is provided in the active region. Fine SJ cells in which n drift regions and p partition regions are alternately bonded to each other at a pitch less than that of the n drift region and the p partition region of the main SJ cell are arranged in the drift layer in the temperature detection region. The temperature detecting diode is formed above the fine SJ cells with an insulating film) interposed therebetween. The temperature detecting diode includes a p | 2014-03-06 |
20140061645 | Thin Film Transistor Array Substrate, Manufacturing Method Thereof, And Display Device - A thin film transistor (TFT) array substrate, a manufacturing method thereof and a display device are provided. The manufacturing method comprises: forming a first passivation layer ( | 2014-03-06 |
20140061646 | Arrray Substrate And Display Device - Embodiments of the invention provide an array substrate and a display device. The array substrate comprises a common electrode and a pixel electrode that are formed on a base substrate. The common electrode comprises a first common electrode and a second common electrode, the first common electrode is provided below the pixel electrode and separated from the pixel electrode by an insulating layer, the second common electrode is provided in the same layer as the pixel electrode. The pixel electrode comprises a plurality of strip electrodes, the second common electrode also comprises a plurality of strip electrodes, and the strip electrodes of the pixel electrode and the strip electrodes of the second common electrode are alternately arranged. | 2014-03-06 |
20140061647 | Field-Effect Semiconductor Device and Manufacturing Method Therefor - According to an embodiment of a field-effect semiconductor device, the field-effect semiconductor device includes a semiconductor body and a source electrode. The semiconductor body includes a drift region, a gate region and a source region of a first semiconductor material having a first band-gap and an anode region of a second semiconductor material having a second band-gap lower than the first band-gap. The drift region is of a first conductivity type. The gate region forms a pn-junction with the drift region. The source region is of the first conductivity type and in resistive electric connection with the drift region and has a higher maximum doping concentration than the drift region. The anode region is of the second conductivity type, forms a heterojunction with the drift region and is spaced apart from the source region. The source metallization is in resistive electric connection with the source region and the anode region. | 2014-03-06 |
20140061648 | THIN FILM TRANSISTOR INCLUDING DIELECTRIC STACK - A transistor includes a substrate; a gate including a first electrically conductive layer stack on the substrate; and a first inorganic thin film dielectric layer on the substrate with the first inorganic thin film dielectric layer having a first pattern. A second inorganic thin film dielectric layer, having a second pattern, is in contact with the first inorganic thin film dielectric layer. The first inorganic thin film dielectric layer and the second thin film dielectric layer have the same material composition. A semiconductor layer has a third pattern. A source/drain includes a second electrically conductive layer stack. | 2014-03-06 |
20140061649 | HIGH PERFORMANCE THIN FILM TRANSISTOR - A transistor includes a substrate; a gate including a first electrically conductive layer stack on the substrate; and a first inorganic thin film dielectric layer on the substrate with the first inorganic thin film dielectric layer having a first pattern. A second inorganic thin film dielectric layer, having a second pattern, is in contact with the first inorganic thin film dielectric layer. The first inorganic thin film dielectric layer and the second thin film dielectric layer have the same material composition. A third inorganic thin film dielectric layer has a third pattern. A semiconductor layer is in contact with and has the same pattern as the third inorganic thin film dielectric material layer. A source/drain includes a second electrically conductive layer stack. | 2014-03-06 |
20140061650 | TRANSISTOR STRUCTURES AND METHODS OF FABRICATION THEREOF - An electronic device is presented, such as a thin film transistor. The device comprises a patterned electrically-conductive layer associated with an active element of the electronic device. The electrically-conductive layer has a pattern defining an array of spaced-apart electrically conductive regions. This technique allows for increasing an electric current through the device. | 2014-03-06 |
20140061651 | ELECTROPHORETIC DISPLAY DEVICE WITH PHOTO DETECTING INPUT - An electrophoretic display device includes a photosensitive transistor in a thin-film-transistor layer that may be used to receive an optical signal as input control signal. The thin-film-transistor layer also includes an electrical switch element for driving an electrophoretic layer to display content. A switching transistor may also be included in the thin-film-transistor layer for selectively turning on the photosensitive transistor. By incorporating the photosensitive transistor and the switching transistor into the existing thin-film-transistor layer of an active matrix electrophoretic display device, optical sensing touch control is made applicable in the electrophoretic display device without compromising its advantageous light, flexible, thin features. | 2014-03-06 |
20140061652 | ROUTING FOR HIGH RESOLUTION AND LARGE SIZE DISPLAYS - Embodiments of the present disclosure related to electronic displays and electronic devices incorporating such displays which employ a device, method, or combination thereof for reducing the width of gate lines and/or data lines in the display. The result of which allows for increased pixel aperture size. The present disclosure provides techniques for reducing the width of gate lines and/or data lines while maintaining an acceptable resistance level in the gate lines and/or data lines. | 2014-03-06 |
20140061653 | SUBSTRATE INCLUDING OXIDE THIN FILM TRANSISTOR, METHOD FOR FABRICATING THE SAME, AND DRIVING CIRCUIT FOR LIQUID CRYSTAL DISPLAY DEVICE USING THE SAME - There are provided a substrate including an oxide TFT having improved initial threshold voltage degradation characteristics included in a driving circuit of a liquid crystal display (LCD) device, a method for fabricating the same, and a driving circuit for an LCD device using the same. The substrate including an oxide thin film transistor (TFT) includes: a base substrate divided into a pixel region and a driving circuit region; and a plurality of TFTs formed on the base substrate, wherein an initial threshold voltage of at least one of the plurality of TFTs formed in the driving circuit region is positive-shifted to have a predetermined level. | 2014-03-06 |
20140061654 | SEMICONDUCTOR DEVICE - A semiconductor device including a capacitor having an increased charge capacity without decreasing an aperture ratio is provided. The semiconductor device includes a transistor including a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, and a pixel electrode electrically connected to the transistor. In the capacitor, a conductive film formed on the same surface as the light-transmitting semiconductor film in the transistor serves as one electrode, the pixel electrode serves as the other electrode, and a nitride insulating film and a second oxide insulating film which are provided between the light-transmitting semiconductor film and the pixel electrode serve as the a dielectric film. | 2014-03-06 |
20140061655 | METHOD FOR EXTREME ULTRAVIOLET ELECTROSTATIC CHUCK WITH REDUCED CLAMPING EFFECT - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a front surface and a backside surface; integrated circuit features formed on the front surface of the semiconductor substrate; and a polycrystalline silicon layer disposed on the backside surface of the semiconductor substrate. | 2014-03-06 |
20140061656 | Two Doping Regions in Lightly Doped Drain for Thin Film Transistors and Associated Doping Processes - A method is provided for fabricating thin-film transistors (TFTs) for an LCD having an array of pixels. The method includes depositing a first photoresist layer over a portion of a TFT stack that includes a conductive gate layer, and a semiconductor layer. The method also includes doping the exposed semiconductor layer with a first doping dose. The method further includes etching a portion of the conductive gate layer to expose a portion of the semiconductor layer, and doping the exposed portion of the semiconductor layer with a second doping dose. The method also includes depositing a second photoresist layer over a first portion of the doped semiconductor layer in an active area of the pixels to expose a second portion of the doped semiconductor layer in an area surrounding the active area, and doping the second portion of the doped semiconductor layer with a third doping dose. | 2014-03-06 |
20140061657 | ARRAY SUBSTRATE FOR ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - An array substrate for an organic electroluminescent display device includes a substrate including a display area and a non-display area; a gate line and a data line; a thin film transistor including a semiconductor layer of polycrystalline silicon, a gate insulating layer, a gate electrode, an inter insulating layer, a source electrode, and a drain electrode; auxiliary lines formed of a same material and on a same layer as the data line; a passivation layer of organic insulating material and including a drain contact hole exposing the drain electrode, and an auxiliary line contact hole exposing one of the auxiliary lines; and a first electrode and a line connection pattern on the passivation layer, wherein the first electrode contacts the drain electrode and the line connection pattern contacts the one of the first auxiliary pattern. | 2014-03-06 |
20140061658 | High Electron Mobility Transistor and Manufacturing Method Thereof - The present invention discloses an enhanced mode high electron mobility transistor (HEMT) which includes: a P-type gallium nitride (GaN) layer; a barrier layer, which is formed on and connected to the GaN layer; a dielectric layer, which is formed on and connected to the GaN layer, wherein the barrier layer does not overlap at least part of the dielectric layer; a gate, which is formed on the dielectric layer for receiving a gate voltage; and a source and a drain, which are formed at two sides of the gate on the GaN layer respectively; wherein a two dimensional electron gas (2DEG) is formed at a junction of the GaN layer and the barrier layer which does not include a portion of the junction below the gate, and the 2DEG does not electrically connect the source to the drain when there is no voltage applied to the gate. | 2014-03-06 |
20140061659 | GaN Dual Field Plate Device with Single Field Plate Metal - A low leakage current transistor ( | 2014-03-06 |
20140061660 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor light emitting device includes a supporting substrate, a light emitting layer including a nitride semiconductor, and a nitride multilayer film. The nitride multilayer film includes a first layer including a first nitride semiconductor containing aluminum nitride, a second layer including a second nitride semiconductor containing gallium nitride, and a third layer including the first nitride semiconductor containing aluminum nitride. | 2014-03-06 |
20140061661 | SAPPHIRE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME AND NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT - [Technical Problem] | 2014-03-06 |
20140061662 | GROUP III NITRIDE WAFER AND ITS PRODUCTION METHOD - The present invention discloses a group III nitride wafer such as GaN, AlN, InN and their alloys having one surface visually distinguishable from the other surface. After slicing of the wafer from a bulk crystal of group III nitride with a mechanical method such as multiple wire saw, the wafer is chemically etched so that one surface of the wafer is visually distinguishable from the other surface. The present invention also discloses a method of producing such wafers. | 2014-03-06 |
20140061663 | SEMICONDUCTOR BUFFER STRUCTURE, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF - A semiconductor structure including a first nitride semiconductor layer, a second nitride semiconductor layer, and a third layer between the first nitride semiconductor layer and the second nitride semiconductor layer. The first nitride semiconductor layer has a first gallium composition ratio, the second nitride semiconductor layer has a second gallium composition ratio different from the first metal composition ratio, and the third layer has a third gallium composition ratio greater than at least one of the first gallium composition ratio or the second gallium composition ratio. The structure may also include a fourth layer for reducing tensile stress or increasing compression stress experienced by at least the second nitride semiconductor layer. | 2014-03-06 |
20140061664 | LIGHT EMITTING DEVICE USING GAN LED CHIP - A light emitting device is constituted by flip-chip mounting a GaN-based LED chip. The GaN-based LED chip includes a light-transmissive substrate and a GaN-based semiconductor layer formed on the light-transmissive substrate, wherein the GaN-based semiconductor layer has a laminate structure containing an n-type layer, a light emitting layer and a p-type layer in this order from the light-transmissive substrate side, wherein a positive electrode is formed on the p-type layer, the electrode containing a light-transmissive electrode of an oxide semiconductor and a positive contact electrode electrically connected to the light-transmissive electrode, and the area of the positive contact electrode is half or less of the area of the upper surface of the p-type layer. | 2014-03-06 |
20140061665 | NITRIDE SEMICONDUCTOR WAFER - A nitride semiconductor wafer includes a substrate, and a buffer layer formed on the substrate and including an alternating layer of Al | 2014-03-06 |
20140061666 | METHOD AND APPARATUS FOR PRODUCING LARGE, SINGLE-CRYSTALS OF ALUMINUM NITRIDE - Bulk single crystals of AlN having a diameter greater than about 25 mm and dislocation densities of about 10,000 cm | 2014-03-06 |
20140061667 | SEMICONDUCTOR CHIP, DISPLAY COMPRISING A PLURALITY OF SEMICONDUCTOR CHIPS AND METHODS FOR THE PRODUCTION THEREOF - An optoelectronic semiconductor chip including a semiconductor body of semiconductor material, an outcoupling face arranged downstream of the semiconductor body in an emission direction and a mirror layer, wherein the semiconductor body includes an active layer that generates radiation, the mirror layer is arranged on the side of the semiconductor body remote from the outcoupling face, and a gap between the active layer and the mirror layer is set such that radiation emitted by the active layer towards the outcoupling face interferes with radiation reflected at the mirror layer such that the semiconductor chip features an emitted radiation pattern with a selected direction in the forward direction. | 2014-03-06 |
20140061668 | GaN Single Crystal Substrate and Method of Manufacturing Thereof and GaN-based Semiconductor Device and Method of Manufacturing Thereof - A GaN single crystal substrate has a main surface with an area of not less than 10 cm | 2014-03-06 |
20140061669 | CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP PACKAGE - A chip package is provided, the chip package including: a carrier including at least one cavity; a chip disposed at least partially within the at least one cavity; at least one intermediate layer disposed over at least one side wall of the chip; wherein the at least one intermediate layer is configured to thermally conduct heat from the chip to the carrier. | 2014-03-06 |
20140061670 | WIDE GAP SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A wide gap semiconductor device has a substrate and a Schottky electrode. The substrate is made of a wide gap semiconductor material and has a first conductivity type. The Schottky electrode is arranged on the substrate to be in contact therewith and is made of a single material. The Schottky electrode includes a first region having a first barrier height and a second region having a second barrier height higher than the first barrier height. The second region includes an outer peripheral portion of the Schottky electrode. Thus, a wide gap semiconductor device capable of achieving less leakage current and a method for manufacturing the same can be provided. | 2014-03-06 |
20140061671 | WIDE GAP SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A wide gap semiconductor device includes a substrate and a Schottky electrode. The substrate formed of a wide gap semiconductor material has a main face, and includes a first-conductivity-type region and a second-conductivity-type region. The Schottky electrode is arranged adjoining the main face of the substrate. At the substrate, there is foamed a trench having a side face continuous with the main face and a bottom continuous with the side face. The Schottky electrode adjoins the first-conductivity-type region at the side face of the trench and the main face, and adjoins the second-conductivity-type region at the bottom of the trench. The side face of the trench is inclined relative to the main face of the substrate. | 2014-03-06 |
20140061672 | SEMICONDUCTOR DEVICE - A semiconductor device includes an active region in which current flows when the semiconductor device is in an on state and a breakdown voltage structure portion which surrounds the active region. In the active region, a MOS gate structure includes, a p well region, an n | 2014-03-06 |
20140061673 | SEMICONDUCTOR UNIT AND SEMICONDUCTOR DEVICE USING THE SAME - In some aspects of the invention, semiconductor unit can produce chips performing uniform parallel operation and a low-thermal-resistance. Aspects of the invention can include a plurality of small semiconductor chips of one and the same kind formed by use of an SiC substrate, which is a wide gap substrate are sandwiched between two conductive plates. In this manner, there can be provided a high-reliability semiconductor unit in which parallel operation of the semiconductor chips is uniformized so that breakdown caused by current concentration can be prevented. | 2014-03-06 |
20140061674 | SiC SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In some aspects of the invention, a layer containing titanium and nickel is formed on an SiC substrate. A nickel silicide layer containing titanium carbide can be formed by heating. A carbon layer precipitated is removed by reverse sputtering. Thus, separation of an electrode of a metal layer formed on nickel silicide in a subsequent step is suppressed. The effect of preventing the separation can be further improved when the relation between the amount of precipitated carbon and the amount of carbon in titanium carbide in the surface of nickel silicide from which the carbon layer has not yet been removed satisfies a predetermined condition. | 2014-03-06 |
20140061675 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device that is able to increase the gate reliability, and to provide a method for manufacturing the silicon carbide semiconductor device, and that includes: a source electrode selectively formed on a source region; a gate insulating film formed so as to extend over the source region; and a gate electrode formed on the gate insulating film. The source region includes a first source region located below the source electrode, and a second source region surrounding the first source region. The doping concentration in a superficial layer of the second source region is lower than the doping concentration in a superficial layer of the first source region. The doping concentration in the second source region is higher in a deep portion than in a superficial portion thereof. | 2014-03-06 |
20140061676 | METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT AND COMPONENT PRODUCED IN SUCH MANNER - A method of producing an optoelectronic component includes providing a semiconductor chip having an active layer that generates radiation and is arranged on a carrier, applying a dispersed material including a matrix material and particles embedded therein to the semiconductor chip and/or the carrier at least in regions, wherein before the dispersed material is applied, at least one chip edge of the semiconductor chip facing away from the carrier is modified such that the dispersed material at least partly separates into its constituents during application at the chip edge. | 2014-03-06 |
20140061677 | Opto-Electronic Sensor - Some embodiments of the present disclosure relate to an infrared (IR) opto-electronic sensor having a silicon waveguide implemented on a single silicon integrated chip. The IR sensor has a semiconductor substrate having a silicon waveguide extends along a length between a radiation input conduit and a radiation output conduit. The radiation input conduit couples radiation into the silicon waveguide, while the radiation output conduit couples radiation out from the silicon waveguide. The silicon waveguide conveys the IR radiation from the radiation input conduit to the radiation output conduit at a single mode. As the radiation is conveyed by the silicon waveguide, an evanescent field is formed that extends outward from the silicon waveguide to interact with a sample positioned between the radiation input conduit and the radiation output conduit. | 2014-03-06 |
20140061678 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a primary side lead, a light-emitting element electrically connected to the primary side lead, and a thyristor-type light-receiving element. The light-receiving element includes a first face for detecting light emitted from the light-emitting element, and a second face provided on an opposite side of the first face. The light-receiving element includes an anode electrode, a cathode electrode, and a gate electrode that are provided on the first face. The device further includes a secondary side first lead electrically connected to the anode electrode, a secondary side second lead electrically connected to the cathode electrode, and a secondary side third lead electrically connected to the gate electrode. The secondary side third lead is connected to the second face of the light-receiving element. | 2014-03-06 |
20140061679 | SEMICONDUCTOR ELECTRICITY CONVERTER - A semiconductor electricity converter is provided. The semiconductor electricity converter includes: an AC input module, for converting an input AC electric energy into a light energy, the AC input module including a plurality of semiconductor electricity-to-light conversion structures, each semiconductor electricity-to-light conversion structure including an electricity-to-light conversion layer; and an AC output module, for converting the light energy into an output AC electric energy, the AC output module including a plurality of semiconductor light-to-electricity conversion structures, each semiconductor light-to-electricity conversion structure including a light-to-electricity conversion layer; in which an emitting spectrum of each semiconductor electricity-to-light conversion structure and an absorption spectrum of each semiconductor light-to-electricity conversion structure are matched with each other. | 2014-03-06 |
20140061680 | HIGH VOLTAGE SOLID-STATE TRANSDUCERS AND SOLID-STATE TRANSDUCER ARRAYS HAVING ELECTRICAL CROSS-CONNECTIONS AND ASSOCIATED SYSTEMS AND METHODS - Solid-state transducer (“SST”) dies and SST arrays having electrical cross-connections are disclosed herein. An array of SST dies in accordance with a particular embodiment can include a first terminal, a second terminal and a plurality of SST dies coupled between the first and second terminals with at least a pair of the SST dies being coupled in parallel. The plurality of SST dies can individually include a plurality of junctions coupled in series with an interconnection between each individual junction. Additionally, the individual SST dies can have a cross-connection contact coupled to the interconnection. In one embodiment, the array can further include a cross-connection between the cross-connection contacts on the pair of the SST dies. | 2014-03-06 |
20140061681 | DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE SAME AND ELECTRO-WETTING DISPLAY PANEL HAVING THE SAME - In a display substrate, a method for manufacturing the display substrate and an electro-wetting display apparatus including the display substrate, the display substrate includes a base substrate, a sidewall defining a unit pixel area, a pixel electrode, a hydrophobic insulating layer and a light blocking layer. The sidewall is on the base substrate and defines the unit pixel area. The pixel electrode is in the unit pixel area. The hydrophobic insulating layer is on the sidewall and the pixel electrode. The light blocking layer is on the hydrophobic insulating layer and overlaps the sidewall. | 2014-03-06 |
20140061682 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a conductive member, a semiconductor element, a sealing section. The semiconductor element is provided on an upper surface of the conductive member. The sealing section seals part of the conductive member and the semiconductor element. The upper end of the semiconductor element is located above the uppermost portion of the conductive member. The conductive member includes an inclined surface and a lower surface. The inclined surface is provided on an outside of the sealing section and makes an acute angle with the upper surface. The lower surface is provided outside the sealing section and makes an obtuse angle with the inclined surface. | 2014-03-06 |
20140061683 | LIGHT EMITTING DIODE PACKAGE AND METHOD FOR MANUFCTURING THE SAME - An LED package includes a substrate, an LED chip mounted on the substrate, and a lens formed on the substrate and encapsulating the LED chip therein. The lens includes a top surface and a bottom surface connecting a bottom end of the top surface. The bottom surface is directly formed on the substrate. A tangent of the top surface extends through a joint of the top surface and the bottom surface to define a contacting angle between the tangent and a plumb line, and the contacting angle is not larger than 60 degrees. | 2014-03-06 |
20140061684 | LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light-emitting device may comprise a substrate, an electric wire fixed to the substrate, and a plurality of light-emitting diodes mounted to the electric wire. According to one embodiment, each of the plurality of light-emitting diodes is an LED chip, and the light-emitting diodes on the substrate are sealed individually or collectively by one or more sealing members. According to another embodiment, the substrate has a plurality of through holes, wherein a plurality of portions of the electric wire provided on a rear surface side of the substrate communicates with a front surface side of the substrate at the plurality of through holes of the substrate, and wherein the plurality of light-emitting diodes is respectively mounted to the respective portions of the electric wire that communicate with the front surface side of the substrate. Other embodiments relate to methods of manufacturing a light-emitting device. | 2014-03-06 |
20140061685 | LIGHT EMITTING DEVICE - A light emitting device includes a conductive support member, and first and second light emitting structures. A channel layer is provided around lower portions of the first and second light emitting structures. A first electrode is coupled to a first conductive first semiconductor layer of the first light emitting structure, and a second electrode is coupled to a second semiconductor layer of the first light emitting structure. A third electrode is coupled to a third semiconductor layer of the second light emitting structure, and a fourth electrode is coupled to a fourth semiconductor layer of the second light emitting structure. A first connection part is coupled to the first electrode and the conductive support member, and a second connection part is coupled to the second and third electrodes. A third connection part is coupled to the fourth electrode and has one end provided on the channel layer. | 2014-03-06 |
20140061686 | DISPLAY APPARATUS WITH GATE ELECTRODES FORMED IN A PROJECTING MANNER - A capacitance setting line is disposed at the top end of a pixel, a light emission setting line is disposed at the bottom end of the pixel, and a gate line is disposed at the center between both the lines. A selection transistor, a potential control transistor and a capacitor are disposed between the gate line and a capacitance setting line. A short-circuit transistor, a drive transistor and a drive control transistor are disposed between the gate line and the light emission setting line. With such an arrangement, the efficient arrangement of wiring contacts can be performed, and an aperture ratio can be increased. | 2014-03-06 |
20140061687 | LED ARRAY - A method of fabricating and transferring a micro device and an array of micro devices to a receiving substrate are described. In an embodiment, an electrically insulating layer is utilized as an etch stop layer during etching of a p-n diode layer to form a plurality of micro p-n diodes. In an embodiment, an electrically conductive intermediate bonding layer is utilized during the formation and transfer of the micro devices to the receiving substrate. | 2014-03-06 |
20140061688 | LED Structure - A light emitting diode (LED) structure comprises a first dopant region, a dielectric layer on top of the first dopant region, a bond pad layer on top of a first portion the dielectric layer, and an LED layer having a first LED region and a second LED region. The bond pad layer is electrically connected to the first dopant region. The first LED region is electrically connected to the bond pad layer. | 2014-03-06 |
20140061689 | LED BASED LIGHTING SYSTEM - An LED device comprises an LED chip or LED chip array for emitting light of a color spectrum, the LED chip or array being mounted on a component having a component surface. At least one color is applied to the component surface where the color is selected to reflect light to color tune the light emitted from the LED device to obtain a desired CRI. | 2014-03-06 |
20140061690 | LIGHT EMITTING DEVICE HAVING SURFACE-MODIFIED QUANTUM DOT LUMINOPHORES - Exemplary embodiments of the present invention relate to a light emitting device including a light emitting diode and a surface-modified luminophore. The surface-modified luminophore includes a quantum dot luminophore and a fluorinated coating arranged on the quantum dot luminophore. | 2014-03-06 |
20140061691 | Array Substrate, Manufacturing Method And Display Device Thereof - The invention provides an array substrate, a manufacturing method and a display device thereof. The array substrate comprises a substrate, a gate line and a pixel electrode disposed on the substrate, a common electrode disposed above and overlaying the gate line, wherein a strip-shaped through hole is disposed on the common electrode and at least a portion of the strip-shaped through hole is positioned right above the gate line. | 2014-03-06 |
20140061692 | MULTILAYERED LED PRINTED CIRCUIT BOARD - A multilayered LED printed circuit board with electrically insulating layers includes at least one electrically insulating material and electrically conductive layers consisting of an electrically conductive material, wherein at least one of the electrically conductive layers is structured with a conductor track structure, wherein the at least one structured electrically conductive layer is arranged on an upper side of the LED printed circuit board, and wherein a plurality of LEDs is arranged on the at least one structured electrically conductive layer on the upper side. The LED printed circuit board further includes: a thermally conducting element, and thermal paths comprising an electrically conductive material, which are arranged, in each case in contact-making fashion, between the LEDs and the thermally conducting element. | 2014-03-06 |
20140061693 | NITRIDE SEMICONDUCTOR WAFER, NITRIDE SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR WAFER - According to one embodiment, a nitride semiconductor wafer includes: a silicon substrate; a buffer section provided on the silicon substrate; and a functional layer provided on the buffer section and contains nitride semiconductor. The buffer section includes first to n-th buffer layers (n being an integer of 4 or more) containing nitride semiconductor. An i-th buffer layer (i being an integer of 1 or more and less than n) of the first to n-th buffer layers has a lattice length Wi in a first direction parallel to a major surface of the first buffer layer. An (i+1)-th buffer layer provided on the i-th buffer layer has a lattice length W(i+1) in the first direction. In the first to n-th buffer layers the i-th buffer layer and the (i+1)-th buffer layer satisfy relation of (W(i+1)−Wi)/Wi≦0.008. | 2014-03-06 |
20140061694 | Method for Producing a Thin-Film Semiconductor Body and Thin-Film Semiconductor Body - A method for producing a thin-film semiconductor body is provided. A growth substrate is provided. A semiconductor layer with funnel-shaped and/or inverted pyramid-shaped recesses is epitaxially grown onto the growth substrate. The recesses are filled with a semiconductor material in such a way that pyramid-shaped outcoupling structures arise. A semiconductor layer sequence with an active layer is applied on the outcoupled structures. The active layer is suitable for generating electromagnetic radiation. A carrier is applied onto the semiconductor layer sequence. At least the semiconductor layer with the funnel-shaped and/or inverted pyramid-shaped recesses is detached, such that the pyramid-shaped outcoupling structures are configured as projections on a radiation exit face of the thin-film semiconductor body. | 2014-03-06 |
20140061695 | LIGHT-EMITTING DIODE WITH A MIRROR PROTECTION LAYER - A light-emitting diode (LED) with a mirror protection layer includes sequentially stacked an N-type electrode, an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, a metal mirror layer, a protection layer, a buffer layer, a binding layer, a permanent substrate, and a P-type electrode. The protection layer is made of metal oxide, and has a hollow frame for covering or supporting edges of the metal mirror layer. Accordingly, the metal mirror layer can be protected by the protection layer to prevent from oxidation in subsequent processes and to prevent metal deterioration during high-current operations. Thus the metal mirror layer can maintain high reflectivity, thereby increasing light extraction efficiency and electrical stability of the LED. | 2014-03-06 |
20140061696 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device is provided that includes a support substrate, a first metal layer formed on the support substrate, a transparent conductive layer formed on the first metal layer, a second metal layer embedded in the transparent conductive layer, and a semiconductor light emitting layer formed on the transparent conductive layer. A reflectance of the second metal layer to light emitted by the semiconductor light emitting layer is higher than a reflectance of the first metal layer to light emitted by the semiconductor light emitting layer. | 2014-03-06 |
20140061697 | LIGHT EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - An LED package includes adjacent first and second electrodes, first and second extension electrodes protruding sideward from the first and second electrodes, a molded body surrounding the first and second electrodes and an LED die. The molded body forms a reflecting cup located over the first and second electrodes, with each reflecting cup defining a receiving cavity in a top face thereof to receive the LED die. The first and second extension electrodes are exposed from an outer periphery of the molded body. The first electrode has a first bottom face. The second electrode has a second bottom face. The first and second bottom faces of the first and second electrodes are exposed out from a bottom face of the molded body. A method for manufacturing the LED package is also provided. | 2014-03-06 |
20140061698 | LIGHT EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - An LED package includes a first electrode, a second electrode adjacent to the first electrode, a molded body surrounding and encapsulating the first and second electrodes, and an LED die mounted on the second electrode. The molded body includes a reflecting cup located over the first and second electrodes and the reflecting cup defines a receiving cavity in a top face to receive the LED die. A first extension electrode protrudes sideward from the first electrode and a second extension electrode protrudes sideward from the second electrode. The first and second extension electrodes are exposed from an outer periphery of the molded body. A method for manufacturing the LED package is also provided. | 2014-03-06 |
20140061699 | OPTICAL LENS, LIGHT EMITTING DEVICE, AND LIGHTING DEVICE HAVING THE SAME - The light emitting device includes a light emitting chip, and an optical lens provided over the light emitting chip. The optical lens includes an incident surface into which a light emitted from the light emitting chip is incident, a recess portion opposite to the incident surface and recessed in a direction of the incident surface, an exit surface provided at a peripheral portion of the recess portion to output a light incident through the incident surface, and a convex portion protruding between the recess portion and the exit surface and connected with at least one of the recess portion and the exit surface through an inflection point. The convex portion is located inward of a line segment ranging from the light emitting chip to a first inflection point provided at an outermost portion of the recess portion. | 2014-03-06 |
20140061700 | FLIP-CHIP LIGHT-EMITTING DIODE STRUCTURE AND MANUFACTURING METHOD THEREOF - A flip-chip light-emitting diode structure comprises a carrier substrate, a light-emitting die structure, a reflective layer, an aperture, a dielectric layer, a first contact layer and a second contact layer. The light-emitting die structure, located on the carrier substrate, comprises a first type semiconductor layer, a second type semiconductor layer and a light emitting layer. The light emitting layer is formed between the first type and the second type semiconductor layer. The reflective layer is located on the first type semiconductor layer. The aperture penetrates the light-emitting die structure. The dielectric layer covers an inner sidewall of the aperture and extends to a portion of a surface of the reflective layer. The first contact layer is disposed on the part of the reflective layer not covered by the dielectric layer. The second contact layer fills up the aperture and is electrically connected to the second type semiconductor layer. | 2014-03-06 |
20140061701 | Electrode Foil and Electronic Device - There is provided an electrode foil, which can show superior light scattering, while preventing short circuit between electrodes. The electrode foil of the present invention comprises a metal foil having a thickness of from 1 μm to 250 μm, wherein the electrode foil comprises, on at least one outermost surface thereof, a light-scattering surface having a Pv/Pp ratio of 2.0 or higher, wherein the Pv/Pp ratio is a ratio of a maximum profile valley depth Pv of a profile curve to a maximum profile peak height Pp of the profile curve as measured in a rectangular area of 181 μm×136 μm in accordance with JIS B 0601-2001. | 2014-03-06 |
20140061702 | Optoelectronic Semiconductor Chip - An optoelectronic semiconductor chip includes a semiconductor layer sequence and a carrier substrate. A first and a second electrical contact layer are arranged at least regionally between the carrier substrate and the semiconductor layer sequence and are electrically insulated from each other by an electrically insulating layer. A minor layer is arranged between the semiconductor layer sequence and the carrier substrate. The semiconductor chip comprises a transparent encapsulation layer covering side surfaces of the semiconductor layer sequence, side surfaces of the minor layer and side surfaces of the electrically insulating layer facing towards the side surfaces of the semiconductor chip. | 2014-03-06 |
20140061703 | OPTOELECTRONIC SEMICONDUCTOR CHIP - An optoelectronic semiconductor chip includes a carrier including a carrier element having a mounting side; one electrically conductive n-type wiring layer arranged at the mounting side; a structured, electrically conductive contact layer having a p-side and n-side contact region and arranged at a side of the n-type wiring layer facing away from the carrier element; at least one insulation region electrically insulating the p-side contact region from the n-side contact region; at least one electrically insulating spacer layer arranged at a side of the n-type wiring layer facing away from the carrier element in a vertical direction between the p-side contact region and the n-type wiring layer, wherein the n-side contact region and the n-type wiring layer electrically conductively connect to one another, and the p-side contact region and the spacer layer border the n-side contact region in a lateral direction; an optoelectronic structure connected to the carrier. | 2014-03-06 |
20140061704 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a light emitting device comprises (a) preparing a structure including a substrate, a semiconductor layer formed on the substrate, and a p-side electrode and an n-side electrode formed on the semiconductor layer; (b) preparing a support member including a p-side wiring and an n-side wiring on the same surface thereof; (c) electrically connecting the p-side electrode and the n-side electrode of the structure to the p-side wiring and the n-side wiring of the support member, respectively, using an anisotropic conductive material containing conductive particles and a first resin; and after step (c), (d) removing the substrate from the structure. | 2014-03-06 |
20140061705 | LIGHT-EMITTING DIES INCORPORATING WAVELENGTH-CONVERSION MATERIALS AND RELATED METHODS - In accordance with certain embodiments, semiconductor dies are embedded within polymeric binder to form, e.g., freestanding white light-emitting dies and/or composite wafers containing multiple light-emitting dies embedded in a single volume of binder. | 2014-03-06 |
20140061706 | ULTRAVIOLET LIGHT EMITTING DIODE PACKAGE - An ultraviolet light emitting diode package for emitting ultraviolet light is disclosed. The ultraviolet light emitting diode package comprises an LED chip emitting light with a peak wavelength of 350 nm or less, and a protective member provided so that surroundings of the LED chip is covered to protect the LED chip, the protective member having a non-yellowing property to energy from the LED chip. | 2014-03-06 |
20140061707 | SOLID STATE LIGHT SOURCES BASED ON THERMALLY CONDUCTIVE LUMINESCENT ELEMENTS CONTAINING INTERCONNECTS - Solid state light sources based on LEDs mounted on or within thermally conductive luminescent elements provide both convective and radiative cooling. Low cost self-cooling solid state light sources can integrate the electrical interconnect of the LEDs and other semiconductor devices. The thermally conductive luminescent element can completely or partially eliminate the need for any additional heatsinking means by efficiently transferring and spreading out the heat generated in LED and luminescent element itself over an area sufficiently large enough such that convective and radiative means can be used to cool the device. | 2014-03-06 |
20140061708 | LIGHT-EMITTING DEVICE - A light-emitting device includes a first electrode; a light-emitting stacked layer on the first electrode; a first contact layer on the light-emitting stacked layer, wherein the first contact layer includes a first contact link and a plurality of first contact lines connected to the first contact link; a first conductive post in the light-emitting stacked layer and electrically connecting the first electrode and the first contact layer; and a passivation layer between the first conductive post and the light-emitting stacked layer. | 2014-03-06 |
20140061709 | WAFER LEVEL LED PACKAGE AND METHOD OF FABRICATING THE SAME - Disclosed are a light emitting diode (LED) package and a method of fabricating the same. The LED package includes a first substrate, a semiconductor stack disposed on a front surface of the first substrate, a second substrate including a first lead electrode and a second lead electrode, a plurality of connectors electrically connecting the semiconductor stack to the first and second lead electrodes, and a wavelength converter covering a rear surface of the first substrate. The semiconductor stack includes a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer. | 2014-03-06 |
20140061710 | METHOD OF FABRICATING LIGHT-EMITTING APPARATUS WITH IMPROVED LIGHT EXTRACTION EFFICIENCY AND LIGHT-EMITTING APPARATUS FABRICATED USING THE METHOD - Provided are a method of fabricating a light-emitting apparatus with improved light extraction efficiency and a light-emitting apparatus fabricated using the method. The method includes: preparing a monocrystalline substrate; forming an intermediate structure on the substrate, the intermediate structure comprising a light-emitting structure which comprises a first conductive pattern of a first conductivity type, a light-emitting pattern, and a second conductive pattern of a second conductivity type stacked sequentially, a first electrode which is electrically connected to the first conductive pattern, and a second electrode which is electrically connected to the second conductive pattern; forming a polycrystalline region, which extends in a horizontal direction, by irradiating a laser beam to the substrate in the horizontal direction such that the laser beam is focused on a beam-focusing point within the substrate; and cutting the substrate in the horizontal direction along the polycrystalline region. | 2014-03-06 |
20140061711 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element suppressing non-uniformity in light emission on a light emitting surface is provided. An n-type semiconductor layer, a light emitting layer and a p-type semiconductor layer are laminated in order, and a translucent electrode film is laminated on the p-type semiconductor layer and a p-electrode is provided on the translucent electrode film. On the other hand, an n-electrode is provided on a semiconductor layer exposure surface that exposes the n-type semiconductor layer. The p-electrode includes a connecting portion having a circular planar shape and an extending portion that extends like a long and slender strip from the connecting portion to encircle and face the n-electrode. Holes in the translucent electrode film are provided such that the density thereof is decreased along with a move from the n-electrode side toward the p-electrode side. | 2014-03-06 |
20140061712 | SIDE VIEW LIGHT EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A side view light emitting diode (LED) package includes an electrode structure, an LED die disposed on the electrode structure and an encapsulation layer covering the LED die. The encapsulation layer includes a light outputting surface. The electrode structure includes a first electrode and a second electrode spaced from each other to define a tortuous gap therebetween. Resin material for forming a substrate of the LED package fills in the gap to interconnect the first and second electrode together. The LED die is electrically connected to the first electrode and the second electrode. The present disclosure also provides a method for manufacturing the side view LED package. | 2014-03-06 |
20140061713 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes: a first conductive semiconductor layer including first and second areas; an active layer disposed on the second area; a second conductive semiconductor layer disposed on the active layer; first and second electrode branches disposed on the first and second conductive semiconductor layers, respectively; a first electrode pad electrically connected to the first electrode branch and disposed on the first electrode branch; and a second electrode pad electrically connected to the second electrode branch and disposed on the second electrode branch. | 2014-03-06 |
20140061714 | P-N SEPARATION METAL FILL FOR FLIP CHIP LEDS - A light emitting diode (LED) structure ( | 2014-03-06 |
20140061715 | ZENER DIODE DEVICE AND FABRICATION - A disclosed Zener diode includes, in one embodiment, an anode region and a cathode region that form a shallow sub-surface latitudinal Zener junction. The Zener diode may further include an anode contact region interconnecting the anode region with a contact located away from the Zener junction region and a silicide blocking structure overlying the anode region. The Zener diode may also include one or more shallow, sub-surface longitudinal p-n junctions at the junctions between lateral edges of the cathode region and the adjacent region. The adjacent region may be a heavily doped region such as the anode contact region. In other embodiments, the Zener diode may include a breakdown voltage boost region comprising a more lightly doped region located between the cathode region and the anode contact region. | 2014-03-06 |
20140061716 | ESD PROTECTION DEVICE - An electrostatic discharge protection clamp adapted to limit a voltage appearing across protected terminals of an integrated circuit to which the electrostatic discharge protection clamp is coupled is presented. The electrostatic discharge protection clamp includes a substrate, and a first electrostatic discharge protection device formed over the substrate. The first electrostatic discharge protection device includes a buried layer formed over the substrate, the buried layer having a first conductivity type and defining an opening located over a region of the substrate, a first transistor formed over the opening of the buried layer, the first transistor having an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp, and a second transistor formed over the buried layer, the second transistor having an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp | 2014-03-06 |
20140061717 | POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a power semiconductor device including: a base substrate having one surface and the other surface and formed of a first conductive type drift layer; a first conductive type diffusion layer formed on one surface of the base substrate and having a concentration higher than that of the first conductive type drift layer; and a trench formed so as to penetrate through the second conductive type well layer and the first conductive type diffusion layer from one surface of the base substrate including the second conductive type well layer in a thickness direction. | 2014-03-06 |
20140061718 | INSULATED GATE BIPOLAR TRANSISTOR - There is provided an insulated gate bipolar transistor, including: an active region including a gate electrode, a first emitter metal layer, a first well region, and one portion of a third well region; a termination region including a second well region supporting diffusion of a depletion layer; and a connection region located between the active region and the termination region and including a second emitter metal layer, a gate metal layer, and the other portion of the third well region, wherein the third well region is formed over the active region and the connection region, and the first emitter metal layer and the second emitter metal layer are formed on the third well region. | 2014-03-06 |
20140061719 | MOS TYPE SEMICONDUCTOR DEVICE - A MOS type semiconductor device wherein on voltage is low, the rate of rise of current at turn-on time is low, and it is possible to hold down the rate of rise of collector current at turn-on time, and reduce radiation noise. The device includes a stripe-shaped plan-view pattern of protruding semiconductor region on an n-type substrate and having a p-type region sandwiched between an upper side n-type first region and a lower side n-type second region, a top flat portion including a depression region with a depth reaching the p-type region, and an inclined portion between the top flat portion and a bottom flat portion around the protruding semiconductor region; and a gate electrode with one end portion of the gate electrode on a surface within the inclined portion, and another end portion on a surface of the lower side n-type second region in the p-type region side vicinity. | 2014-03-06 |
20140061720 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first main electrode, a base layer of a first conductivity type, a barrier layer of the first conductivity type, a diffusion layer of a second conductivity type, a base layer of the second conductivity type, a first conductor layer, a second conductor layer, and a second main electrode. Bottoms of the barrier layer of the first conductivity type and the diffusion layer of the second conductivity type are positioned on the first main electrode side of lower ends of the first conductor layer and the second conductor layer. The barrier layer of the first conductivity type and the diffusion layer of the second conductivity type form a super junction proximally to tips of the first conductor layer and the second conductor layer. | 2014-03-06 |
20140061721 | MOS DEVICE AND METHOD FOR FABRICATING THE SAME - An improved MOS device is provided whereby the p-top layer is defined by a series of discretely placed p type top diffusion regions. The invention also provides methods for fabricating the MOS device of the invention. | 2014-03-06 |
20140061722 | Transistors, Semiconductor Devices, and Methods of Manufacture Thereof - Transistors, semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a transistor over a workpiece. The transistor includes a sacrificial gate material comprising a group III-V material. The method includes combining a metal (Me) with the group III-V material of the sacrificial gate material to form a gate of the transistor comprising a Me-III-V compound material. | 2014-03-06 |
20140061723 | MOS TRANSISTOR - A MOS transistor including a U-shaped channel-forming semiconductor region and source and drain regions having the same U shape located against the channel-forming region on either side thereof, the internal surface of the channel-forming semiconductor region being coated with a conductive gate, a gate insulator being interposed. | 2014-03-06 |
20140061724 | High Electron Mobility Transistor and Manufacturing Method Thereof - The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT includes a semiconductor layer, a barrier layer on the semiconductor layer, a piezoelectric layer on the barrier layer, a gate on the piezoelectric layer, and a source and a drain at two sides of the gate respectively, wherein each bandgap of the semiconductor layer, the barrier layer, and the piezoelectric layer partially but not entirely overlaps the other two bandgaps. The gate is formed for receiving a gate voltage. A two dimensional electron gas (2DEG) is formed in a portion of a junction between the semiconductor layer and the barrier layer but not below at least a portion of the piezoelectric layer, wherein the 2DEG is electrically connected to the source and the drain. | 2014-03-06 |
20140061725 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - According to example embodiments, a higher electron mobility transistor (HEMT) may include a first channel layer, a second channel layer on the first channel layer, a channel supply on the second channel layer, a drain electrode spaced apart from the first channel layer, a source electrode contacting the first channel layer and contacting at least one of the second channel layer and the channel supply layer, and a gate electrode unit between the source electrode and the drain electrode. The gate electrode unit may have a normally-off structure. The first and second channel layer form a PN junction with each other. The drain electrode contacts at least one of the second channel layer and the channel supply layer. | 2014-03-06 |
20140061726 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an electron transit layer formed with a semiconductor material, the electron transit layer being formed on a semiconductor substrate; an n-type semiconductor layer formed with a semiconductor material having a wider bandgap than the electron transit layer, the n-type semiconductor layer being formed on the electron transit layer; a δ doping area having an n-type impurity doped in a sheet-shaped region, the δ doping area being formed on the n-type semiconductor layer; and a barrier layer formed with a semiconductor material having a wider bandgap than the electron transit layer, the barrier layer being formed on the δ doping area. | 2014-03-06 |
20140061727 | INTEGRATED CIRCUIT STRUCTURE HAVING AIR-GAP TRENCH ISOLATION AND RELATED DESIGN STRUCTURE - A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate. | 2014-03-06 |
20140061728 | Gate Biasing Electrodes For FET Sensors - A FET sensor with a gate biasing electrode is disclosed in one embodiment. In another embodiment, a process for forming a finFET sensor with a polysilicon gate biasing electrode is disclosed. In a further embodiment, a process for forming a finFET sensor with a single crystal gate biasing electrode is disclosed. | 2014-03-06 |
20140061729 | ION SENSITIVE FIELD EFFECT TRANSISTOR - A CMOS or bipolar based Ion Sensitive Field Effect Transistor (ISFET) comprising an ion sensitive recess for holding a liquid wherein the recess is formed at least partly on top of a gate of the transistor. There is also provided a method of manufacturing an I on Sensitive Field Effect Transistor (ISFET) utilizing CMOS processing steps, the method comprising forming an ion sensitive recess for holding a liquid at least partly on top of a gate of the transistor. | 2014-03-06 |
20140061730 | Cap and Substrate Electrical Connection at Wafer Level - A cap and substrate having an electrical connection at a wafer level includes providing a substrate and forming an electrically conductive ground structure in the substrate and electrically coupled to the substrate. An electrically conductive path to the ground structure is formed in the substrate. A top cap is then provided, wherein the top cap includes an electrically conductive surface. The top cap is bonded to the substrate so that the electrically conductive surface of the top cap is electrically coupled to the path to the ground structure. | 2014-03-06 |
20140061731 | Tunable Schottky Diode - A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device. The device isolating region is electrically coupled to the second electrode such that a voltage at the second electrode during operation is applied to the buried region to deplete the conduction path region. | 2014-03-06 |