10th week of 2009 patent applcation highlights part 79 |
Patent application number | Title | Published |
20090063806 | METHOD FOR DISTRIBUTING HYPERVISOR MEMORY REQUIREMENTS ACROSS LOGICAL PARTITIONS - A method of reallocating memory to a hypervisor in a virtualized computing system, includes: assigning priorities to a plurality of logical partitions configured within the virtualized computing system; determining a memory requirement for the hypervisor, the hypervisor configured to manage the plurality of logical partitions; determining minimum levels of memory required for each of the plurality of logical partitions; determining the amount of available memory in the virtualized computing system; and in the event that the amount of available memory is less than the determined memory requirement of the hypervisor, removing portions of memory from one or more of the plurality of logical partitions based on the assigned priorities until the determined memory requirement for the hypervisor is obtained. | 2009-03-05 |
20090063807 | DATA REDISTRIBUTION IN SHARED NOTHING ARCHITECTURE - A system and method for data redistribution. In one embodiment, the method includes dividing data into batches at a sending partition; populating a first data structure with the first pages and the first control information in a first data structure; storing the first data structure in a cache at the sending partition; sending the changes over the network to the receiving partition; receiving a notification that the changes have been successfully stored in the second hard disk at the receiving partition; and storing, in response to the notification, the changes on the first hard disk at the sending partition. | 2009-03-05 |
20090063808 | Microprocessor and method of processing data - A data storing part outputs n-bit data according to a reading address generated by an address generator. A peak value candidate selecting part selects a maximum value of a plurality of elements forming the n-bit data as a peak value candidate when data of one data unit is expressed as one element and outputs the peak value candidate together with a positional information indicating an element position of the peak value candidate. When the peak value candidate is larger than a peak value held in a peak value holding part, a peak value calculating part calculates an address of the peak value candidate using the positional information of the peak value candidate and a reading address, outputs the address and the peak value candidate to the peak value holding part, and updates content held in the peak value holding part. | 2009-03-05 |
20090063809 | SYSTEM AND METHOD FOR PARALLEL SCANNING - A system and method for parallel scanning among multiple scanning entities. According to various embodiments of the present invention, buffers are allocated from a pool of memory pages, with one packet being located on each page. Each of the pages is mapped such that unprivileged scanners, privileged scanners, and hardware-based scanners are all capable of accessing the pages. By having the packets located on separate pages, additional data other than the packets at issue do not have to be shared, and copying is not necessary to complete the scanning process. | 2009-03-05 |
20090063810 | Computing Device with Automated Page Based RAM Shadowing, and Method of Operation - Where a computing device is provided with executable programs in relatively slow non-volatile memory, such as ROM, the device performance can be improved by shadowing, a process by which those programs are copied into relatively fast volatile memory, such as RAM. Shadowing is often inefficient because code is copied that is too infrequently used to benefit from the procedure, wasting processing time and memory. The present invention determines which parts of the slow memory are most frequently accessed, either by profiling or by intimate knowledge of the working of the device, and then shadows only those pages of executable programs whose frequent use warrants it. In a preferred embodiment the most frequently used code areas are clustered together onto certain pages of the non-volatile memory and the least frequently used code areas are clustered onto other pages of non-volatile memory. | 2009-03-05 |
20090063811 | System for Data Processing Using a Multi-Tiered Full-Graph Interconnect Architecture - A system is provided for implementing a multi-tiered full-graph interconnect architecture. In order to implement a multi-tiered full-graph interconnect architecture, a plurality of processors are coupled to one another to create a plurality of processor books. The plurality of processor books are coupled together to create a plurality of supernodes. Then, the plurality of supernodes are coupled together to create the multi-tiered full-graph interconnect architecture. Data is then transmitted from one processor to another within the multi-tiered full-graph interconnect architecture based on an addressing scheme that specifies at least a supernode and a processor book associated with a target processor to which the data is to be transmitted. | 2009-03-05 |
20090063812 | PROCESSOR, DATA TRANSFER UNIT, MULTICORE PROCESSOR SYSTEM - A processor includes a CPU capable of performing predetermined arithmetic processing, a memory accessible by the CPU, and a data transfer unit capable of controlling data transfer with the memory by substituting for the CPU. The data transfer unit is provided with a command chain unit for continuously performing data transfer by execution of a preset command chain, and a retry controller for executing a retry processing in case a transfer error occurs during data transfer by the command chain unit. Then, the data transfer unit reports a command relating to the transfer error to the CPU after completion of the execution of the command chain, thereby lessening the number of interruptions for error processing, and attaining enhancement in performance of a system. | 2009-03-05 |
20090063813 | METHOD AND SYSTEM FOR FLEXIBLE AND NEGOTIABLE EXCHANGE OF LINK LAYER FUNCTIONAL PARAMETERS - A proposal is discussed that facilitates exchanging parameters for a link layer that allows a variable number of parameters without changing a communication protocol. Likewise, the proposal allows for both components connected via the link to negotiate values for the parameters that are exchanged without a need for external agent intervention or redundancy. | 2009-03-05 |
20090063814 | System and Method for Routing Information Through a Data Processing System Implementing a Multi-Tiered Full-Graph Interconnect Architecture - A method, computer program product, and system are provided for routing information through the data processing system. Data is received at a source processor within a set of processors that is to be transmitted to a destination processor, where the data includes address information. A first determination is performed as to whether the destination processor is within a same processor book as the source processor based on the address information. A second determination is performed as to whether the destination processor is within a same supernode as the source processor based on the address information if the destination processor is not within the same processor book. A routing path is identified for the data based on results of the first determination, the second determination, and one or more routing table data structures. The data is then transmitted from the source processor along the identified routing path toward the destination processor. | 2009-03-05 |
20090063815 | System and Method for Providing Full Hardware Support of Collective Operations in a Multi-Tiered Full-Graph Interconnect Architecture - A method, computer program product, and system are provided for performing collective operations. In hardware of a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the collective operation, thereby establishing a plurality of processors comprising the parent processor and the other processors. In hardware of the parent processor, the plurality of processors are logically arranged as a plurality of nodes in a hierarchical structure. The collective operation is transmitted to the plurality of processors based on the hierarchical structure. In hardware of the parent processor, results are received from the execution of the collective operation from the other processors, a final result is generated of the collective operation based on the received results, and the final result is output. | 2009-03-05 |
20090063816 | System and Method for Performing Collective Operations Using Software Setup and Partial Software Execution at Leaf Nodes in a Multi-Tiered Full-Graph Interconnect Architecture - A method, computer program product, and system are provided for performing collective operations. In software executing on a parent processor in a first processor book, a number of other processors are determined in a same or different processor book of the data processing system that is needed to execute the collective operation, thereby establishing a plurality of processors comprising the parent processor and the other processors. In software executing on the parent processor, the plurality of processors are logically arranged as a plurality of nodes in a hierarchical structure. The collective operation is transmitted to the plurality of processors based on the hierarchical structure. In hardware of the parent processor, results are received from the execution of the collective operation from the other processors, a final result is generated of the collective operation based on the received results, and the final result is output. | 2009-03-05 |
20090063817 | System and Method for Packet Coalescing in Virtual Channels of a Data Processing System in a Multi-Tiered Full-Graph Interconnect Architecture - A method, computer program product, and system are provided for packet coalescing in virtual channels of a data processing system. A first processor bundles original data to be transmitted to a destination processor, the original data provided by a first source processor. The first processor transmits the bundle of data to a second processor along a path to the destination processor. The second processor determines if the second processor has additional data destined for the same destination processor, the additional data being provided by a second source processor that is different from the first source processor. Responsive to the second processor having additional data, the second processor unbundles the original data, adds the additional data to the original data, and rebundles the data along with the additional data. Then the second processor transmits the rebundled data to at least one other processor along the path to the destination processor. | 2009-03-05 |
20090063818 | Alignment of Cache Fetch Return Data Relative to a Thread - A method of obtaining data, comprising at least one sector, for use by at least a first thread wherein each processor cycle is allocated to at least one thread, includes the steps of: requesting data for at least a first thread; upon receipt of at least a first sector of the data, determining whether the at least first sector is aligned with the at least first thread, wherein a given sector is aligned with a given thread when a processor cycle in which the given sector will be written is allocated to the given thread; responsive to a determination that the at least first sector is aligned with the at least first thread, bypassing the at least first sector, wherein bypassing a sector comprises reading the sector while it is being written; and responsive to a determination that the at least first sector is not aligned with the at least first thread, delaying the writing of the at least first sector until the occurrence of a processor cycle allocated to the at least first thread by retaining the at least first sector in at least one alignment register, thereby permitting the at least first sector to be bypassed. | 2009-03-05 |
20090063819 | Method and Apparatus for Dynamically Managing Instruction Buffer Depths for Non-Predicted Branches - A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path. | 2009-03-05 |
20090063820 | Application Specific Instruction Set Processor for Digital Radio Processor Receiving Chain Signal Processing - This invention is an application specific integrated processor to implement the complete fixed-rate DRX signal processing paths (FDRX) for a reconfigurable processor-based multi-mode 3G wireless application. This architecture is based on the baseline 16-bit RISC architecture with addition functional blocks (ADU) tightly coupled with the based processor's data path. Each ADU accelerates a computation-intensive tasks in FDRX signal path, such as multi-tap FIRs, IIRs, complex domain and vectored data processing. The ADUs are controlled through custom instructions based on the load/store architecture. The whole FDRX data path can be easily implemented by the software employing these custom instructions. | 2009-03-05 |
20090063821 | PROCESSOR APPARATUS INCLUDING OPERATION CONTROLLER PROVIDED BETWEEN DECODE STAGE AND EXECUTE STAGE - A processor apparatus includes a sequence controller that decodes the instruction code stored in an instruction memory, an operation array that executes operation of the decoded instruction code, and an asynchronous FIFO. The asynchronous FIFO is provided between a decode stage for decoding the instruction code into at least one instruction by the sequence controller and an execute stage for executing the decoded instruction by the operation array. The asynchronous FIFO executes control, so that the read timing and the execute timing of the decoded instruction are different from each other, and the decoded instruction is continuously executed by the operation array. | 2009-03-05 |
20090063822 | MICROPROCESSOR - A microprocessor includes: a processor core that performs pipeline processing; an instruction analyzing section that analyzes an instruction to be processed by the processor core and outputs analysis information indicating whether the instruction matches with a specific instruction; and a memory that temporary stores the instruction with the analysis information, wherein the processor core includes: an instruction fetch unit that fetches the instruction stored in the memory; an instruction decode unit that decodes the instruction fetched by the instruction fetch unit; an instruction execute unit that executes the instruction decoded by the instruction decode unit; and a specific instruction execute controller that reads out the analysis information stored in the memory and controls operation of at least one of the instruction fetch unit and the instruction decode unit when the analysis instruction indicates that the instruction matches with the specific instruction. | 2009-03-05 |
20090063823 | Method and System for Tracking Instruction Dependency in an Out-of-Order Processor - A method of tracking instruction dependency in a processor issuing instructions speculatively includes recording in an instruction dependency array (IDA) an entry for each instruction that indicates data dependencies, if any, upon other active instructions. An output vector read out from the IDA indicates data readiness based upon which instructions have previously been selected for issue. The output vector is used to select and read out issue-ready instructions from an instruction buffer. | 2009-03-05 |
20090063824 | Compound instructions in a multi-threaded processor - A multi-threaded processor determines which threads to execute, switches between execution of threads in dependence on the determination, each thread being coupled to a respective register for storing the state of the thread and used in executing instructions on the thread and includes a further register shared by all the threads. The executing threads use the further register to improve execution performance and prevents the switching of execution to another thread while the internal register is in use. | 2009-03-05 |
20090063825 | SYSTEMS AND METHODS FOR COMPRESSING STATE MACHINE INSTRUCTIONS - Systems and methods for compressing state machine instructions are disclosed herein. In one embodiment, the method comprises associating input characters associated with states to respective indices, where each index comprises information indicative of a particular transition instruction. | 2009-03-05 |
20090063826 | Quad aware Locking Primitive - A method and computer system for efficiently handling high contention locking in a multiprocessor computer system. At least some of the processors in the system are organized into a hierarchy, and process an interruptible lock in response to the hierarchy. The method utilizes two alternative methods of acquiring the lock, including a conditional lock acquisition primitive and an unconditional lock acquisition primitive, and an unconditional lock release primitive for releasing the lock from a particular processor. To prevent races between processors requesting a lock acquisition and a processor releasing the lock, a release flag is utilized. Furthermore, in order to ensure that the a processor utilizing the unconditional lock acquisition primitive is granted the lock, a handoff flag is utilized. | 2009-03-05 |
20090063827 | PARALLEL PROCESSOR AND ARITHMETIC METHOD OF THE SAME - A parallel processor includes a fetch unit configured to hold a processor instruction having a composite arithmetic instruction with repeat designation and a sync instruction, a decoder unit configured to decode the processor instruction, a plurality of pipeline arithmetic units configured to execute arithmetic operations parallel on the basis of the composite arithmetic instruction, pipeline connection between the pipeline arithmetic units being controlled in accordance with the sync instruction, and a sync control unit equipped between the fetch unit and the decoder unit, and configured to control an execution start timing of the pipeline connection between the pipeline arithmetic units in accordance with the sync instruction. | 2009-03-05 |
20090063828 | Systems and Methods for Communication between a PC Application and the DSP in a HDA Audio Codec - Systems and methods implemented in a PC for enabling communication between an application executing on the CPU and a DSP that is incorporated into a codec in the High Definition Audio (HDA) system, wherein the communication is carried out via the HDA bus. In one embodiment, an HDA codec includes one or more conventional HDA widgets coupled to a programmable processor such as a DSP. The codec includes a set of registers that are configured to store HDA verbs and data transmitted via the HDA bus. The programmable processor is configured to identify verbs that indicate associated information is a communication from an application executing on the CPU, read the associated information, and process the information according to the associated verbs. The information may be program instructions, parametric data, requests for information, etc. | 2009-03-05 |
20090063829 | Method, System, computer program product and data processing program for verifying a processor Design - An improved method of verifying a processor design using a processor simulation model in a simulation environment is disclosed, wherein the processor simulation model comprises at least one execution unit for executing at least one instruction of a test file. The method comprises tracking each execution of each of the at least one instruction, monitoring relevant signals in each simulation cycle, maintaining information about the execution of the at least one instruction, wherein said maintained information comprises a determination of an execution length of a completely executed instruction, matching said maintained information about said completely executed instruction against a set of trap elements provided by the user through a trap file, and collecting the maintained information about the completely executed instruction in a monitor file in response to a match found between the maintained information and at least one of the trap elements. | 2009-03-05 |
20090063830 | DEBUGGING MECHANISM FOR A PROCESSOR, ARITHMETIC OPERATION UNIT AND PROCESSOR - A debugging mechanism equipped within a processor and receiving, as inputs, respective pieces of arithmetic operation data related to a plurality of arithmetic units comprised within the processor, and receiving, as inputs, respective control signals used for the respective arithmetic operations, comprising: an unit which comprises a counter performing a counting operation synchronously with the arithmetic operation and comprises a plurality of OR circuits each receiving, as inputs, any of the respective control signals and a signal that is output when the counter value of the counter is a specific counter value; and a debug storage unit which comprises a plurality of storage units each receiving any of the respective pieces of arithmetic operation data, any of the respective outputs of the individual OR circuits, and the counter value, and each storing the arithmetic operation data and counter value when the output of the input OR circuit is valid. | 2009-03-05 |
20090063831 | BRANCH PREDICTOR FOR BRANCHES WITH ASYMMETRIC PENALTIES - A mechanism is disclosed for enabling a plurality of nodes on a network to collaboratively exchange sets of rendering information respecting a file. In one implementation, each node maintains its own copy of the file, and each node may access its copy of the file. Whenever a node does access the locations of the file, that node sends out a rendering information message. The rendering information message comprises the set of rendering information for the file that has been updated. The rendering information message is forwarded to each of the other nodes. When each of the other nodes receives the rendering information message, it stores the set of rendering information contained therein to a rendering history associated with a user. In this manner, histories of access in the file by all users are exchanged among the nodes, and the user on each node is able to see rendering information generated by users on the other nodes. Collaboration among the users is thus achieved. | 2009-03-05 |
20090063832 | FAULT DISCOVERY AND SELECTION APPARATUS AND METHOD - A method and apparatus are disclosed for discovering and selecting faults where more than one programming model is involved. The present invention enables selection of faults and the mappings necessary to handle exceptions across multiple code environments. | 2009-03-05 |
20090063833 | BOOTLESS ACTIVATION - In an Internet Protocol (IP) based network having a distributed end devices that receive their respective IP routing and device specific configuration information from a central location using dynamic host configuration protocol (DHCP) and other related protocols, bootless activation enables the network operator to dynamically control and automatically switch an end device on an individual or group basis from one peer IP network to another peer IP network without requiring an individual user to manually reboot or reset the respective distributed end device. Examples of IP networks include broadband networks such as cable modem, fiber-based and digital subscriber line (DSL) network; wireless IP based networks; and IP based metropolitan networks; and local area networks and multiple site enterprise networks. | 2009-03-05 |
20090063834 | Auto-Switching Bios System and the Method Thereof - An auto-switching BIOS system and the method thereof, switches to dual BIOS by a hardware control circuit. After the system has been started with the first BIOS to the predetermined period of time and the BIOS_READY signal is detected as disabled, the hardware control circuit switches the system from the first BIOS to the second BIOS and restarts the system with the second BIOS. | 2009-03-05 |
20090063835 | Method for firmware isolation - In one embodiment, the present invention includes a method for determining if an isolation driver is present and a processor supports virtualization, launching the isolation driver in a first privilege level different than a system privilege level and user privilege level, creating a 1:1 virtual mapping between a virtual address and a physical address, using the isolation driver, and controlling access to a memory page using the isolation driver. Other embodiments are described and claimed. | 2009-03-05 |
20090063836 | Extended fault resilience for a platform - In one embodiment, the present invention includes a method for allocating a fail-over memory region, determining if multiple processors have reached a rendezvous state, and verifying a memory failure in a system software memory region associated with a non-rendezvousing processor and sending a message to the non-rendezvousing processor to update a range register to the fail-over memory region. Other embodiments are described and claimed. | 2009-03-05 |
20090063837 | User influenced loading sequence - There is provided a method for altering a sequence in which programs and content are loaded upon startup of an electronic device. A user may change the loading sequence by selecting a program or content before the loading sequence has finished. In addition, the altered loading sequence may be saved and utilized when the electronic device is powered on again. There is also provided a tangible, machine-readable medium for performing the described method. Finally, there is provided an electronic device having a memory device for storing a loading program that defines a loading sequence, a processor for loading programs and content based on the loading sequence, and a user interface for delivering user input to the loading program to alter the loading sequence. | 2009-03-05 |
20090063838 | MULTI-OPERATING SYSTEM DOCUMENT EDITING MODE FOR BATTERY POWERED PERSONAL COMPUTING DEVICES - Embodiments of the present invention provide a method, system and computer program product for a low power document editing mode for mobile computing devices. In an embodiment of the invention, a battery powered computing device can be configured for power optimized document editing, the computing device. The device can include a central processing unit (CPU), both coupled to a battery, memory, fixed storage and a display within a single computing case. The device also can include a primary personal computing operating system and also an auxiliary low-power consumption operating system each stored in fixed storage, each including a configuration to access an editable document in the fixed storage. Finally, the device can include a boot read only memory (ROM) programmed to selectively bootstrap into either the primary personal computing operating system or the auxiliary low-power consumption operating system. | 2009-03-05 |
20090063839 | LOW POWER DATA TRANSFER MODE FOR BATTERY POWERED PERSONAL COMPUTING DEVICES - Embodiments of the present invention provide a method, system and computer program product for a low power data transfer mode for mobile computing devices. In an embodiment of the invention, a method for low power data transfer in a battery powered computing device can be provided. The method can include powering up a battery powered computing device, booting into a primary personal computing operating system in the device and storing a document into fixed storage for the device, and subsequently re-booting into an auxiliary low-power consumption operating system in the device, establishing a short range radio frequency communications link between the battery powered computing device and an external pervasive device, and transmitting the stored document to the pervasive device over the short range radio frequency communications link. | 2009-03-05 |
20090063840 | Information Processing Apparatus and Program - If a defect flag stored in a CF | 2009-03-05 |
20090063841 | MOTHERBOARD, COMPUTER SYSTEM AND MULTI-MONITORING METHOD THEREOF - A computer system includes a center processor, a monitoring unit, a water-cooling system and a basic input output system (BIOS) unit. The monitoring unit is coupled to the central processor, and it is used for monitoring a plurality of processor working states of the central processor and generating a plurality of signals. The water-cooling system is coupled to the monitoring unit, and then the monitoring unit is allowed to monitor a plurality of system working states of the water-cooling, system, wherein each of the system working states is respectively corresponding to one of the processor working states. The BIOS unit is coupled to the monitoring unit, and it is used for outputting a plurality of control commands to adjust the operation of the central processor and the water-cooling system according to the signals and the setting value of a user. | 2009-03-05 |
20090063842 | PRINTER - A printer includes: a nonvolatile storage unit, storing a plurality of types of software and enable keys for the respective pieces of the software; and a software update unit, when update information including several pieces of software and verification keys and new enable keys for the respective pieces of the software is provided, determining, whether or not the enable key in the nonvolatile storage unit pertaining to the corresponding software has a predetermined relationship with the verification key in the update information, with respect to each of the pieces of the software in the update information, and performing rewrite processing for rewriting the software and the enable key in the nonvolatile storage unit respectively to the software and the new enable key in the update information, with respect to each of the pieces of the software for which the enable key has the predetermined relationship with the verification key. | 2009-03-05 |
20090063843 | Systems and Methods for Booting a Codec Processor over a High Definition Audio Bus - Systems and methods for booting a programmable processor such as a DSP that is incorporated into an HDA codec. The codec and a system memory containing boot program instructions are connected to an HDA bus. In a first mode, the DSP receives boot program instructions via the HDA bus and boots using these instructions. In a second mode, the DSP boots from instructions that are contained in a memory that is connected to the DSP. In one embodiment, the memory connected to the DSP is a component of a plug-in card, and the DSP is configured to determine whether the plug-in card is present, then boot from the memory on the plug-in card if it is present or boot from the system memory via the HDA bus if the plug-in card is not present. | 2009-03-05 |
20090063844 | Radio frequency control for communication systems - Methods and systems for updating a source image file in a BIOS memory are provided. In one embodiment of the method, an initialization document is loaded to generate a first image file, and the initialization document comprises a function setting and first and second address information associated with the function setting, and the function setting represents whether a system locked pre-installation (SLP) 2.0 is supported. The initialization document is loaded to write an SLP mark and an OEM public key to the first image file according to the first and second address information, serving as a second image file. The second image file is written into the source image file in the BIOS memory. | 2009-03-05 |
20090063845 | SYSTEM AND ELECTRONIC DEVICE HAVING MULTIPLE OPERATING SYSTEMS AND OPERATING METHOD THEREOF - A system and an electronic device having multiple operating systems and an operating method thereof are provided. The electronic device includes a display and a system having a first operating system, a second operating system, and an embedded controller. The first operating system consumes less power than the second operating system. The embedded controller receives an input signal to switch between the first operating system and the second operating system and display an interface of the switched operating system on a screen of the display. The first operating system and the embedded controller remain in an alive state after the electronic device is turned on, and the second operating system enters a non-working state after a preset idle time. | 2009-03-05 |
20090063846 | SYSTEMS AND METHODS FOR PREVENTION OF PEER-TO-PEER FILE SHARING - A secure digital content delivery system includes a content provider and a content user. The content provider delivers encrypted content to the content user in response to delivery requests. The content provider generates encryption algorithms on the fly and encrypts the content prior to delivery, using a different encryption algorithm and key for each content delivery. The content user subsequently requests access permission from the content provider, to access the encrypted content. The content provider grants access by generating an executable decryption module on the fly and providing the executable decryption module to the content user. The content user decrypts the content and accesses it on the fly, using the executable decryption module. The accessed content is then re-encrypted using a different encryption algorithm and key, to preserve the integrity of the secure content delivery system. The content delivery system uses a programmably configurable protocol parsing engine to encrypt and decrypt content. | 2009-03-05 |
20090063847 | CONTENT PROTECTION METHOD AND APPARATUS - There is disclosed a content protection method and apparatus. The content protection method and apparatus further improves such related schemes by facilitating spatial as well as temporal management of content. This is achieved by storing encrypted content and a corresponding decryption key and destroying the decryption key when suitable. In order to further facilitate the content protection, the decryption key may be received periodically, which allows for a large number of people to connect to the network at different times. | 2009-03-05 |
20090063848 | METHOD AND SYSTEM FOR SENDING/RECEIVING DATA, CENTRAL APPARATUS, AND COMPUTER READABLE STORAGE MEDIUM THEREOF - A product data category for sale among product data to be stored in a memory unit of a wireless tag is sent from a first client to a web server. The web server sends the product data category to a second client. The second client sends purchase data for the product data category to the web server. The web server sends an encryption key to the first client. The first client encrypts the product data with the encryption key and writes the encrypted product data in the memory unit of the wireless tag via a reader/writer. The web server sends a decryption key to the second client. On receiving the decryption key, the second client reads the encrypted product data in the wireless tag via a reader/writer to decrypt the encrypted product data with the decryption key. | 2009-03-05 |
20090063849 | DEVICE CERTIFICATE BASED APPLIANCE CONFIGURATION - Embodiments of the present invention address deficiencies of the art in respect to configuring a computing appliance and provide a method, system and computer program product for device certificate based virtual appliance configuration. In one embodiment of the invention, a virtual appliance secure configuration method can be provided. The method can include mounting non-volatile storage to the virtual appliance, retrieving a device certificate from the mounted storage and extracting a signature from the device certificate, activating the virtual appliance in a network domain and acquiring an adapter address and unique identifier for the virtual appliance, and authenticating the signature with the adapter address and unique identifier to ensure a unique active instance of the virtual appliance. | 2009-03-05 |
20090063850 | MULTIPLE FACTOR USER AUTHENTICATION SYSTEM - The present invention describes a method and a system for multi-level authentication of a user and a server. The user registration process in the invention enables user to personalize the web page of the server. Further, the user authentication takes place in a multi-step process including entering credentials such as user ID, subset of user's password, subset of shared secret and a One Time Password (OTP). The system of the present invention provides various means of entering the said credentials which prevents phishing attacks. | 2009-03-05 |
20090063851 | ESTABLISHING COMMUNICATIONS - A method of establishing direct and secure communication between two wireless communications devices is disclosed. The wireless communications devices each have an existing trust relationship with an authentication server operable to authenticate access to a communication network on the basis of those existing trust relationships. The method comprises: (i) sending a communication request message directly from a first wireless communications device to a second wireless communications device; (ii) operating one of said wireless communication devices to request a symmetric encryption key from an authentication server; (iii) responsive to said request, operating said authentication server to: authenticate said one of said wireless communications devices on the basis of said existing trust relationship; generate said symmetric encryption key on successful authentication of said one of said wireless communications devices; and send said symmetric encryption key to said one of said wireless communications devices; (iv) responsive to receiving said symmetric encryption key, storing said symmetric encryption key at said one of said wireless communications devices and communicating it directly to the other wireless communications device; (v) securing direct communications between said wireless communications devices using said symmetric encryption key. | 2009-03-05 |
20090063852 | AUTHENTICATION FOR AD HOC NETWORK SETUP | 2009-03-05 |
20090063853 | INFORMATION PROCESSING APPARATUS, SERVER APPARATUS, MEDIUM RECORDING INFORMATION PROCESSING PROGRAM AND INFORMATION PROCESSING METHOD - A client PC | 2009-03-05 |
20090063854 | Method for revoking a digital signature - A method and apparatus for revoking a digital signature using a signature revocation list. In one embodiment, the method includes generating the signature revocation list to indicate revocation status of a signature. The signature is created from an encryption key and a document. The method also includes computing an identifier of the signature in the signature revocation list based on contents of the signature. The method further includes publishing the signature revocation list for access by users of the document. | 2009-03-05 |
20090063855 | Reduced computation for generation of certificate revocation information - A method and apparatus for propagating certificate revocation information. A first query is received regarding a revocation status of a first digital certificate. One or more additional queries are received regarding revocation statuses of one or more additional digital certificates. A response to the first query and the one or more additional queries is generated, the response including the revocation status of the first digital certificate and the revocation statuses of the one or more additional digital certificates. | 2009-03-05 |
20090063856 | System and Method for Identifying Encrypted Conference Media Traffic - A method for identifying conference media traffic includes receiving a plurality of dummy packets and matching a series of the plurality of dummy packets to a signature key. The method also includes extracting a first identification from one or more of the plurality of dummy packets in response to matching a series of the plurality of dummy packets to a signature key and determining that a second identification associated with one or more encrypted media packets matches the first identification. The method also includes associating one or more encrypted media packets with a conference in response to determining that the first identification matches the second identification. | 2009-03-05 |
20090063857 | METHOD AND SYSTEM FOR PROVIDING A TRUSTED PLATFORM MODULE IN A HYPERVISOR ENVIRONMENT - A method is presented for implementing a trusted computing environment within a data processing system. A hypervisor is initialized within the data processing system, and the hypervisor supervises a plurality of logical, partitionable, runtime environments within the data processing system. The hypervisor reserves a logical partition for a hypervisor-based trusted platform module (TPM) and presents the hypervisor-based trusted platform module to other logical partitions as a virtual device via a device interface. Each time that the hypervisor creates a logical partition within the data processing system, the hypervisor also instantiates a logical TPM within the reserved partition such that the logical TPM is anchored to the hypervisor-based TPM. The hypervisor manages multiple logical TPM's within the reserved partition such that each logical TPM is uniquely associated with a logical partition. | 2009-03-05 |
20090063858 | Systems, methods, and media for retransmitting data using the secure real-time transport protocol - Systems, methods, and media for retransmitting data using the SRTP are provided. In some embodiments, methods for retransmitting data using the SRTP are provided. The methods include: receiving at least one data unit associated with a media session; determining the index of the at least one data unit; determining the session key of the media session using the index; authenticating the at least one data unit using the session key; and retransmitting the at least one data unit. | 2009-03-05 |
20090063859 | CONTENT DISTRIBUTION SERVER AND CONTENT DISTRIBUTION SYSTEM USING THE SAME - The present invention relates to a content distribution server or the like, capable of more surely preventing an unauthorized use of a content. Content distribution servers | 2009-03-05 |
20090063860 | Printer driver that encrypts print data - A system for transmitting encrypted print job data across a network. The printer driver on the client device encrypts the print job data using a random AES key and uses the printer's public key to encrypt the random AES key. The print job data remains encrypted during transmission from the client device to the printer via the server. As such, the contents of the print job cannot be viewed by anyone who eavesdrops on the communications between the client device and the printer or by anyone who obtains the print job data from the server's data storage medium. The printer's public certificate, containing the printer's public key, is promulgated to the client device via the server which stores the printer's public certificate with other data pertinent to the client device's printer driver. | 2009-03-05 |
20090063861 | Information security transmission system - An information security transmission system is disclosed. The system comprises a first information equipment and a second information equipment, wherein the first information equipment can obtain at least one certification data, connecting to the second information equipment through a network for processing an information transmission, accordingly, a key pair used for encryption/decryption can be obtained through the certificate authority or that can be obtained without the certificate authority selectively, such that the information transmission security channel can be established and the data transmission security can be ensured. The first information equipment and the second information equipment respectively comprises a first dynamic codec and a second dynamic codec for processing a coding/decoding process depending on a dynamic code book, furthermore, an automatic error detecting mechanism and an error correcting mechanism can be associated for ensuring the data transmission security and the data correction especially at one time transmission. The transmission data is under the protection of accessing limit, such as time limit, number of times limit, or equipment limit, such that once the receiver end has received the transmission data, the transmission data can be read under the accessing limit, therefore, if the accessing limit is overtook, then the transmission data would be removed for preventing the data to be lost. | 2009-03-05 |
20090063862 | MASHUP SERVICE SUPPORT METHOD AND APPARATUS - A mashup service support method includes externally receiving a mashup service application, acquiring and managing an authentication key corresponding to the received mashup service application, and executing the received mashup service application using the acquired authentication key. A user can use a variety of web services by normally operating a mashup service application through Open API due to the storing and managing of an authentication key. | 2009-03-05 |
20090063863 | Secure authenticated channel - A protocol (i.e. method) and corresponding apparatuses for calculating a session key. Two peers with knowledge of a common Diffie-Hellman permanent key, K | 2009-03-05 |
20090063864 | CRYPTOGRAPHIC AUTHENTICATION WITH EPHEMERAL MODULES - A method enabling a personal computer to be authenticated by a server is provided. The method comprises the step, which includes for the user in launching the execution of a log-on procedure software, introducing personal identifiers providing access to a signature private key for long-term use relative to the duration of the session. The log-on procedure software produces: identification data of the session Id, a public ephemeral module, a public exponent and at least a pair of ephemeral pubic numbers and ephemeral private numbers related by a generic equation of the type: G=Q | 2009-03-05 |
20090063865 | Configurable Signature for Authenticating Data or Program Code - System and method for authenticating data or program code via a configurable signature. Configuration information is retrieved from a protected first memory, e.g., an on-chip register, where the configuration information specifies a plurality of non-contiguous memory locations that store the signature, e.g., in an on-chip memory trailer. The signature is retrieved from the plurality of non-contiguous memory locations based on the configuration information, where the signature is useable to verify security for a system. The signature corresponds to specified data and/or program code stored in a second memory, e.g., in off-chip ROM. The specified data and/or program code may be copied from the second memory to a third memory, and a signature for the specified data and/or program code calculated based on the configuration information. The calculated signature may be compared with the retrieved signature to verify the specified data and/or program code. | 2009-03-05 |
20090063866 | USER AUTHENTICATION VIA EVOKED POTENTIAL IN ELECTROENCEPHALOGRAPHIC SIGNALS - Techniques are disclosed for authentication and identification of a user by use of an electroencephalographic (EEG) signal. For example, a method for authenticating a user includes the following steps. At least one electroencephalographic response is obtained from a user in accordance with perceptory stimuli presented to the user. The user is authenticated based on the obtained electroencephalographic response. The authenticating step may be based on detection of an event-related potential in the obtained electroencephalographic response. The event-related potential may be a P300 event-related potential. The method may also include the step of enrolling the user prior to authenticating the user. The enrolling step may include a supervised enrollment procedure or an unsupervised enrollment procedure. | 2009-03-05 |
20090063867 | Method, System and Computer Program Product for Preventing Execution of Software Without a Dynamically Generated Key - A method, system and computer program product for partitioning the binary image of a software program, and partially removing code bits to create an encrypted software key, to increase software security. The software program's binary image is partitioned along a random segment length or a byte/nibble segment length, and the code bits removed, and stored, along with their positional data in a software key. The software key is encrypted and is separately distributed from the inoperable binary image to the end user. The encrypted key is stored on a secure remote server. When the end user properly authenticates with the developer's remote servers, the encrypted security key is downloaded from the secure remote server and is locally decrypted. The removed code bits are reinserted into the fractioned binary image utilizing the positional location information. The binary image is then operable to complete execution of the software program. | 2009-03-05 |
20090063868 | Method, System and Computer Program Product for Preventing Execution of Pirated Software - A method, system and computer program product for preventing execution of pirated software. A file is loaded on an end user's computer containing a binary image that is generated by removing one or more code bits from an executable code. A request is sent to a remote server to return a software key required for execution of the executable code from the binary image. The software key is downloaded to the end user's computer on which the binary image is loaded. One or more bits from the software key is inserted into the appropriate location of the binary image to regenerate the executable code. The executable code is enabled for execution on the end user's computer only following the embedding of the one or more bits. | 2009-03-05 |
20090063869 | Securing Data in a Networked Environment - Apparatus for securing data, comprising: an isolated processing environment having a boundary across which data cannot cross and a channel for allowing data to cross the boundary. A filter restricts data passage across the channel. Protected data is initially located in a secure area and is only released to such a secure processing environment so that access for authorized users to the secure data is available, but subsequent release of the secure data by the authorized users to the outside world is controlled. | 2009-03-05 |
20090063870 | Method, Apparatus, and Product for Prohibiting Unauthorized Access of Data Stored on Storage Drives - A method, apparatus, and computer program product are disclosed in a data processing system for prohibiting unauthorized access of data that is stored on storage drives. Multiple logical partitions are generated. A different unique randomizer seed is associated with each one of the logical partitions. In response to one of the logical partitions needing to access a storage drive, the logical partition transmits a seed to the storage drive. The transmitted seed is associated with the one of the logical partitions. A transmitting one of the logical partitions is unable to transmit a seed that is other than a seed that is associated with the transmitting one of the logical partitions. The storage drive utilizes the transmitted seed to randomize and de-randomize data for the one of the logical partitions. Data randomized for one of the logical partitions cannot be de-randomized for a different one of the logical partitions. | 2009-03-05 |
20090063871 | Method and device for managing proprietary data format content - The invention provides a method for generating a protected data object from an original content by means of digital rights management (DRM) protection techniques, wherein said original content has a proprietary data format. Further, a method for providing a proprietary data format content included in a protected data object having a MIME-type field is proposed, wherein said protected data object is generated by means of digital rights management (DRM) techniques. | 2009-03-05 |
20090063872 | MANAGEMENT METHOD FOR ARCHIVE SYSTEM SECURITY - Creating a plaintext index from a text that is extracted from a file presents the risk of a leak of confidential information from the created index. To address this problem, provided is a computer system which has a computer, a storage subsystem coupled to the computer, and a network coupling the computer and the storage subsystem. The computer has an interface coupled to the network, a first processor coupled to the interface, and a memory coupled to the first processor. The storage subsystem has a disk device which stores data. A storage area of the disk device is divided into a plurality of storage areas including, at least, a first storage area and a second storage area. The first processor reads a part of data stored in the first storage area, encrypts the part of data read from the first storage area when the data stored in the first storage area is judged as encrypted data, and writes the encrypted part of data in the second storage area. | 2009-03-05 |
20090063873 | DOCUMENT VIEWING MODE FOR BATTERY POWERED COMPUTING DEVICES - Embodiments of the present invention address deficiencies of the art in respect to document viewing within a battery powered computing device and provide a method, system and computer program product for the power optimized use of a battery powered computing device for selective document viewing. In one embodiment, a battery powered computing device configured for power optimized selective document viewing can be provided. The device can include a central processing unit (CPU) and a microcontroller, both coupled to a battery, static memory, and a display within a single computing case. The device further can include a boot read only memory (ROM) programmed to selectively bootstrap into either a personal computing mode powering the CPU and display, or a document viewing mode powering the microcontroller and display. | 2009-03-05 |
20090063874 | Power sharing between midspan and endspan for higher power PoE - Methods and systems for higher power PoE are provided. Embodiments overcome system limitations to PSE power scaling by using an endspan-midspan configuration which allocates power to the PD from both an endspan PSE and a midspan PSE. Embodiments are particularly suitable for deployed PoE systems having limited power supplies and/or ports designed for lower power. Further, embodiments include power management schemes to enable the proposed endspan-midspan configuration to intelligently allocate power between the endspan PSE and the midspan PSE according to required PD power. | 2009-03-05 |
20090063875 | DATA PROCESSING DEVICE, POWER SUPPLY VOLTAGE GENERATOR AND METHOD OF CONTROLLING POWER SUPPLY VOLTAGE THEREOF - A data processing device including a power supply terminal having a first power supply voltage applied thereto; a regulator that generates a second power supply voltage based on the first power supply voltage; an internal circuit having an operation clock, wherein the second power supply voltage is supplied to the internal circuit through a power supply; and a power supply voltage variation suppressor connected between the power supply terminal and the power supply line. In this device, the power supply voltage variation suppressor sets an auxiliary period and supplies auxiliary current to the power supply line during the auxiliary period, and wherein the auxiliary period is synchronized with the operation clock of the internal circuit. | 2009-03-05 |
20090063876 | INFORMATION PROCESSING APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT - The information processing apparatus equipped with a microprocessor is provided. The information processing apparatus equipped with a microprocessor includes: an operation clock signal generator that generates a frequency-variable operation clock signal supplied to the microprocessor; and a power supply voltage generator that determines a value of a power supply voltage to be supplied to the microprocessor according to a logarithm of a frequency of the operation clock signal and generates the power supply voltage. | 2009-03-05 |
20090063877 | Systems and methods for power management - Systems and methods for providing smart power management to one or more external interfaces of an information handling system that is capable of acting as a host for charging and/or otherwise powering one or more external devices via external interface/s that have both data exchange and power transfer capability, such as USB or Firewire interfaces. A host-based power source may be provided that is capable of managing power when a host information handling system is in inactive, and a user-based methodology may be implemented to selectively provide power to one or more external interfaces of a host information handling system based on user need or desire for access to external interface power, even when the host information handling system is inactive. | 2009-03-05 |
20090063878 | GROUP POWER MANAGEMENT OF NETWORK DEVICES - A method and apparatus for group power management of network devices. Some embodiments of an apparatus include a power management module, where the power management module is to transition the apparatus from a normal state to a low power state. The apparatus includes a wake module having a processor that remains active in the low power state, and a register to store a group address. The apparatus includes a network interface that is monitored by the processor in the low power state, where the processor detects a data packet identifying the group address at the network interface, and where the power management module returns the apparatus to the normal state upon detection of the data packet. | 2009-03-05 |
20090063879 | Information transmission device, system, and method - A network includes nodes that transmit information to each other. Some nodes operate intermittently; other nodes operate continuously. Information is transmitted to an intermittently operating node by a handshaking protocol in which the intermittently operating node indicates that it is ready to receive. Information is transmitted to a continuously operating node without such handshaking, thereby saving time and power. Each transmitting node has a memory storing information indicating which other nodes require handshaking. | 2009-03-05 |
20090063880 | System and Method for Providing a High-Speed Message Passing Interface for Barrier Operations in a Multi-Tiered Full-Graph Interconnect Architecture - A method, computer program product, and system are provided performing a Message Passing Interface (MPI) job. A first processor chip receives a set of arrival signals from a set of processor chips executing tasks of the MPI job in the data processing system. The arrival signals identify when a processor chip executes a synchronization operation for synchronizing the tasks for the MPI job. Responsive to receiving the set of arrival signals from the set of processor chips, the first processor chip identifies a fastest processor chip of the set of processor chips whose arrival signal arrived first. An operation of the fastest processor chip is modified based on the identification of the fastest processor chip. The set of processor chips comprises processor chips that are in one of a same processor book or a different processor book of the data processing system. | 2009-03-05 |
20090063881 | Low-overhead/power-saving processor synchronization mechanism, and applications thereof - A low-overhead/power-saving processor synchronization mechanism, and applications thereof. In an embodiment, the present invention provides a processor having a load-linked register. The processor implements instructions related to the load-linked register. A first instruction, when executed by the processor, causes the processor to load a first value specified by the first instruction in a first register of a register file and to load a second value in the load-linked register. A second instruction, when executed by the processor, causes the processor to suspend execution of a stream of instructions associated with the load-linked register if the second value in the load-linked register is unaltered until the second value in the load-linked register is altered. A third instruction, when executed by the processor, causes the processor to conditionally move a third value to a memory location specified by the third instruction and to move a value representing the state of the load-linked register to the third register. | 2009-03-05 |
20090063882 | Power Saving Apparatus and Method for a Portable Appliance - A power saving apparatus and method for a portable appliance to automatically enter into power saving mode when the portable appliance is turned off. The invention provides a power saving apparatus and method for a portable appliance to prevent the dam age of electronic elements and damage to saved data caused by the vibration from moving the portable appliance. | 2009-03-05 |
20090063883 | STORAGE SYSTEM AND POWER CONSUMPTION REDUCTION METHOD FOR THE SAME - This invention achieves data capacity efficiency via data de-duplication and maximizes a power-saving effect by disk operation control. In a storage system, when data is received from a computer, a value representing the bit string for the data is calculated and whether or not a value identical to the calculated value is stored in a data management table is judged. If it is judged that an identical value is not stored, the received data is registered in the data management table and stored, based on a group management table, in disk device(s) associated with a logical unit number of a logical unit constituting an active group. Meanwhile, if it is judged that an identical value is stored, the received data is stored in disk device(s) based on the group information managed in the group management table and the management information managed in the data management table. | 2009-03-05 |
20090063884 | Application of Multiple Voltage Droop Detection and Instruction Throttling Instances with Customized Thresholds Across a Semiconductor Chip - A method and system for applying multiple voltage droop detection and instruction throttling instances with customized thresholds across semiconductor chips. Environmental parameters are detected for various locations on a chip, and timing margins are determined for each location on the chip. An acceptable voltage droop for each location is determined based on the environmental parameters and the timing margins for the corresponding location. A droop threshold is then determined for each location based on the corresponding acceptable voltage droop determined for the corresponding location. | 2009-03-05 |
20090063885 | System and Computer Program Product for Modifying an Operation of One or More Processors Executing Message Passing Interface Tasks - A system and computer program product for modifying an operation of one or more processors executing message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing workloads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors. | 2009-03-05 |
20090063886 | System for Providing a Cluster-Wide System Clock in a Multi-Tiered Full-Graph Interconnect Architecture - A system for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture. | 2009-03-05 |
20090063887 | MEMORY MODULE WITH TERMINATION COMPONENT - A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal. The second interface is provided to sample data in response to a second clock signal, having a frequency that is at least twice the frequency of the first clock signal. The second interface includes inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal. | 2009-03-05 |
20090063888 | METHOD AND APPARATUS FOR CLOCK CYCLE STEALING - A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of a plurality of clock divider units which each divide the received reference clock signal to produce a corresponding divided clock signal. The method then removes one or more clock cycles (per a given number of cycles) in order to produce a plurality of domain clock signals each having an effective frequency based on a frequency and a number of cycles removed from the correspondingly received divided clock signal. | 2009-03-05 |
20090063889 | ALIGNING DATA ON PARALLEL TRANSMISSION LINES - The lane skew alignment device of the present invention facilitates the use of the SFI-5 standard interface in an FPGA without the need to rely on feedback signals from a remote device. The delay between lanes is determined using a D-Flip Flop or other type of phase comparator. To minimize the components needed to physically implement the solution a cross-point switch is used to select one of the parallel lanes at a time to be compared to a reference lane, over which the same test signal is transmitted. | 2009-03-05 |
20090063890 | MEMORY CONTROLLER WITH MULTIPLE DELAYED TIMING SIGNALS - A memory controller with multiple delayed timing signals. Control information is provided by a first output driver circuit to a first signal path. Write data, associated with the control information, is provided by a second output driver circuit to a second signal path. Timing information is provided by a third output driver to a third signal path. Rising and falling edge transitions of the timing information indicate times at which subsequent symbols of the write data are valid on the signal path. The timing information is delayed with respect to the control information to account for a difference between a time that the control information takes to reach the destination device while traversing the first signal path and a time that the write data takes to reach the destination device while traversing the second signal path. | 2009-03-05 |
20090063891 | System and Method for Providing Reliability of Communication Between Supernodes of a Multi-Tiered Full-Graph Interconnect Architecture - A method, computer program product, and system are provided for providing reliability of communication. A first processor determines a current state of links coupled to ports of a first processor of the data processing system. Each port of the first processor comprises a plurality of links to a corresponding port on a second processor of the data processing system. The current state of the links indicates a level of error associated with each link. The first processor determines, for each link, if a level of error associated with the link exceeds a threshold. For each link whose level of error exceeds the threshold, the first processor tags the link with an error identifier in a switch associated with the ports of the first processor. The first processor reduces a level of usage for transmitting data on ports associated with links tagged with the error identifier. | 2009-03-05 |
20090063892 | PROPOGATION BY A CONTROLLER OF RESERVATION MADE BY A HOST FOR REMOTE STORAGE - Provided are a method, system, and article of manufacture wherein a primary controller receives a request from a primary host to set reservations on a primary storage and a secondary storage, wherein the primary host, the primary controller and the primary storage are at a first site, and wherein a secondary host, a secondary controller, and the secondary storage are at a second site. The primary controller sets a first reservation on the secondary storage via a storage area network coupling the secondary storage to the primary controller, wherein the setting of the first reservation causes the secondary storage to be read only for a secondary host. The primary controller sets a second reservation on the primary storage, wherein the setting of the second reservation allows the primary host to perform read and write operations on the primary storage. | 2009-03-05 |
20090063893 | REDUNDANT APPLICATION NETWORK APPLIANCES USING A LOW LATENCY LOSSLESS INTERCONNECT LINK - Redundant application network appliances using a low latency lossless interconnect link are described herein. According to one embodiment, in response to receiving at a first network element a packet of a network transaction from a client over a first network for accessing a server of a datacenter, a layer 2 network process is performed on the packet and a data stream is generated. The data stream is then replicated to a second network element via a layer 2 interconnect link to enable the second network element to perform higher layer processes on the data stream to obtain connection states of the network transaction. In response to a failure of the first network element, the second network element is configured to take over processes of the network transaction from the first network element using the obtained connection states without user interaction of the client. Other methods and apparatuses are also described. | 2009-03-05 |
20090063894 | Autonomic PCI Express Hardware Detection and Failover Mechanism - A system with an autonomic PCI Express hardware detection and failover mechanism includes a plurality of combination root complex capable and endpoint capable devices. A combination root complex capable and endpoint capable device may be selectively configured to operate in either a root complex mode or an endpoint mode. One of the devices assumes the root complex mode and the remaining devices each assume the endpoint mode. Each of the endpoint mode devices is adapted to detect a failure of the root complex mode device. In response to detection of the failure of the root complex mode device, one of the endpoint mode devices assumes root complex mode. An endpoint device may include a timer with a timeout value. Whenever, an endpoint device receives a communication from the root complex device, the endpoint device restarts its timer. If the timer times out with the endpoint device receiving a communication from the root complex device, the endpoint device issues a read request to the root complex device. If the root complex device does not respond to the read request, the endpoint device assumes root complex mode. Different endpoint devices may be assigned different timeout values. Accordingly, the endpoint device that is assigned the shortest time out value will assume root complex mode upon detection of a root complex device failure. | 2009-03-05 |
20090063895 | SCALEABLE AND MAINTAINABLE SOLID STATE DRIVE - Methods and apparatus for maintaining a solid state disk drive facilitate expansion of storage capacity and maintenance of internal memory storage media, for example, are disclosed. Memory modules are adapted for removable installation in a solid state drive allowing for expansion of drive storage capacity and servicing of failed or worn out memory storage media. Data can be managed to mitigate loss during expansion, maintenance and servicing of the solid state drive. | 2009-03-05 |
20090063896 | SYSTEM AND METHOD FOR PROVIDING DRAM DEVICE-LEVEL REPAIR VIA ADDRESS REMAPPINGS EXTERNAL TO THE DEVICE - A system and method for providing DRAM device-level repair via address remappings external to the device. A system includes a memory controller having an interface to one or more memory devices via a memory module. The memory devices include addressable redundant and non-redundant memory blocks. The memory controller also includes a mechanism for utilizing one or more redundant memory blocks in place of one or more failing non-redundant memory blocks via an address remapping external to the memory device. The remapping occurs while the system is on-line. | 2009-03-05 |
20090063897 | METHOD OF INCREASING SYSTEM AVAILABILITY BY ASSIGNING PROCESS PAIRS TO PROCESSOR PAIRS - A method is provided of assigning processors in a multiprocessor environment to a plurality of processes that are executed in the multiprocessor environment. Each process has a process pair defined by a primary process that executes on a first processor, and a backup process that executes on a second processor. There are a plurality of process pairs. The processors are in communication with one another via a communication network. The processors are associated with a plurality of predefined processor pairs. First, a plurality of process pairs are provided that are initially assigned to a respective plurality of pairs of processors, wherein at least one of the processors in the plurality of pairs of processors is initially assigned to more than one processor pair. Each processor is then assigned to only one of the predefined processor pairs so that no processor belongs to more than one processor pair. Then, each of the plurality of process pairs are assigned to a respective one of the predefined processor pairs. This assigning process results in a configuration that reduces the number of failure modes from the number of failure modes that exists in the initial configuration. | 2009-03-05 |
20090063898 | Processor Instruction Retry Recovery - Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution. | 2009-03-05 |
20090063899 | Register Error Correction of Speculative Data in an Out-of-Order Processor - In one embodiment, a processor comprises a first register file configured to store speculative register state, a second register file configured to store committed register state, a check circuit and a control unit. The first register file is protected by a first error protection scheme and the second register file is protected by a second error protection scheme. A check circuit is coupled to receive a value and corresponding one or more check bits read from the first register file to be committed to the second register file in response to the processor selecting a first instruction to be committed. The check circuit is configured to detect an error in the value responsive to the value and the check bits. Coupled to the check circuit, the control unit is configured to cause reexecution of the first instruction responsive to the error detected by the check circuit. | 2009-03-05 |
20090063900 | LOG COLLECTING SYSTEM, COMPUTER APPARATUS AND LOG COLLECTING PROGRAM - A log collecting system includes a computer apparatus and at least one peripheral apparatus connected to the computer apparatus, the computer apparatus collecting a log that records operation of the at least one peripheral apparatus. The peripheral apparatus includes, a first log memory controlling section that stores a first log relating to all operation of the at least one peripheral apparatus in a first log memory region, and a second log memory controlling section that stores, in a second log memory region, a second log indicative of any influence on the operation of the at least one peripheral apparatus among the first logs. The computer apparatus includes, a third log memory controlling section that stores, in a third log memory region, a third log relating to the operation of the computer apparatus concerning the at least one peripheral apparatus, a fourth log memory controlling section that continuously or discontinuously acquires the second log stored in the second log memory region, and stores the second log in a fourth log memory region, a first log acquiring section that acquires, at a predetermined timing, the first log stored in the first log memory region and a log information creating section that creates one log information with the acquired first log, the third log stored in the third log memory region, and the second log stored in the fourth log memory region when the first log acquiring section acquires the first log. | 2009-03-05 |
20090063901 | Storage system that finds occurrence of power source failure - One or more switches are interposed between a controller portion and a storage device. When transmission of a command to a certain storage device fails, a command is transmitted starting from an upstream side to a downstream side of a path between the controller portion and the switch to which the certain storage device is connected, and when command transmission fails while transmitting a command from a k | 2009-03-05 |
20090063902 | Preliminary Classification of Events to Facilitate Cause-Based Analysis - The present invention provides methods and systems for performing preliminary cause-based classification of events in a computer or networked computer system. Methods are provided in which, based on an event message, cause-based preliminary classification of an associated event is performed. The result of the preliminary classification is used to facilitate subsequent cause-based analysis, such as root cause analysis, relating to the event. Methods are provided in which preliminary classification is performed using a database including a catalog associating event messages with appropriate preliminary classifications of events associated with the event messages. | 2009-03-05 |
20090063903 | METHOD AND APPARATUS FOR DEBUGGING APPLICATION SOFTWARE IN INFORMATION HANDLING SYSTEMS OVER A MEMORY MAPPING I/O BUS - A test system includes a debugging system and a system under test (SUT). The debugging system includes a debugging processor that couples to an SUT processor in the SUT via a memory mapping interface bus therebetween. In one embodiment, the debugging processor operates as a master to conduct test operations on the SUT via the memory mapping interface bus. The debugging processor and the SUT processor operate together in a cluster mode to provide non-invasive debugging of the (SUT) while the SUT executes application software in a real time environment. | 2009-03-05 |
20090063904 | DESCRIPTION OF ACTIVITIES IN SOFTWARE PRODUCTS - A method for describing activities in software products is provided. The method provides for identifying a plurality of activities in a software product that are of interest, defining an event structure to describe each identified activity as an event, associating each identified activity with one or more problem determination technologies, executing the software product, and responsive to detecting one of the plurality of identified activities during execution of the software product, creating one or more event records for the one detected activity based on the defined event structure, initiating the one or more problem determination technologies associated with the one detected activity, and passing the one or more event records to each of the one or more problem determination technologies. | 2009-03-05 |
20090063905 | System and Method for Error Checking of Failed I/O Open Calls - A system and method in a data processing system for error checking and resolving failed input/output open calls. A configuration mechanism configures the options, such as the information stored in databases, details of how each error check is performed, and what actions should be taken when improper error checking occurs. Based on data stored in databases, such as an I/O calls database, a rules with syntax database, and an usage calls database, a code analyzer analyzes code in software programs for an error check of a failed input/output open call. A reporting mechanism reports data from the analyzed code to a report file, such as why software programs have proper and improper error-checking instances, sends errors from the analyzed code to an error file, and enables these files to be displayed on a display. Finally, the code analyzer enables resolving an improper error check for the failed input/output open call. | 2009-03-05 |