10th week of 2009 patent applcation highlights part 37 |
Patent application number | Title | Published |
20090059590 | Portable surface skimming illumination device for locating small items on a planar surface - This invention describes a light source that is designed to illuminate a floor or other flat work surface for the purpose of locating small hard to see objects. This can be for the purpose of cleaning or simply locating a small valuable object. The light source is fashioned such that it provides a very low grazing angle of illumination that it skims across a surface. Small objects or particles are visible as being brighter than the surroundings and set off by a long shadow on the side of the particle away from the light. | 2009-03-05 |
20090059591 | LIGHT-EMITTING DEVICE - The present invention provides a light-emitting device realizing high directivity without using a cavity, which minimizes wire-breakage deformation of electrodes and generation of bubbles. | 2009-03-05 |
20090059592 | LIGHT SOURCE DEVICE - A light source device includes a light source lamp, a rotary plate, a heat absorbing portion, and a filter mounting member. The light source lamp emits illumination light. The rotary plate includes multiple opening portions that are selectively disposed in the illumination light path of the light source lamp. A reflective filter that reflects light of a wavelength that acts a heat source in illumination light is provided in one of the multiple opening portions of the rotary plate. The heat absorbing portion absorbs heat included in reflected light reflected by the reflective filter in the opening portion. The filter mounting member disposes the reflective filter in the opening portion at a predetermined angle of inclination to the optical axis of the illumination light. By disposing the inclined reflective filter in the illumination light path, reflected light reflected by the reflective filter is reflected towards the heat absorbing portion. | 2009-03-05 |
20090059593 | LIGHT EMITTING UNIT - The light emitting unit of this invention mainly comprises: a lamp holder made of insulating ceramics with high thermal conductivity; a plurality of heat dissipating fins protruding integrally from the outer end face of the lamp holder; a light-transmissive lamp tube provided on the lamp holder; a light source mounted in the light-transmissive lamp tube; a lampshade having a light reflecting surface in the inner edge being provided on the lamp holder corresponding to the light-transmissive lamp tube; and a light-transmitting element, corresponding to the transmissive lamp tube, provided outside the lampshade. According to this structure, significant illumination effect can be obtained from the entire light emitting device. Moreover, good heat dissipation effect can also be achieved by the lamp holder made of insulating ceramics with high thermal conductivity and the heat dissipating fins formed integrally with the lamp holder, such that the reduced service life, light depreciation and burn-out of the inside light source caused by overheating of the light source can be avoided so as to increase the entire performance in use. | 2009-03-05 |
20090059594 | Heat dissipating apparatus for automotive LED lamp - In a heat dissipating apparatus for an automotive LED lamp, the automotive LED lamp includes an automotive lamp set, a heat dissipating module, a plurality of LEDs, and a reflecting unit. The heat dissipating module is wrapped to form an insulation circuit for separating heat energy and electric power of the insulation circuit and heat dissipating module. The LED is electrically connected to the insulation circuit, and a main base of the LED installs a metal conducting plate for conducting the heat produced by the LED to the heat dissipating module. The reflecting unit is installed in the automotive lamp set, so that the heat dissipating module can use a cold air or a liquid coolant as the heat dissipating medium for dissipating heat, preventing a drop of light output caused by an overheat, and avoiding damages to the LED to extend the life expectancy of the automotive LED lamp. | 2009-03-05 |
20090059595 | LED AND LED LAMP - This invention relates to a light emitting diode (LED) and a LED lamp consisted of LEDs. The LED comprises at least one LED chip. The LED is mounted on a high heat conductivity base and is connected to an applied power supply through a circuit board. The LED chip also has a transparent medium layer on it. The base top surface acts as a light reflective surface, or a light reflective surface is provided around the base, the LED comprises a screw extended downwards from the base bottom or a screw hole in the base bottom to connect the LED to a heat sink mechanically. The LED is electrically connected to a driving circuit through its outgoing wires. The driving circuit is in turn electrically connected to an electrical connector through its housing. A LED lamp can be fabricated after the LED is enclosed in a transparent bulb housing. The LED has high efficiency, high power and long lifetime and can be used to fabricate LED traffic lamps, LED plane light sources, etc. | 2009-03-05 |
20090059596 | CUSTOMIZED ELECTRONIC CANDLE - A system for the customization of an electronic candle, which system includes an electronic candle assembly comprising an illumination element and means for illuminating the illumination element for providing a simulated illuminated wax candle effect, a first sleeve having a translucent portion and first customizing indicia, a second sleeve having a translucent portion and second customizing indicia, a second indicia being visually distinguishable from the first indicia, the assembly and each sleeve has cooperable constructions for selective assembly of each sleeve to the electronic candle assembly for customizing the alternative electronic candle. | 2009-03-05 |
20090059597 | Energy-saving lampshade with even light distribution - An energy-saving lampshade with even light distribution is disclosed to include a lampshade body disposed at the top side to hold a light source, a light-transmissive plate at the bottom side, a light condenser and a curved light reflector mounted inside the lampshade body, and a reflector cone mounted on the light-transmissive plate inside the lampshade right below the light source. When the light source is controlled to emit light, the light condenser condenses light from the light source onto the reflector cone, and the reflector cone and the light reflector reflects light rays, and therefore light rays are evenly distributed in the illumination without showing the normal distribution (Gaussian distribution) and avoiding dazzling. | 2009-03-05 |
20090059598 | METHOD AND APPARATUS FOR CREATING HIGH EFFICIENCY EVEN INTENSITY CIRCULAR LIGHTING DISTRIBUTIONS - A surface mount LED lamp includes a central first section having a flat circular window that provides a direct view window to the source energy and having an angle equal to the total intended output viewing angle of the LED lamp thereby providing a smooth and relatively undistorted output intensity distribution. The window allows the energy from the wide angle LED source to exit the lamp with minimal distortion, creating a smooth generally cosine shaped light distribution through the intended viewing angle of the device. A second outer section has both refractive and internally reflective surfaces for the purpose of collecting the wider output angle light from the LED source thereby adding to the intensity at the outer edges of the distribution. | 2009-03-05 |
20090059599 | Optical scanner illumination system and method - An optical scanner having a scanner glass with a bottom surface includes an LED illumination source and a reflector, disposed below the glass. The illumination source has a target-oriented surface oriented to direct light toward the glass at a non-perpendicular angle. The reflector is oriented to direct light reflected off of the bottom surface toward the target-oriented surface. | 2009-03-05 |
20090059600 | Lighting device with a wallwash reflector assembly - A wallwash reflector assembly includes a downlight body mounted within a wallwash body, the wallwash body being of multi-piece construction including an active body having an upper wallwash reflector for illuminating a first portion of a wall and a wallside body having a lower wallwash reflector for illuminating for a second portion of the wall. The upper and lower wallwash reflectors are optically optimized to provide a smooth, imperceptible transition between the illumination provided to the wall by the upper wallwash reflector and the illumination provided to the wall by the lower wallwash reflector. | 2009-03-05 |
20090059601 | LIGHT SOURCE DEVICE, LIGHTING DEVICE, PROJECTOR, AND MONITORING DEVICE - A light source device includes: a light source which emits light; an optical member through which light emitted from the light source enters; a base on which the light source is mounted; a first holding member which fixes the optical member; and a second holding member which holds the first holding member and stands on the base in the emission direction of the light emitted from the light source. | 2009-03-05 |
20090059602 | Directional evacuation lights - A directional evacuation lighting apparatus used during an emergency evacuation situation for a building where an emergency sign with direction is projected on the floor to help direct and locate closest safety exit. | 2009-03-05 |
20090059603 | WIRELESS LIGHT BULB - The claimed subject matter provides systems and/or methods that employ a control component integrated in a light bulb to control the light bulb wirelessly. The wireless light bulb can include a light source, a control component that manages operation of the light source, an input component that wirelessly obtains input signals that can be utilized by the control component, and a power source. For instance, the light source can be one or more light emitting diodes (LEDs) and/or the power source can be one or more batteries. Moreover, the input component can receive the input signals (e.g., radio frequency, infrared, . . . ) from a remote control, a sensor, a differing wireless light bulb, a radio frequency identifier (RFID) tag, etc. Further, the wireless light bulb can be mechanically coupled to a lighting fixture, where the lighting fixture may or may not be electrically coupled to an alternating current (AC) power source. | 2009-03-05 |
20090059604 | HEAT DISSIPATION DEVICE FOR LIGHT EMITTING DIODE MODULE - A heat dissipation device for a light emitting diode (LED) module includes a heat sink, a plurality of heat pipes received in the heat sink and a heat-absorbing plate thermally attached to the heat pipes and the LED module and located therebetween. The heat sink includes a base and a plurality of fins mounted on the base. The base defines a plurality of grooves for accommodating the heat pipes therein. Top surfaces of the heat pipes are coplanar with a top face of the base of the heat sink so that the heat-absorbing plate has an intimate contacting with the top face of the base of the heat sink and the top surfaces of the heat pipes, whereby the heat pipes can quickly transfer heat from the LED module to the heat sink via the heat-absorbing plate. | 2009-03-05 |
20090059605 | LED LAMP - An LED lamp includes a heat dissipation apparatus with a base, an LED module mounted on the base, and an AC-DC converter electrically connected to the LED module. The AC-DC converter is mounted on the base near the LED module. Heat generated by the LED module and heat-generating components of the AC-DC converter is transferred to the base from which the heat is dissipated by the heat dissipation apparatus. Heat pipes are embedded in the base of the heat dissipation apparatus. | 2009-03-05 |
20090059606 | Removable LED light device - The removable LED track light device has plurality of LED light-units fit within track means. At least one of LED element(s) are fit within the LED light-unit geometric construction and element(s) electric poles are connected with conductive mean, resilient conductive means, contact means, bus means to build the electric signal(s) deliver from the preferred AC or DC power source, circuit means, switch means, sensor means, timer means, control means to element(s) to make desired light function for illumination. The said LED-units have geometric construction and space to allow element(s) fix on position or incorporated with reflector means to make the said reflector means can be rotating, swivel, tilt by rotating means. LED light-unit incorporate with bracket means to arrange LED element assembly away from the LED light-unit base which has variety different construction and polarization consideration to make the contact means to fit within track means. Hanging means or other electric device also can add on the said LED light-unit or LED light device or increase more practical extra functions. | 2009-03-05 |
20090059607 | Lamp Support - A lamp support includes a clamp, a ratchet member, a lamp housing and a latch member. The clamp is capable of being attached to a human body. The clamp has a circular receiving groove. A plurality of ratchet grooves is formed at a bottom face of the receiving groove along a first rotation direction. The ratchet member is rotatably received in the receiving groove along the first rotation direction. The ratchet member has a ratchet projection selectively inserted into the ratchet grooves. The lamp housing is rotatably connected to the ratchet member along a second rotation direction substantially perpendicular to the first rotation direction. The lamp housing has an inner space for receiving a lamp. The lamp housing has a plurality of latch grooves arranged along the second rotation direction. The latch member is fixed to the ratchet member. The latch member is selectively inserted into the latch grooves. | 2009-03-05 |
20090059608 | LAMP SYSTEM AND LAMP DEFLECTION CONTROL METHOD - A lamp system is provided. The lamp system includes a deflection angle calculating section configured to calculate a deflection angle of an irradiation direction of a lamp based on a steering angle of a steering wheel of a vehicle and a speed of the vehicle, a swivel control section configured to control the irradiation direction in accordance with the calculated deflection angle, a filter section configured to change an output response of a change of the speed of the vehicle to be input to the deflection angle calculating section, and a filter control section configured to compare the calculated deflection angle with a reference value and to control the filter section to change the output response in accordance with a result of the comparison. | 2009-03-05 |
20090059609 | STARRY SKY LIGHTING PANELS - A lighting panel capable of producing a “Starry Sky” lighting effect and which is easily retrofitted into existing aircraft includes a first substrate, a plurality of microminiature light sources, such as LEDs, mounted on an upper surface of the first substrate, a plurality of electrically conductive traces written on the upper surface of the first substrate so as to make electrical interconnections with respective leads of the light sources, a clear filler material surrounding each light source and tapering down to the upper surface of the first substrate so as to planarize it, and a flexible decorative film laminated over the upper surface of the first substrate and light sources, the decorative film containing a plurality of apertures therethrough, each corresponding in location to a respective light source. | 2009-03-05 |
20090059610 | Starry Sky Lighting Panels - A lighting panel capable of producing a “Starry Sky” lighting effect and which is easily retrofitted into existing aircraft includes a structural panel, a plurality of inserts containing microminiature light sources, such as LEDs, mounted in openings in the panel, a plurality of electrically conductive traces written on the upper surface of the panel so as to make electrical interconnections with respective leads of the light sources, and a decorative film applied over a bottom surface of the panel and the light sources, the decorative film being translucent or transparent or containing a plurality of apertures therethrough, each corresponding in location to a respective one of the light sources. | 2009-03-05 |
20090059611 | MOTORCYCLE - A motorcycle is easily recognized by other vehicles or pedestrians and is hardly damaged during a maximum bank, by devising the disposition of lighting fixtures. An area surrounded by a vertical line passing on each of both side surfaces of a front wheel, a horizontal line passing through a protrusion of a step serving as a first grounding portion, and a straight line for connecting the first grounding portion with an intersection between the vertical line and the ground, is set. Lighting fixtures are provided in the area, as seen from the front side. The lighting fixtures are mounted to lower ends of front forks that support a shaft of the front wheel. The lighting fixture are mounted to lower rear ends of swing arms that support a shaft of the rear wheel. A lamp of each of the lighting fixtures is composed of an assembly of a plurality of light-emitting diodes. | 2009-03-05 |
20090059612 | Head lamp assembly for vehicles - A head lamp assembly includes a reflection member with a lamp located at a focus of the reflection member and a fixed board is fixed to the reflection member. A recess is defined in a top edge of the fixed board a high beam reflected from the reflection member passes through the recess. An electromagnetic valve is connected to a connection portion perpendicularly extending from the fixed board and located beside the reflection member. A barrier plate is pivotably connected to the fixed board by a pivot and normally blocks the recess of the fixed board. The barrier plate is pivoted away from the recess when the electromagnetic valve is operated. The electromagnetic valve is affected by the high temperature by the fixed board. | 2009-03-05 |
20090059613 | Remotely deployable vehicle light apparatus - A remotely deployable vehicle light apparatus includes a support which is connected to a vehicle. A remotely-controlled light assembly deployment mechanism is connected to the support. One or more light assemblies are connected to the light assembly deployment mechanism. A remote control unit is provided for controlling the remotely-controlled light assembly deployment mechanism. Preferably, a second light assembly is included for providing a pair of light assemblies. Generally, the light assembly deployment mechanism provides for adjustable vertical deployment of the light assemblies up and down in a vertical plane. Also, a remotely-controlled light assembly rotation mechanism can be provided for rotating light assemblies. Generally, the light assembly rotation mechanism provides for rotation of the light units in a horizontal plane. | 2009-03-05 |
20090059614 | ILLUMINATION SYSTEM USING A PLURALITY OF LIGHT SOURCES - An illumination system includes a plurality of radiation generating sources, such as LED dies. A corresponding plurality of optical waveguides is also provided, with each waveguide having a first and a second end, with each first end being in optical communication with the corresponding LED die. An array of corresponding passive optical elements is interposed between the plurality of LED dies and the corresponding first ends of the plurality of optical waveguides. The illumination system provides for substantially high light coupling efficiency and an incoherent light output that can appear to the human observer as arising from a single point of light. In addition, the light can be output remotely at one or more locations and in one or more directions. | 2009-03-05 |
20090059615 | Fiber optically enhanced reflective strip - A fiber optically enhanced reflective strip having a first material, a light pipe inside the first material having an end, and a LED positioned proximate the end of the light pipe to transmit visible or infrared light to the first material to illuminate the material is described. The LED transmits single or multiple colored light energies in separated or combined forms through the light pipes. The strip produces multiple spectrums of visible and/or infrared light output that can be recognized by special IR sensitive equipment. The strip includes an external removable battery source and current limiting resistor that run on quiescent technology allowing the strip to output light for at least two to three weeks on lightweight and tiny batteries that are operated via a manual or automatic switch. The strip includes attachment means that can be attached to the safety apparels. The strip is used for quick identification and allocation of an individual in low or no visibility environments. | 2009-03-05 |
20090059616 | Illumination light assembly with self-retaining lightpipe for minimizing specular reflection in electro-optical reader - An assembly for illuminating indicia includes a chassis, an illuminator for emitting illumination light, and a self-retaining lightpipe constituted of an optical material and non-adhesively mounted on the chassis with a snap action in an assembled position. The lightpipe is optically aligned with the illuminator in the assembled position, for optically guiding the illumination light from the illuminator to the indicia. The lightpipe has a textured exit surface, preferably with a predetermined scattering directionality, for scattering the illumination light exiting therefrom toward the indicia in a controlled manner to minimize specular reflection. | 2009-03-05 |
20090059617 | VOLUME EMITTER - An apparatus for treating organic tissue includes: (i) a flash lamp defining a bore; (ii) a current source adapted for providing current to the flash lamp and operating at a current density adapted for forming a volume of optically transparent plasma within the bore, where the volume of optically transparent plasma is capable of emitting electromagnetic radiation and allowing the transmission of the electromagnetic radiation through the volume of optically transparent plasma; and (iii) a delivery system adapted for employing at least a portion of the electromagnetic radiation to treat the organic tissue. | 2009-03-05 |
20090059618 | LIGHTGUIDE PLATE AND ELECTRONIC DEVICE - An electronic device includes a casing having a display part ( | 2009-03-05 |
20090059619 | Backlight Assembly And Display Device Having The Same - A backlight assembly may include a light guide unit, a light source and a reflection module. The light source provides light onto an incident face of the light guide unit. The reflection module may include a first substrate having reflection regions, a lower electrode disposed in each reflection region, a switch element applying an on or off signal to the lower electrode, and an upper electrode. The upper electrode makes contact with or is spaced apart from a reflective face of the light guide unit in accordance with the on or off signal. Thus, light selectively exits the light guide unit through an exiting face of the light guide unit corresponding to each reflection region. A display device has a display module disposed on the exiting face of the light guide unit to display an image. Therefore, the display device has a simplified structure. | 2009-03-05 |
20090059620 | BACK LIGHT MODULE - A back light module including a back plate, a light source and a bar lens is disclosed. The bar lens includes a top and a bottom center transparent surfaces, a right and a left top total internal reflection surfaces, a right and a left first emitting surfaces, a right and a left second emitting surfaces, a right and a left bottom total internal reflection surfaces and a right and a left bottom incident surfaces. The center bottom transparent surface is located between the top center transparent surface and the light source. The connecting sequence along the right of bar lens from top center transparent surface is the right top total internal reflection surface, the right first emitting surface, the right second emitting surface, right bottom total internal reflection surface, the right incident surface and the center bottom transparent surface. The connecting sequence on the left is similar to the right. | 2009-03-05 |
20090059621 | LIQUID CRYSTAL DISPLAY DEVICE - In a backlight which arranges light emitting diodes on a side surface of a light guide plate, irregularities of radiation light from the backlight can be decreased. In a liquid crystal display device having a backlight which radiates light to a liquid crystal panel, LEDs which constitute a light emitting element are mounted on a light guide plate formed on the backlight, and teardrop-shaped lenses are formed on a light radiation surface of the light guide plate. By changing the advancing directions of lights radiated from the light emitting element using the teardrop-shaped lenses, it is possible to decrease irregularities of a planar light source by scattering the radiation lights from the light guide plate. | 2009-03-05 |
20090059622 | BI-DIRECTIONAL DC-DC CONVERTER AND METHOD FOR CONTROLLING THE SAME - A bi-directional DC-DC converter has a transformer for connecting a voltage type full bridge circuit connected to a first power source and a current type switching circuit connected to a second power source. A voltage clamping circuit constructed by switching elements and a clamping capacitor is connected to the current type switching circuit. The converter has a control circuit for cooperatively making switching elements operative so as to control a current flowing in a resonance reactor. | 2009-03-05 |
20090059623 | Switched-mode Power Supply With EMI Isolation - Embodiments disclosed herein describe a switched-mode power supply with the EMI isolated from a input power, by disconnecting the input power from the switched-mode power supply when the switched-mode power supply is switching. | 2009-03-05 |
20090059624 | DC to DC converter - An exemplary direction current (DC) to DC converter includes a first rectifying and filtering circuit configured to receive an alternating current (AC) voltage and transform the AC voltage to a first DC voltage, a pulse width modulation (PWM) circuit, a first transformer configured to receive the first DC voltage and transform the first DC voltage to a second AC voltage under control of the PWM circuit, and a second rectifying and filtering circuit including a first transistor and a control circuit for switching on or switching off the first transistor so as to transform the second AC voltage to a second DC voltage. | 2009-03-05 |
20090059625 | SINGLE-PHASE TO THREE-PHASE CONVERTER - Single-phase to three-phase converter comprising a rectifier stage, a DC link and an inverter stage, wherein the rectifier comprises a filter choke, one controllable switch for power factor correction, rectifying diodes arranged in a diode bridge configuration having input terminals and output terminals, the controllable switch being connected to the output terminals of the diode bridge, an upper blocking diode arranged between the positive output terminal of the diode bridge and the positive input of the DC link and a lower blocking diode arranged between the negative output terminal of the diode bridge and the negative input of the DC link, the DC link comprises a capacitor bank connected between the DC link, which capacitor bank has a center point. The inverter stage comprises three phase outputs, two of which are formed with a series connections of controllable switches arranged between the DC link for switching either positive voltage or negative voltage of the DC link to the phase outputs, and one phase output is formed of the voltage of the center point of the capacitor bank, and in that the center point of the capacitor bank is configured to be optionally connected to the neutral line of the single-phase AC input by using a connection switch element providing thereby doubled voltage to the DC link. | 2009-03-05 |
20090059626 | SWITCHING POWER SUPPLY DEVICE AND CONTROL DEVICE THEREOF - The invention provides a switching power supply device that can restrain the variation in the ripple of the output voltage corresponding to the variation in the input voltage and a control device thereof. When output voltage Vout is higher than a target value, switching converter circuit | 2009-03-05 |
20090059627 | LINEAR VOLTAGE REGULATOR - A linear voltage regulator is provided. The linear voltage regulator includes a first circuit configured to receive the first voltage from a voltage source and to remove frequency components of the first voltage in a first frequency range to obtain an output voltage at a primary output node. The linear voltage regulator further includes a second circuit having first and second inverters electrically coupled to the primary output node of the first circuit. The second circuit is configured to receive the output voltage and to remove frequency components of the output voltage in a second frequency range. The second frequency range is greater than the first frequency range. | 2009-03-05 |
20090059628 | METHOD FOR REGULATING A VOLTAGE USING A LINEAR VOLTAGE REGULATOR - A method for regulating a voltage using a linear voltage regulator is provided. The linear voltage regulator has a first circuit with a primary output node and a second circuit having first and second inverters electrically coupled to the primary output node. The method includes receiving a first voltage from a voltage source at the first circuit. The method further includes removing frequency components of the first voltage in a first frequency range to obtain an output voltage at the primary output node utilizing the first circuit. The method further includes removing frequency components of the output voltage in a second frequency range utilizing the first and second inverters of the second circuit, the second frequency range being greater than the first frequency range. | 2009-03-05 |
20090059629 | VOLTAGE REGULATOR FOR INTEGRATED CIRCUITS - A voltage regulator for a charge pump includes a capacitor divider and a reset circuit. The capacitor divider produces, based on an input voltage (VPP), a sample voltage at a sampling node. The sampling node and a reference voltage VREF are connected to respective inputs of a comparator that generates an enable signal for the charge pump. The reset circuit connects to the divider and includes a first transistor connected between the sampling node and a biasing node. During a sampling mode, the reset circuit biases VDS of the first transistor to approximately zero at the regulation point to minimize subthreshold IDS. During reset intervals, the reset circuit applies VREF to the biasing node. The reset circuit may include a second transistor connected between the biasing node and a known level (e.g., ground) and a biasing transistor connected between the biasing node and VREF. | 2009-03-05 |
20090059630 | High-efficiency DC/DC voltage converter including capacitive switching pre-converter and down inductive switching post-regulator - A DC/DC converter includes a pre-converter stage, which may include a charge pump, and a post-regulator stage, which may include a Buck converter. The duty factor of the post-regulator stage is controlled by a feedback path that extends from the output terminal of the DC/DC converter to an input terminal in the post-regulator stage. The pre-converter steps the input DC voltage up or down by a positive or negative integral or fractional value, and the post-regulator steps the voltage down by a variable amount depending on the duty factor at which the post-regulator is driven. The converter overcomes the problems of noise glitches, poor regulation, and instability, even near unity input-to-output voltage conversion ratios. | 2009-03-05 |
20090059631 | VOLTAGE-SENSED SYSTEM AND METHOD FOR ANTI-ISLANDING PROTECTION OF GRID-CONNECTED INVERTERS - A method is provided for preventing islanding of a power source connected to an electric AC grid via an interface. The method senses an output voltage waveform of the interface, controls an output current waveform of the interface to track a reference current waveform having a mathematical relationship with the sensed output voltage waveform, and discontinues the output current waveform when the output voltage waveform is sensed to be outside a predetermined waveform range. | 2009-03-05 |
20090059632 | System And Method For Controlling A Current Limit With Primary Side Sensing Using A Hybrid PWM and PFM Control - A hybrid constant current control system that uses both pulse width modulation (PWM) and pulse frequency modulation (PFM) control. When transitioning from constant voltage mode to constant current mode the present invention can continue to control using PWM. Thereafter, when the voltage has dropped, the present invention smoothly transitions to PFM mode. The point of transition is based upon the switching frequency and the lowest rated voltage of operation. The system and method avoids very short (narrow) Ton times which ensures accurate constant current (CC) control with bipolar junction transistor (BJT) devices. The present invention also avoids acoustic noise because the switching frequency is maintained at a high enough level to avoid such acoustic noise even when the energy transferred through the transformer is still substantial and the output voltage is not too low. In addition the output current limit is insensitive to variation in the inductance-input voltage ratio, and is minimized against leakage inductance. | 2009-03-05 |
20090059633 | MATRIX CONVERTER APPARATUS - There is provided a matrix converter apparatus including both functions of outputting a step up voltage and outputting a step down voltage. In a matrix converter apparatus for directly connecting respective phases of a three phase alternating current power source ( | 2009-03-05 |
20090059634 | Switching power supply - To provide a half-bridge switching power supply using a series resonance that can realize both of a smaller size and higher reliability of a device. | 2009-03-05 |
20090059635 | Rectifier device for automotive alternator - An AC generator, referred to as an alternator, is mounted on an automotive vehicle for supplying electric power to an on-board battery and other electric loads. The alternator includes a rectifier device for rectifying alternating current to direct current. The rectifier is composed of a minus-side heat-radiating plate on which six minus-side rectifier elements are mounted and a plus-side heat-radiating plate on which six plus-side rectifier elements are mounted. Each rectifier is mounted on the heat-radiating plate in the same manner, i.e., by forcibly inserting the rectifier element into a mounting hole formed in the heat-radiating plate. A disc portion of the rectifier element has an outer peripheral surface on which knurls are formed. The outer peripheral surface having the knurls is tapered so that the disc portion is easily inserted into the mounting hole while establishing a firm grip and a good heat-conductive contact between the rectifier element and the heat-radiating surface. | 2009-03-05 |
20090059636 | POWER ADAPTER HAVING AN ELECTRICITY STORING CAPABILITY - A power adapter has a body, a pair of blades, a DC output terminal, an AC to DC circuit, a node and a storage unit. The blades are mounted in and protrude from the body to connect to an AC power source to obtain AC power. The DC output terminal is mounted on the body to connect to a load. The AC to DC circuit is mounted in the body, converts the AC power into DC power and has an input terminal and an output terminal. The node is defined between the DC output terminal and the AC to DC circuit. The storage unit is connected to the node to store the DC power output from the AC to DC circuit and provide a stored DC output to the DC output terminal. | 2009-03-05 |
20090059637 | INVERTER DEVICE HAVING SEPARATED MODULE TERMINAL - An inverter device is provided with a semiconductor device, an input terminal, an intermediate terminal, an output terminal and an insulated substrate on which the semiconductor device, the input terminal, the intermediate terminal and the output terminal are mounted. Each of the input terminal, the intermediate terminal and the output terminal is an separated module such that one of the input terminal, the intermediate terminal and the output terminal is spatially independent from the other. | 2009-03-05 |
20090059638 | PORTABLE DEVICE FOR GENERATING TWO PHASES FROM A SINGLE ELECTRICAL PHASE - A portable device for generating two electrical phases from a single electrical phase. The portable device includes a housing having a toroidal transformer therein. An input terminal block and an output terminal block are mounted to the housing and are electrically connected to the toroidal transformer. The portable device is sized to fit on the rear floor of a vehicle and an appropriate weight to be carried by a single person. | 2009-03-05 |
20090059639 | Tree-style and-type match circuit device applied to content addressable memory - A tree-style AND-type match circuit device applied to the content addressable memory (CAM) is provided. In this tree-style AND-type match circuit device, a plurality of AND-type match circuit groups branchingly connect with each other by a first AND logic gate. The tree-style AND-type match circuit increases the parallelism of the evaluation of the entire match circuit so that it can efficiently reduce the searching period and the switching activity. Thus, the switching caused by the transformation activity is also shortened. As a result, the match circuit device will not increase the loading of the clock signal so the power consumption is reduced significantly. | 2009-03-05 |
20090059640 | SEMICONDUCTOR DEVICE HAVING MULTIPORT MEMORY - A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC is disposed in a matrix shape, each word line is disposed in the order like WLA | 2009-03-05 |
20090059641 | MEMORY DEVICE INTERFACE METHODS, APPARATUS, AND SYSTEMS - Apparatus and systems may include a substrate, an interface chip disposed on the substrate, a first memory die having a plurality of memory arrays disposed on the interface chip, the first memory die coupled to a plurality of through wafer interconnects (TWI), and a second memory die having a plurality of memory arrays disposed on the first memory die, the second memory die including a plurality of vias, wherein the plurality of vias are configured to allow the plurality of TWI to pass through the second memory die. The second memory die may be coupled to a second plurality of TWI. In this way, the interface chip may be used to communicatively couple the first memory die and the second memory die using the first and second plurality of TWI. Other apparatus, systems, and methods are disclosed. | 2009-03-05 |
20090059642 | Memory Controller With Multi-Modal Reference Pad - A memory controller operates in two modes to support different types of memory devices. In a first mode, the memory controller distributes a dedicated reference voltage with each of a plurality of signal bundles to a corresponding plurality of memory devices. The reference voltages are conveyed using pads that are alternatively used for e.g. timing-reference signals in a second mode, so the provision for bundle-specific reference voltages need not increase the number of pads on the memory controller. | 2009-03-05 |
20090059643 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has a simple layout pattern of a sub hole region. The semiconductor memory device includes a segment input/output line, a first local input/output line and a second local input/output line corresponding to the segment input/output line, an input/output switch configured to selectively connect the segment input/output line and the first local input/output line in response to a first switch control signal, and a dummy input/output switch which is connected to a second local input/output line but is not connected to the segment input/output line. | 2009-03-05 |
20090059644 | Semiconductor memory device having vertical transistors - A semiconductor memory device includes a memory cell array region in which vertical transistors each having a lower electrode connected to a bit line is regularly arranged with a predetermined pitch, including memory cells formed using at least the vertical transistors; a peripheral circuit region arranged adjacent to the memory cell array region in a bit line extending direction; and a predetermined circuit arranged overlapping the peripheral circuit region and the memory cell array region. In the semiconductor memory device, the vertical transistors each having an upper electrode connected to the predetermined circuit are included in an end region of the memory cell array region, in which no word line is provided. | 2009-03-05 |
20090059645 | One time programmable memory - A one-time programmable memory. The one-time programmable memory has an antifuse and a read circuit configured to read the antifuse. An isolation transistor couples the antifuse to the read circuit. The read circuit and the isolation transistor have different power domains. | 2009-03-05 |
20090059646 | SEMICONDUCTOR INTEGRATED CIRCUIT - A field-effect transistor for nonvolatile memory holding use and a field-effect transistor for logical operation use are manufactured in the same structure on the same semiconductor substrate without separately providing manufacturing processes for the field-effect transistors for the two uses. Both a memory circuit and a logic circuit of a semiconductor integrated circuit are composed of n-channel and p-channel field-effect transistors including a memory holding material in a gate insulating structure. A logical operation state, a memory writing state and a nonvolatile memory holding state are electrically switched by controlling the level and application timing of a voltage to be applied between a gate conductor and a substrate region of the n-channel and p-channel field-effect transistors including the memory holding material in the gate insulating structure. | 2009-03-05 |
20090059647 | SEMICONDUCTOR STORAGE DEVICE - A memory cell array has memory cells, each of which has a ferroelectric capacitor and a selection transistor. A plate line is connected to one end of the ferroelectric capacitor and applied a certain plate line voltage. A sense amplifier circuit senses and amplifies voltage of the bit line. An error correction circuit corrects any error in retained data in the memory cells sensed by the sense amplifier. A plate line control circuit controls the timing for switching a potential of the plate line to a ground potential, based on absence or presence of error correction by the error correction circuit. | 2009-03-05 |
20090059648 | FERROELECTRIC SEMICONDUCTOR STORAGE DEVICE - This ferroelectric semiconductor storage device includes: a ferroelectric capacitor; and a transistor having one end of its current path connected to one electrode of the ferroelectric capacitor. A plate line is connected to the other electrode of the ferroelectric capacitor. A word line is connected to the gate of the transistor. A bit line is connected to the other electrode of a capacitor and the other end of the transistor, the capacitor having its one electrode connected to the ground. A bit line potential detection circuit detects a potential of the bit line. A connection circuit provides the same potential between a potential of the plate line and a potential of the bit line based on an output from the bit line potential detection circuit. | 2009-03-05 |
20090059649 | SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC APPARATUS - A semiconductor memory device includes: a memory cell array with m memory cells arranged in a first direction and n memory cells arranged in a second direction in a grid, each memory cell having a capacitor part using a ferroelectric film, and also having a first terminal, a second terminal, and a third terminal; two or more first wirings connecting the first terminals of the m memory cells arranged in the first direction; two or more second wirings connecting the second terminals of the n memory cells arranged in the second direction; and two or more third wirings connecting the third terminals of the m memory cells, the third wirings including, from among unit blocks resulting from dividing the memory cell array into q sections in the first direction and r sections in the second direction, each unit block having s memory cells arranged in the first direction and t memory cells arranged in the second direction in a grid, first to t-th wiring parts connecting the s memory cells arranged in the first direction in a first unit block, first to t-th wiring parts connecting the s memory cells arranged in the first direction in a second unit block located next to the first unit block in the first direction, and connection wiring parts connecting the first to t-th wiring parts in the first unit block and the first to t-th wiring parts in the second unit block so that the wiring parts with the same level are not connected, and also connecting ends on the second unit block side of the wiring parts in the first unit block and ends on the first unit block side of the wiring parts in the second unit block, wherein the connection wiring parts are crossed between the first unit block and the second unit block. | 2009-03-05 |
20090059650 | Memory Device, Semiconductor Device, and Electronic Device - To provide a memory device which can maintain data accurately even when memory characteristics of a memory element deteriorate over time. The memory device includes a memory cell | 2009-03-05 |
20090059651 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF WRITING INTO THE SAME - A method of writing into a semiconductor memory device, which includes a resistance memory element | 2009-03-05 |
20090059652 | Resistive memory cell array with common plate - In the present method of changing the state of a resistive memory device which is capable of adopting an erased, relatively higher resistance state and a programmed, relatively lower resistance state, the resistive memory device having first and second electrodes and an active layer between the first and second electrodes, an electrical potential is applied across the electrodes and current through the resistive memory device is limited by means of a first current limiting structure to change the resistive memory device from the erased, higher resistance state to the programmed, lower resistance state. Furthermore, an electrical potential is applied across the electrodes and current through the resistive memory device is limited by means of a second current limiting structure to change the resistive memory device from the programmed, lower resistance state to the erased, higher resistance state. | 2009-03-05 |
20090059653 | MULTI-PORT DYNAMIC MEMORY METHODS - A dynamic random access memory circuit is provided, having at least one write bit line, at least one read bit line, a capacitive storage device, a write access device operatively coupled to the capacitive storage device and the at least one write bit line, a sense amplifier operatively coupled to the at least one read bit line and configured to generate an output signal, a refresh bypass device operatively associated with the sense amplifier and the at least one write bit line so as to selectively pass the output signal to the at least one write bit line, and a write-read bypass device operatively coupled to the at least one write bit line and the at least one read bit line and configured to selectively pass a write signal from a write bit line signal point along the at least one write bit line to a read bit line signal point along the at least one read bit line for output to a data output. the output signal is selectively passed to the at least one write bit line. The write signal is selectively passed from the write bit line signal point along the at least one write bit line to the read bit line signal point along the at least one read bit line for output to the data output. | 2009-03-05 |
20090059654 | HIGH DENSITY MAGNETIC MEMORY BASED ON NANOTUBES - A novel magnetic memory cell utilizing nanotubes as conducting leads is disclosed. The magnetic memory cell may be built based on MTJ (Magnetic Tunnel Junction) or GMR (Giant Magneto Resistance) sensors or devices of similar nature. A SET (Single Electron Transistor) made of semiconducting nanotubes may be used as access devices and/or to build peripheral circuitry. | 2009-03-05 |
20090059655 | Memory cell and semiconductor memory device having thereof memory cell - Conventional semiconductor memory devices have a problem of a data read failure caused by a leak current. To address this problem, a semiconductor memory device of the present invention including memory cells each formed of a transfer transistor, a load transistor and a drive transistor. Each of the memory cells includes: a first transfer transistor connected to a connection point of the drive transistor and the load transistor; a second transfer transistor connected between the first transfer transistor and a bit line DB; and a compensation transistor connected between a constant voltage node and a connection point of the first transfer transistor and the second transfer transistor. The compensation transistor is switched to a conductive state exclusively from at least one of the first transfer transistor and the second transfer transistor. | 2009-03-05 |
20090059656 | Method and Structure for Improved Lithographic Alignment to Magnetic Tunnel Junctions in the Integration of Magnetic Random Access Memories - A magnetic memory device including a Magnetic Tunnel Junction (MTJ) device comprises a substrate and Front End of Line (FEOL) circuitry. A Via level (VA) InterLayer Dielectric (ILD) layer, a bottom conductor layer, and an MTJ device formed over the top surface of the VA ILD layer are formed over a portion of the substrate. An alignment region including alignment marks extends through the bottom conductor layer and extends down into the device below the top surface of the VA ILD layers is juxtaposed with the MJT device. | 2009-03-05 |
20090059657 | CMOS STORAGE DEVICES CONFIGURABLE IN HIGH PERFORMANCE MODE OR RADIATION TOLERANT MODE - A radiation tolerant circuit, structure of the circuit and method of autonomic radiation event device protection. The circuit includes a charge storage node connected to a resistor, the resistor comprising a material having an amorphous state and a crystalline state, the amorphous state having a higher resistance than the crystalline state, the material reversibly convertible between the amorphous state and the crystalline state by application of heat; an optional resistive heating element proximate to the resistor; and means for writing data to the charge storage node and means for reading data from the charge storage node. | 2009-03-05 |
20090059658 | MEMORY SYSTEM, MEMORY DEVICE AND APPARATUS INCLUDING WRITING DRIVER CIRCUIT FOR A VARIABLE RESISTIVE MEMORY - An apparatus, a nonvolatile memory device and a nonvolatile memory system include an array of nonvolatile variable resistive memory (VRM) cells and a writing driver circuit having a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse. | 2009-03-05 |
20090059659 | SPIN TRANSISTOR AND MAGNETIC MEMORY - A spin transistor includes a first ferromagnetic layer provided on a substrate and having an invariable magnetization direction, a second ferromagnetic layer provided on the substrate apart from the first ferromagnetic layer in a first direction, and having a variable magnetization direction, a plurality of projecting semiconductor layers provided on the substrate to extend in the first direction, and sandwiched between the first ferromagnetic layer and the second ferromagnetic layer, a plurality of channel regions respectively provided in the projecting semiconductor layers, and a gate electrode provided on the channel regions. | 2009-03-05 |
20090059660 | REDUCING THE IMPACT OF INTERFERENCE DURING PROGRAMMING - A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells. | 2009-03-05 |
20090059661 | SEQUENCE DETECTION FOR FLASH MEMORY WITH INTER-CELL INTERFERENCE - A memory integrated circuit (IC) includes a read module and a sequence detector module. The read module reads S memory cells (cells) located along one of a bit line and a word line and generates S read signals, where S is an integer greater than 1. The sequence detector module detects a data sequence based on the S read signals and reference signals. The data sequence includes data stored in the S cells. Each of the reference signals includes an interference-free signal associated with one of the S cells and an interference signal associated with another of the S cells that is adjacent to the one of the S cells. | 2009-03-05 |
20090059662 | MULTI-LEVEL CELL MEMORY DEVICES AND METHODS USING SEQUENTIAL WRITING OF PAGES TO CELLS SHARING BIT BUFFERS - An apparatus includes a nonvolatile memory including a plurality of memory cells, each configured to store data having at least two bits and a control circuit configured to write data to a first memory cell connected to a wordline of the nonvolatile memory and to then write data to a second memory cell that is connected to wordline and shares a bit buffer with the first memory cell. | 2009-03-05 |
20090059663 | Method for preventing memory from generating leakage current and memory thereof - A method for preventing a memory from generating a leakage current is disclosed. The memory includes a boundary memory cell and a neighboring memory cell. The neighboring memory cell is adjacent to the boundary memory cell. The method includes the following step. The first terminal of the neighboring memory cell is connected to the second terminal through a metal line. | 2009-03-05 |
20090059664 | Electrically Erasable Programmable Read-Only Memory (EEPROM) Cell and Methods for Forming and Reading the Same - In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated. | 2009-03-05 |
20090059665 | Semiconductor Memory - A semiconductor memory is achieved which allows a reduction in the area of a memory array block without reducing the gate widths of floating gates. A plurality of select gates extend in straight lines in the X direction. Between the upper- and lower-side select gates, two rows' worth of floating gates are arranged. The plurality of floating gates are placed in a staggered arrangement (in other words, in a zigzag pattern). That is, looking at one floating gate in a specific column and another floating gate in a column adjacent to that specific column, those floating gates deviate from each other in the Y direction. | 2009-03-05 |
20090059666 | MEMORY CELL ARRAY AND NON-VOLATILE MEMORY DEVICE - A memory cell array, divided into multiple row memory cell arrays, includes multiple memory banks and sense amplifiers. Each of the memory banks includes multiple logical sectors and at least two sub-memory banks of multiple sub-memory banks. The at least two sub-memory banks are included in different row memory cell arrays, and each of the sub-memory banks includes multiple physical sectors. The sense amplifiers are dedicated to the sub-memory banks, respectively. | 2009-03-05 |
20090059667 | MEMORY CELL ARRAY AND NON-VOLATILE MEMORY DEVICE - A memory cell array is disclosed which includes a plurality of memory banks, each memory bank including a plurality of logical sectors. The memory cell array includes a plurality of sub-memory banks, wherein each one of the plurality of sub-memory banks includes a plurality of physical sectors, and each one of the plurality of physical sectors is part of one of the plurality of logical sectors, and a plurality of sense amplifiers respectively associated with the plurality of sub-memory banks. | 2009-03-05 |
20090059668 | Virtual ground array memory and programming method thereof - A method for programming a virtual ground array memory, which includes a first cell and a second cell adjacent to first cell, includes the following steps. First, the first cell is selected as a target cell, wherein the second cell has been programmed to have data. Next, the second cell is read and the data is recorded in a register. Then, the target cell is programmed. Next, a program verifying operation is performed on the second cell. Afterwards, the data recorded in the register is programmed back to the second cell when the program verifying operation performed on the second cell fails. | 2009-03-05 |
20090059669 | NAND TYPE NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING SIDEFACE ELECTRODE SHARED BY MEMORY CELLS - An electrically erasable programmable read-only memory (EEPROM) device of the NAND type having sideface electrodes as auxiliary electrodes on the opposite lateral surfaces of a transistor channel region to thereby improve operation margins is disclosed. The NAND EEPROM, also known as NAND flash memory, has on a semiconductive substrate an array of memory cells including a serial combination of memory cell transistors. Each of memory cell transistors has a pair of source and drain regions, a channel region, a tunnel insulator film, a charge storage layer, a control dielectric film, a control electrode, a sideface dielectric film on the sidefaces of the channel region, and sideface electrodes which are formed on the side surfaces of channel region with the channel region being laterally interposed therebetween. The sideface electrodes are commonized or “shared” by adjacent ones of the serially coupled memory cell transistors. | 2009-03-05 |
20090059670 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - There is provided a nonvolatile semiconductor memory device which can read and verify a cell with a negative threshold voltage by biasing voltages of a source line and well line to a positive voltage. The nonvolatile semiconductor memory device includes a voltage control circuit which applies a select gate voltage obtained by adding the biased positive voltage to a voltage set at read time of a cell with a positive threshold voltage to a select gate at a read time and verify time for the cell with the negative threshold voltage. | 2009-03-05 |
20090059671 | Method of programming non-volatile memory device - A method of programming a non-volatile memory device may include performing a first programming operation including applying a program voltage to a memory cell and verifying the memory cell using a first verification voltage. A perturbation pulse may be applied to the memory cell to facilitate thermalization of charges in the memory cell if the memory cell passes the verification using the first verification voltage. The memory cell may be verified using a second verification voltage greater than the first verification voltage after the perturbation pulse is applied. | 2009-03-05 |
20090059672 | SELF-TIMED INTEGRATING DIFFERENTIAL CURRENT SENSE AMPLIFIER - A reference current integrator and a sensed current integrator are coupled to form a differential sense amplifier. The differential sense amplifier is coupled to receive a bitline current signal from a flash memory, and the reference current integrator is coupled to receive a current signal from a reference memory cell. Integration continues until a desired voltage or time is reached, resulting in a sufficiently reliable output. The differential current integrating sense amplifier is also used for instrumentation, communication, data storage, sensing, biomedical device, and analog to digital conversion. | 2009-03-05 |
20090059673 | Method of Operating an Integrated Circuit for Reading the Logical State of a Memory Cell - In an embodiment of the invention, a method of operating an integrated circuit for reading the logical state of a selected one of a plurality of memory cells included within a memory cell string in the integrated circuit is provided. | 2009-03-05 |
20090059674 | STORAGE APPARATUS, CONTROLLER AND CONTROL METHOD - Proposed is a highly reliable storage apparatus with fast access speed and low power consumption, as well as a controller and control method for controlling such a storage apparatus. This storage apparatus is equipped with a flash memory that provides a storage extent for storing data, a disk-shaped memory device with more data write cycles than the flash memory, and a cache memory with faster access speed than the flash memory. Data provided from a host system is stored in the cache memory, this data is read from the cache memory at a prescribed timing, data read from the cache memory is stored in the disk-shaped memory device, and, when a prescribed condition is satisfied, this data is read from the disk-shaped memory device, and the data read from the disk-shaped memory device is stored in the flash memory. | 2009-03-05 |
20090059675 | Radiation hardened multi-bit sonos non-volatile memory - In one aspect, a radiation hardened transistor includes a buried source, buried drain and a poly-silicon gate separated from the buried source and the buried drain by a buried oxide. A recessed P+ implant or a blanket P+ implant is disposed in a substrate. A portion of the recessed P+ implant or a portion of the blanket P+ implant is disposed beneath outer edges of the poly-silicon gate, in a channel separating the buried source and the buried drain. | 2009-03-05 |
20090059676 | HIGH-k CAPPED BLOCKING DIELECTRIC BANDGAP ENGINEERED SONOS AND MONOS - A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric comprising a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably comprises a high-κ material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used. | 2009-03-05 |
20090059677 | SEMICONDUCTOR DEVICE - In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a flash memory formation region, p wells are placed in the form isolated from each other. In each of the p wells, a capacitor portion, a capacitor portion for programming/erasing data and an MIS•FET for reading data are placed. In the capacitor portion for programming/erasing data, rewriting (programming and erasing) of data is performed by means of an FN tunnel current of an entire channel surface. | 2009-03-05 |
20090059678 | Memory Cell Arrangement, Method for Controlling a Memory Cell, Memory Array and Electronic Device - In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well. | 2009-03-05 |
20090059679 | ERASING METHOD OF NON-VOLATILE MEMORY - An erasing method of a non-volatile memory is provided. The non-volatile memory includes a control gate disposed in a substrate, a floating gate, a gate oxide layer disposed between the floating gate and the substrate, a source region disposed in the substrate, a drain region disposed in the substrate, a first dielectric layer disposed on the floating gate, a second dielectric layer disposed on sidewalls of the floating gate, and an erase gate. The erasing method includes applying a first voltage on the control gate, applying a second voltage on the drain, applying a third voltage on the source, applying a fourth voltage on the erase gate, and applying a fifth voltage on the substrate, such that electrons are drawn from the floating gate to the erase gate to be erased. | 2009-03-05 |
20090059680 | Integrated Circuit Memory Devices That Support Selective Mode Register Set Commands - A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation. An enable signal may be provided from the memory controller to a second one of the integrated circuit memory devices over a signal line between the memory controller and the second integrated circuit memory device to thereby enable implementation of the mode register set command for the second integrated circuit memory device during the mode register set operation. Moreover, the disable signal may not be provided to the second integrated circuit memory device during the mode register set operation, and the enable signal may not be provided to the first integrated circuit memory device during the mode register set operation. Related systems, devices and additional methods are also discussed. | 2009-03-05 |
20090059681 | SEMICONDUCTOR MEMORY DEVICE - Semiconductor memory device includes a detection circuit configured to detect a voltage level of an external power supply voltage and a core voltage generation circuit configured to vary a voltage level of the core voltage according to an output signal of the detection circuit to generate a uniform core voltage. | 2009-03-05 |
20090059682 | SEMICONDUCTOR MEMORY DEVICE HAVING ANTIFUSE CIRCUITRY - A semiconductor memory device includes a fuse box including a plurality of address antifuse circuits, each address antifuse circuit outputting an address fuse signal according to a program state of an antifuse included in the corresponding address antifuse circuit, an address comparator including a plurality of address comparison signal generators, each address comparison signal generator combining a first test signal for determining an initial defect of the antifuse and a corresponding bit of an externally applied address signal to generate a test address, and comparing the test address with the address fuse signal to generate an address comparison signal, and a redundant enable signal generator for enabling a redundancy enable signal in response to a plurality of address comparison signals. | 2009-03-05 |
20090059683 | Semiconductor memory device - A semiconductor memory device that includes a first high voltage oscillator configured to generate a first control pulse in response to a first enable signal, a level shifter configured to generate a high voltage control pulse by boosting a level of the first control pulse using a source high voltage, and a first high voltage generator configured to generate a high voltage by boosting an external power supply voltage in response to the high voltage control pulse. | 2009-03-05 |
20090059684 | Method and Apparatus for Storing Data in a Write-Once Non-Volatile Memory - An apparatus and method for forming a write-once non-volatile memory cell. A memory cell comprises a first and a second MOSFET, wherein the first MOSFET undergoes a process to modify the threshold voltage such that a modified threshold voltage represents a first stored logic value. By determining which one of the first and the second MOSFETS has an altered threshold voltage, the stored logic value is determinable. The threshold voltage of the first MOSFET is altered by supplying current through a MOSFET gate, causing a gate heating effect that results in a threshold voltage shift. | 2009-03-05 |
20090059685 | SRAM BIAS FOR READ AND WRITE - An integrated circuit includes a SRAM array including a plurality of SRAM cells arranged in a plurality of rows and columns and having a plurality of word lines and bit lines for accessing rows and columns of cells. A power supply controller has an input operable for receiving an operation signal indicative of whether the array is in a read or write operation. The power supply controller is operable to provide a variable low voltage for the array (VSSM) coupled to a low voltage supply terminal of the array. A level of the VSSM is based on the operation signal, wherein VSSM is at a lower level when in the read operation than when in the write operation. A high voltage supply for said array (VDDM) coupled to a high voltage supply terminal for the array is biased above a word line voltage (VWL) level in the read operation. | 2009-03-05 |
20090059686 | Sensing scheme for the semiconductor memory - The present invention provides a sensing scheme for semiconductor memory. N-type devices coupling between ground and a bit line and a bit line-bar of memory cells quickly discharge a bit line and a bit line-bar during non-accessing mode. During data accessing mode, one P-type device of an SRAM memory cell pulls up bit line or bit line-bar node slowly to minimize the inductive coupling noise and VDD, Ground bouncing, hence allows smaller amount of differential voltage input to the sense amplifier and results in lower power consumption. A self-timer counts the needed time and sends a signal to enable the current driven sense amplifier and to turn off the word line to avoid further pulling up the bit line or bit line-bar voltage and to reduce the power dissipation. | 2009-03-05 |
20090059687 | Semiconductor memory device and layout method thereof - Example embodiments relate to a semiconductor memory device, for example, a semiconductor memory device including an efficient layout circuit and method thereof. The method may include sharing a first active area between a first precharger and a second precharger and sharing a second active area between a third precharger and a fourth precharger. The semiconductor memory device may include a level shifter configured to receive a first precharge control signal and boost a logic high level of the first precharge control signal to an external power supply voltage level to output a boosted first precharge control signal. The semiconductor memory device may further include first, second, third and fourth prechargers. The first and third prechargers may be configured to precharge data signals transmitted to a first and second pair of local input/output data lines to the first precharge voltage in response to the boosted first precharge control signal during a data read operation. | 2009-03-05 |
20090059688 | Single-ended read and differential write scheme - A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a circuit to read and write at least one static memory cell is described, said cell comprising a cross-coupled inverter pair and two pass-devices. Said circuit is characterized in that for each pass-device of the cell an individual wordline is connected with a gate of the particular pass-device, wherein both wordlines are selected for write and a single wordline is selected for read. | 2009-03-05 |
20090059689 | Apparatus and method for transmitting/receiving signals at high speed - A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage level of the data transferrer is higher than a logic threshold voltage, and to increase the voltage level of the data transferrer when the voltage level of the data transferrer is lower than the logic threshold voltage prior to activation of the control signal. | 2009-03-05 |