09th week of 2013 patent applcation highlights part 13 |
Patent application number | Title | Published |
20130049733 | FAULT DETECTION BASED ON CURRENT SIGNATURE ANALYSIS FOR A GENERATOR - A method of detecting faults in a wind turbine generator based on current signature analysis is disclosed herein. The method includes acquiring a set of electrical signals representative of an operating condition of a generator. Further, the electrical signals are processed to generate a normalized spectrum of electrical signals. A fault related to a gearbox or bearing or any other component associated with the generator is detected based on analyzing the current spectrum. | 2013-02-28 |
20130049734 | WIND TURBINE LIGHTNING PROTECTION AND MONITORING SYSTEMS - A wind turbine hub ( | 2013-02-28 |
20130049741 | ROTATION SENSOR AND ROTATIONAL ANGLE DETECTION APPARATUS - A resolver includes three resolver coils, which are arranged spaced apart in a circumferential direction of a rotor, and an excitation coil that generates a magnetic field to induce voltages in the resolver coils when receiving electric power. When the magnetic fields provided from the excitation coil to the three resolver coils are changed through rotation of the rotor, the voltages induced in the resolver coils are changed. This causes each of the three resolver coils to output three-phase signals having amplitude that changes in a sinusoidal manner with respect to the rotational angle of the rotor. The angular intervals between the corresponding adjacent pairs of the first to third resolver coils in the circumferential direction of the rotor are defined as first, second, and third division angles. Specifically, the first to third division angles are set to values different from one another. | 2013-02-28 |
20130049742 | VARIABLE RELUCTANCE RESOLVER - In a variable reluctance resolver having terminal pins at an insulator, a technique for preventing deformation of the terminal pins, shorting between the terminal pins, and contact failure at portions of the terminal pins is provided. A first insulator | 2013-02-28 |
20130049743 | FLOAT POSITION SENSOR - [Problem] To provide a float position sensor with a simple structure in which, even when a float is moved after the power is turned off, adjustment is not particularly necessary when the power is turned on next time. | 2013-02-28 |
20130049744 | High Frequency Loss Measurement Apparatus and Methods for Inductors and Transformers - Core loss in an inductor is measured with reduced sensitivity to phase measurement error by connecting a reactive component to resonate with the inductor and thus cancel a portion of the reactive voltage on the inductor; reducing the phase difference between the inductor voltage and current and making the observed power more resistive. The reactive component may be a capacitor for sinusoidal excitation or an inductance such as an air core transformer for arbitrary excitation. | 2013-02-28 |
20130049745 | METAL DETECTION APPARATUS - A metal detection apparatus that uses one or more operating frequencies. The metal detection apparatus comprises, among other things, a transmitter unit that provides transmitter signals to a transmitter coil that is coupled to a receiver coil, which is connected to the input of a receiver unit. The transmitter unit comprises a frequency generator that provides an operating frequency to the input of an amplifier stage, whose output is connected via a transformer to the transmitter coil. The amplifier stage is connected to a first tap and the transmitter coil is connected to a second tap of the same transformer winding of the transformer. A resonant circuit is formed that is tuned to the operating frequency, and can be tuned optimally and independently of other parts of the transmitter unit. | 2013-02-28 |
20130049746 | Semiconductor Chip Package and Method - A semiconductor chip package and a method to manufacture a semiconductor chip package are disclosed. An embodiment of the present invention comprises a substrate and a semiconductor chip disposed on the substrate and laterally surrounded by a packaging material. The package further comprises a current rail adjacent the semiconductor chip, the current rail isolated from the semiconductor chip by an isolation layer, a first external pad, and a via contact contacting the current rail with the first external pad. | 2013-02-28 |
20130049749 | Semiconductor Fluxgate Magnetometer - A fluxgate magnetometer is formed in a semiconductor wafer fabrication sequence, which significantly reduces the size and cost of the fluxgate magnetometer. The semiconductor wafer fabrication sequence attaches a die, which has drive and sense circuits, to the bottom surface of a cavity formed in a larger structure, and forms drive and sense coils around a magnetic core structure on the top surface of the larger structure. | 2013-02-28 |
20130049750 | Giant Magnetoresistance Current Sensor - A giant magnetoresistance current sensor comprises an amorphous alloy magnetic ring having an air gap; a DC magnetic bias coil wound onto the amorphous alloy magnetic ring; a DC constant current source supplying power for the DC magnetic bias coil; a giant magnetoresistance chip disposed in the air gap and having positive and negative outputs; an instrument amplifier having a non-inverting input connected to the positive output of the giant magnetoresistance chip, and an inverting input connected to the negative output of the giant magnetoresistance chip; an operational amplifier having a non-inverting input connected to an output of the instrument amplifier; a voltage following resistance connected between an inverting input and an output of the operational amplifier; an analog to digital converter having an input connected to the output of the operational amplifier; and a digital tube display connected to an output of the analog to digital converter. | 2013-02-28 |
20130049751 | METHOD AND APPARATUS FOR DETECTING A MAGNETIC CHARACTERISTIC VARIABLE IN A CORE - A technique is provided for detecting a magnetic characteristic variable in particular the magnetic field strength in a section of a core permeated by a magnetic flux. A portion of the magnetic flux is branched off from the core and passed via a magnetic shunt branch, in which at least one non-ferromagnetic gap is formed. A shunt part is disposed in the shunt branch, wherein the magnetic material of the shunt part is not saturated. At least one section of the shunt part is wound with at least one sensor coil in which the branched-off portion of the magnetic flux generates a sensor signal by induction. The magnetic characteristic variable is determined from the branched-off portion of the magnetic flux or a variable derived therefrom using a sensor and evaluation device to which the sensor signal is fed. | 2013-02-28 |
20130049752 | SAMPLING PATTERN FOR ITERATIVE MAGNETIC RESONANCE IMAGE RECONSTRUCTION - In a method to generate magnetic resonance (MR) images of an examination subject, MR signals are detected simultaneously with multiple coils, each coil having its own coil characteristic. In the detection of the MR signals, raw data space is incompletely filled with MR signals; with raw data space being undersampled in a central raw data region with a coherent acquisition pattern that is composed of a spatially repeating set of raw data points; and raw data space outside of the central raw data region is sampled with an incoherent acquisition pattern. The MR image is reconstructed from the detected MR signals, step-by-step in an iterative reconstruction procedure using a reconstruction matrix A, starting from an initial estimate; wherein the reconstruction matrix has continuing information about the coil characteristics with which the MR signals were detected. | 2013-02-28 |
20130049753 | MAGNETIC RESONANCE IMAGING APPARATUS - The present invention provides an image processing technique which enables various contrast control, by quantitatively handling a degree of phase enhancement in a contrast control as a post-processing of the image reconstruction. A complex operation is performed on each pixel value of a complex image obtained by an MRI, thereby generating an image with desired contrast. Intensity is controlled by increasing or decreasing the argument of the pixel value of each pixel by a constant amount, and the degree of phase enhancement is controlled by multiplying the phase (argument) of each pixel by a constant. | 2013-02-28 |
20130049754 | ITERATIVE RECONSTRUCTION METHOD WITH PENALTY TERMS FROM EXAMINATION OBJECTS - A method is disclosed for calculating an MR image of a target layer from an examination object, wherein the MR image is calculated using iterative reconstruction. In at least one embodiment, the method includes: acquiring MR data from an initial layer of the examination object, determining information produced by the examination object from the acquired MR data of the initial layer, determining a penalty term from the information produced by the examination object, and performing the iterative reconstruction of the MR image for the target layer taking into account the determined penalty term. | 2013-02-28 |
20130049755 | HELICAL GRADIENT COIL FOR MAGNETIC RESONANCE IMAGING APPARATUS - A gradient coil is provided. The gradient coil comprises: a first layer comprised of a first plurality of turns of wires; and a second layer of coil comprised of a second plurality of turns of wires. Each turn of wire in the first and second plurality of turns of wires circles along the side walls of a cylindrical substrate and each turn of wire in the first and second plurality of turns of wires include a first portion wound along the inner side wall of the substrate and a second portion wound along the outer side wall of the substrate. | 2013-02-28 |
20130049756 | METHODS, SYSTEMS, AND DEVICES FOR INTRA-SCAN MOTION CORRECTION - Systems, methods, and devices for intra-scan motion correction to compensate not only from one line or acquisition step to the next, but also within each acquisition step or line in k-space. The systems, methods, and devices for intra-scan motion correction can comprise updating geometry parameters, phase, read, and/or other encoding gradients, applying a correction gradient block, and/or correcting residual errors in orientation, pose, and/or gradient/phase. | 2013-02-28 |
20130049757 | Device and Method for Detecting an Underground Power Line - A device for detecting an underground power line includes, for example, a sensor unit that has a magnetic field sensor element that is configured for receiving a received signal depending on the features of the power line and the underground, a control and evaluation unit configured for controlling the sensor unit and for evaluating the received signal, and a display unit for displaying the received signal evaluated by the control and evaluation unit. The sensor unit includes, for example, at least one additional magnetic field sensor element configured to receive a received signal depending on the features of the power line and the underground, wherein the magnetic field sensor elements can be independently controlled by the control and evaluation unit. | 2013-02-28 |
20130049758 | STUN DEVICE TESTING APPARATUS AND METHODS - A method of testing an electric discharge stun device includes the steps of identifying a stun device to be tested and absorbing a discharge from the stun device into a tester. The discharge is characterized by a discharge characteristic that is then compared automatically to information such as (a) a previous corresponding characteristic associated with a previous discharge of the stun device or (b) a corresponding characteristic associated with a prior discharge of at least one other stun device. The characteristic can be a waveform, a peak voltage, duration, current, joule, and temperature. | 2013-02-28 |
20130049761 | BATTERY STACK CELL MONITOR - A battery monitor system for determining a cell voltage between a low side contact and a high side contact of a cell in situ as one of a plurality of cells connected in series to form a battery. The system uses an arrangement of switches and capacitors to shift relatively high absolute voltages of a battery stack to a relative low voltage level so lower voltage electronics can be used to monitor cell voltages. The system may be configured to provide a single ended measurement or a differential measurement indicative of a cell voltage. The differential measurement may be advantageous to correct or offset signal noise caused by electromagnetic interference (EMI). | 2013-02-28 |
20130049762 | Battery Management - Battery management may be provided. First, a battery string in a battery bank may be charged for a charge time. After charging the battery string, the battery string may be isolated from charging for a rest time. Once the charging and resting from charging is complete, a test open circuit voltage for each battery in the first battery string may be measured. In addition, a defective indicator that a battery is defective may be recorded in a database. Next, a battery may be loaded with a preset load for a load time. After loading the battery, a test load voltage for each of the batteries loaded with the preset load may be measured. A second defective indicator that a battery is defective may be recorded in the database when the test load voltage for the second battery is greater than a load voltage differential. | 2013-02-28 |
20130049765 | In-Situ Cable Unplug Detector Operating During Normal Signaling Mode - An in-situ unplug detector circuit detects when a cable is disconnected or unplugged. Detection does not have to wait for normal signaling to pause, such at the end of a frame or timeout. Instead, detection occurs during normal signaling. When the cable is disconnected, the transmitter no longer drives the load at the far end of the cable, and thus can drive the near end to a higher high voltage and to a lower low voltage. The increased voltage swing is detected by a detector at the near end that amplifies the transmitter output to the cable. A fast detector has a higher bandwidth and faster response time than a slow detector, and generates a fast detect signal that crosses over a slow detect signal. When the cable is disconnected, the fast detect signal again crosses over the slow detect signal, and decision logic activates an unplug signal. | 2013-02-28 |
20130049766 | MEASURING DEVICE AND A METHOD FOR MEASURING A CHIP-TO-CHIP-CARRIER CONNECTION - A measuring device is provided: the measuring device including: a power supply configured to provide electric power to a chip via at least one of a chip connection and a chip-carrier connection; a chip arrangement receiving portion configured to receive a chip arrangement, the chip arrangement including a chip and a chip-carrier connected to the chip via one or more chip-to-chip-carrier connections; a detection portion including a plate; a detection circuit coupled to the plate and configured to detect an electrical signal from the plate; wherein the plate is configured such that it covers at least part of at least one of the chip, the chip-carrier, and the chip-to-chip-carrier connection; and wherein the plate is further configured such that at least part of the at least one of the chip, the chip-carrier, and the chip-to-chip-carrier connection is uncovered by the plate. | 2013-02-28 |
20130049773 | Measurement Tool and Method of Use - This invention relates to a measurement tool and method of use, and in particular to a measurement tool for use in determining a parameter of a stationary or moving fluid. The measurement tool has been designed primarily for use in borehole formation testing. The measurement tool can measure the dielectric constant of a fluid within a pipe or surrounding the tool. The pipe or wall between the tool and the fluid is electrically insulating. The tool has pair of capacitor plates mounted adjacent to the pipe or wall, a signal generator which can deliver an alternating electrical signal to at least one of the capacitor plates, and a detector for measuring a signal dependent upon the electrical capacitance between the capacitor plates. The measurement tool can additionally measure the electrical resistivity of the fluid. | 2013-02-28 |
20130049774 | SURFACE CHARGE REDUCTION TECHNIQUE FOR CAPACITIVE SENSORS - A differential capacitive transducer system is disclosed that includes first and second capacitive cores and a chopping system. The first core a first input coupled to a first capacitor, a second input coupled to a second capacitor, and a first output. The second core includes a third input coupled to a third capacitor, a fourth input coupled to a fourth capacitor, and a second output. The chopping system has first and fourth inputs coupled to positive signals, and second and third inputs coupled to negative signals. As the chopping system switches between high and low states, it couples the core inputs to different polarity signals reducing charge buildup. The different polarity signals can have substantially same magnitudes. Chopper clock and main clock frequencies can be selected to provide substantially zero average voltages at the core inputs. The system can include an integrator circuit and differential summing circuits. | 2013-02-28 |
20130049775 | SURFACE CHARGE REDUCTION TECHNIQUE FOR CAPACITIVE SENSORS - A differential capacitive transducer system is disclosed that includes first and second capacitive cores and a chopping system. The first core a first input coupled to a first capacitor, a second input coupled to a second capacitor, and a first output. The second core includes a third input coupled to a third capacitor, a fourth input coupled to a fourth capacitor, and a second output. The chopping system has first and fourth inputs coupled to positive signals, and second and third inputs coupled to negative signals. As the chopping system switches between high and low states, it couples the core inputs to different polarity signals reducing charge buildup. The different polarity signals can have substantially same magnitudes. Chopper clock and main clock frequencies can be selected to provide substantially zero average voltages at the core inputs. The system can include an integrator circuit and differential summing circuits. | 2013-02-28 |
20130049776 | READOUT CIRCUIT FOR SELF-BALANCING CAPACITOR BRIDGE - A capacitive transducer and a readout circuit for processing a signal from a capacitive transducer. The readout circuit includes a high gain circuit element, two summing amplifiers and two feedback path. The high gain circuit element generates an amplified transducer signal, and the summing amplifiers sum the amplified transducer signal with a positive reference voltage and the negative reference voltage, respectively, to generate a first summation signal and a second summation signal. The feedback paths feed back the summation signals to the transducer. Output circuitry generates an output signal based on the summation signals. The high gain circuit element can be a switched capacitor integrator. The output circuitry can generates the output signal based on the first and second summation signals. | 2013-02-28 |
20130049777 | DEVICE IDENTIFICATION AND TEMPERATURE SENSOR CIRCUIT - An integrated circuit includes a device identification circuit and a temperature sensor diode connected in parallel from a common node. The device identification circuit includes a resistor connected to a diode-connected transistor. The device identification circuit and the temperature sensor diode are adapted to not be simultaneously operating in an ON state. A first voltage is applied to the common node to place the device identification circuit in an ON state and place the temperature sensor diode in an OFF state to identify the integrated circuit. A second voltage is applied to the common node to place the device identification circuit in an OFF state and place the temperature sensor diode in an ON state to determine a temperature of the integrated circuit. | 2013-02-28 |
20130049778 | BALANCING RESISTOR TESTING APPARATUS - A balancing resistor testing apparatus is configured for acquiring a resistance of a balancing resistor electronically connected to a supercapacitor of a series supercapacitor assembly in parallel. The balancing resistor testing apparatus includes a controller and a digital potentiometer. The controller detects a voltage across each supercapacitor of the series supercapacitor. The digital potentiometer comprising a plurality of variable resistors each of which is electronically connected to a supercapacitor in parallel, the controller controls the digital potentiometer to continuously adjust the effective resistance of each potentiometer until the controller detects that each supercapacitor has the same or very similar voltage. | 2013-02-28 |
20130049779 | INTEGRATED CIRCUIT - An integrated circuit comprising a first pair ( | 2013-02-28 |
20130049780 | BUILT-IN SELF-TEST FOR RADIO FREQUENCY SYSTEMS - Techniques for performing built-in self-test (BIST) of performance of an RF system are disclosed. The techniques may be used, for example, for measuring distortion generated by the RF system under test, detecting faults in the system, determining calibration of the system, and/or assisting in compensating analog circuitry that is sensitive to temperature, supply voltage, and/or process variations. Also, a BIST architecture for determining RF performance of an RF systems is disclosed. | 2013-02-28 |
20130049781 | Semiconductor Devices with Self-heating Structures, Methods of Manufacture Thereof, and Testing Methods - Semiconductor devices with self-heating structures, methods of manufacture thereof, and testing methods are disclosed. In one embodiment, a semiconductor device includes a workpiece, an active electrical structure disposed over the workpiece, and at least one self-heating structure disposed proximate the active electrical structure. | 2013-02-28 |
20130049782 | METHOD FOR CLEANING A CONTACT PAD OF A MICROSTRUCTURE AND CORRESPONDING CANTILEVER CONTACT PROBE AND PROBE TESTING HEAD - A method for cleaning a contact pad of a microstructure or device to be tested when it is in electric contact with a measure apparatus, being obtained by electrically contacting a flexible probe with said contact pad. The method includes mechanically engaging a free end of the flexible probe in a manner that sticks the free end in the pad; and laterally flexing, by means of a tip charge, the flexible probe in a manner that keeps the free end stuck in the pad, so as to locally dig into a covering layer of the pad and realize a localized crushing thereof. | 2013-02-28 |
20130049785 | INSPECTION DEVICE FOR GLASS SUBSTRATE - Disclosed is an inspection device for a glass substrate, comprising at least one probe, a holder, a stretch controller and a control circuit. The probe is installed on the stretch controller, the stretch controller is employed to stretch the probe out of the holder as an electrical signal is received; and to retract the probe backward in the holder as the electrical signal stops. The present invention promotes the inspection efficiency for the glass substrate. | 2013-02-28 |
20130049786 | NON-SYNCHRONIZED RADIO-FREQUENCY TESTING - A device under test (DUT) may be tested using a test station having a test host, a non-signaling tester, and a test cell. During testing, the DUT may be placed within the test cell, and the DUT may be coupled to the test host and the tester. In one suitable arrangement, the DUT may be loaded with a predetermined test sequence. The predetermined test sequence may configure the DUT to transmit test signals using different network access technologies without synchronizing with the tester. The tester may receive corresponding test signals and perform desired radio-frequency measurements. In another suitable arrangement, the tester may be loaded with the predetermined test sequence. The predetermined test sequence may configure the tester to generate test signals using different network access technologies without establishing a protocol-compliant data link with the DUT. The DUT may receive corresponding test signals and compute receive signal quality. | 2013-02-28 |
20130049789 | DIE HAVING WIRE BOND ALIGNMENT SENSING STRUCTURES - A semiconductor die includes a substrate having a topside including active circuitry having an array of bond pads thereon separated by gaps including a minimum gap. At least a portion of the array of bond pads are connected to nodes in the active circuitry. At least one wire bond alignment sensing structure includes a first bond pad selected from the array of bond pads, and a guard element positioned along at least a portion of the first bond pad. The guard element is spaced apart by a distance shorter than the minimum gap from the first bond pad. | 2013-02-28 |
20130049790 | Electrical Characterization for a Semiconductor Device Pin - Embodiments related to electrically characterizing a semiconductor device are provided. In one example, a method for characterizing a pin of a semiconductor device is provided, the method comprising providing a test pattern to the semiconductor device. Further, the method includes adjusting a selected electrical state of a pin of the semiconductor device and measuring a value for a dependent electrical state of the pin responsive to the selected electrical state. The example method also includes generating an electrical characterization for the pin by correlating the dependent electrical state with the selected electrical state and outputting the electrical characterization for display. | 2013-02-28 |
20130049793 | ANALYZING EM PERFORMANCE DURING IC MANUFACTURING - A testing structure, system and method for monitoring electro-migration (EM) performance. A system is described that includes an array of testing structures, wherein each testing structure includes: an EM resistor having four point resistive measurement, wherein a first and second terminals provide current input and a third and fourth terminals provide a voltage measurement; a first transistor coupled to a first terminal of the EM resistor for supplying a test current; the voltage measurement obtained from a pair of switching transistors whose gates are controlled by a selection switch and whose drains are utilized to provide a voltage measurement across the third and fourth terminals. Also included is a decoder for selectively activating the selection switch for one of the array of testing structures; and a pair of outputs for outputting the voltage measurement of a selected testing structure. | 2013-02-28 |
20130049794 | EXTENDED SYSTEMS AND METHODS FOR TESTING POWER SUPPLIES - A system and method for testing multiple power supplies. Multiple power supplies are received including a power-end and an adapter end for connection to a power supply tester. Programmable loads and test parameters are configured for the power supply tester in response to a user selection. The multiple power supplies are automatically tested utilizing the test parameters. Performance characteristics of the multiple power supplies are measured during testing. The performance characteristics of the multiple power supplies are recorded. Results indicating whether each of the multiple power supplies passed the testing are displayed utilizing one or more displays and light emitting diodes. | 2013-02-28 |
20130049797 | IMPEDANCE CALIBRATION CIRCUIT AND METHOD - An embodiment of an impedance calibration circuit and method, a device including an impedance calibration circuit, and a transmission link system. | 2013-02-28 |
20130049798 | MOTHERBOARD WITH DUAL NETWORK CARD CONNECTORS AND LOW SIGNAL REFLECTIVITY - An exemplary motherboard includes a controller, and two different network card connectors. At least one of the two network card connectors is electronically connected to the controller via a resistor. A user of the motherboard may choose to use either the first network card connector, or the second network card connector, or the first network card connector and the second network card connector simultaneously. | 2013-02-28 |
20130049805 | ONE-OF-N N-NARY LOGIC IMPLEMENTATION OF A STORAGE CELL - A one-of-n storage cell for use in an N-nary dynamic logic (NDL) circuit. The storage cell may accept an input value and provide a complemented output value that corresponds to the input value. However, if an input value that corresponds to a precharge input value is received, the output value remains the previous output value. The storage cell may be implemented to accept either inverted or non-inverted one-of-n NDL signals and to provide as an output either non-inverted or inverted one-of-N NDL signals, respectively, where N is greater than two. | 2013-02-28 |
20130049806 | SEMICONDUCTOR DEVICE - A semiconductor device is provided, which includes a switch having a first transistor and a logic circuit having an output terminal. The logic circuit includes a bootstrap circuit having at least one second transistor. The bootstrap circuit is electrically connected to the output terminal. The first transistor and the second transistor have the same conductivity type. Each of the first transistor and the second transistor includes an oxide semiconductor layer including a channel formation region and a pair of gate electrodes with the oxide semiconductor layer provided therebetween. | 2013-02-28 |
20130049809 | MICRO ELECTRO-MECHANICAL SYSTEM CIRCUIT CAPABLE OF COMPENSATING CAPACITANCE VARIATION AND METHOD THEREOF - A micro electro-mechanical system (MEMS) circuit includes a MEMS differential capacitor, a read-out circuit, a control circuit, and a compensation circuit. The MEMS differential capacitor includes a first capacitor and a second capacitor. The read-out circuit is coupled to the MEMS differential capacitor for reading a difference between the first capacitor and the second capacitor in a zero-G condition, and generating an output signal according to the difference. The control circuit is coupled to the read-out circuit for receiving the output signal and generating a control signal. The compensation circuit is coupled to the control circuit for compensating the MEMS differential capacitor according to the control signal. | 2013-02-28 |
20130049810 | Methods and Apparatus for Time to Current Conversion - A time to current conversion apparatus and methods. An impedance having an input for selectively receiving a time varying periodic signal or a known voltage signal is provided; and a current output is coupled to the impedance. By observing the average current through the impedance for the known voltage signal over a time period, and by observing the average current through the impedance for a time varying periodic signal, the duty cycle of the time varying periodic signal may be determined by evaluating a ratio of a first average current observed at the current output while the time varying periodic signal is coupled to the impedance to a second average current observed at the current output while the known voltage signal is coupled to the impedance. An embodiment time to current converter circuit is disclosed. Method embodiments for determining the duty cycle of a time varying periodic signal are provided. | 2013-02-28 |
20130049811 | HIGH EFFICIENCY DRIVING CIRCUIT - A high efficiency driving circuit includes a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, a first N-type metal-oxide-semiconductor transistor, a second N-type metal-oxide-semiconductor transistor, a current source, a third N-type metal-oxide-semiconductor transistor, a fourth N-type metal-oxide-semiconductor transistor, a fifth N-type metal-oxide-semiconductor transistor, a first resistor, and a second resistor. The first P-type metal-oxide-semiconductor transistor charges a third terminal of the first P-type metal-oxide-semiconductor transistor according to a first control signal, and the first N-type metal-oxide-semiconductor transistor discharges the third terminal of the first P-type metal-oxide-semiconductor transistor according to a second control signal. A high voltage level of the first control signal is at a first voltage, and a low voltage level of the first control signal is at a third voltage; a high voltage level of the second control signal is at a fourth voltage, and a low voltage level of the second control signal is ground. | 2013-02-28 |
20130049812 | MONOLITHIC HIGH-SIDE SWITCH CONTROL CIRCUITS - A high-side switch control circuit is provided. The high-side switch control circuit includes an on/off transistor, a bias resistor, a zener diode, a level-shifting transistor, and a current source. The on/off transistor operates as a switch. The bias resistor is coupled to turn off the on/off transistor. The zener diode is coupled to clamp the maximum voltage of the on/off transistor. The level-shifting transistor is coupled to turn on the on/off transistor. The current source is coupled to the level-shifting transistor. The current source limits the maximum current of the level-shifting transistor. | 2013-02-28 |
20130049819 | Method and Control Unit for Controlling an Electrical Component - An electrical component having a primary winding, a first field-effect transistor, configured as a switch of the primary winding, for switching the primary winding, a quench winding for quenching the inductive load of the primary winding when switching off the primary winding, and a second field-effect transistor, configured as a switch of the quench winding, for switching the quench winding. In the process, the first field-effect transistor is operated in linear operation and the second field-effect transistor is operated in linear operation or in a clock-pulsed operation between the linear operation and a switched-off state during a switching-off process of the quench winding. | 2013-02-28 |
20130049820 | CLOCK DIVIDER UNIT - A clock divider unit includes a plurality of divider circuits which divides a common reference clock, and a gate circuit disposed before the plurality of divider circuits. The reference clock is supplied to the divider circuits via the gate circuit after a reset state of each divider circuit is released so that dividing action of each divider circuit is allowed. | 2013-02-28 |
20130049823 | SEMICONDUCTOR DEVICE - A semiconductor device includes a variable resistor that sets a resistance value as a first resistance value in an emphasis mode, and as a second resistance value smaller than the first resistance value in a de-emphasis mode, a first driver that sets an output impedance as a third resistance value in the emphasis mode, and as a fourth resistance value larger than the third resistance value in the de-emphasis mode, a second driver that sets the output impedance as a fifth resistance value in the emphasis mode, and as a sixth resistance value larger than the fifth resistance value in the de-emphasis mode, and a controller that controls conductive states of the first and second drivers according to an input signal, and switches the output impedances of the first and second drivers and the resistance value of the variable resistor between the emphasis mode and the de-emphasis mode. | 2013-02-28 |
20130049824 | 3D CHIP STACK SKEW REDUCTION WITH RESONANT CLOCK AND INDUCTIVE COUPLING - There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor. | 2013-02-28 |
20130049829 | VARIABLE DELAY LINE FOR DELAY LOCKED LOOP - In a multi-stage switching-type delay circuit, occurrence of a hazard is inhibited at the time of the switching of the number of stages. With the multi-stage switching-type delay circuit, an input IN of the delay circuit is connected to a stage that is not selected as a path for causing a delay in order to prevent a logic state of each of the internal nodes of the delay circuit from being changed between before and after the switching of the number of stages. | 2013-02-28 |
20130049830 | DELAY LOCK LOOP CIRCUIT - The invention provides a delay lock loop circuit (DLL) for generating a locked signal, the DLL circuit includes: a phase detector, a first and a second voltage controlled delay chains, a charge pump and a duty cycle detection pump. The phase detector generates a phase detecting result by detecting a phase difference between the clock signal and the locked signal. The first and the second voltage controlled delay chains generate a first and a second delayed signals by delaying the clock signal according to the first and the second control signals, respectively. The charge pump is used for generating the first and the second control signal according to the phase detecting result. The duty cycle detection pump is used for controlling a voltage level of the second control signal according to the first and the second delayed signals. | 2013-02-28 |
20130049831 | POLYPHASE CLOCK GENERATOR - A polyphase clock generator for use in clock data recovery (CDR) includes a phase selector and a four-to-eight phase converter further including a plurality of delay paths, switches, and phase interpolators. The switches switch over the delay paths so as to select a group of delay paths suited to a clock frequency which is determined in advance. A plurality of reference clock signals with a predetermined phase difference (e.g. 90°) therebetween is selectively delayed while passing through the selected group of delay paths. The phase interpolators interpolate the delayed reference clock signals, passing through the selected group of delay paths, into the reference clock signals, thus generating a plurality of clock signals. The phase selector selectively combines the clock signals with a mixing ratio according to clock data recovery, thus generating a plurality of recovery clock signals with a precise phase difference (e.g.) 45°) therebetween. | 2013-02-28 |
20130049832 | CLOCK GENERATOR WITH DUTY CYCLE CONTROL AND METHOD - A clock generator circuit for producing a clock output having a controlled duty cycle is disclosed. A bi-stable circuit provides the clock output which is switchable to a first state in response to an edge of the input clock signal and to a second state in response to a feedback signal. A duty cycle detection circuit is configured to source a current to a node and to sink a current from the node depending upon the output clock state. A capacitor is connected to receive a duty cycle current relating to the current at the node, with a comparator circuit being configured to sense a voltage on the capacitor and to produce the feedback signal when the voltage is at a selected level. | 2013-02-28 |
20130049839 | Circuit Arrangement and Receiver Including the Circuit Arrangement - According to embodiments of the present invention, a circuit arrangement is provided. The circuit arrangement includes a first input terminal and a second input terminal, a first transistor and a second transistor, each of the first transistor and the second transistor having a first controlled terminal, a second controlled terminal and a control terminal, the first controlled terminal of the first transistor being coupled to the first controlled terminal of the second transistor, the control terminal of the first transistor being coupled to the first input terminal, the control terminal of the second transistor being coupled to the second input terminal, and the second controlled terminal of the first transistor being coupled to the second controlled terminal of the second transistor, an input matching circuit coupled to the first input terminal, the second input terminal, the first transistor and the second transistor, a first resistive element coupled between the control terminal of the first transistor and the second controlled terminal of the first transistor, a second resistive element coupled between the control terminal of the second transistor and the second controlled terminal of the second transistor, and an output terminal coupled to the second controlled terminal of the first transistor and the second controlled terminal of the second transistor, wherein the input matching circuit includes a first inductor, a second inductor, a third inductor, a first capacitor and a second capacitor, wherein the first inductor is coupled between the first input terminal and the control terminal of the first transistor, wherein the second inductor is coupled between the first controlled terminal of the first transistor and the first controlled terminal of the second transistor, wherein the third inductor is coupled between the second input terminal and the control terminal of the second transistor, wherein the first capacitor is coupled between the control terminal of the first transistor and the first controlled terminal of the first transistor, and wherein the second capacitor is coupled between the control terminal of the second transistor and the first controlled terminal of the second transistor. According to further embodiments of the present invention, a receiver including the circuit arrangement is provided. | 2013-02-28 |
20130049840 | IMPLEMENTING DIFFERENTIAL RESONANT CLOCK WITH DC BLOCKING CAPACITOR - A method and circuit for implementing differential resonant clocking with a DC blocking capacitor, and a design structure on which the subject circuit resides are provided. An on-chip inductor and an on-chip capacitor are connected between a pair of differential active clock load nodes to form a resonant tank circuit. The on-chip inductor has a selected value based upon a value of a load capacitor of the differential active clock load nodes to determine the resonant frequency. The on-chip capacitor has a selected value substantially greater than the value of the load capacitor. | 2013-02-28 |
20130049843 | REVERSE CONDUCTION MODE SELF TURN-OFF GATE DRIVER - There is provided a power electronic module that includes a power switch module and a drive circuit operatively coupled to the power switch module. The drive circuit is configured to enable and disable a forward conduction mode operation of the switch module. The drive circuit disables forward conduction mode operation of the power switch module when the power switch module is operating in reverse conduction mode. | 2013-02-28 |
20130049844 | CAPACITIVE TOUCH SENSOR HAVING LIGHT SHIELDING STRUCTURES - This disclosure provides systems, methods, and apparatus related to a capacitive touch sensor with light shielding structures. In one aspect, a device includes an array formed by a plurality of row electrodes and a plurality of non-transparent column electrodes, wherein at least a first portion of the row electrodes is non-transparent and coplanar with the column electrodes and at least a second portion of the row electrodes is non-coplanar with the column electrodes. The device further includes light shielding structures that are non-transparent and coplanar with the column electrodes, wherein the light shielding structures substantially overlap the second portion. | 2013-02-28 |
20130049847 | BOOTSTRAPPING TECHNIQUES FOR CONTROL OF CMOS TRANSISTOR SWITCHES - Techniques to provide bootstrap control of a CMOS transistor switch. The techniques may include driving a control terminal of a CMOS transistor switch to a first predetermined voltage to set the CMOS transistor switch to an off-state. The first predetermined voltage may be drained to a discharge voltage and the control terminal may be driven to a second predetermined voltage to set the CMOS transistor switch to an on-state. The control terminal may be driven to the first predetermined voltage to return the CMOS transistor switch to the off-state. | 2013-02-28 |
20130049848 | ELECTRONIC COMPONENT AND REFLECTED-WAVE CANCELLING METHOD - An electronic component includes a driver that outputs a signal to a reception apparatus; a storage device storing therein reflection information related to a reflected wave that returns to the driver when the signal is reflected back by the reception apparatus; a reflected wave detector that based on the reflection information, determines a measurement period for measuring the reflected wave and that based on the measurement period, measures an arrival time and a peak amplitude of the reflected wave; and a controller that based on the arrival time and the peak amplitude, extracts reflected-wave cancelling information for inhibiting effects of the reflected wave from the reception apparatus and that sets the extracted reflected-wave cancelling information in the driver. | 2013-02-28 |
20130049849 | FILTER SYSTEM CAPABLE OF AUTOMATICALLY ADJUSTING BANDWIDTH AND METHOD OF AUTOMATICALLY ADJUSTING BANDWIDTH OF A FILTER - A filter system capable of automatically adjusting bandwidth includes a filter and an adaptive unit. The filter is used for filtering a digital signal to generate an output signal to an application unit. The adaptive unit is used for generating an adjustment signal to the filter according to the digital signal and the output signal. The filter dynamically adjusts bandwidth of the filter according to the adjustment signal. | 2013-02-28 |
20130049850 | CHARGE DOMAIN FILTER APPARATUS - A charge domain filter (CDF) apparatus having a bandwidth compensation circuit is provided. The bandwidth compensation circuit includes a configurable power-reference cell (CPC) and/or a programmable-delay cell (PDC). The CPC receives and adjusts an output of the CDF to obtain a sensing power, and outputs the sensing power to the CDF. The PDC receives and delay an output of the CDF, and outputs a delay result to the CDF. The bandwidth compensation circuit having a flexible structure, so as to implement X-axis (frequency) compensation and/or Y-axis (power or gain) compensation of a frequency response diagram according to a design requirement. | 2013-02-28 |
20130049851 | ACTIVE PULL-UP/PULL-DOWN CIRCUIT - A circuit includes circuit portions operating from separate power supplies which are switched sequentially. An output of a first portion powered by a power supply (A) is provided as an input to a second portion powered by another power supply (B). Power supply (A) is switched-ON a delay interval later than power supply (B). In an embodiment, the first portion also receives a control input which enables or disables response of the first portion to changes in its inputs. An active circuit is connected between the control terminal and a constant reference potential node of the circuit, and has one transistor of a current-mirror pair connected across supplies (A) and (B). The active circuit connects the control terminal to the constant reference potential node in the delay interval, but is an open circuit otherwise. Power dissipation in the circuit is thereby reduced. | 2013-02-28 |
20130049852 | MOFSET MISMATCH CHARACTERIZATION CIRCUIT - A semiconductor device comprising a first inverter circuit including a first PMOS transistor and a first NMOS transistor, a drain electrode of the first PMOS transistor coupled to a drain electrode of the first NMOS transistor, and a second inverter circuit including a second PMOS transistor and a second NMOS transistor, a drain electrode of the second PMOS transistor coupled to a drain electrode of the second NMOS transistor. A first output voltage pad coupled to gate electrodes of the first and second PMOS and NMOS transistors, and between the drain electrode of the first PMOS transistor and the drain electrode of the NMOS transistor to self-bias the first inverter circuit. A second output voltage pad coupled between the drain electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor. | 2013-02-28 |
20130049853 | SUPPRESSION OF OVERVOLTAGE CAUSED BY AN INDIRECT LIGHTNING STRIKE - A coupling circuit for a bus subscriber on a bus line of a field bus with DC-voltage-free and differential EIA-485/EIA-422-compliant signal transmission according to a TTP protocol, in which the two inputs/outputs of a transmission/reception component of the bus subscriber are connected to a first winding of a signal transformer, and the two poles of the bus line are connected to a second winding of the signal transformer, and the first winding has a center tap, wherein the center tap is connected to the local reference-earth potential of the bus subscriber via a capacitor, the capacitance of which is at least 100 times the parasitic capacitance of the transformer. | 2013-02-28 |
20130049854 | POWER EFFICIENT RADIO FREQUENCY TRANSMITTER - A power efficient, small-packaged radio frequency (RF) transmitter for use in avionics applications. The RF transmitter utilizes Cartesian feedback to operate a power amplifier with Class AB biasing and efficiency, while delivering Class A biasing performance. The RF transmitter includes interstage pads and high pass filters specially configured to meet demanding requirements for both adjacent channel power (ACP) limits and wideband spurious energy limits. The RF transmitter is much smaller in size and dissipates less DC power and heat than previous RF transmitters used in avionics applications. | 2013-02-28 |
20130049855 | INTEGRATED CIRCUIT - An integrated circuit comprising a Class-D amplifier for amplifying an input signal at an input terminal is disclosed. The Class-D amplifier is switchable between an operational mode, in which a comparator ( | 2013-02-28 |
20130049856 | Self Oscillating Modulator - There is described a self oscillating modulator circuit comprising at least two coupled self oscillating loop modules, that achieved a good efficiency and a good linearity. | 2013-02-28 |
20130049859 | SATURATION PROTECTION OF A REGULATED VOLTAGE - A system for preventing power amplifier supply voltage saturation includes a multiple stage voltage regulator configured to provide a regulated voltage, a power amplifier configured to receive the regulated voltage, and a saturation protection circuit configured to apply a current into a first stage of the multiple stage voltage regulator when the regulated voltage reaches a reference voltage, the applied current causing a subsequent stage of the multiple stage voltage regulator to prevent the regulated voltage from exceeding the reference voltage. | 2013-02-28 |
20130049860 | BICYCLE-USE MEASURING APPARATUS AND CONTROL METHOD - A bicycle-use measuring apparatus includes a sensor, a signal amplifying section and a gain control section. The sensor is configured to be installed on a bicycle having a rotating part. The signal amplifying section amplifies an output of the sensor. The gain control section adjusts a gain of the signal amplifying section in accordance with changes in a rotational state of the rotating part. | 2013-02-28 |
20130049861 | MODULATOR AND AN AMPLIFIER USING THE SAME - A linear amplification with nonlinear components (LINC) modulator is provided. The LINC modulator includes: a separator that generates a plurality of constant envelope signals from a source signal; a processor that receives an input signal and detects and removes a phase jump in phase trajectory of the input signal to generate a first signal having a continuous phase trajectory and a second signal having a discontinuous phase trajectory; and a quadrature modulator that mixes the first signal with the second signal to reconstruct the input signal. | 2013-02-28 |
20130049862 | SWITCHING CIRCUIT AND ENVELOPE SIGNAL AMPLIFIER - A switching circuit according to one embodiment has: N switching elements; a connection circuit including N−1 first inductance elements that are connected in series; a second inductance element; and N third inductance elements. Control terminals of the N switching elements are connected to ends of the connection circuit and connection contacts, respectively. One end of the second inductance element is connected to a power supply. The N third inductance elements electrically connects one ends of the N switching elements and the other end of the second inductance element with each other, respectively. | 2013-02-28 |
20130049867 | CLASS OF POWER AMPLIFIERS FOR IMPROVED BACK OFF OPERATION - One embodiment of the present invention relates to a power amplifier comprising a plurality of amplifying elements connected in a serial-parallel matrix configuration, containing parallel columns having amplifying elements connected in series. The parallel columns are connected to a common output path coupled to a supply voltage source configured to provide an equal supply voltage to each of the columns. One or more input signals (e.g., RF input signals) are connected to the power amplifier by way of input terminals on a first row of amplifying elements. The remaining amplifying elements have control terminals that are connected to independent control signals, which allow each amplifying element to be operated independent of the other amplifying elements in the matrix. This selective operation of amplifying elements allows for improved efficiency over a wide range of power amplifier output powers. | 2013-02-28 |
20130049868 | AMPLIFIER CIRCUIT WITH VARIABLE TUNING PRECISION - Systems and methods are provided for facilitating variable precision tuning of an amplifier circuit. In accordance with one aspect of the present disclosure, the system includes an amplifier having multiple tuning stages to set the gain of the amplifier to discrete gain levels. In particular embodiments, the tuning stages are connected in series and each of the tuning stages includes a resistor connected in parallel to a switch, which can be disengaged to cause the amplifier to set the gain to an adjacent gain level. In certain embodiments, the difference in gain between each adjacent one of the plurality of gain levels is more at higher gain levels than at lower gain levels. | 2013-02-28 |
20130049875 | RELAXATION OSCILLATOR CIRCUIT INCLUDING TWO CLOCK GENERATOR SUBCIRCUITS HAVING SAME CONFIGURATION OPERATING ALTERNATELY - A control circuit controls first and second clock generator subcircuits so that one subcircuit of the first and second clock generator subcircuits operates for a comparison voltage generating interval, then another subcircuit operates for a clock generating interval, and so that the first and second clock generator subcircuits alternately repeat processes of the comparison voltage generating interval and the clock generating interval. For the comparison voltage generating interval, each of the first and second clock generator subcircuits is controlled to generate a comparison voltage and output the same voltage to an inverted output terminal of a comparator. For the clock generating interval, each of the first and second clock generator subcircuits compares an output voltage from a current-voltage converter circuit with the comparison voltage. | 2013-02-28 |
20130049876 | OSCILLATOR - A second piezoelectric vibrator ( | 2013-02-28 |
20130049877 | MODULATOR AND AN AMPLIFIER USING THE SAME - The LINC modulator includes: a separator that generates a plurality of constant envelope signals from a source signal; a plurality of arms through which the plurality of the constant envelope signals are passed, wherein each arm includes a filter that compares frequencies of components of the constant envelope signals with a threshold frequency to generate a first signal including a first frequency part of the source signal, the first frequency part being composed of frequencies lower than a predetermined frequency; a processor that generates a second signal including a second frequency part of the source signal whose frequencies are different from the first frequency part and performs a frequency signal distortion of the second signal to generate a distorted signal; and a quadrature modulator that multiplies the first and distorted signals to reconstruct the constant envelope signals. | 2013-02-28 |
20130049878 | DIFFERENTIAL MODE TRANSMISSION LINES WITH WEAK COUPLING STRUCTURE - A differential mode transmission line with a weak coupling structure is presented. The differential mode transmission line with a weak coupling structure includes a first transmission line and a second transmission line. The first transmission line includes a first wiring portion, a second wiring portion, and a third wiring portion. The second transmission line also includes a first wiring portion, a second wiring portion, and a third wiring portion. The wiring portions of the present disclosure are connected through connection portions, and the connection portions are designed as a corner structure. Due to the characteristics of the corner structure of the present disclosure, a pitch between the second wiring portions is greater than that between the first wiring portions or the third wiring portions, thereby generating a weak coupling structure to suppress common mode noises. | 2013-02-28 |
20130049881 | FILTER CIRCUIT AND RADIO TERMINAL INCLUDING FILTER CIRCUIT - There is provided a filter circuit including a passive mixer circuit, and a passive switched capacitor circuit that is connected to a rear stage of the passive mixer and includes a flying capacitor. The passive mixer circuit generates a baseband signal by multiplying an input signal supplied from a predetermined signal source impedance by each local oscillation signal and outputs the baseband signal to the passive switched capacitor circuit, the passive switched capacitor circuit performs predetermined filtering on the baseband signal supplied from the passive mixer circuit and outputs the processed baseband signal, and a capacitance of the flying capacitor of the passive switched capacitor circuit is a capacitance by which input impedance of the passive mixer circuit is matched to the signal source impedance. | 2013-02-28 |
20130049882 | COMMUNICATION MODULE - A communication module includes a plurality of duplexers, wherein at least either IDT electrodes of transmit filters of at least two of the plurality of duplexers having a different transmit band or IDT electrodes of receive filters of at least two of the plurality of duplexers having a different receive band are composed of a same material, have a same thickness and are provided on a single piezoelectric substrate. | 2013-02-28 |
20130049883 | WAVEGUIDE NETWORK - Conventional technologies using copper tracks to couple integrated circuits (ICs) disposed on printed circuit boards (PCBs) face limitations in scaling beyond a certain transmission rate, restricting their future applications. Described herein is a waveguide network, in which the network comprises ICs on a PCB coupled via a dielectric waveguide, which advantageously overcomes these limitations. The dielectric waveguide is able to transmit radio frequency (RF) signals and has a bandwidth of at least 100 GHz, among other features. Further, the network can be arranged with different topologies such as ring, star or bus based, and is also couplable to other equivalent networks on the PCB using suitable waveguide-based networking devices. | 2013-02-28 |
20130049884 | METHODS AND CIRCUITS FOR ATTENUATING HIGH-FREQUENCY NOISE - Low-frequency digital data input signals in an integrated circuit are controlled between first and second stages in a signal input path of the integrated circuit by a capacitance in the signal input path between the first and second stages. The capacitance is sized to attenuate high-frequency noise in the signal input path. In one embodiment, the integrated circuit may be an input buffer circuit in which the capacitance is a capacitor between the signal input path and a reference potential, a voltage source, or both. In another embodiment, the integrated circuit may be an oscillator circuit in which the capacitance is provided between corresponding elements of a differential pair of transistors in the first stage. | 2013-02-28 |
20130049887 | Electromagnetically transparent metamaterial - The present disclosure relates to an electromagnetically transparent metamaterial, which comprises a substrate and a plurality of man-made metal microstructures arranged periodically inside the substrate. When an electromagnetic wave propagates through the metamaterial, each of the man-made metal microstructures is equivalent to two identical two-dimensional (2D) circuits, which are placed respectively in a direction perpendicular to an incident direction of the electromagnetic wave and in a direction parallel to the incident direction of the electromagnetic wave, and each of which comprises an inductor branch and two identical capacitor branches that are symmetrically connected in parallel with the inductor branch. The 2D circuits are associated with a waveband of the electromagnetic wave so that both a dielectric constant and a magnetic permeability of the metamaterial are substantially 1 when the electromagnetic wave propagates through the metamaterial. | 2013-02-28 |
20130049888 | ACOUSTIC RESONATOR FORMED ON A PEDESTAL - An acoustic resonator structure comprises a substrate having a trench, a conductive pattern formed in the trench, a pillar formed within the trench, and an acoustic resonator supported at a central location by the pillar and suspended over the trench. | 2013-02-28 |
20130049891 | FILTER - A multi-mode cavity filter, comprising: at least one dielectric resonator body incorporating a piece of dielectric material, the piece of dielectric material having a shape such that it can support at least a first resonant mode and at least a second substantially degenerate resonant mode; and a coupling structure comprising a patterned conductive layer for at least one of coupling signals to the piece of dielectric material and coupling signals from the piece of dielectric material. | 2013-02-28 |
20130049892 | FILTER - A multi-mode cavity filter, comprising: at least one dielectric resonator body incorporating a piece of dielectric material, the piece of dielectric material having a shape such that it can support at least a first resonant mode and at least a second substantially degenerate resonant mode; a layer of conductive material in contact with and covering the dielectric resonator body; and a coupling structure comprising at least one electrically conductive coupling path for at least one of inputting signals to the dielectric resonator body and outputting signals from the dielectric resonator body, the at least one electrically conductive coupling path being arranged for at least one of directly coupling signals to the first resonant mode and the second substantially degenerate resonant mode in parallel, and directly coupling signals from the first resonant mode and the second substantially degenerate resonant mode in parallel. | 2013-02-28 |
20130049895 | FILTER - A multi-mode cavity filter having a dielectric resonator body incorporating a piece of dielectric material, the piece of dielectric material having a shape such that it can support at least two substantially degenerate resonant modes; and a coupling structure comprising a plurality of independent coupling elements for coupling signals to the piece of dielectric material. | 2013-02-28 |
20130049896 | FILTER - A multi-mode cavity filter includes a dielectric resonator body incorporating a piece of dielectric material, the piece of dielectric material having a shape such that it can support at least two substantially degenerate resonant modes; and a phased array of coupling elements for coupling signals to the piece of dielectric material. | 2013-02-28 |
20130049901 | MULTI-MODE FILTER - A multi-mode cavity filter, comprising a resonator body of dielectric material capable of supporting at least two degenerate electromagnetic standing wave modes and having a face, and a conductive pattern on at least part of the face for coupling a radio frequency signal between the pattern and the resonator body. | 2013-02-28 |
20130049902 | MULTI-MODE FILTER - A multi-mode cavity filter, comprising: a dielectric resonator body incorporating a piece of dielectric material, the piece of dielectric material having a shape such that it can support at least a first resonant mode and a second substantially degenerate resonant mode; a conductive layer substantially covering the dielectric resonator body but having one or more apertures therein allowing access to the dielectric resonator body; and a coupling structure arranged in an aperture of the one or more apertures, comprising at least one coupling path for at least one of coupling an input signal to the first and second resonant modes and coupling an output signal from the first and second resonant modes, the coupling path having an open-circuit end located adjacent to an edge of the aperture for controlling a strength of electric field generated by the coupling structure. | 2013-02-28 |
20130049903 | ARTIFICIAL MICROSTRUCTURE AND METAMATERIAL WITH THE SAME - An artificial microstructure made of conductive wires includes a split resonant ring with a split, and two curves. The two curves respectively start from first end and the second end of the split resonant ring and curvedly extend inside the split resonant ring, where the two curves do not intersect with each other, and do not intersect with the split resonant ring. | 2013-02-28 |
20130049904 | TRIP UNIT - A trip unit includes an actuator and a cylindrical housing container the actuator. The actuator includes a cylindrical pin; a cylindrical closed chamber; a biasing member; a permanent magnet; a coil housing; and a coil supported by the coil housing. The pin is axially movably disposed in the chamber and extends out of the chamber through a sealed opening. The biasing member may comprise a spring, such as a helical spring, and may be configured to bias the pin for an axial movement in a direction out of the chamber. The permanent magnet may at least partly surround the pin during a latched condition of the trip unit. The coil housing may at least partly define the cylindrical closed chamber. In embodiments, an annular gap is provided between the pin and the permanent magnet. Methods associated with the manufacturing trip units are also disclosed. | 2013-02-28 |
20130049907 | APPARATUS FOR SUPPORTING A HINGED ARMATURE - An apparatus is disclosed, which includes a hinged armature and a yoke. In at least one embodiment, the hinged armature is supported in a cutout in the yoke and can pivot between at least two positions, the cutout in the yoke having an edge, on which the hinged armature is supported. | 2013-02-28 |
20130049908 | COMPONENT AND MANUFACRING PROCESS OF RARE EARTH PERMANENT MAGNET MATERIAL - The invention relates to a component of rare earth permanent magnet material, and the atomic percents of the material are Re(x)Fe(100x-z-a-b-c)B(z)Nb(a)Al(b)M(c), wherein x=12-16, z=5.5-6.5, a=0.05-1, b=0-0.8, and c=0-3. Re stands for rare earth elements, which comprises one or more of Nd, Pr, Gd, Ho, Dy and Tb. By adding Nb, Hcj can be improved, the rectangle degree of J-H demagnetization curve can be improved, and the temperature stability of the product can also be improved; and by adding Nb, the amount of Dy and Tb in heavy rare earth can be reduced, and the cost of the material can also be reduced. | 2013-02-28 |
20130049913 | COIL DEVICE - A coil device | 2013-02-28 |
20130049914 | SURFACE MOUNTED PULSE TRANSFORMER - A surface mounted pulse transformer ( | 2013-02-28 |
20130049915 | MAGNETIC COMPONENT - Provided is a magnetic component capable of omitting a process of binding both ends of a lead wire to terminals and having stable connection between the lead wire and the terminals. The magnetic component is provided with a core ( | 2013-02-28 |
20130049916 | SEMICONDUCTOR STRUCTURE WITH GALVANICALLY-ISOLATED SIGNAL AND POWER PATHS - A galvanic die has signal structures and a transformer structure that provide galvanically-isolated signal and power paths for a high-voltage die and a low-voltage die, which are both physically supported by the galvanic die and electrically connected to the signal and transformer structures of the galvanic die. | 2013-02-28 |
20130049917 | CONDUCTOR PATTERN AND ELECTRONIC COMPONENT HAVING THE SAME - Disclosed herein are a conductor pattern of an electronic component formed in an oval coil shape on a magnetic substrate, the conductor pattern including: a straight part; and a curved part connected to the straight part at both sides thereof, wherein a line width of the curved part is smaller than that of the straight part, and an electronic component including the same. With the conductor pattern and the electronic component including the same according to the present invention, the high precision fine line width and the high resolution conductor pattern may be implemented to improve connectivity, thereby improving characteristics and reliability of the electronic component. | 2013-02-28 |
20130049918 | Common Mode Choke Apparatus and Method - An embodiment integrated common mode choke comprises a magnetic core, a magnetic plate, a first winding coil and a second winding coil. The magnetic plate is inserted within an inner circumference of the magnetic core. The first winding coil and the second winding coil are wound are wound in the same direction through the magnetic core. The integrated common mode choke is equivalent to a common mode choke and a differential mode choke connected in series. The inductance value of the differential mode choke can be changed by adjusting either the gap between the magnetic plate and the magnetic core or the thickness of the magnetic plate. | 2013-02-28 |