09th week of 2014 patent applcation highlights part 61 |
Patent application number | Title | Published |
20140059316 | CONCURRENT ACCESS TO A MEMORY POOL SHARED BETWEEN A BLOCK ACCESS DEVICE AND A GRAPH ACCESS DEVICE - A graph access device and block access device can simultaneously access a memory pool shared between the devices. The memory pool may include one or more memory arrays accessed as a single logical memory. The block access device accesses the memory pool as a flat array of memory blocks, and the graph access device accesses the memory pool as hierarchical file system. The simultaneous access is accomplished by monitoring one or more memory block access operations performed by the block access device, while it is accessing the memory pool. The block access operations are translated into a graph data structure including a plurality of pointers mapping the memory pool to the hierarchical file system. A processor regulates access to the memory pool, and is configured to permit the graph access device to access the memory pool concurrently with the block access device, in accordance with the graph data structure. | 2014-02-27 |
20140059317 | DATA TRANSFER DEVICE - A data transfer device includes a FIFO memory and a control unit which obtains a data amount of the FIFO memory to control the FIFO memory and outputs a selection signal corresponding to the obtained data amount of the FIFO memory. An output data generation unit generates output data including either one of the second output data and an interpolation data selected based on the selection signal, and a first output data stored in a frame memory. | 2014-02-27 |
20140059318 | MEMORY TIMING OPTIMIZATION USING PATTERN BASED SIGNALING MODULATION - According to some embodiments, a method and apparatus are provided to determine a worst-case setup and hold bit pattern stream associated with a load on a bus, and determine a time shift to apply to an incoming bit pattern being conveyed relative to a DLL associated with the load. | 2014-02-27 |
20140059319 | RESOURCE ALLOCATION APPARATUS AND METHOD, AND STORAGE MEDIUM - There is provided with a resource allocation apparatus. An attribute indicating a requirement for a data storage resource to be allocated to a plurality of data flows to which the attribute is provided beforehand is acquired. A data flow relationship graph indicating a relationship between the plurality of data flows which potentially lead to access contention in the data storage resource is generated. Based on the attribute and the data flow relationship graph, allocation of the data storage resource to the plurality of data flows is determined such that no access contention occurs. | 2014-02-27 |
20140059320 | SYNCHRONIZING A TRANSLATION LOOKASIDE BUFFER WITH AN EXTENDED PAGING TABLE - A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system. | 2014-02-27 |
20140059321 | Load Page Table Entry Address Instruction Execution Based on an Address Tralsnation Format Control Field - What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register. | 2014-02-27 |
20140059322 | APPARATUS AND METHOD FOR BROADCASTING FROM A GENERAL PURPOSE REGISTER TO A VECTOR REGISTER - An apparatus and method are described for broadcasting from a general purpose source register to a destination vector register. For example, a method according to one embodiment includes the following operations: selecting data element position N within the destination vector register to be updated; broadcasting a set of data from the general purpose source register to data element position N within the destination vector register if a mask indicator is set to a first indication; and either copying zeroes to data element position N within the destination vector register or maintaining existing values stored within data element position N within the destination vector register if the mask indicator is set to a second indication. | 2014-02-27 |
20140059323 | SYSTEMS AND METHODS OF DATA EXTRACTION IN A VECTOR PROCESSOR - Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory. | 2014-02-27 |
20140059324 | System Core for Transferring Data Between an External Device and Memory - Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified. | 2014-02-27 |
20140059325 | INTEGRATED CIRCUIT APPARATUS, THREE-DIMENSIONAL INTEGRATED CIRCUIT, THREE-DIMENSIONAL PROCESSOR DEVICE, AND PROCESS SCHEDULER, WITH CONFIGURATION TAKING ACCOUNT OF HEAT - The present invention provides a three-dimensional integrated circuit wherein generation of hot spot which makes a high temperature part as a result of intensively generated heat can be suppressed in. The integrated circuit apparatus comprises: a first circuit made of a memory circuit, a second circuit made of an arithmetic circuit, and a control circuit. The first circuit is partitioned into a plurality of circuit blocks according to the distance from the arranged position of the second circuit, and the control circuit controls the partitioned respective circuit blocks separately. | 2014-02-27 |
20140059326 | CALCULATION PROCESSING DEVICE AND CALCULATION PROCESSING DEVICE CONTROLLING METHOD - A calculation-processing-device includes: a decoder unit including, a first-counter to increment a first-count-value and to decrement the-first-count-value, and a second-counter configured to increment a second-count-value and to decrement the second-count-value; a first-instruction-executing-unit to execute an instruction of the first-class; a second-instruction-executing-unit to execute an instruction of the-second class; a first-instruction holding unit including a plurality of first-entries, to input the instruction of the first-class held in one of the plurality of first-entries into the first-instruction-executing-unit; a second-instruction-holding-unit including a plurality of second-entries, to input the instruction of the second-class held in one of the plurality of second-entries into the second-instruction-executing-unit; and first-control-unit to output the second-release-notification, and to change the output timing of the second-release-notification when a predetermined relationship is established between the first-timing and the second-timing, and the register is used by the subsequent instruction of the second-class. | 2014-02-27 |
20140059327 | DETECTING CROSS-TALK ON PROCESSOR LINKS - A first of a plurality of data lanes of a first of a plurality of processor links is determined to have a weakest of base performance measurements for the plurality of data lanes. A switching data pattern is transmitted via a first set of the remainder processor links and a quiet data pattern is transmitted via a second set of the remainder processor links. If performance of the first data lane increases vis-à-vis the corresponding base performance measurement, the first set of remainder processor links is eliminated from the remainder processor links. If performance of the first data lanes decreases vis-à-vis the corresponding base performance measurement, the second set of remainder processor links is eliminated from the remainder processor links. The above operations are repeatedly executed until an aggressor processor link that is determined to decrease performance of the first of the plurality of data lanes is identified. | 2014-02-27 |
20140059328 | MECHANISM FOR PERFORMING SPECULATIVE PREDICATED INSTRUCTIONS - A mechanism for executing speculative predicated instructions may include execution of initiating execution of a vector instruction when one or more operands upon which the vector instruction depends are available for use, even if a predicate vector that the vector instruction also depends is not available. If the predicate vector was not available, the results of the execution of the vector instruction may be temporarily held until the predicate vector becomes available, at which time, a destination vector may be updated with the results. | 2014-02-27 |
20140059329 | ALLOCATION OF COUNTERS FROM A POOL OF COUNTERS TO TRACK MAPPINGS OF LOGICAL REGISTERS TO PHYSICAL REGISTERS FOR MAPPER BASED INSTRUCTION EXECUTIONS - A computer system assigns a particular counter from among a plurality of counters currently in a counter free pool to count a number of mappings of logical registers from among a plurality of logical registers to a particular physical register from among a plurality of physical registers, responsive to an execution of an instruction by a mapper unit mapping at least one logical register from among the plurality of logical registers to the particular physical register, wherein the number of the plurality of counters is less than a number of the plurality of physical registers. The computer system, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool. | 2014-02-27 |
20140059330 | PARSING-ENHANCEMENT FACILITY - An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general registers, wherein a first general register stores an argument address, a second general register stores a function code, a third general register stores length of an argument-character buffer, and the fourth of which contains the address of the function-code data structure. | 2014-02-27 |
20140059331 | BRANCH TARGET BUFFER FOR EMULATION ENVIRONMENTS - Branch instructions are managed in an emulation environment that is executing a program. A plurality of entries is populated in a branch target buffer that resides within an emulated environment in which the program is executing. Each of the entries comprises an instruction address and a target address of a branch instruction of the program. When an indirect branch instruction of the program is encountered a processor analyzes one of the entries in the branch target buffer to determine if the instruction address of the one entry is associated with a target address of the indirect branch instruction. If the instruction address of the one entry is associated with the target address of the indirect branch instruction a branch to the target address of the one entry is performed. | 2014-02-27 |
20140059332 | BRANCH TARGET BUFFER FOR EMULATION ENVIRONMENTS - Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction. | 2014-02-27 |
20140059333 | METHOD, APPARATUS, AND SYSTEM FOR SPECULATIVE ABORT CONTROL MECHANISMS - An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions. | 2014-02-27 |
20140059334 | Autonomic Hotspot Profiling Using Paired Performance Sampling - A processor performance profiler is enabled to for identify specific instructions causing performance issues within a program being executed by a microprocessor through random sampling to find the worst-case offenders of a particular event type such as a cache miss or a branch mis-prediction. Tracking all instructions causing a particular event generates large data logs, creates performance penalties, and makes code analysis more difficult. However, by identifying and tracking the worst offenders within a random sample of events without having to hash all events results in smaller memory requirements for the performance profiler, lower performance impact while profiling, and decreased complexity to analyze the program to identify major performance issues, which, in turn, enables better optimization of the program in shorter developer time. | 2014-02-27 |
20140059335 | INFORMATION PROCESSING APPARATUS AND ACTIVATION METHOD - An information processing apparatus manages activation of a program by a task which is a unit of execution, and executes a task for each sequence in units of process block. The information processing apparatus has a nonvolatile memory which keeps an execution state management table. The execution state of the process block is stored in the execution state management table. The control unit performs a first activation procedure which initializes the execution state management table and, while updating the execution state in the execution state management table, executes the task. When activation by the first activation procedure has failed, the control unit performs activation by a second activation procedure and identifies a suspicious sequence. When activation by the second activation procedure has failed, the control unit performs activation by a third activation procedure and identifies a suspicious task. | 2014-02-27 |
20140059336 | PROBING THE BOOT SEQUENCE OF A COMPUTER SYSTEM - Probes are instrumented into a boot sequence of a computer system to enable probing of the boot sequence. As part of the boot sequence, a value stored in a predetermined storage location within a boot device is read and, if the value indicates that probing of the boot sequence has been enabled, executable code for probing the boot sequence is injected into the boot sequence. Outputs of the probing during the boot process are collected into a buffer and analyzed after the completion of the boot process. | 2014-02-27 |
20140059337 | COMPUTING PERFORMANCE AND POWER MANAGEMENT WITH FIRMWARE PERFORMANCE DATA STRUCTURE - In some embodiments, a PPM interface for a computing platform may he provided with functionality to facilitate, to an OS through the PPM interface, firmware performance data. | 2014-02-27 |
20140059338 | METHOD FOR SECURE BOOTING OF A PRINTER CONTROLLER - A printing system is provided with a secure boot program and a detachable memory device with an installable secure boot program. Upon switching on the printer controller, the secure boot program will check if a detachable memory device containing the secure boot program is plugged in. If this is the case, the controller will boot from the detachable memory device, otherwise the controller will invoke the printer control program to bring the printer in its normal operational mode. | 2014-02-27 |
20140059339 | APPARATUS AND METHOD FOR DOWNLOADING CONTENTS USING AN INTERIOR MASS STORAGE IN A PORTABLE TERMINAL - A method and apparatus for downloading content to a large-capacity internal memory in a portable terminal are provided. The method includes performing a booting process of the portable terminal at the occurrence of a booting event, examining whether a Universal Serial Bus (USB) port is enabled during the booting process, if the USB port is enabled, receiving data through the USB port before driver loading, and storing the received data into the large-capacity internal memory and performing the booting process. | 2014-02-27 |
20140059340 | PERIMETER ENCRYPTION METHOD AND SYSTEM - A method and system for consistent format preserving encryption (C-FPE) are provided to protect data while the data is in a domain while allowing encrypted data to be treated inside the domain as if it were the unencrypted data. The method includes inserting a coupling into a data flow at a perimeter of the domain, and translating a data element from an unprotected data element to a protected data element using the coupling such that the data element is a protected data element within the domain. | 2014-02-27 |
20140059341 | CREATING AND ACCESSING ENCRYPTED WEB BASED CONTENT IN HYBRID APPLICATIONS - In a method and program product for decrypting web based content in a hybrid mobile application, a computer receives a request to access encrypted content. The computer determines that a secret key is not cached on the computer. The computer decrypts an encrypted secret key to expose the secret key. The computer caches the secret key on the computer and decrypts the encrypted content. | 2014-02-27 |
20140059342 | System and Method of Accessing Keys for Secure Messaging - Methods and systems for handling on an electronic device a secure message to be sent to a recipient. Data is accessed about a security key associated with the recipient. The received data is used to perform a validity check related to sending a secure message to the recipient. The validity check may uncover an issue that exists with sending a secure message to the recipient. A reason is determined for the validity check issue and is provided to the mobile device's user. | 2014-02-27 |
20140059343 | ALGORITHM-BASED ANONYMOUS CUSTOMER REFERENCES - A system and methodology that facilitates management and utilization of domain-specific anonymous customer references (ACRs) for protecting subscriber privacy across different domains is disclosed herein. In one aspect, on receiving user authorization, an ACR services (ACRS) component can generate an ACR that is to be inserted in a communication or message transmitted from a user equipment to an untrusted entity. The ACR can be generated based on address data associated with the untrusted entity and/or a unique subscriber identifier associated with the user equipment. As an example, the ACR creation component can generate the ACR based on a cryptographic hash, a static encryption key, and/or a dynamic encryption key. If the ACR is forwarded to a trusted entity, the trusted entity can calculate the unique subscriber identifier based on evaluating the ACR and/or exchange the ACR for the unique subscriber identifier via a secure communication with the ACRS component. | 2014-02-27 |
20140059344 | FILE PROTECTION USING SESSION-BASED DIGITAL RIGHTS MANAGEMENT - Systems and methods are provided for encrypting electronic files during a transfer to a low-security storage location is provided. In one embodiment, a method comprises receiving a file copy request for a file stored on a source storage system to be copied to a destination storage system; determining a desired file security level of the file based on a desired security level for the file when the file is accessed; determining a destination security level of the destination storage system; comparing the file security level and the destination security level; encrypting the file to create an encrypted file when the destination security level is less than the file security level prior to copying the file; and copying at least one of the file and the encrypted file to the destination storage system as a function of the comparison of the file security level and the destination security level. | 2014-02-27 |
20140059345 | OBLIVIOUS TRANSFER WITH HIDDEN ACCESS CONTROL LISTS - A method, apparatus, and a computer readable storage medium having computer readable instructions to carry out the steps of the method for anonymous access to a database. Each record of the database has different access control permissions (e.g. attributes, roles, or rights). The method allows users to access the database record while the database does not learn who queries a record. The database does not know which record is being queried: (i) the access control list of that record or (ii) whether a user's attempt to access a record had been successful. The user can only obtain a single record per query and only those records for which he has the correct permissions. The user does not learn any other information about the database structure and the access control lists other than whether he was granted access to the queried record, and if so, the content of the record. | 2014-02-27 |
20140059346 | METHOD OF LAWFUL INTERCEPTION FOR UMTS - A method of providing, to a user equipment, first information for generating a cipher key used for encryption, and for providing, to an authorized intercept device, second information for generating the cipher key, the method including determining a generator function that, based on an input state value, outputs a next cipher key and a next state value, determining an initial state value for the generator function, providing, to the authorized intercept device, the generator function and the initial state value as the second information, generating the cipher key and a state value based on the function generator and the input state value, generating a pseudo-random value based on the cipher key, and transmitting, to the user equipment, the pseudo-random value as the first information, wherein the user equipment generates the cipher key based on the pseudo-random value. | 2014-02-27 |
20140059347 | SYSTEMS AND METHODS FOR RESTRICTING ACCESS TO NETWORK RESOURCES VIA IN-LOCATION ACCESS POINT PROTOCOL - Methods and systems described herein relate to enhancing security on a mobile device. Systems and methods for mobile device security include restricting access to network resources via an in-location access point device, based on whether the mobile device is in proximity of the in-location access point device. | 2014-02-27 |
20140059348 | SYSTEM AND METHODS FOR ONLINE AUTHENTICATION - A method of establishing a communication channel between a network client and a computer server over a network is described. The network client may be configured to communicate with the computer server over the network and to communicate with a token manager. The token manager may be configured with a parent digital certificate that is associated with the token manager. The token manager or network client generates a credential from the parent digital certificate, and transmits the credential to the computer server. The credential may be associated with the computer server. The network client may establish the communications channel with the computer server in accordance with an outcome of a determination of validity of the credential by, the computer server. | 2014-02-27 |
20140059349 | METHOD FOR PROTECTING A RECORDED MULTIMEDIA CONTENT - A method for protecting recorded multimedia content and enabling the recorded multimedia content to be shared between recorders and readers of multimedia content connected to one another via a wide area information transmission network. | 2014-02-27 |
20140059350 | UNAUTHORIZED CONNECTION DETECTING DEVICE, UNAUTHORIZED CONNECTION DETECTING SYSTEM, AND UNAUTHORIZED CONNECTION DETECTING METHOD - An unauthorized connection detecting device, which detects whether or not a power storage device is an unauthorized power storage device, includes: a communications unit receiving first charge/discharge information in which first identification information and first connection information are associated each other, the first identification information identifying an encryption key of the power storage device used for mutual authentication between a charge/discharge device and the power storage device, and the first connection information being on the power storage device and obtained when the power storage device is connected to the charge/discharge device; and an unauthorization detecting unit detecting whether or not the power storage device is the unauthorized power storage device, by determining, using the first identification information and the first connection information, whether or not two or more power storage devices associated with a single first identification information item are present. | 2014-02-27 |
20140059351 | METHOD AND DEVICE FOR CONNECTING TO A WIRELESS NETWORK USING A VISUAL CODE - A method for connecting a wireless communication device to a wireless network using a visual code includes reading the visual code that includes an access token that is associated with a wireless access point of the wireless network. The method further includes establishing a secure channel with the wireless access point, and sending the access token to the wireless access point over the secure channel, wherein the access token is used for network access control. Moreover, the method includes receiving security key information from the wireless access point over the secure channel, wherein the security key information is different than the access token. Additionally, the method includes establishing a secure link with the wireless access point using the security key information. | 2014-02-27 |
20140059352 | KEY MANAGEMENT SYSTEM, KEY MANAGEMENT METHOD, AND COMMUNICATION DEVICE - In a key management system, a RFID tag decrypts a first key encrypted by a master key and stores the decrypted first key to a service key storage region, then decrypts a second key encrypted by the first key in a third party server, then, encrypts the decrypted second key by the master key and transmits the second key encrypted by the master key to an application of a mobile information terminal, and then decrypts the encrypted second key returned from the application and stores the decrypted second key to the service key storage region. | 2014-02-27 |
20140059353 | FACILITATING ELECTRONIC SIGNATURES BASED ON PHYSICAL PROXIMITY OF DEVICES - Systems and methods for requesting transmission of a document from a sender device to a signer device, for purposes of obtaining an e-signature from the signer device, are disclosed. In some example embodiments, the systems and methods establish and/or determine a physical proximity between a signer device and a sender device, such as via a handshake between the devices, and a document to be signed is provided to the signer device in response to the established physical proximity. | 2014-02-27 |
20140059354 | Scalable Session Management - Scalable session management is achieved by generating a cookie that includes an encrypted session key and encrypted cookie data. The cookie data is encrypted using the session key. The session key is then signed and encrypted using one or more public/private key pairs. The encrypted session key can be decrypted and verified using the same private/public key pair(s). Once verified, the decrypted session key can then be used to decrypt and verify the encrypted cookie data. A first server having the private/public key pair(s) may generate the cookie using a randomly generated session key. A second server having the same private/public key pair(s) may decrypt and verify the cookie even if the session key is not initially installed on the second server. A session key cache may be used to provide session key lookup to save public/private key operations on the servers. | 2014-02-27 |
20140059355 | Data Protection Compliant Deletion of Personally Identifiable Information - The disclosure generally describes computer-implemented methods, software, and systems for modeling and deploying decision services. One computer-implemented method includes encrypting, by operation of a computer, personally-identifiable information (PII) data using a first cryptographic key, wherein the PII data is associated with non-encrypted associated data, encrypting the encrypted first cryptographic key with a second cryptographic key, determining that the occurrence of a PII data disassociation event associated with the second cryptographic key has occurred, and rendering the PII data inaccessible by disassociating the second cryptographic key from the encrypted first cryptographic key. | 2014-02-27 |
20140059356 | TECHNIQUE FOR RECONFIGURABLE DATA STORAGE MEDIA ENCRYPTION - A technique for managing encryption keys includes encrypting the contents of a piece of media with a first encryption key, encrypting the first encryption key with a second encryption key, and storing the encrypted first encryption key on or in connection with the piece of media. Encrypted data may be recovered by receiving the encrypted first encryption key from the piece of media, receiving the second encryption key (e.g., from a user to whom the key is assigned), recovering the first encryption key using the second encryption key, and decrypting the data from the piece of media using the first encryption key. | 2014-02-27 |
20140059357 | System and Method for Providing Secure Inter-Process Communications - A user device provides a mechanism for securing messages communicated between trusted processes along an established Inter-Process Communication (IPC) channel. The mechanism permits the trusted processes to determine which messages to protect, and executes independently of platform-dependent IPC mechanisms. | 2014-02-27 |
20140059358 | REVOKEABLE MSR PASSWORD PROTECTION - A microprocessor includes a model specific register (MSR) having an address, fuses manufactured with a first predetermined value, and a control register. The microprocessor initially loads the first predetermined value from fuses into the control register. The microprocessor also receives a second predetermined value into the control register from system software of a computer system comprising the microprocessor subsequent to initially loading the first predetermined value into the control register. The microprocessor prohibits access to the MSR by an instruction that provides a first password generated by encrypting a function of the first predetermined value and the MSR address with a secret key manufactured into the first instance of the microprocessor and enables access to the MSR by an instruction that provides a second password generated by encrypting the function of the second predetermined value and the MSR address with the secret key. | 2014-02-27 |
20140059359 | POWER MANAGEMENT - The present disclosure includes methods and apparatuses for power management. One method includes transferring data between a memory and a controller via an input/output (I/O) bus, and adjusting an amount of power consumed in association with transferring the data by throttling the I/O bus. | 2014-02-27 |
20140059360 | POWER SUPPLIES MANAGEMENT IN AN ANALYTE DEVICE HAVING PRIMARY AND SECONDARY BATTERIES - Described herein are systems and methods (including system and method) to allow users of analyte monitors to continue to perform analyte measurement tests by using a secondary battery when the main battery is exhausted. By using applicants' technique, the monitor can be used for twice as long as compared to a monitor that only relies on a single battery as the only power supply. Moreover, applicants have devised systems and methods to indicate to the user which of the primary and secondary batteries should be replaced without disrupting the utilization of the monitor. | 2014-02-27 |
20140059361 | INFORMATION PROCESSING SYSTEM, EXTERNAL APPARATUS, AND METHOD FOR SUPPLYING POWER FROM HOST APPARATUS TO EXTERNAL APPARATUS - An information processing apparatus including a first external interface configured to be connected to a host apparatus, a first power supply section configured to be connected to an external power supply and a second power supply section configured to receive power via the first external interface. The information processing apparatus configured to detect whether power is received at the first power supply section; and declare, to the host apparatus, a maximum current value equal to or smaller than a prescribed maximum current value defined by the host apparatus when the information processing apparatus is connected to the host apparatus via the first external interface and it is detected that power is received at the first power supply section. | 2014-02-27 |
20140059362 | APPARATUS, METHOD, AND SYSTEM FOR IMPROVED POWER DELIVERY PERFORMANCE WITH A DYNAMIC VOLTAGE PULSE SCHEME - An apparatus and method is described herein for providing a dynamic pulse scheme for a voltage supply. A load (current) demand event of a processor is either predicted and/or detected. In response to the current demand event, such as a change in the current demand; a temporary, transient voltage pulse is generated by a voltage supply to compensate for the current transient demand. As result, dynamic voltage supply pulses generated based on the load current or the prediction of the load current demand increases performance, decreases power consumption, and saves expensive addition of compensation components, such as capacitors to a processor package. | 2014-02-27 |
20140059363 | Electronic device having USB interface and method for starting USB communication with such device - The present disclosure provides an electronic device having a USB interface and a method for starting USB communication with such an electronic device, so as to solve the problem of a risk of damaging a mobile phone terminal device arising from sharing of an interface by a charger and a USB communication cable in the related art. In the electronic device, a port GPIO of a baseband chip is connected to a pin USB_VBUS of a USB interface of the baseband chip; based on this circuit, a power management chip detects a state of plugging-in-or-pulling-out of the charger and generates a corresponding interrupt request; and the baseband chip controls the GPIO to output a corresponding level according to the interrupt request. By connecting the port GPIO and the pin USB_VBUS and controlling an output level of GPIO with a software, a high level or a low level (as a triggering signal for starting or terminating the USB communication) is input to the pin USB_VBUS, thus avoiding damage to the device. | 2014-02-27 |
20140059364 | APPARATUS FOR POWERING A DEVICE - An apparatus includes a processor and a device. The processor generates an output signal and a control signal. The device consumes power while operating in first and second states. The device consumes less power while in the first state than while in the second state. The processor: accounts for a transition time for the device to transition among a powered off state, the first state, and the second state; and generates the control signal based on the transition time. The device: in response to the control signal, transitions to the second state at a speed of periodicity of a periodic signal of the processor; subsequent to the transitioning to the second state, performs a function based on the output signal; and subsequent to performing the function, transitions from the second state to either the first state or the powered off state. | 2014-02-27 |
20140059365 | ULTRA LOW POWER APPARATUS AND METHOD TO WAKE UP A MAIN PROCESSOR - An apparatus and method for waking up a main processor (MP) in a low power or ultra-low power device preferably includes the MP, and a sub-processor (SP) that utilizes less power than the MP to monitor ambient conditions than the MP, and may be internalized in the MP. The MP and SP can remain in a sleep mode while an interrupt sensor monitors for changes in the ambient environment. A sensor is preferably an interrupt-type sensor, as opposed to polling-type sensors conventionally used to detect ambient changes. The MP and SP may remain in sleep mode, as a low-power or an ultra-low power interrupt sensor operates with the SP being in sleep mode, and awakens the SP via an interrupt indicating a detected change. The SP then wakes the MP after comparing data from the interrupt sensor with values in storage or with another sensor. | 2014-02-27 |
20140059366 | ELECTRONIC DEVICE AND CONTROL METHOD - An electronic device comprises a wireless unit, a control unit starting up the wireless unit at a predetermined startup time and a storage unit, wherein the wireless unit queries a wireless base station about a message and, when the message addressed to the electronic device exists, receives the message from the wireless base station, the control unit, when the message received by the wireless unit is an erase message, executes a process of erasing data stored in the storage unit, and the control unit, whereas when the message received by the wireless unit is not the erase message or when there is not the message addressed to the electronic device, stops the wireless unit. | 2014-02-27 |
20140059367 | SAVING POWER BY MANAGING THE STATE OF INACTIVE COMPUTING DEVICES - A system method and computer program product for managing readiness states of a plurality of computing devices. In response to a request, a computer system operates to either: provide one or more computing devices from an inactive pool to an active pool, or accept one or more active computing devices into the inactive pool. An Inactive Pool Manager proactively manages the inactive states of each computing device by: determining the desired number (and identities) of computing devices to be placed in each inactive state of readiness by solving a constraint optimization problem that describes a user-specified trade-off between expected readiness (estimated time to be able to activate computing devices when they are needed next) and conserving energy; generating a plan for changing the current set of inactive states to the desired set; and, executing the plan. Multiple alternative ways of quantifying the desired responsiveness to surges in demand are provided. | 2014-02-27 |
20140059368 | COMPUTING PLATFORM INTERFACE WITH MEMORY MANAGEMENT - In some embodiments, a PPM interface may be provided with functionality to facilitate an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface. | 2014-02-27 |
20140059369 | EFFICIENT SERVICE ADVERTISEMENT AND DISCOVERY IN A PEER-TO-PEER NETWORKING ENVIRONMENT - A local device broadcasts a service advertisement in a wireless network, where the service advertisement includes one or more service identifiers (IDs) identifying one or more services being advertised and an availability schedule of the local device. Optionally, the local device reduces power to at least a portion of the local device and wakes up at a time according to the availability schedule. The local device listens in the wireless network according to the availability schedule of the local device. In response to a service request received from a remote device during the availability window, the local device transmits a service response to the remote device. The service request includes one or more service IDs identifying one or more services being inquired by the remote device and the service response includes detailed information associated with one or more services identified by the one or more service IDs. | 2014-02-27 |
20140059370 | WAKE-ON-LOCAL-AREA-NETWORK OPERATIONS IN A MODULAR CHASSIS USING A VIRTUALIZED INPUT-OUTPUT-VIRTUALIZATION ENVIRONMENT - A method for waking an information handling system includes receiving in a chassis a plurality of modular information handling systems and a plurality of modular information handling resources, routing access of one of the modular information handling resources to one or more of the plurality of modular information handling systems, monitoring a plurality of power management event lines, determining a wake message received at one of the modular information handling resources, determining which of the plurality of modular information handling systems is associated with the received wake message, forwarding a wake signal to the determined modular information handling system, and powering on the determined information handling system. The modular information handling resource is configured to receive a wake message. Each line is coupled one of the modular information handling resources. | 2014-02-27 |
20140059371 | POWER MANAGEMENT OF MULTIPLE COMPUTE UNITS SHARING A CACHE - We report methods, integrated circuit devices, and fabrication processes relating to power management transitions of multiple compute units sharing a cache. One method includes indicating that a first compute unit of a plurality of compute units of an integrated circuit device is attempting to enter a low power state, determining if the first compute unit is the only compute unit of the plurality in a normal power state, and in response to determining the first compute unit is the only compute unit in the normal power state: saving a state of a shared cache unit of the integrated circuit device, flushing at least a portion of a cache of the shared cache unit, repeating the flushing until either a second compute unit exits the low power state or the cache is completely flushed, and permitting the first compute unit to enter the low power state. | 2014-02-27 |
20140059372 | METHOD AND APPARATUS TO SAVE POWER UPON RESUME IN MULTI-CORE SYSTEM - A method is provided for resuming one or more cores of a multi-core processor that is part of an electronic device, the method comprising: grouping wakeup sources into a plurality of computing domains; receiving an interrupt associated with a wakeup source; identifying a first computing domain from the plurality that the wakeup source is part of; mapping the first computing domain to a first indication of one or more states of a first core of the processor; configuring the first core to enter the one or more states that are indicated by the first indication; and resuming the first core after the first core is configured. | 2014-02-27 |
20140059373 | Method In A Controller Controlling A Dynamic Compensator, A Controller, Computer Programs And Computer Program Products - A method in a controller controlling a dynamic power compensator. The dynamic power compensator is arranged to provide active and reactive power to an electric power system, the dynamic power compensator including a battery energy storage. The method includes the steps of: monitoring a state of charge of the battery energy storage; detecting a voltage level in the electric power system requiring increased delivery of the reactive power to the electric power system; and controlling the battery energy storage in dependence on the monitored state of charge and detected voltage level. The invention also relates to a controller, computer programs and computer program products. | 2014-02-27 |
20140059374 | METHOD AND APPARATUS FOR SETTING A FREQUENCY OF A CLOCK SIGNAL FOR A BUS BASED ON A NUMBER OF REQUESTS ASSERTED TO TRANSFER DATA ON THE BUS - An integrated circuit includes a generator. The generator, based on a summation signal, generates a clock signal having a frequency. Multiple devices generate respective requests. Each of the requests requests transfer of data on a bus. Each of the devices is configured to, based on the frequency of the clock signal, transfer the data for the corresponding request on the bus. A summer receives the requests and based on a number of the requests being in an asserted state during a first period of time, generates the summation signal. A first module, based on the summation signal, increases a second period of time that a first request is in an asserted state. The second period of time is increased to include or overlap the first period of time. The summer, as a result of the increase, generates the summation signal further based on the first request. | 2014-02-27 |
20140059375 | RECOVERY SYSTEM AND METHOD FOR RECREATING A STATE OF A DATACENTER - Embodiments include a recovery system, a computer-readable storage medium, and a method of recreating a state of a datacenter. The embodiments include a plurality of program modules that is executable by a processor to gather metadata from a first datacenter that includes at least one virtual machine (VM), wherein the metadata includes data representative of a virtual infrastructure of the first datacenter. The program modules are also executable by the processor to recreate a state of the first datacenter within a second datacenter using the metadata upon a determination that a failure occurred within the first datacenter, and to recreate the VM within the second datacenter. | 2014-02-27 |
20140059376 | RECOVERING A VOLUME TABLE AND DATA SETS FROM A CORRUPTED VOLUME - Provided are a computer program product, system, and method for recovering a volume table and data sets from a corrupted volume. Data corruption is detected in a volume having data sets. A volume table having information on the data sets allocated in the volume is diagnosed. A backup volume table comprising a most recent valid backup of the volume table is accessed from a backup of the volume in response to determining that the diagnosed volume table is not valid. Content from the backup volume table is processed to bring to a current state in a recovery volume table for a recovery volume. The data sets in the volume are processed to determine whether they are valid. The valid data sets are moved to the recovery volume. A data recovery operation is initiated for the data sets determined not to be valid. | 2014-02-27 |
20140059377 | DYNAMIC Y-BUFFER SIZE ADJUSTMENT FOR RETAINED SECTOR REPROCESSING - Aspects of the disclosure pertain to a system and method for providing dynamic y-buffer size adjustment for retained sector reprocessing (RSR). The system and method implement dynamic y-buffer size adjustment for RSR for promoting improved Sector Failure Rate (SFR) performance of the system. The system is a read channel system. | 2014-02-27 |
20140059378 | METHOD OF SYSTEM RECOVERY OF CLIENT DEVICE, WIRELESS CONNECTION DEVICE AND COMPUTER PROGRAM - The present disclosure provides a technique of easily enabling recovering of a client device via wireless communication. In one embodiment, the configuration includes a wireless connection device that establishes wireless communication with the client device; obtains restoration data that is stored in advance in a specified storage; and sends the obtained restoration data via the wireless communication to the client device. | 2014-02-27 |
20140059379 | PROACTIVE RESOURCE RESERVATION FOR PROTECTING VIRTUAL MACHINES - A system for proactive resource reservation for protecting virtual machines. The system includes a cluster of hosts, wherein the cluster of hosts includes a master host, a first slave host, and one or more other slave hosts, and wherein the first slave host executes one or more virtual machines thereon. The first slave host is configured to identify a failure that impacts an ability of the one or more virtual machines to provide service, and calculate a list of impacted virtual machines. The master host is configured to receive a request to reserve resources on another host in the cluster of hosts to enable the impacted one or more virtual machines to failover, calculate a resource capacity among the cluster of hosts, determine whether the calculated resource capacity is sufficient to reserve the resources, and send an indication as to whether the resources are reserved. | 2014-02-27 |
20140059380 | PROTECTING PAIRED VIRTUAL MACHINES - A system for monitoring virtual machines includes a master host and a slave host. The slave host includes a primary virtual machine and a secondary virtual machine. The slave host is configured to identify a failure that impacts an ability of at least one of the primary virtual machine and the secondary virtual machine to provide service. If the failure is a Permanent Device Loss failure, the slave host is configured to terminate each impacted virtual machine. If the failure is an All Paths Down failure, the master host is configured to apply one of the following: a first remedy if the primary virtual machine is impacted and the secondary virtual machine is not impacted; a second remedy if the secondary virtual machine is impacted and the primary virtual machine is not impacted; or a third remedy if both the primary virtual machine and the secondary virtual machine are impacted. | 2014-02-27 |
20140059381 | METHODS FOR TESTING ODATA SERVICES - The present disclosure describes computer implemented methods, computer systems, and computer readable mediums for recursively testing an OData service. One method may include extracting resource identifiers from an initial service document, and for each of the resource identifiers, retrieving a respective response document from the OData service. The method may further include applying a test function to each of the resource identifiers and respective response documents and recording a result of the test function for each of the resource identifiers. The method may further include recursively extracting new resource identifiers from the response documents and retrieving respective new response documents for each new resource identifier from the OData service until no additional resource identifiers are extracted from the new response documents. | 2014-02-27 |
20140059382 | REAL-TIME RULE ENGINE FOR ADAPTIVE TESTING OF INTEGRATED CIRCUITS - A method of testing a device is disclosed. Test data is obtained for a device testing program that tests the device. An adaptation command for testing the device is determined at an adaptive testing engine using obtained test data. The adaptation command is sent from the adaptive testing engine to a tool control application. The tool control application uses the adaptation command to control an operation related to the testing of the device. | 2014-02-27 |
20140059383 | Effective Validation of Execution Units Within a Processor - A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated. | 2014-02-27 |
20140059384 | TEST AND MEASUREMENT INSTRUMENT WITH AUTO-SYNC FOR BIT-ERROR DETECTION - Embodiments of the invention include methods, apparatuses, and systems for automatically identifying a synchronization sub-pattern associated with a test pattern. A test and measurement instrument is triggered in response to a first instance of a trigger pattern in a data stream. A trigger-to-trigger counter begins counting at the time of the first trigger event. The test and measurement instrument is again triggered in response to a second instance of the trigger pattern in the data stream. The count is ended at this time. The count is then compared to a predefined length of the test pattern, and if equal, it is automatically determined that the trigger pattern is the unique synchronization sub-pattern associated with the test pattern. | 2014-02-27 |
20140059385 | COMPLIANCE TESTING ENGINE FOR INTEGRATED COMPUTING SYSTEM - A technique tests whether an integrated computing system having server, network and storage components complies with a configuration benchmark expressed as rules in first markup-language statements such as XML. The rules are parsed to obtain test definition identifiers identifying test definitions in a second set of markup-language statements, each test definition including a test value and an attribute identifier of system component attribute. A management database is organized as an integrated object model of all system components. An interpreter invoked with the test definition identifier from each rule process each test definition to (a) access the management database using the attribute identifier obtain the actual value for the corresponding attribute, and (b) compare the actual value to the test value of the test definition to generate a comparison result value that can be stored or communicated as a compliance indicator to a human or machine user. | 2014-02-27 |
20140059386 | REAL-TIME RULE ENGINE FOR ADAPTIVE TESTING OF INTEGRATED CIRCUITS - A method of testing a device is disclosed. Test data is obtained for a device testing program that tests the device. An adaptation command for testing the device is determined at an adaptive testing engine using obtained test data. The adaptation command is sent from the adaptive testing engine to a tool control application. The tool control application uses the adaptation command to control an operation related to the testing of the device. | 2014-02-27 |
20140059387 | MANAGEMENT OF TEST ARTIFACTS USING CASCADING SNAPSHOT MECHANISM - Described are an apparatus and method for managing test artifacts. A test plan is selected for a product having a plurality of test artifacts comprising one selected from a group consisting of an execution record and a product requirement. One of the test artifacts is selected for a snapshot at a current time. The snapshot includes a storage record that includes information associated with the selected test artifact and its relationship with other test artifacts at the current time. The snapshot of the selected test artifact is acquired. A current state of the selected test artifact is stored as an element of the snapshot. A current state of relationships of the selected test artifact to the other test artifacts is stored. A current state of the other test artifacts having a relationship with the selected test artifact is stored. A type of snapshot is determined, comprising cascading through artifacts of the test plan to capture all information and relationships associated with the test artifact, its child artifacts, and the group consisting of the execution record and the product requirement. | 2014-02-27 |
20140059388 | DIAGNOSTIC AND PERFORMANCE DATA COLLECTION - Technologies are generally described for systems and methods effective to provide an automatic diagnostic data collection system to facilitate diagnosis of technical problems associated with computing device and to facilitate the analysis of marketing and performance metrics of the computing devices. When a user of a computing device calls or accesses a help desk and/or call center, data can be automatically collected from the computing device to allow the help desk operator quickly and accurately diagnose the problem. If no error is specified, general diagnosis data including results of a trace route between a server and the computing device can be collected. If an error is specified, error logs associated with the error can also be collected. The data can be filtered based on a diagnosis request and transferred to the relevant technical support system. | 2014-02-27 |
20140059389 | COMPUTER AND MEMORY INSPECTION METHOD - In a memory inspection in a computer installing a x86 CPU, system software related to low-frequent processing is prevented from going down, and the suppression of performance degradation and the avoidance of a reduction in memory capacity by the memory inspection is realized. The computer having a processor, a memory, and an I/O device. The memory stores a system software realizing a system control unit, and an inspection program realizing an inspection unit. The processor has a memory fault notifying unit notifying the system control unit of a fault address. The system control unit includes an adjustment unit that determines whether the inspection program needs to be executed, or not, based on the type of event occurring, plural event processing units processing the event by using different storage areas of the memory, a fault recording unit recording the memory fault, and an event processing unit selector. | 2014-02-27 |
20140059390 | USE OF SERVICE PROCESSOR TO RETRIEVE HARDWARE INFORMATION - Various techniques and hardware are described for retrieving information in a processing system. In one embodiment, a method is provided for retrieving information in a processing system that includes a central processing unit and a service processor. Here, the service processor retrieves central processing unit information from the central processing unit and resets the processing system after the retrieval of the central processing unit information. | 2014-02-27 |
20140059391 | SYSTEM AND METHOD FOR CAPTURING LOGGING INFORMATION - A method, computer program product, and computer system for receiving, by a processor, an initiation indication that a test is initiating on a computing device. A logging process is activated to record to a log one or more log messages generated as a result of the test in response to receiving the initiation indication that the test is initiating. A completion indication is received that the test is complete. The logging process is deactivated to stop recording to the log in response to receiving the completion indication that the test is complete. The one or more log messages are associated with the test in response to receiving the completion indication that the test is complete. | 2014-02-27 |
20140059392 | PROTECTING VIRTUAL MACHINES AGAINST STORAGE CONNECTIVITY FAILURES - A system for monitoring a virtual machine executed on a host. The system includes a processor that receives an indication that a failure caused a storage device to be inaccessible to the virtual machine, the inaccessible storage device impacting an ability of the virtual machine to provide service, and applies a remedy to restore access to the storage device based on a type of the failure. | 2014-02-27 |
20140059393 | MONITORING APPARATUS AND SYSTEM - A monitoring system for response to incidents sensed by at least one sensor of an individual signal unit; said response comprising in a first instance, transmission to a central control facility by a said individual signal unit, of at least a unique identifying code for that individual signal unit, over a communication network; said response comprising in a second instance, transmission of data from said central control facility to one or more recipients nominated by a registered owner of said individual signal unit; and wherein registration of a said individual signal unit and configuration of sensing and of said response is via a web-based interface. | 2014-02-27 |
20140059394 | TICKET CONSOLIDATION FOR MULTI-TIERED APPLICATIONS - Consolidating problem tickets for a multi-tiered application may comprise identifying a plurality of correlated virtual machines that are running one or more application components of the multi-tiered application. Problem reports may be identified that are generated by one or more of the plurality of correlated virtual machines and caused by a failure of a same single component of the multi-tiered application. The identified problem reports may be consolidated into a single ticket and placed into a ticket handling system. | 2014-02-27 |
20140059395 | TICKET CONSOLIDATION FOR MULTI-TIERED APPLICATIONS - Consolidating problem tickets for a multi-tiered application may comprise identifying a plurality of correlated virtual machines that are running one or more application components of the multi-tiered application. Problem reports may be identified that are generated by one or more of the plurality of correlated virtual machines and caused by a failure of a same single component of the multi-tiered application. The identified problem reports may be consolidated into a single ticket and placed into a ticket handling system. | 2014-02-27 |
20140059396 | MEMORY SYSTEM HAVING NAND-TYPE FLASH MEMORY AND MEMORY CONTROLLER USED IN THE SYSTEM - According to one embodiment, a memory system includes a NAND-type flash memory and a memory controller. A comparison module of the memory controller compares a first threshold voltage distribution of a first memory area with a second threshold voltage distribution of the first memory area acquired earlier than the first threshold voltage distribution, if an error is detected in data read from the first memory area. An error factor determination module of the memory controller determines a cause of the error based on the comparison result, and inhibits a data move operation of moving data of the first memory area to the second memory area based on the determination result. | 2014-02-27 |
20140059397 | SYSTEM AND METHOD FOR TESTING RADIO FREQUENCY DEVICE UNDER TEST CAPABLE OF COMMUNICATING USING MULTIPLE RADIO ACCESS TECHNOLOGIES - System and method for testing a radio frequency (RF) device under test (DUT) communicating using multiple radio access technologies (RATs). Single data signal sequences having characteristics of multiple RATs as prescribed by signal standards are exchanged between a tester and DUT. The tester and DUT process received signal sequences substantially in parallel with their reception. A pattern of contemporaneous signal sequence reception and processing continues for as many RATs as the DUT is capable of supporting. | 2014-02-27 |
20140059398 | ADAPTIVE ERROR CORRECTION FOR NON-VOLATILE MEMORIES - Methods and systems are disclosed for adaptive error correction for non-volatile memories that dynamically adjust sense amplifier read detection windows. Memory control circuitry uses error correction code (ECC) routines to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry then dynamically adjusts sense amplifier read detection windows to allow for correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously suffered bit failures. The disclosed methods and systems can also be used with respect to memories that are not non-volatile memories. | 2014-02-27 |
20140059399 | TEST DESIGN OPTIMIZER FOR CONFIGURABLE SCAN ARCHITECTURES - Roughly described, a scan-based test architecture is optimized in dependence upon the circuit design under consideration. In one embodiment, a plurality of candidate test designs are developed. For each, a plurality of test vectors are generated in dependence upon the circuit design and the candidate test design, preferably using the same ATPG algorithm that will be used downstream to generate the final test vectors for the production integrated circuit device. A test protocol quality measure such as fault coverage is determined for each of the candidate test designs, and one of the candidate test designs is selected for implementation in an integrated circuit device in dependence upon a comparison of such test protocol quality measures. Preferably, only a sampling of the full set of test vectors that ATPG could generate, is used to determine the number of potential faults that would be found by each particular candidate test design. | 2014-02-27 |
20140059400 | Hybrid Automatic Repeat-Request Combination for Wireless Transmissions - In one embodiment, a method for data communication may include receiving a first set of soft bit values in a Hybrid Automatic Repeat-Request (HARQ) buffer using a first bit width. The method may also include soft combining the first set of soft bit values with a second set of soft bit values to obtain a set of combined soft bit values. The method may also include transforming the set of combined soft bit values from the first bit width to a decoder input bit width to obtain a set of transformed soft bit values. | 2014-02-27 |
20140059401 | HARD-DECISION DECODING METHOD AND LOW-DENSITY PARITY-CHECK DECODER USING SAME - A hard-decision decoding method includes performing operations necessary for first updating of a check node while loading data, which is input to a decoder, to an input buffer; first updating the check node by using a result of the performing of the operations after storing data, corresponding to one codeword, to the input buffer; and performing low-density parity check (LDPC) decoding by using a result of the first updating of the check node. | 2014-02-27 |
20140059402 | METHOD AND APPARATUS FOR CONTROLLING THE DECODING OF CODEWORDS RECEIVED BY A LINEAR BLOCK CODE PIPELINED DECODER FROM AN INPUT BUFFER - A computer implemented method of controlling the decoding of codewords received by a linear block code pipelined decoder from an input buffer, the pipelined decoder comprising at least two decoding stages. The method comprises iteratively: loading the decoding stages of the pipelined decoder, executing a decoding step, determining the number of residual errors in the codewords and outputting error free codewords. The method allows the different decoding stages to be loaded with any codeword coming from the buffer or from any decoding stage of the decoder. Accordingly, the occupation rate of the pipeline is improved. | 2014-02-27 |
20140059403 | PARAMETER ESTIMATION USING PARTIAL ECC DECODING - In some embodiments, a method includes accepting a code word of a composite Error Correction Code (ECC), which was produced by encoding data with multiple component ECCs, and which was received with one or more reception parameters. One or more of the component ECCs are decoded, but without fully decoding the code word. The one or more reception parameters are estimated based on the decoded component ECCs. In other embodiments, a method includes accepting a code word of an ECC, which encodes data and which was received with one or more reception parameters. An Error Locator Polynomial (ELP), having one or more roots that indicate respective locations of one or more errors in the code word, is derived from the accepted code word. The one or more reception parameters are estimated based on the ELP. | 2014-02-27 |
20140059404 | MEMORY CONTROL DEVICE, MEMORY DEVICE, INFORMATION PROCESSING SYSTEM AND MEMORY CONTROL METHOD - There is provided a memory control device, including a request determining unit that determines a type of a request, and a control unit that writes read data read from a memory cell array in the memory cell array in units of predetermined pages of the memory cell array when the request is a refresh request, and divides the page of write data into units of groups and writes the page of the write data in the memory cell array over twice or more when the request is a write request. | 2014-02-27 |
20140059405 | SOLID-STATE DRIVE RETENTION MONITOR USING REFERENCE BLOCKS - A solid-state storage retention monitor determines whether user data in a solid-state device is in need of a scrubbing operation. One or more reference blocks may be programmed with a known data pattern, wherein the reference block(s) experiences substantially similar P/E cycling, storage temperature, storage time, and other conditions as the user blocks. The reference blocks may therefore effectively represent data retention properties of the user blocks and provide information regarding whether/when a data refreshing operation is needed. | 2014-02-27 |
20140059406 | REDUCED LEVEL CELL MODE FOR NON-VOLATILE MEMORY - Apparatuses, systems, methods, and computer program products are disclosed for reduced level cell solid-state storage. A method includes determining that an erase block of a non-volatile storage device is to operate in a reduced level cell (RLC) mode. The non-volatile storage device may be configured to store at least three bits of data per storage cell. A method includes instructing the non-volatile storage device to program first and second pages of the erase block with data. A method includes instructing the non-volatile storage device to program a third page of the erase block with a predefined data pattern. Programming of a predefined data pattern may be configured to adjust which abodes of the erase block are available to represent stored user data values. | 2014-02-27 |
20140059407 | CHASE CODING FOR ERROR CORRECTION OF ENCRYPTED PACKETS WITH PARITY - A plurality of encrypted packets having common payload data are received, wherein each of the plurality of encrypted packets includes a corresponding parity check field, and wherein a corresponding parity check syndrome for each of the plurality of encrypted packets indicates at least one bit error. A payload portion of each of the plurality of encrypted packets is decrypted to generate a plurality of decrypted payload portions. At least one chase coding technique is used to generate a corrected decrypted payload, based on at least one candidate bit error position and further based on the corresponding parity check syndrome for at least one of the plurality of encrypted packets. | 2014-02-27 |
20140059408 | ACCUMULATING LDPC (LOW DENSITY PARITY CHECK) DECODER - Accumulating LDPC (Low Density Parity Check) decoder. The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (γ) values and check edge message (λ) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size. | 2014-02-27 |
20140059409 | SYSTEM AND METHOD HAVING OPTIMAL, SYSTEMATIC q-Ary CODES FOR CORRECTING ALL ASYMMETRIC AND SYMMETRIC ERRORS OF LIMITED MAGNITUDE - A computer-implemented method and computer program product comprising optimal, systematic q-ary codes for correcting all asymmetric and symmetric errors of limited magnitude are provided. | 2014-02-27 |
20140059410 | COMPUTATIONALLY EFFICIENT CONVOLUTIONAL CODING WITH RATE-MATCHING - An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate. | 2014-02-27 |
20140059411 | NOVEL COMPUTING SYSTEM - A computing system including a processor, display, pointing device and memory; wherein the memory includes a text file, a graphics file corresponding to said text file and executable instructions to perform at least these actions (i) identify a selection of an alphanumeric identifier within a displayed text file, and then (ii) identify the appearance of the identifier in a corresponding graphics file, and then (iii) display a page of the graphics file comprising the appearance of the identifier. | 2014-02-27 |
20140059412 | USER INTERFACE FOR CREATING A SPREADSHEET DATA SUMMARY TABLE - A graphical user interface for creating a data summary table includes a field pane including a list of a plurality of fields, and a layout pane including a plurality of zones. The zones represent areas of the data summary table, and the layout pane allows a field of the plurality of fields from the field pane to be added to a first zone of the zones. A data summary table is updated upon the field being added to the layout pane. | 2014-02-27 |
20140059413 | APPLICATION MODULE FOR MANAGING JOBS ASYNCHRONOUSLY - A method to synchronize data between a spreadsheet application and a marketplace application is disclosed. The method includes receiving a request to synchronize data items between the spreadsheet application and the marketplace application, the data items relating to a type of listing of items associated with the marketplace application. Additionally, the method includes executing a process to synchronize the data items between the spreadsheet application and the marketplace application, the process to include at least one of downloading one of the data items from the spreadsheet application and uploading one of the plurality of data items to the marketplace application, the executing of the process to occur independently of the executing of the spreadsheet application. Furthermore, the method includes displaying a status of the executing of the process in a native user interface element of the spreadsheet application. | 2014-02-27 |
20140059414 | ARRANGEMENT FOR AND METHOD OF READING FORMS IN CORRECT ORIENTATION BY IMAGE CAPTURE - An arrangement for, and a method of, electro-optically reading forms, each form having a plurality of form fields arranged at locations relative to one another, by image capture, includes storing form templates, each template having a plurality of template fields arranged at locations relative to one another, and capturing images over a field of view. A form and a correct orientation of the form, whose image is being captured, are automatically identified by matching the locations of the form fields in the captured image of the form with the locations of the stored template fields. The form fields on the identified form in the correct orientation are thereupon processed. | 2014-02-27 |
20140059415 | SYSTEM AND METHOD FOR POPULATING AN ELECTRONIC STATEMENT OF WORK TEMPLATE BASED ON CORRESPONDING CONTENT OF ANOTHER ELECTRONIC STATEMENT OF WORK TEMPLATE - A method may be used to populate content within an electronic statement of work (SOW) template. A computing device may retrieve a first template to generate a SOW between a first and second party, wherein the first party is an organization and the second party is either a customer or provider to the organization. The first template may include references to the second party and the organization. The computing device may populate a second template based on the first template to generate a SOW between the organization and a third party. It may then identify within the first template references to the second party and to the organization, and may convert references to the second party in the first template into references to the organization within the second template, and may convert references to the organization within the first template into references to the third party within the second template. | 2014-02-27 |