| 08th week of 2010 patent applcation highlights part 49 |
| Patent application number | Title | Published |
|---|
| 20100047912 | APPARATUS, METHOD AND SYSTEM FOR CREATING, COLLECTING AND INDEXING SEED PORTIONS FROM INDIVIDUAL SEED - A method, apparatus, and system for coating, singulating, aligning, ablating, and indexing a number of seeds for testing is described. The apparatus has a carrier designed to hold seeds in a predetermined alignment for ablating a seed sample from a seed portion, the seed portions are indexed to the seed samples. The carrier is then located on the apparatus which delivers the seed samples from the carrier to a collector for laboratory testing. | 2010-02-25 |
| 20100047913 | Colloidal Gold Single Reagent Quantitative Protein Assay - The invention provides methods for determining the concentration of polypeptides. The methods generally comprise labeling a polypeptide with a metal label such as colloidal gold and quantifiably detecting the polypeptide-metal complex; the methods are improvements over other quantification assays that use colloidal gold. The invention further provides kits for practicing the methods. | 2010-02-25 |
| 20100047914 | AGENT DETECTION AND/OR QUANTITATION IN A BIOLOGICAL FLUID - A method of assessing retinal disease in an eye of a patient by rapid, point of care, quantitative detection of cytokine levels is provided. | 2010-02-25 |
| 20100047915 | IDENTIFYING PATIENTS AT RISK FOR LIFE THREATENING ARRHYTHMIAS - The invention is a method for identifying proteins associated with sudden cardiac death (SCD) and for assessing a patient's risk of SCD by determining the amount of one or more SCD-associated proteins in the patient. Typically, the patient submits a sample, such as a blood sample, which is tested for one or more SCD-associated proteins. Based upon the results of the tests, the patient's risk of SCD may be assessed. | 2010-02-25 |
| 20100047916 | DETECTION OF MATERIALS VIA NITROGEN OXIDE - Methods and devices for detecting the presence of a NO forming material (e.g., a material that can form, or is, a nitrogen monoxide molecule) are disclosed based on detection of fluorescence exhibited by NO molecules in a first vibrationally excited state of a ground electronic state. Such excited NO molecules can be formed, for example, when small amounts of explosives are photodissociated. By inducing fluorescence of the material, a distinct signature of the explosive can be detected. Such techniques can be performed quickly and with a significant standoff distance, which can add to the invention's utility. In another aspection of the invention, methods and apparatus for generating electromagnetic radiation are disclosed. Such methods and apparatus can be used in conjunction with any detection method disclosed herein. | 2010-02-25 |
| 20100047917 | METHOD FOR ASSAYING SULFUR AND APPARATUS THEREFOR - The present invention relates to a sulfur assaying method comprising converting carbon monoxide in a sample gas generated by combustion of the sample to nitrogen dioxide by a pretreatment, and then measuring the intensity of fluorescence of sulfur dioxide in the sample gas, the pretreatment comprising irradiating the sample gas with light from a low pressure mercury lamp, and also relates to a sulfur assaying apparatus comprising a combustor ( | 2010-02-25 |
| 20100047918 | TEST-SENSOR CARTRIDGE - A test-sensor cartridge including a plurality of test sensors adapted to assist in determining an analyte concentration of a fluid sample. The test-sensor cartridge further includes a housing forming a cavity. The cavity is adapted to contain the plurality of test sensors. The test-sensor cartridge further includes a lid adapted to enclose the cavity. The test-sensor cartridge further includes a closing feature adapted to maintain the lid in a closed position. The closing feature is distorted when the lid is in an open position and generally released when the lid is in a closed position. | 2010-02-25 |
| 20100047919 | BIOSENSOR DEVICE AND METHOD FOR DETECTING MOLECULES IN AN ANALYTE - A biosensor device ( | 2010-02-25 |
| 20100047920 | DEVICE IMPROVING THE DETECTION OF A LIGAND - A device and method is disclosed for improving the detection of a ligand by a receptor by concentrating microbes by removing particulates from fluid-borne samples and/or causing selective aggregation of concentrated microbes. The device may be configured as a multipath valve capable purifying/concentrating a sample in one orientation and delivering the concentrated sample in another orientation. In one embodiment, the device includes a body that defines a plurality of chambers and pathways and supports a pathogen capture unit that houses a receptor that exhibits specificity for a ligand. In another embodiment, the capture unit houses a plurality of antibody coated generally spherical particles capable of binding to a ligand. | 2010-02-25 |
| 20100047921 | METHOD FOR ISOLATION OF BIOPOLYMER BY USING RE-CIRCULATING CHROMATOGRAPHY - It is an object of the present invention to provide a method for isolating biopolymers, which is capable of simultaneously isolating many types of biopolymers from a single biological sample under the same conditions. The present invention provides a method for isolating biopolymers, which comprises repeating at least twice a process consisting of: (1) a step of preparing at least two vessels each containing a carrier retaining a substance having an affinity for a target biopolymer; then simultaneously introducing a single sample solution containing the target biopolymer into at least the two vessels, and then allowing said sample solution to come into contact with said carrier, so that the target biopolymer can be adsorbed on said carrier; (2) a step of discharging said sample solution from said vessels; and (3) a step of stirring the discharged sample solution. | 2010-02-25 |
| 20100047922 | TURBIDIMETRIC IMMUNOASSAY FOR ASSESSING HUMAN CYSTATIN C - There is a demand for improved turbidimetric immunoassays for human Cystatin C in biological samples, especially in human clinical samples of body fluids. The present invention provides a turbidimetric immunoassay method and reagent set enabling measurement of human Cystatin C by turbidimetric methods, resulting in a surprisingly stronger and faster turbidimetric signal than in the present state of the art. The increased and faster signal is accomplished by the use of new reagents and compositions, and enables shorter assay times and kinetic reading with a stronger signal, improving overall assay speed and quality. Improved robustness to lipid interference and improved linearity is achieved. | 2010-02-25 |
| 20100047923 | TWO HELIX BINDERS - An isolated polypeptide, Z domain, derived from B domain of | 2010-02-25 |
| 20100047924 | STABLE NANOREPORTERS - The present invention relates to compositions and methods for detection and quantification of individual target molecules in biomolecular samples. In particular, the invention relates to improved, stable nanoreporter probes that are capable of binding to and identifying target molecules based on the probes' uniquely detectable signal. Methods for identifying target-specific sequences for inclusion in the probes are also provided, as are methods of making and using such probes. Polynucleotide sequences of certain nanoreporter components are also provided. The probes can be used in diagnostic, prognostic, quality control and screening applications. | 2010-02-25 |
| 20100047925 | SEQUENTIAL ANALYSIS OF BIOLOGICAL SAMPLES - Methods for detecting multiple targets in a biological sample are provided. The methods includes contacting the sample with a first probe; physically binding the first probe to a first target; observing a first signal from the first probe; applying a chemical agent to modify the first signal; contacting the sample with a second probe; physically binding the second probe to a second target; and observing a second signal from the second probe. The methods disclosed herein also provide for multiple iterations of binding, observing, signal modification for deriving information about multiple targets in a single sample. An associated kit and device are also provided. | 2010-02-25 |
| 20100047926 | HYBRIDIZATION CHAIN REACTION - The present invention relates to the use of nucleic acid probes to identify analytes in a sample. In the preferred embodiments, metastable nucleic acid monomers are provided that associate in the presence of an initiator nucleic acid. Upon exposure to the initiator, the monomers self-assemble in a hybridization chain reaction. The initiator nucleic acid may be, for example, a portion of an analyte to be detected or may be part of an initiation trigger such that it is made available in the presence of a target analyte. | 2010-02-25 |
| 20100047927 | KIT FOR MEASUREMENT OF TERMITE INSECTICIDE ACTIVE INGREDIENT BY IMMUNOASSAY METHOD - A kit and a method are provided for easily measuring the concentration of an active ingredient of a termite insecticide persisting in soil, particularly on site where a termite insecticide was actually applied. A kit of the present invention comprises 1) an extraction unit for extracting, with an solvent, a termite insecticide active ingredient from an object of measurement and 2) a reaction unit including a reaction container for encapsulating an identifying antigen, a fixing member for immobilizing an antibody against an active ingredient, and a sealing member capable of fitting to the reaction container. The kit optionally includes 3) a detection unit for visually or optically detecting a change depending on the concentrations of the active ingredient in the object of measurement, and 4) a dilution unit for diluting the sample solution to a certain ratio. | 2010-02-25 |
| 20100047928 | TARGET SUBSTANCE DETECTION ELEMENT, TARGET SUBSTANCE DETECTION METHOD, AND METHOD FOR PRODUCING TARGET SUBSTANCE DETECTION ELEMENT - It is intended to provide a target substance detection element wherein a target substance capturing body for capturing target substances is immobilized with good orientation in a desired region on the surface of the target substance detection element, a method for producing the target substance detection element, and a detection method using the target substance detection element. The present invention provides a target substance detection element for detecting the presence or absence or concentration of a target substance in a sample, characterized in that: the target substance detection element includes at least a detection substrate including plural layers and a target substance capturing body immobilized on the surface of the detection substrate; the target substance capturing body has at least a first peptide region specifically recognizing a first layer of the plural layers constituting the detection substrate and binding to the first layer and a second peptide region specifically recognizing a second layer different from the first layer of the plural layers and binding to the second layer; and the first layer and the second layer are adjacent to each other. | 2010-02-25 |
| 20100047929 | Novel underlayer for high performance magnetic tunneling junction MRAM - An MRAM structure is disclosed in which the bottom electrode has an amorphous TaN capping layer to consistently provide smooth and dense growth for AFM, pinned, tunnel barrier, and free layers in an overlying MTJ. Unlike a conventional Ta capping layer, TaN is oxidation resistant and has high resistivity to avoid shunting of a sense current caused by redeposition of the capping layer on the sidewalls of the tunnel barrier layer. Alternatively, the α-TaN layer is the seed layer in the MTJ. Furthermore, the seed layer may be a composite layer comprised of a NiCr, NiFe, or NiFeCr layer on the α-TaN layer. An α-TaN capping layer or seed layer can also be used in a TMR read head. An MTJ formed on an α-TaN capping layer has a high MR ratio, high Vb, and a RA similar to results obtained from MTJs based on an optimized Ta capping layer. | 2010-02-25 |
| 20100047930 | MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - A magnetic random access memory includes a first wiring, a second wiring formed above and spaced apart from the first wiring, a magnetoresistive effect element formed between the first wiring and the second wiring, formed in contact with an upper surface of the first wiring, and having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer, a metal layer formed on the magnetoresistive effect element and integrated with the magnetoresistive effect element to form stacked layers, a first side insulating film formed on side surfaces of the metal layer, the magnetoresistive effect element, and the first wiring, a first contact formed in contact with a side surface of the first side insulating film, and a third wiring formed on the metal layer and the first contact to electrically connect the magnetoresistive effect element and the first contact. | 2010-02-25 |
| 20100047931 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - When adopting a stack-type capacitor structure for a ferroelectric capacitor structure ( | 2010-02-25 |
| 20100047932 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, SUBSTRATE PROCESSING PROGRAM, AND COMPUTER READABLE RECORDING MEDIUM HAVING SUBSTRATE PROCESSING PROGRAM THEREIN - Disclosed is a substrate processing apparatus to supply processing liquid having a predetermined flow rate and concentration to a substrate processing unit of the substrate processing apparatus with high accuracy. The substrate processing apparatus processes substrates in a plurality of substrate processing units by using the processing liquid supplied from a processing liquid supply part. If the flow rate of the processing liquid simultaneously used by the substrate processing units is less than a control flow rate that is controllable at the processing liquid supply part, the processing liquid is supplied from the processing liquid supply part such that the flow rate of the processing liquid is substantially identical to the control flow rate. If the flow rate of the processing liquid simultaneously used by the substrate processing units is substantially identical to the control flow rate that is controllable at the processing liquid supply part, the processing liquid having the flow rate simultaneously used by the substrate processing units is supplied from the processing liquid supply part. | 2010-02-25 |
| 20100047933 | SUBSTRATE, SUBSTRATE INSPECTING METHOD AND METHODS OF MANUFACTURING AN ELEMENT AND A SUBSTRATE - A substrate inspection method allowing inspection of all a plurality of substrates each provided at its surface with a plurality of layers by determining quality of the plurality of layers as well as methods of manufacturing the substrate and an element using the substrate inspection method are provided. The substrate inspection method includes a step of preparing the substrate provided at its main surface with the plurality of layers, a film forming step, a local etching step, and an inspection step or a composition analysis step. In the step, a concavity is formed in a region provided with an epitaxial layer of the main surface of the substrate by removing at least partially the epitaxial layer. In the inspection step, the inspection is performed on the layer exposed in the concavity. | 2010-02-25 |
| 20100047934 | Method For Fabricating Semiconductor Component Having Encapsulated Through Wire Interconnect (TWI) - A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate. | 2010-02-25 |
| 20100047935 | LED PACKAGING METHOD USING A SCREEN PLATE - A LED packaging method includes a procedure of placing a screen plate having stepped holes on a substrate carrying LED chips, a procedure of reversing the screen plate with respect to the substrate, and a procedure of packaging the LED chips with a first packaging adhesive and a second packaging adhesive by means of applying the first packaging adhesive to the small diameter portion of each stepped hole when the first side of the screen plate is attached to the substrate and then applying the second packaging adhesive to the big diameter portion of each stepped hole after the screen plate is reversed. | 2010-02-25 |
| 20100047936 | METHOD FOR PACKAGING LIGHT-EMITTING DIODE - Disclosed is a method for packaging an LED by a thermoplastic copolymer. The copolymer is polymerized by 100 parts by weight of an acrylic ester, 0.1 to 30 parts by weight of a hydrogen bond monomer, and 0.1 to 70 parts by weight of a bulky monomer. The copolymer has transparency greater than 90%, thermal resistance greater than 130° C., and moisture absorption less than 0.5 wt %, such that the copolymer may be applied as packaging material for a light emitting device. | 2010-02-25 |
| 20100047937 | LED PACKAGE - A Chip on Board (COB) package which can reduce the manufacturing costs by using a general PCB as a substrate, increase a heat radiation effect from a light source, thereby realizing a high quality light source at low costs, and a manufacturing method thereof. The COB package includes a board-like substrate with a circuit printed on a surface thereof, the substrate having a through hole. The package also includes a light source positioned in the through hole and including a submount and a dome structure made of resin, covering and fixing the light source to the substrate. The invention allows a good heat radiation effect by using the general PCB as the substrate, enabling manufacture of a high quality COB package at low costs. This in turn improves emission efficiency of the light source, ultimately realizing a high quality light source. | 2010-02-25 |
| 20100047938 | FLAT PANEL DISPLAY DEVICE AND METHOD FOR FABRICATING SAME - Provided is a flat panel display device and a method for fabricating the same. The flat panel display device comprises a first substrate, a light emitting unit, a second substrate, and insulating films. The light emitting unit comprises thin film transistors positioned on the first substrate, a first electrode electrically connecting with the thin film transistors, a second electrode facing the first electrode, and an emission layer or a liquid crystal layer interposed between the first and second electrodes. The second substrate is sealed with the first substrate by an ultraviolet curing sealant, and has a greater thermal expansion coefficient than the first substrate. The insulating films are positioned on one or more surfaces of the first and/or second substrates. | 2010-02-25 |
| 20100047939 | SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - In a semiconductor light emitting device, light is lost from a side surface of a substrate; therefore, if a substrate side surface occupies a large area, it decreases light extraction efficiency. The area of the substrate side surface may be reduced by reducing a thickness of the substrate. However, a thin substrate has low mechanical strength and is cracked by a stress during work process, and that decreases the yield. | 2010-02-25 |
| 20100047940 | METHOD OF MANUFACTURING LIGHT EMITTING DIODE DEVICE - A method of manufacturing light-emitting diode device has steps of isolating a light-emitting side of an LED chip from a wire-bonding region by disposing partition panels on the wire-bonding region and coating phosphors on the light-emitting side of the LED chip in a phosphor-coating process. The method can be applied to manufacturing LED device having a flip chip structure or a vertical chip structure. According to the method, a white LED device can be directly manufactured without adopting a phosphor package technique, and thereby a whole package process of the white LED device is simplified. | 2010-02-25 |
| 20100047941 | HIGH POWER LED PACKAGE AND FABRICATION METHOD THEREOF - An LED diode package includes a heat connecting part for mounting a light emitting part on an upper surface thereof, frames electrically connected to the light emitting part while holding the heat connecting part and a molded part fixing the heat connecting part and the frames together. The light emitting part generates light in response to current applied thereto, and the upper surface of the heat connecting part is protruded beyond an upper surface of the molded part to a predetermined height. This can optimize the unique beam angle of the light source thereby to maximize lighting efficiency as well as prevent overflow of the encapsulating material in the assembling process of the lens, which may otherwise soil adjacent components. | 2010-02-25 |
| 20100047942 | METHOD OF MAKING WHITE LED PACKAGE STRUCTURE HAVING A SILICON SUBSTRATE - A method of making a white LED package structure having a silicon substrate comprises providing a silicon substrate and performing an etching process to form a plurality of cup-structures on a top surface of the silicon substrate. Next, a reflective layer on the top surface of the silicon substrate is formed, and a transparent insulating layer on the reflective layer is formed. Subsequently, a plurality of blue LEDs are respectively bonded in each cup-structure, wherein the blue LEDs have various wavelengths. Last, a plurality of kinds of phosphor powders corresponding to the wavelengths of the blue LEDs are mixed with each other and added to a sealing material, and a sealing process is performed to form a phosphor structure on the cup-structures. | 2010-02-25 |
| 20100047943 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a light emitting device and a method of manufacturing the light emitting device. According to the present invention, the light emitting device comprises a substrate, an N-type semiconductor layer formed on the substrate, and a P-type semiconductor layer formed on the N-type semiconductor layer, wherein a side surface including the N-type or P-type semiconductor layer has a slope of 20 to 80° from a horizontal plane. Further, the present invention provides a light emitting device comprising a substrate formed with a plurality of light emitting cells each including an N-type semiconductor layer and a P-type semiconductor layer formed on the N-type semiconductor layer, and a submount substrate flip-chip bonded onto the substrate, wherein the N-type semiconductor layer of one light emitting cell and the P-type semiconductor layer of another adjacent light emitting cell are connected to each other, and a side surface including at least the P-type semiconductor layer of the light emitting cell has a slope of 20 to 80° from a horizontal plane. Further, the present invention provides a method of manufacturing the light emitting device. Accordingly, there is an advantage in that the characteristics of a light emitting device such as luminous efficiency, external quantum efficiency and extraction efficiency are enhanced and the reliability is secured such that light with high luminous intensity and brightness can be emitted. | 2010-02-25 |
| 20100047944 | Light-emitting element with improved light extraction efficiency, light-emitting device including the same, and methods of fabricating light-emitting element and light-emitting device - Provided are a light-emitting element, a light-emitting device including the same, and methods of fabricating the light-emitting element and the light-emitting device. The light-emitting element includes a substrate on which a dome pattern is formed and a light-emitting structure conformally formed on the dome pattern. The light-emitting structure includes a first conductive layer of a first conductivity type, a light-emitting layer, and a second conductive layer of a second conductivity type sequentially stacked on the substrate. The light-emitting element also includes a first electrode formed on the first conductive layer and a second electrode formed on the second conductive layer. | 2010-02-25 |
| 20100047945 | Methods Of Forming Particle-Containing Materials - The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials. One aspect of the invention includes a method in which a first monolayer is formed across at least a portion of a semiconductor substrate, particles are adhered to the first monolayer, and a second monolayer is formed over the particles. Another aspect of the invention includes a construction containing a semiconductor substrate and a particle-impregnated conductive material over at least a portion of the semiconductor substrate. The particle-impregnated conductive material can include tungsten-containing particles within a layer which includes tantalum or tungsten. | 2010-02-25 |
| 20100047946 | THIN FILM ARRAY PANEL AND MANUFACTURING METHOD THEREOF - A method of manufacturing a thin film array panel is provided, which includes: forming a gate line formed on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact layer on the semiconductor layer; forming a data line and a drain electrode disposed at least on the ohmic contact layer, forming an oxide on the data line; etching the ohmic contact layer using the data line and the drain electrode as an etch mask; and forming a pixel electrode connected to the drain electrode. | 2010-02-25 |
| 20100047947 | Semiconductor light-emitting element, fabrication method thereof, convex part formed on backing, and convex part formation method for backing - A convex part formation method of forming a convex part in parallel with a <110> direction of a backing on the backing having a {100} face as the top surface thereof, includes: (a) forming a mask layer in parallel with the <110> direction on the backing; (b) etch the backing so as to form a convex-part upper layer whose sectional shape on a cutting plane corresponding to a {110} face is an isosceles trapezoid, the base of which is longer than the upper side thereof, and the side surface of which has an inclination of θ | 2010-02-25 |
| 20100047948 | SENSOR AND METHOD OF MANUFACTURING THE SAME - A sensor comprising a semiconductor film having a plurality of mesopores and containing an oxide, and electrodes electrically connected to the semiconductor film, wherein at least part of surfaces in the mesopores is coated with an organic material. | 2010-02-25 |
| 20100047949 | STACK TYPE SURFACE ACOUSTIC WAVE PACKAGE, AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a stack type surface acoustic wave package. The surface acoustic wave package comprises a first bare chip having a plurality of electrodes formed thereon, a second bare chip having a plurality of electrodes and via-holes formed thereon, a connecting portion electrically connecting the first bare chip to an upper surface of the second bare chip such that the electrodes of the first bare chip face the electrodes of the second bare chip, and a sealing member provided on the first and second bare chips to form an air-tight space on an operating surface between the first and second bare chips. The surface acoustic wave package can prevent deformation due to thermal impact from the outside during a packaging process, enhancing reliability of the product, minimizing the size of the product, and reducing manufacturing costs by reducing the number of components and material costs. | 2010-02-25 |
| 20100047950 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - A complementary metal oxide semiconductor (CMOS) device and a method for fabricating the same are provided. The CMOS image sensor includes: a first conductive type substrate including a trench; a channel stop layer formed by using a first conductive type epitaxial layer over an inner surface of the trench; a device isolation layer formed on the channel stop layer to fill the trench; a second conductive type photodiode formed in a portion of the substrate in one side of the channel stop layer; and a transfer gate structure formed on the substrate adjacent to the photodiode to transfer photo-electrons generated from the photodiode. | 2010-02-25 |
| 20100047951 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor and a method for fabricating the same are provided. The image sensor includes a first conductive type substrate including a trench formed in a predetermined portion of the first conductive type substrate, a second conductive type impurity region for use in a photodiode, formed below a bottom surface of the trench in the first conductive type substrate, and a first conductive type epitaxial layer for use in the photodiode, buried in the trench. | 2010-02-25 |
| 20100047952 | METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - A fragile layer is formed in a single crystal silicon substrate, a first impurity silicon layer is formed on the one surface side in the single crystal silicon substrate, and a first electrode is formed thereover. After one surface of a supporting substrate and the first electrode are bonded, the single crystal silicon substrate is separated along the fragile layer to form a single crystal silicon layer over the supporting substrate. Crystal defect repair treatment or crystal defect elimination treatment of the single crystal silicon layer is performed; then, epitaxial growth is conducted on the single crystal silicon layer by activating a source gas containing at least a silane-based gas with plasma generated at atmospheric pressure or near atmospheric pressure. A second impurity silicon layer is formed on a surface side in the single crystal silicon layer which is epitaxial grown. | 2010-02-25 |
| 20100047953 | METHOD FOR PRODUCING WAFER FOR BACKSIDE ILLUMINATION TYPE SOLID IMAGING DEVICE - In the production of a wafer for backside illumination type solid imaging device having a plurality of pixels inclusive of a photoelectric conversion device and a charge transfer transistor formed at its front surface side and a light receiving surface at its back surface side, an active layer made of a given epitaxial film is formed on a silicon wafer made of a C-containing CZ crystal directly or through an insulating film, and then subjected to a heat treatment to form precipitates containing C and O as a gettering sink at a position just beneath the active layer. | 2010-02-25 |
| 20100047954 | PHOTOVOLTAIC PRODUCTION LINE - The present invention generally relates to a system that can be used to form a photovoltaic device, or solar cell, using processing modules that are adapted to perform one or more steps in the solar cell formation process. The automated solar cell fab is generally an arrangement of automated processing modules and automation equipment that is used to form solar cell devices. The automated solar fab will thus generally comprise a substrate receiving module that is adapted to receive a substrate, one or more absorbing layer deposition cluster tools having at least one processing chamber that is adapted to deposit a silicon-containing layer on a surface of the substrate, one or more back contact deposition chambers, one or more material removal chambers, a solar cell encapsulation device, an autoclave module, an automated junction box attaching module, and one or more quality assurance modules that are adapted to test and qualify the completely formed solar cell device. | 2010-02-25 |
| 20100047955 | Interconnection system for photovoltaic modules - Methods for forming series-interconnected solar cells that use metal foils as substrates are provided. In an embodiment of the invention, a metallic substrate-type solar cell having the following structure is provided: a metal substrate, a semiconductor, and a transparent conducting front contact. In another embodiment of the invention, optional current collecting grids may be provided. An insulating carrier material layer may be provided bonded to the metal substrate. | 2010-02-25 |
| 20100047956 | METHODS OF FABRICATING INTEGRATED IMAGER AND MICROCONTROLLER - A method and apparatus providing a CMOS imager with an integrated controller on a common integrated circuit substrate. Also integrated on the common substrate are, a serializer circuit including a dynamic arbiter under the control of the microcontroller core and a set of extended special function registers through which data is passed to allow the microcontroller to control the CMOS imager and the serializer circuit. | 2010-02-25 |
| 20100047957 | METHOD FOR FORMING SOLAR CELL HAVING ACTIVE REGION WITH NANOSTRUCTURES HAVING ENERGY WELLS - A method and apparatus for solar cell having graded energy wells is provided. The active region of the solar cell comprises nanostructures. The nanostructures are formed from a material that comprises a III-V compound semiconductor and an element that alters the band gap of the III-V compound semiconductor. For example, the III-V compound semiconductor could be gallium nitride (GaN). As an example, the “band gap altering element” could be indium (In). The concentration of the indium in the active region is non-uniform such that the active region has a number of energy wells, separated by barriers. The energy wells may be “graded”, by which it is meant that the energy wells have a different band gap from one another, generally increasing or decreasing from one well to another monotonically. | 2010-02-25 |
| 20100047958 | METHOD FOR MANUFACTURING CIS BASED THIN FILM SOLAR CELL DEVICE - Before a buffer layer deposition step P | 2010-02-25 |
| 20100047959 | Epitaxial Lift Off on Film Mounted Inverted Metamorphic Multijunction Solar Cells - A process for selectively freeing an epitaxial layer from a single crystal substrate upon which it was grown, by providing a first substrate; depositing a separation layer on the first substrate; depositing on the separation layer a sequence of layers of semiconductor material forming a solar cell; mounting and bonding a thin flexible support having a coefficient of thermal expansion substantially greater than that of the adjacent semiconductor material on top of the sequence of layers at an elevated temperature; and etching the separation layer while the temperature of the support and layers of semiconductor material decrease, so that the support and the attached layer curls away from the first substrate in view of their differences in coefficient of thermal expansion, so as to remove the epitaxial layer from the substrate. | 2010-02-25 |
| 20100047960 | METHOD OF FABRICATING A PHASE-CHANGE MEMORY - A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are electrically connected via the first phase-change material. Since the phase-change material can have a diameter less than the resolution limit of the photolithography process, an operating current for a state conversion of the phase-change material pattern may be reduced so as to decrease a power dissipation of the phase-change memory device. | 2010-02-25 |
| 20100047961 | Placement Of An Integrated Circuit - Disclosed herein is a method of positioning and placing an integrated circuit on a printed circuit board. The integrated circuit comprises first geometrical elements. The first geometrical elements are of one or more predefined shapes and are located on one or more predefined surfaces of the integrated circuit. The printed circuit board comprises second geometrical elements. The second geometrical elements are shaped to accommodate the first geometrical elements. The first geometrical elements are designed to fit into the second geometrical elements. The first geometrical elements are positioned and placed over the second geometrical elements. The first geometrical elements come in contact with the second geometrical elements at two or more points. The positioning and placement of the first geometrical elements over the second geometrical elements limits displacement of connections of the integrated circuit from the printed circuit board. | 2010-02-25 |
| 20100047962 | MULTI-CHIP PRINTHEAD ASSEMBLER - The invention relates to an assembler for assembling printhead integrated circuitry on a carrier. The assembler includes a support assembly, a wafer positioning assembly arranged on the support assembly and configured to retain and position a wafer defining a plurality of die to be picked from the wafer; and a die picking assembly arranged on the support assembly and configured to pick a pre-selected dice from the wafer. The assembler also includes a die placement assembly arranged on the support assembly and configured to receive the pre-selected dice and to place the dice on the carrier, and a die conveyance mechanism arranged on the support assembly and configured to convey the dice from the die picking assembly to the die placement assembly. Further included is a control system operatively engaged with the wafer positioning, die picking, die placement and die conveyance assemblies to control operation thereof. | 2010-02-25 |
| 20100047963 | Through Silicon Via Bonding Structure - System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate. | 2010-02-25 |
| 20100047964 | 3D INTEGRATED CIRCUIT DEVICE FABRICATION USING INTERFACE WAFER AS PERMANENT CARRIER - A method is provided for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer. Also provided is a tangible computer readable medium encoded with a program that comprises instructions for performing such a method. | 2010-02-25 |
| 20100047965 | FABRICATING METHOD OF PACKAGING STRUCTURE - A fabricating method of packaging structure is provided. First, a capacitive element is formed. Then, a first dielectric layer is formed on a first electronic component by performing a build-up process, an interconnection is formed in the first dielectric layer, and a plurality of contacts are formed on the upper and lower surfaces of the first dielectric layer, wherein the capacitive element is embedded in the first dielectric layer during the fabrication of the interconnection and the capacitive element is electrically connected to the corresponding contacts through the interconnection. A second electronic component is disposed on the first dielectric layer, wherein the second electronic component is electrically connected to the corresponding contacts. | 2010-02-25 |
| 20100047966 | INTEGRATED CIRCUIT APPARATUS, SYSTEMS, AND METHODS - High density circuit modules are formed by stacking integrated circuit (IC) chips one above another. Unused input/output (I/O) locations on some of the chips can be used to connect other I/O locations, resulting in decreased impedance between the chips. Additional apparatus, systems, and methods are disclosed. | 2010-02-25 |
| 20100047967 | METHOD OF MANUFACTURING STACKED SEMICONDUCTOR PACKAGE USING IMPROVED TECHNIQUE OF FORMING THROUGH VIA - A method of manufacturing a stacked semiconductor package using an improved technique of forming a through via in order to enable 3-dimensional vertical interconnection of stacked packages is provided. The method includes forming a seed layer required for forming a via core on a bottom surface of a wafer, forming at least one via hole vertically through the wafer, forming a via core in the via hole, insulating the via hole from the via core, and removing the seed layer from the bottom surface of the wafer. The stacked semiconductor package is suitable for high-speed signal transmission. | 2010-02-25 |
| 20100047968 | ADHESIVE SHEET FOR PRODUCING A SEMICONDUCTOR DEVICE, AND A METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE USING THE SAME - The present invention relates to an adhesive sheet for producing a semiconductor device, which is used when a semiconductor element is caused to adhere onto an adherend and the semiconductor element is wire-bonded, in which a lipophilic lamellar clay mineral is contained. | 2010-02-25 |
| 20100047969 | BACKGRINDING-UNDERFILL FILM, METHOD OF FORMING THE SAME, SEMICONDUCTOR PACKAGE USING THE BACKGRINDING-UNDERFILL FILM, AND METHOD OF FORMING THE SEMICONDUCTOR PACKAGE - A semiconductor package forming method includes mounting a backgrinding-underfill film which includes a laminated backgrinding film and a laminated underfill film on a semiconductor wafer so that the underfill film adheres to a front side of the semiconductor wafer; backgrinding a back side of the semiconductor wafer on which the backgrinding-underfill film has been mounted and removing the backgrinding film of the backgrinding-underfill film from the semiconductor wafer. The method further includes dicing the semiconductor wafer from which the backgrinding film has been removed, so that semiconductor chips are separated from the semiconductor wafer. | 2010-02-25 |
| 20100047970 | INTEGRATED CONDUCTIVE STRUCTURES AND FABRICATION METHODS THEREOF FACILITATING IMPLEMENTING A CELL PHONE OR OTHER ELECTRONIC SYSTEM - Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer. | 2010-02-25 |
| 20100047971 | Electromigration-resistant and compliant wire interconnects, nano-sized solder compositions, systems made thereof, and methods of assembling soldered packages - A nano-sized metal particle composite includes a first metal that has a particle size of about 50 nanometer or smaller. A wire interconnect is in contact with a reflowed nanosolder and has the same metal or alloy composition as the reflowed nanosolder. A microelectronic package is also disclosed that uses the reflowed nanosolder composition. A method of assembling a microelectronic package includes preparing a wire interconnect template. A computing system includes a nanosolder composition coupled to a wire interconnect. | 2010-02-25 |
| 20100047972 | SEMICONDUCTOR STRUCTURE WITH FIELD SHIELD AND METHOD OF FORMING THE STRUCTURE - Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate. | 2010-02-25 |
| 20100047973 | METHOD FOR FORMING MICROWIRES AND/OR NANOWIRES - A method for forming a wire in a layer based on a monocrystalline or amorphous material. The method forms two trenches in the layer, crossing through one face of the layer, separated from each other by one portion of the layer, by an etching of the layer on which is arranged an etching mask, and anneals, under hydrogenated atmosphere, the layer, the etching mask being maintained on the layer during the annealing. The depths and widths of the sections of the two trenches, and the width of a section of the portion of the layer, are such that the annealing eliminates a part of the portion of the layer, the two trenches then forming a single trench in which a remaining part of the portion of the layer forms the wire. | 2010-02-25 |
| 20100047974 | METHOD OF MANUFACTURING THIN FILM TRANSISTOR ARRAY SUBSTRATE - A simplified method of manufacturing a thin film transistor array substrate is disclosed. The method includes: forming gate electrodes, gate lines and gate pads on a substrate with the use of a first mask; forming a gate insulation film, a semiconductor layer, and a metal layer on the substrate; forming a first photoresist pattern on the metal layer with the use of a second mask; forming first contact holes for the gate pads with the use of the first photoresist pattern; forming a second photoresist pattern, and providing patterns for data pads, data lines, and thin film transistors with the use of the second photoresist pattern; providing a third photoresist pattern, and forming contact holes for source/drain electrodes and second contact holes the gate pads with the use of the third photoresist pattern; forming a protective film on the substrate and providing a fourth photoresist pattern on the protective film with the use of a third mask; forming third contact holes for the gate pads, contact holes for the data pads, gate lines, and drain electrodes, and contact holes for pixel electrodes, with the use of the fourth photoresist pattern; and forming a transparent conduction film on the fourth photoresist pattern having the contact holes. | 2010-02-25 |
| 20100047975 | Method for fabricating low temperature poly-silicon thin film transistor substrate background - An exemplary method for fabricating an LTPS-TFT substrate is as follows. In step S | 2010-02-25 |
| 20100047976 | METHOD FOR FORMING NITRIDE SEMICONDUCTOR LAMINATED STRUCTURE AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR ELEMENT - The method for forming a nitride semiconductor laminated structure according to the present invention includes: a first layer forming step of forming an n-type or i-type first layer composed of a group III nitride semiconductor; a second layer forming step of laminating a p-type second layer composed of a group III nitride semiconductor and containing Mg on the first layer; and a third layer forming step of forming an n-type or i-type third layer composed of a group III nitride semiconductor on the second layer after the second layer forming step. | 2010-02-25 |
| 20100047977 | STRAINED SILICON WITH ELASTIC EDGE RELAXATION - A thin blanket epitaxial layer of SiGe is grown on a silicon substrate to have a biaxial compressive stress in the growth plane. A thin epitaxial layer of silicon is deposited on the SiGe layer, with the SiGe layer having a thickness less than its critical thicknesses. Shallow trenches are subsequently fabricated through the epitaxial layers, so that the strain energy is redistributed such that the compressive strain in the SiGe layer is partially relaxed elastically and a degree of tensile strain is induced to the neighboring layers of silicon. Because this process for inducing tensile strain in a silicon over-layer is elastic in nature, the desired strain may be achieved without formation of misfit dislocations. | 2010-02-25 |
| 20100047978 | MANUFACTURE OF SEMICONDUCTOR DEVICE WITH STRESS STRUCTURE - A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers. | 2010-02-25 |
| 20100047979 | METHOD OF REDUCING COUPLING BETWEEN FLOATING GATES IN NONVOLATILE MEMORY - A nonvolatile memory array includes floating gates that have an inverted-T shape in cross section along a plane that is perpendicular to the direction along which floating cells are connected together to form a string. Adjacent strings are isolated by shallow trench isolation structures. | 2010-02-25 |
| 20100047980 | PROCESS FOR FORMING DIFFERENTIAL SPACES IN ELECTRONICS DEVICE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE - A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the whole electronic device; forming a first mask to cover the first transistor; removing the first conformal insulating layer not covered by the first mask; removing the first mask; forming a second conformal insulating layer of a second thickness on the whole device; and removing the insulating layers until the protective layer is exposed to form first spacers of a first width on the side walls of the gate electrodes of the first transistor and second spacers of a second width on the side walls of the gate electrodes of the second transistor. | 2010-02-25 |
| 20100047981 | Method of fabricating EEPROM - There is provided a method of fabricating an EEPROM for forming a memory cell transistor and a selection transistor, the method includes: forming a first source region and a first drain region of the memory cell transistor; forming a first gate oxide film; forming a resist having at least one through hole on the first gate oxide film; adding conductivity type impurities through the through hole; partially removing the first gate oxide film and forming a tunnel oxide film in a region corresponding to the through hole; forming a floating gate electrode and a second gate oxide film formed on the floating gate electrode; forming a control gate electrode and a selection transistor gate electrode on the second gate oxide film and at a region in which the selection transistor is formed; and forming a second source region and a second drain region of the selection cell transistor. | 2010-02-25 |
| 20100047982 | Flash Memory Cell Arrays Having Dual Control Gates Per Memory Cell Charge Storage Element - A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers. | 2010-02-25 |
| 20100047983 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor. | 2010-02-25 |
| 20100047984 | SELF-ALIGNED METAL-SEMICONDUCTOR ALLOY AND METALLIZATION FOR SUB-LITHOGRAPHIC SOURCE AND DRAIN CONTACTS - A lateral double-gate FET structure with sub-lithographic source and drain regions is disclosed. The sub-lithographic source and drain regions are defined by a sacrificial spacer. Self-aligned metal-semiconductor alloy and metal contacts are made to the sub-lithographic source and drain using conventional silicon processing. | 2010-02-25 |
| 20100047985 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE WITH SELF-ALIGNED STRESSOR AND EXTENSION REGIONS - Methods are provided for fabricating a MOS transistor having self-aligned stressor and extension regions. A method comprises forming a gate stack overlying a layer of semiconductor material and forming a spacer about sidewalls of the gate stack. The method further comprises forming cavities in the layer of semiconductor material, wherein the cavities are substantially aligned with the spacer. The method further comprises forming a stress-inducing semiconductor material in the cavities, and implanting ions of a conductivity-determining impurity type into the stress-inducing semiconductor material using the gate stack and the spacer as an implantation mask. | 2010-02-25 |
| 20100047986 | GROUP III-V COMPOUND SEMICONDUCTOR BASED HETEROJUNCTION BIPOLAR TRANSISTORS WITH VARIOUS COLLECTOR PROFILES ON A COMMON WAFER - A wafer comprising at least one high F | 2010-02-25 |
| 20100047987 | METHOD OF FABRICATING A BIPOLAR TRANSISTOR - The invention provides a method for fabricating a bipolar transistor applying a standard shallow trench isolation fabrication method to simultaneously form a vertical bipolar transistor ( | 2010-02-25 |
| 20100047988 | METHODS OF FORMING A LAYER, METHODS OF FORMING A GATE STRUCTURE AND METHODS OF FORMING A CAPACITOR - In a method of forming a layer, a precursor including a metal and a ligand coordinating to the metal is stabilized by contacting the precursor with an electron donating compound to provide a stabilized precursor into a substrate. A reactant is introduced into the substrate to bind to the metal in the stabilized precursor. The precursor stabilized by the electron donating compound has an improved thermal stability and thus the precursor is not dissociated at a high temperature atmosphere, and the layer having a uniform thickness is formed on the substrate. | 2010-02-25 |
| 20100047989 | CAPACITOR WITH ZIRCONIUM OXIDE AND METHOD FOR FABRICATING THE SAME - A capacitor with zirconium oxide and a method for fabricating the same are provided. The method includes: forming a storage node; forming a multi-layered dielectric structure on the storage node, the multi-layered dielectric structure including a zirconium oxide (ZrO | 2010-02-25 |
| 20100047990 | METHOD OF FABRICATING A HIGH Q FACTOR INTEGRATED CIRCUIT INDUCTOR - A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor. | 2010-02-25 |
| 20100047991 | HIGH-K DIELECTRIC FILM, METHOD OF FORMING THE SAME AND RELATED SEMICONDUCTOR DEVICE - A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first silicon content and a top layer of metal-silicon-oxynitride having a second nitrogen content and a second silicon content. The second nitrogen content is higher than the first nitrogen content and the second silicon content is higher than the first silicon content. | 2010-02-25 |
| 20100047992 | METHOD OF FABRICATING STORAGE NODE WITH SUPPORTED STRUCTURE OF STACKED CAPACITOR - A method of fabricating a storage node with a supported structure is provided. A dielectric stacked comprising an etch stop layer, a first dielectric layer, a support layer and a second dielectric layer is formed on a substrate. An opening is etched into the dielectric stacked. A conductive layer is formed on the second dielectric layer and inside the opening. The conductive layer directly above the second dielectric layer is removed to form columnar node structure. The second dielectric layer is then removed. A spacer layer is deposited on the support layer and the columnar node structure. A tilt-angle implant is performed to implant dopants into the spacer layer. The undoped spacer layer is removed to form a hard mask. The support layer not covered by the hard mask is etched away to expose the first dielectric layer. The first dielectric layer and the hard mask are removed. | 2010-02-25 |
| 20100047993 | INTEGRATION OF HIGH-K METAL-GATE STACK INTO DIRECT SILICON BONDING (DSB) HYBRID ORIENTATION TECHNOLOGY (HOT) PMOS PROCESS FLOW - A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation layer, and a second crystal orientation layer, and a border region disposed between the first and second crystal orientations. A high-k metal gate stack is deposited over the first crystal orientation layer that comprises an insulation layer, a high-k dielectric layer, a first metal layer, and a second metal layer thereon. | 2010-02-25 |
| 20100047994 | FABRICATION OF INTEGRATED CIRCUITS WITH ISOLATION TRENCHES - After forming a stack of layers ( | 2010-02-25 |
| 20100047995 | METHOD FOR FORMING SELF-ALIGNED PHASE-CHANGE SEMICONDUCTOR DIODE MEMORY - A method for fabricating a memory device includes depositing a phase-change and/or a resistive change material. The memory device is formed photolithographically using sixteen or fewer masks. | 2010-02-25 |
| 20100047996 | LOCALIZED ANNEALING DURING SEMICONDUCTOR DEVICE FABRICATION - A process for the fabrication of semiconductor devices on a substrate, the semiconductor devices including at least one metal layer. The process includes, removing the substrate and applying a second substrate; and annealing the at least one metal layer by application of a beam of electromagnetic radiation on the at least one metal layer. | 2010-02-25 |
| 20100047997 | METHOD FOR MANUFACTURING SOI SUBSTRATE - It is an object of the preset invention to increase adhesiveness of a semiconductor layer and a base substrate and to reduce defective bonding. An oxide film is formed on a semiconductor substrate and the semiconductor substrate is irradiated with accelerated ions through the oxide film, whereby an embrittled region is formed at a predetermined depth from a surface of the semiconductor substrate. Plasma treatment is performed on the oxide film on the semiconductor substrate and the base substrate by applying a bias voltage, the surface of the semiconductor substrate and a surface of the base substrate are disposed opposite to each other, a surface of the oxide film is bonded to the surface of the base substrate, heat treatment is performed after the surface of the oxide film is bonded to the surface of the base substrate, and separation is caused along the embrittled region, whereby a semiconductor layer is formed over the base substrate with the oxide film interposed therebetween. | 2010-02-25 |
| 20100047998 | MANUFACTURING METHOD OF SUBSTRATE PROVIDED WITH SEMICONDUCTOR FILMS - A plurality of rectangular single crystal semiconductor substrates are prepared. Each of the single crystal semiconductor substrates is doped with hydrogen ions and a damaged region is formed at a desired depth, and a bonding layer is formed on a surface thereof. The plurality of single crystal substrates with the damaged regions formed therein and the bonding layers formed thereover are arranged on a tray. Depression portions for holding the single crystal semiconductor substrates are formed in the tray. With the single crystal semiconductor substrates arranged on the tray, the plurality of single crystal semiconductor substrates with the damaged regions formed therein and the bonding layers formed thereover are bonded to a base substrate. By performing heat treatment and dividing the single crystal semiconductor substrates along the damaged regions, the plurality of single crystal semiconductor layers that are sliced are formed over the base substrate. | 2010-02-25 |
| 20100047999 | WORKING METHOD FOR AN OPTICAL DEVICE WAFER - A dividing method for an optical device wafer includes a protective plate adhering step of releasably adhering the surface of an optical device wafer to the surface of a protective plate, a reverse face grinding step of grinding the reverse face of the optical device wafer, a dicing tape sticking step of sticking the reverse face of the optical device wafer on the surface of a dicing tape, a protective plate grinding step of grinding the reverse face of the protective plate adhered to the optical device wafer stuck on the dicing tape so as to have a predetermined thickness, a laser working step of irradiating a laser beam upon the protective plate along the streets formed on the optical device wafer to carry out laser working, which forms break starting points along the streets, for the protective plate, and a wafer dividing step of applying external force to the protective plate to break the protective plate along the break starting points to break the optical device wafer along the streets thereby to divide the optical device wafer into the individual optical devices. | 2010-02-25 |
| 20100048000 | METHOD OF MANUFACTURING SEMICONDUCTOR CHIPS - A semiconductor wafer is prepared. The wafer has a first and a second surface opposite to each other, and has a recess portion and a rim portion. The semiconductor wafer has semiconductor elements formed on the first surface. The rim portion surrounds the recess portion. The recess portion and the rim portion are composed of the first and second surfaces. The recess portion is formed so as to recede toward the first surface. A tape is adhered to the second surface of the semiconductor wafer. At least the recess portion of the semiconductor wafer is placed on a stage. The tape is sandwiched between the recess portion and the stage. Laser beam is irradiated to the recess portion from the side of the first surface and along predetermined dicing lines. The recess portion is cut off to divide the semiconductor wafer into chips. | 2010-02-25 |
| 20100048001 | PLASMA DICING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR CHIPS - A plasma dicing apparatus in which a semiconductor wafer with a protective sheet stuck thereonto covering the entire circuit-forming surface and with an etching-resistant mask member stuck on the back surface opposite to the circuit-forming surface is mounted on a mounting stage; plasma etching is performed using the mask member as a mask; and the semiconductor wafer is diced into plural semiconductor chips. The plasma dicing apparatus includes a ring-shaped frame member retaining the outer circumference of the mask member extending off the outer circumference of the semiconductor wafer. The mounting stage is composed of a wafer supporting part supporting a semiconductor wafer and a frame member supporting part supporting the frame member. This facilitates carrying a semiconductor wafer into and out of the vacuum chamber. | 2010-02-25 |
| 20100048002 | SILICON NITRIDE LAYER FOR LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE USING THE SAME, AND METHOD OF FORMING SILICON NITRIDE LAYER FOR LIGHT EMITTING DEVICE - Provided are a silicon nitride layer for a light emitting device, light emitting device using the same, and method of forming the silicon nitride layer for the light emitting device. The silicon nitride layer of the light emitting device includes a silicon nitride matrix and silicon nanocrystals formed in the silicon nitride matrix. A light emitting device manufactured by the silicon nitride layer has a good luminous efficiency and emits light in the visible region including the short-wavelength blue/violet region and the near infrared region. | 2010-02-25 |
| 20100048003 | Plasma processing apparatus and method thereof - A plasma processing apparatus using a capacitive coupled plasma (CCP) source requiring a low pressure range of about 25 mT or less and a method thereof are disclosed. Plasma source power may be applied in a pulse mode to either one of upper and lower electrodes in a chamber, which generates plasma and processes a semiconductor substrate, and plasma maintaining power may be continuously applied to the other of the upper and lower electrodes, such that a stable pulse plasma process may be performed in a low pressure range of about 25 mT or less. | 2010-02-25 |
| 20100048004 | SEMICONDUCTOR DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A production method for a semiconductor device includes the steps of: (a) providing a semiconductor substrate having a semiconductor layer | 2010-02-25 |
| 20100048005 | PREPARATION OF ULTRA-SHALLOW SEMICONDUCTOR JUNCTIONS USING INTERMEDIATE TEMPERATURE RAMP RATES AND SOLID INTERFACES FOR DEFECT ENGINEERING - Described herein are processing conditions, techniques, and methods for preparation of ultra-shallow semiconductor junctions. Methods described herein utilize semiconductor surface processing or modification to limit the extent of dopant diffusion under annealing conditions (e.g. temperature ramp rates between 100 and 5000° C./second) previously thought impractical for the preparation of ultra-shallow semiconductor junctions. Also described herein are techniques for preparation of ultra-shallow semiconductor junctions utilizing the presence of a solid interface for control of dopant diffusion and activation. | 2010-02-25 |
| 20100048006 | PHOSPHOROUS-COMPRISING DOPANTS AND METHODS FOR FORMING PHOSPHOROUS-DOPED REGIONS IN SEMICONDUCTOR SUBSTRATES USING PHOSPHOROUS-COMPRISING DOPANTS - Phosphorous-comprising dopants, methods for forming phosphorous-doped regions in a semiconductor material, and methods for fabricating phosphorous-comprising dopants are provided. In one embodiment, a phosphorous-comprising dopant comprises a phosphorous source comprising a phosphorous-comprising salt, a phosphorous-comprising acid, phosphorous-comprising anions, or a combination thereof, an alkaline material, cations from an alkaline material, or a combination thereof, and a liquid medium. | 2010-02-25 |
| 20100048007 | HIGH PLANARIZING METHOD FOR USE IN A GATE LAST PROCESS - A method for performing a chemical-mechanical polishing (CMP) is provided. The method includes processing a semiconductor substrate to form a dummy gate structure on the substrate, to form a hard mask on the dummy gate structure, and to form a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer on the hard mask, performing a first CMP process with a first slurry to modify a non-planar topography of the ILD layer, performing a second CMP process with a second slurry to remove the hard mask, and performing a third CMP process with a third slurry to remove an interfacial layer that forms between the dummy gate and hard mask during semiconductor processing. | 2010-02-25 |
| 20100048008 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a recess with a device separating film and a first hard mask layer so that a pad nitride film for defining a recess gate region may remain with a conventional mask. The method additionally the recess gate region to facilitate a subsequent process for etching a gate electrode without a step difference between the device separating film. | 2010-02-25 |
| 20100048009 | METHOD OF FORMING ALUMINUM-DOPED METAL CARBONITRIDE GATE ELECTRODES - A method for forming an aluminum-doped metal (tantalum or titanium) carbonitride gate electrode for a semiconductor device is described. The method includes providing a substrate containing a dielectric layer thereon, and forming the gate electrode on the dielectric layer in the absence of plasma. The gate electrode is formed by depositing a metal carbonitride film, and adsorbing an atomic layer of an aluminum precursor on the metal carbonitride film. The steps of depositing and adsorbing may be repeated a desired number of times until the aluminum-doped metal carbonitride gate electrode has a desired thickness. | 2010-02-25 |
| 20100048010 | SEMICONDUCTOR DEVICE GATE STRUCTURE INCLUDING A GETTERING LAYER - A method is provided that allows for maintaining a desired equivalent oxide thickness (EOT) by reducing the thickness of an interfacial layer in a gate structure. An interfacial layer is formed on a substrate, a gate dielectric layer such as, a high-k gate dielectric, is formed on the interfacial layer. A gettering layer is formed on the substrate overlying the interfacial layer. The gettering layer may function to getter oxygen from the interfacial layer such that the interfacial layer thickness is decreased and/or restricted from growth. | 2010-02-25 |
| 20100048011 | METHOD OF PATTERNING A METAL GATE OF SEMICONDUCTOR DEVICE - Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process. | 2010-02-25 |
