08th week of 2010 patent applcation highlights part 32 |
Patent application number | Title | Published |
20100046216 | Hot-Melt Glass Pillar Lamp and Multi-Channel Heat Dissipation Method Thereof - A hot-melt glass pillar lamp and a multi-channel heat dissipation method thereof; the pillar lamp comprises a base, a hollow steel frame which is mounted on the middle of the base, several sections of pillar-shaped hot-melt glass lamp which surround the steel frame and are sequentially arranged on the base from down to up in an overlapping manner, and a lamp cover with air outlets, wherein, each section of the pillar-shaped hot-melt glass lamp comprises a fixing framework which is composed of a plurality of supporting bars and a supporting board; each surface of the fixing framework is separately provided with a hot-melt glass lamp plate; an LED lamp plate is arranged at a certain distance from the inner side of each hot-melt glass lamp plate, and on the corresponding surface of the steel frame. The present invention integrates the semiconductor lighting and the crystal optical refraction technologies, has ideal lighting effect and landscape ornament effect; and the pillar lamp is internally provided with at least one air convection channel from down to up, thereby being greatly convenient for the air convection heat dissipation of the power part and the luminous body in the pillar lamp, ensuring a long-term safe use, and meeting the decorative lighting demands of modern high grade buildings. | 2010-02-25 |
20100046217 | OPTICAL SYSTEM AND METHOD FOR MANAGING BRIGHTNESS CONTRASTS BETWEEN HIGH BRIGHTNESS LIGHT SOURCES AND SURROUNDING SURFACES - An optical system and method provides at least one, and preferably an array of relatively small, high brightness light sources with a surrounding surface that exhibits brightness, thereby reducing the contrast between the high brightness produced by the light sources and the brightness of their surrounding surfaces. The optical system includes a light waveguide structure that captures a portion of the light from the individual high-brightness light sources, and then re-emits the source light to create brightness in the light sources' surrounding surfaces. The optical system is particularly adapted for use with LEDs, but could be used with other high brightness light sources. | 2010-02-25 |
20100046218 | LIGHT SOURCE ASSEMBLY - A light source assembly includes a light guide unit and a light emitting unit. The light guide unit includes a hollow enclosure and a lens unit enclosed in the enclosure. The enclosure has a top portion, a bottom portion and a sidewall connected between the bottom portion and the top portion. Protrusions extend from an outer surface of the sidewall and coil the sidewall. A light incident surface is positioned on the bottom portion. The lens unit extends from the bottom portion towards the top portion and has a inverted-frustoconical-shaped light guide portion. A inverted-conical-shaped groove is defined in a topmost portion of the light guide portion. A reflective surface is positioned on an inner wall of the groove. A refractive surface is positioned on an outer surface of the light guide portion and intersects the reflective surface. The light emitting unit is positioned adjacent to the light incident surface. | 2010-02-25 |
20100046219 | LIGHT GUIDE AND LIGHT-OUTPUT DEVICE - A light guide ( | 2010-02-25 |
20100046220 | LED UNIT AND LED LIGHTING LAMP USING THE LED UNIT - The present invention is an LED unit having a thermal-release structure including a base having high thermal conductivity, a circuit board which includes a wiring pattern and is provided on the base, at least one LED element which is electrically connected to the wiring pattern and disposed on the base, and a light-transmitting resinous body provided to cover above the base to seal the LED element. | 2010-02-25 |
20100046221 | LED Source Adapted for Light Bulbs and the Like - A light source and method for making the same are disclosed. The light source includes a housing, a drive assembly, and an LED. The housing has an interior compartment enclosed in an outer surface having a heat dissipating surface and first and second power terminals that are accessible from outside the interior compartment. The drive assembly is located in the interior compartment and electrically connected to the first and second power terminal. The LED is directly attached to the heat dissipating surface and electrically insulated therefrom, the LED having first and second LED power contacts. The housing has first and second housing power terminals disposed outside the housing, electrically isolated from the heat-dissipating surface, and connected to the drive assembly. A first conductor connects the first LED power contact to the first housing power terminal. A second conductor connects the LED second power contact to the second housing power terminal. | 2010-02-25 |
20100046222 | LIGHT EMITTING DIODE LAMP TUBE - An LED lamp tube is applied to satisfy a light source requirement and is used primarily to replace an existing conventional lamp tube, achieving an energy saving requirement. Plural LEDs are used as a luminous source which is assembled in a light permeable tube body, fitted with a drive circuit control module, so as to form the LED lamp tube. In addition, the LED lamp tube can be connected serially in plural sets depending on a length of the tube body, so as to comply with a light source requirement in various environments. | 2010-02-25 |
20100046223 | LED LAMP ASSEMBLY - The present invention relates to lighting assemblies and more particularly to light emitting diode (LED) light bulbs comprising a support for one or more LED lenses, which can be used to position and support the lenses within the lamp housing and which facilitate assembly of the light bulbs during manufacturing. | 2010-02-25 |
20100046224 | ILLUMINATION DEVICE - An illumination device includes a circuit board unit having positioning hole units corresponding respectively to LEDs mounted thereon. Each positioning hole unit includes a first positioning hole, and a second positioning hole having a diameter larger than that of the first positioning hole. A lamp seat has positioning post units corresponding respectively to the positioning hole units in the circuit board unit. Each positioning post unit includes a first positioning post, and a second positioning post having a width larger than that of the first positioning post. When the circuit board unit is mounted on the lamp seat, the first and second positioning posts of each positioning post unit respectively extend through and engage the first and second positioning holes of a corresponding positioning hole unit in the circuit board unit, thereby positioning the circuit board unit to the lamp seat. | 2010-02-25 |
20100046225 | LED LAMP - An LED lamp includes a frame having a bottom surface, a plurality of heat sinks, and a plurality of LED modules. Each of the heat sinks has an engaging surface defined at an acute angle with respect to the bottom surface of the frame. Each of the LED modules is attached on the engaging surface of the heat sink. The heat sinks are rotatable relative to the frame to adjust the angle of the engaging surface of the heat sinks with respect to the bottom surface of the frame, providing variable area and intensity of illumination. | 2010-02-25 |
20100046226 | Light Fixture With An Adjustable Optical Distribution - A light fixture includes a member having a substantially frusto-conical shape. A channel extends between a wide top end of the member and a narrower bottom end of the member. The member includes multiple surfaces (“facets”) disposed around its outer surface. Each facet is configured to receive one or more light emitting diodes (“LEDs”) in a linear or non-linear array. Each facet can be integral to the member or coupled to the member. The channel is configured to transfer heat generated by the LEDs through convection. Fins can be disposed within the channel, extending from the inner surface of the member to an inner channel. The fins are configured to transfer heat away from, and provide a greater surface area for convecting heat away from, the member. For example, one or both of the channels can transfer heat by a venturi effect. | 2010-02-25 |
20100046227 | FINITE ELEMENT AND MULTI-DISTRIBUTION LED LUMINAIRE - A luminaire comprised generally of a mounting plate including a plurality of mounting blocks secured to the mounting plate; and a plurality of LEDs, wherein at least one of the LEDs is positioned upon each of the mounting blocks. The mounting blocks include face portions and may be arranged in a plurality of configurations on the mounting plate. | 2010-02-25 |
20100046228 | COMBINATION SIGNAL RECEIVING DEVICE - A combination signal receiving device includes a printed circuit board, a light source, a light cover, a receiving cover, and at least one signal receiver. The light source is mounted on the printed circuit board. The light cover is lighttight except a light transmissive logo. The light cover covers the light source. The receiving cover surrounds the light cover. The signal receiver is mounted on the printed circuit board beneath the receiving cover, configured for receiving outside signal passing through the receiving cover. Light emitted by the light source is incapable of reaching the signal receiver. The combination signal receiving device does not negatively influence the appearance of an electronic apparatus. | 2010-02-25 |
20100046229 | ARTIFICIAL LIGHT SOURCE GENERATOR - An artificial light source generator includes at least one luminescent set and a projection plane. The luminescent set includes a light source, a parabolic mirror, a supporting seat, a first lens array, and a second lens array. The light source is disposed at the focus of the parabolic mirror, so that light beams generated by the light source are transmitted in a parallel direction through the parabolic mirror. The supporting seat is for supporting the light source. The first lens array has a plurality of first lens units, and each of the first lens units has a first focal distance. The second lens array has a plurality of second lens units. The distance between the second lens array and the first lens array is 0.5 to 1.5 times the first focal distance. A suitable distance exists between the projection plane and the luminescent set, so that the light beams passing through each of the second lens units cover the entire projection plane. Therefore, the projection plane has excellent illumination uniformity. | 2010-02-25 |
20100046230 | LED LAMP - An LED lamp ( | 2010-02-25 |
20100046231 | LED COOLING SYSTEM - The invention relates to a LED cooling system that effects cooling of the LED's during use, and helps the LED's have a longer operating function, and uses less electricity for the LED's to operate. The use of cooling also provides a steadier light and has greater efficiency. | 2010-02-25 |
20100046232 | LIGHT EMITTING MODULE, LIGHTING DEVICE AND DISPLAY DEVICE - A lighting device includes a heatsink | 2010-02-25 |
20100046233 | LED lighting apparatus - A LED light apparatus includes a conical reflection housing and a LED light source. The reflection housing has a vertex, a light opening aligning with the vertex, an inner flat reflection surface. The LED light source includes a light head alignedly pointing towards the vertex, wherein when the light head generates light a first portion of the light is accumulatively reflected by the reflection surface towards the light opening while a second portion of the light is projected towards the non-reflection arrangement to prevent the second portion of the light being reflected back to the light source for minimizing a black spot occurring at the light opening. Accordingly, the wide light pattern is refocused into a narrow beam pattern to improve the lighting efficiency. The distribution of the light output is regulated, and the heat generation is reduced. | 2010-02-25 |
20100046234 | Illumination Systems Utilizing Wavelength Conversion Materials - A wavelength conversion material with an omni-directional reflector is utilized to enhance the optical efficiency of an illumination system. Light guides with restricted output apertures, micro-element plates and optical elements are utilized to enhance the brightness of delivered light through light recycling. In addition, micro-element plates may be used to provide control over the spatial distribution of light in terms of intensity and angle. Efficient and compact illumination systems are also disclosed. | 2010-02-25 |
20100046235 | WINDOW, IN PARTICULAR A WINDOW FOR AN AIRCRAFT CABIN - Such a window is intended to be assembled over an opening ( | 2010-02-25 |
20100046236 | SHEET AND LIGHT EMITTING DEVICE - A sheet and a light emitting device are provided which also emit light having an incident angle larger than or equal to a critical angle to significantly increase light extraction efficiency, prevent ambient light reflection, and suppress the occurrence of a distribution of light intensity varying depending on the direction and an imbalance in color. The light emitting device has a surface structure ( | 2010-02-25 |
20100046237 | Combinational LED lamp - A combinational LED lamp includes an insulating housing, a first conductive contact, a second conductive contact, and an LED body. The insulating housing includes a first engaging surface with a first engaging portion and a second engaging surface with a second engaging portion. The first engaging portion is engaged with the second engaging portion. The two conductive contacts are all fixed on the insulating housing. Both the two conductive contacts include an integral internal section and two exposure sections exposing at the first engaging surface and the second engaging surface of the insulating housing. Two terminals of the LED body are each electrically connected with the internal section of the first conductive contact and of the second conductive contact. Therefore, multiple LED-lamp units can be incorporated so as to form various configurations of LED-lamp combinations. | 2010-02-25 |
20100046238 | Outer shell structure of a decoration lamp string - A kind of outer shell structure of a decoration lamp string mainly are two or more than two flowered shells linked together on a foundation, it is then jointed with a light bulb group which is sleeve-fit a lamp stand with a linking seat. The linking seat is internally connect-set with a light bulb. The said outer shell uses the foundation to be insert-connected with the linking seat and covers the light bulb to form an outer shell of light bulb with several flowered shell linking bodies such that the light of light bulb generates more light illustrating faces through this outer shell to let the light source generated by a single light bulk becomes more dazzling shining. Simultaneously, it is hard to be overheated due to the increasing space in covering light bulb, and its life of usage is increased. | 2010-02-25 |
20100046239 | LAMP HOUSING - A lamp housing includes a top plate and sidewalls. The top plate includes a first edge, a second edge, a first group of top-plate dissipation slots and a plurality of second top-plate dissipation slots. The first edge is opposite to the second edge. Each top-plate dissipation slot has the same width, and is rectangular. Each one of the plurality of first top-plate dissipation slots is separated by two widths thereof, and each of the plurality of second top-plate dissipation slots is separated by two widths thereof. The plurality of first top-plate dissipation slots is parallel and 20 to 24 slot widths away from the first edge toward the center of the top plate, and the plurality of second dissipation slots is parallel and 14 to 18 slot widths away from the second edge. A plurality of sidewall dissipation slots is provided on the sidewalls. | 2010-02-25 |
20100046240 | DECORATIVE SLEEVE FOR FLAMELESS CANDLE - A removable, decorative sleeve for wax-surfaced flameless candles comprising a cylindrical, open-ended form wherein the form is made of one or more preferably overlapping layers of a flexible, transparent or translucent material such as, but not limited to, plastic laminate. The sleeve is decorated in a manner such that the light emitting from the flameless candle passes through the form and serves to accentuate the decoration. Once applied, the sleeve remains in place substantially by friction between the form and the wax surface of the flameless candle. | 2010-02-25 |
20100046241 | SYSTEMS AND METHODS FOR AIRCRAFT LED ANTI COLLISION LIGHT - Aircraft anti-collision light (ACL) systems and methods are operable to emit light from light emitting diode (LED) lamps. An exemplary embodiment includes a housing, a plurality of LED lamps within the housing and configured to emit light in a direction substantially perpendicular to the direction of light emitted from the ACL, and a reflector within the housing that is configured to reflect the light received from the plurality of LED lamps in the direction of light emitted from the ACL. | 2010-02-25 |
20100046242 | High efficiency light pipe - H.E.L.P. - A headlamp assembly which includes an optic used for providing a turn signal which meets the government requirements for luminous intensity when the turn signal is located near or next to the headlamp assembly. The present invention is a headlamp assembly which includes a housing, at least one optic disposed within the housing, as well as at least one light source which is operable with the optic such that light is emitted from the optic which meets or exceeds present regulatory requirements. The present invention also includes an outer lens mounted on the housing such that light emitted from the optic passes through the outer lens. | 2010-02-25 |
20100046243 | Vehicle Lighting Unit and Vehicle Light - A vehicle lighting unit can include a first reflector surface and a second reflector surface disposed vertically with the optical axis of an LED light source interposed therebetween. The first reflecting surface and the second reflecting surface can form respective light distribution patterns. The first reflecting surface can include an edge near the projection lens formed in a substantially elliptic shape and designed so as to take an aberration of the projection lens into consideration. The edge can be disposed so as to coincide with a focus group of the projection lens. The second reflecting surface can be formed to have a substantially conical curved surface or a curved surface having at least a part of a cross section of a substantially conical curved surface. Direct light emitted from the LED light source and passing through/between the first reflecting surface and the second reflecting surface can form a light distribution pattern. | 2010-02-25 |
20100046244 | VEHICLE LAMP UNIT - There is provided a vehicle lamp unit. The vehicle lamp includes: a projection lens disposed on an optical axis extending in a vehicle longitudinal direction; a semiconductor light emitting element comprising a light emitting surface having an almost rectangular shape and disposed behind a rear focal point of the projection lens such that a long side of the light emitting surface is substantially perpendicular to the optical axis; and a reflector comprising a reflection surface having an almost oval shape. A first focal point of the reflector is located on the rear focal point of the projection lens, and a second focal point of the reflector is located on the semiconductor light emitting element, and a minimum distance between the reflection surface and a rear corner portion of the light emitting surface is in a range of about 0.3 millimeters (mm) to about 3 mm. | 2010-02-25 |
20100046245 | System and Method for Heat Dissipation from an Automotive Lighting Assembly Having a Liquid Cooling Circuit - An automotive headlamp assembly having a closed-loop cooling circuit. The headlamp assembly includes a housing cooperating with a transparent lens cover to define a chamber. At least one light source is located within the chamber. The cooling circuit has at least one cold plate thermally coupled to the light source. A radiator is fluidly coupled to the cold plate by a plurality of tubes. The tubes are oriented at least partially upwardly and configured to circulate a fluid through the cooling circuit as a result of heating and cooling of the fluid therein. | 2010-02-25 |
20100046246 | ILLUMINATING TEXTILE WEB, CONVERSION PROCESS, AND LUMINOUS DEVICE COMPRISING A PLURALITY OF ILLUMINATING REGIONS - A textile web for producing a luminous device includes a plurality of contiguous illuminating regions that can be selectively turned on or turned off. The-web incorporates adjacent optical fibres designed to emit, laterally, the light that passes through them. Each optical fibre is, over its length and from one illuminating region to another, alternately woven and then not woven with binding yarns, the alternation of the weaving and the non-weaving of the optical fibres with the binding yarns being reversed between two adjacent groups of at least one optical fibre, so as to define, for each illuminating region, a top side including an illuminating web of optical fibres woven with the binding yarns and a reverse face including a float of optical fibres that are offset in a plane approximately parallel to the illuminating web. | 2010-02-25 |
20100046247 | LIGHT GUIDE DEVICE - A light guide device is provided in an embodiment of the invention. The light guide device comprises a light guide plate and a light source provided on a side surface of the light guide plate. A light guide strip is provided on a side surface of the light guide plate intersecting with the side surface provided with the light source. A side surface of the light guide strip facing the light guide plate is a light exit surface of the light guide strip, a side surface of the light guide strip opposite to the light exit surface is a reflective surface of the light guide strip, and an end surface of the light guide strip adjacent to the light source is a light entrance surface of the light guide strip. | 2010-02-25 |
20100046248 | OPTIC FILM AND BACKLIGHT MODULE USING SAME - An optic film includes a substrate and a condensation layer. The substrate has a light incidence surface and a light emission surface. The light incidence surface is treated to form a roughened frosted surface. The condensation layer is arranged on the light emission surface of the substrate and forms prism-like micro-structures. With the light incidence surface of the substrate being directly subjected to knurling or sand blasting to form the roughened frosted surface, when light enters the substrate through the light incidence surface, the light is diffused first by the frosted surface of the light incidence surface and is then subjected to condensation by the condensation layer, whereby when the optic film is applied to a backlight module, the optic film can effect both diffusion and condensation of light, so that the number of optic films used in the backlight module can be reduced. | 2010-02-25 |
20100046249 | OPTIC FILM AND BACKLIGHT MODULE USING SAME - An optic film includes a body and a condensation layer. The body is formed by stacking a plurality of substrates made of different materials. By means of the different physical characteristics of the different materials, the optic film realizes excellent optic performance. Also provided is a backlight module using the optic film. | 2010-02-25 |
20100046250 | DC-DC CONVERTER - A DC-DC converter includes a switching transistor connected to an inductor and a power input terminal, with the inductor connected to an output terminal, a synchronous rectification transistor connected to a junction node therebetween, a first electric current detector to detect whether or not an electric current flowing through the synchronous rectification transistor is larger than a first electric current, a second electric current detector to detect whether or not the electric current flowing through the synchronous rectification transistor is larger than a second electric current that is larger than the first electric current, and a selection mechanism to select one of the first and second electric current detectors in accordance with a control signal. The synchronous rectification transistor is turned off by outputting an output signal the selected current detector. | 2010-02-25 |
20100046251 | MULTIPLE-OUTPUT SWITCHING POWER SOURCE APPARATUS - A multiple-output switching power source apparatus has a series resonant circuit connected in parallel with a switch Q | 2010-02-25 |
20100046252 | APPARATUS FOR SUPPLYING ISOLATED REGULATED DC POWER TO ELECTRONICS DEVICES - Embodiments of the invention provide an off line DC-DC converter comprising a transformer ( | 2010-02-25 |
20100046253 | Control Circuit for a Switched-Mode Power Supply with Regulation Based on the Secondary-Side Current Flow Time Period - A control circuit for a primary controlled switched-mode power supply that has a primary-side switch and a transmitter. It also relates to an associated switched-mode power supply. The control circuit can be connected to a control input of the primary-side switch so that the primary-side switch is controlled based on a secondary-side current flow time period in which a current flows through the secondary-side winding of the transmitter in order to regulate the output voltage. The secondary-side current flow time period can be used as a control parameter instead of the actual output voltage in order to then control the primary-side switch. Because the secondary-side current flow time period can be determined indirectly on the primary side, no direct feedback is necessary between the output voltage on the secondary side and the control circuit on the primary side. | 2010-02-25 |
20100046254 | ENERGY EFFECTIVE SWITCHING POWER SUPPLY APPARATUS AND AN ENERGY EFFECTIVE METHOD THEREOF - An energy effective switching power supply apparatus and an energy effective method thereof. The energy effective switching power supply apparatus includes a power transforming part having first and second coils to induce a voltage to the second coil using interactions between the first and the second coils with respect to the input voltage, a power outputting part to output a sensing signal when it is determined that a first DC voltage output by rectifying and smoothing the voltage induced to the second coil is greater than or equal to a reference voltage level, and a switching controlling part to adjust a switching frequency of a switching device to interrupt a current flowing in the first coil of the power transforming part when the sensing signal is received. Accordingly, a switching loss is controlled and an energy loss is reduced. | 2010-02-25 |
20100046255 | HVDC SYSTEM - An HVDC network including a first station including a first converter, a second station including a second converter, each converter including non-extinguishable semiconducting elements. A first transmission conductor and a second transmission conductor. The first station includes a first switching arrangement. | 2010-02-25 |
20100046256 | Rush Current Reduction Circuit and Electric Appliance - An output node at a plus side of a diode bridge (DB | 2010-02-25 |
20100046257 | Apparatus and method for controlling power converter - A power converter controlling apparatus that can prevent burnout caused by overcurrent and/or overvoltage generated by low power index operation or output short circuit in a high frequency power converter employing a digital controlling method, and a method thereof. The power converter controlling apparatus includes a digital controller which outputs a gate signal for controlling intermittent operation of a predetermined switch based on inputted control data, a detector which generates a detection signal in response to generation of overcurrent and/or overvoltage, and a registration maintenance unit for maintaining a state where the output of the gate signal is shut off, when the detection signal is generated. | 2010-02-25 |
20100046258 | POWER SUPPLY CONTROL SYSTEM - A digital control system for a switch mode power supply (SMPS), the control system having a demand input for a signal indicating whether an output voltage of said SMPS is above or below a desired value, and a drive output for a switch controlling energy transfer between an input and an output of said SMPS during a power switching cycle, the control system further including: a signal processor coupled to said demand input and to said drive output to control said drive output responsive to said demand signal to regulate said output voltage at said desired value, and wherein said signal processor includes at least one storage element to store at least one value of said demand signal, and wherein said switching control signal for a said power switching cycle is responsive to a value of said demand signal in at least two previous power switching cycles. | 2010-02-25 |
20100046259 | SINGLE-PHASE SELF-DRIVEN FULL-BRIDGE SYNCHROUNOUS RECTIFICATION - A full-bridge rectifier is configured to provide synchronous rectification with either a current-source or a voltage-source. The rectifier has an upper branch and a lower branch and two current loops, with each of the branches including voltage- or current-controlled active switches, diodes or combinations thereof that are selected such that each loop includes one active switch or diode from the upper branch and one active switch or diode from the lower branch, and each current loop comprises at least one diode or current-controlled active switch, and at least one voltage- or current-controlled active switch is included in one of the upper or lower branches. | 2010-02-25 |
20100046260 | Feeding of output-side parallel connected bridge rectifiers with phase-shifted voltages from the secondary windings of at least one transformer - A device is disclosed for generating DC voltage from AC voltage. The device includes parallel connected diode bridges which are fed via at least one transformer, the primary windings of which are connected in series. The DC voltage is used for supplying DC paths, and secondary voltages on the secondary windings of the transformer have different phase angles. This is achieved in at least the embodiment, e.g., by the fact that one secondary winding is connected in a delta configuration, and another secondary winding is connected in a star configuration. | 2010-02-25 |
20100046261 | Apparatus and Method for Zero-Voltage Region Detection - An apparatus and a method for detecting zero-voltage region detection are provided. The apparatus for zero-voltage region detection is configured to detect whether an input voltage approaches a zero voltage through an auxiliary winding, and to detect whether a primary winding almost completely releases the stored energy through the auxiliary winding. | 2010-02-25 |
20100046262 | Control Apparatus and Control Method for a Power Factor Correction Power Converter - A control apparatus and a control method for a power factor correction power converter are provided. The control apparatus is configured to reduce the variation rate of a reference signal with a rising portion and a falling portion. When the primary winding almost completely releases the stored energy, and the falling portion of the reference signal reaches a determined condition, the control apparatus turns on a switch for increasing the stored energy of the primary winding. | 2010-02-25 |
20100046263 | RECTIFIER CIRCUIT WITH A VOLTAGE SENSOR - A rectifier circuit with a synchronously controlled semiconductor element comprising at least one field effect transistor with a control electrode and two switching electrodes. The control electrode operates the reverse state and the forward state between the switching electrodes. For this, the rectifier circuit comprises at least one driver which cooperates with a voltage sensor of the field effect transistor. During the diode operating state of the field effect transistor, the driver operates this to the forward state. The voltage sensor thereby forms at least one part of a non-linear voltage divider which comprises at least one monolithically integrated measuring capacitance. | 2010-02-25 |
20100046264 | GENERALIZED AC-DC SYNCHRONOUS RECTIFICATION TECHNIQUES FOR SINGLE- AND MULTI-PHASE SYSTEMS - Various circuit configurations and topologies are provided for single and multi-phase, single-level or multi-level, full and half-bridge rectifiers in which diodes are replaced by combinations of voltage-controlled self-driven active switches, current-controlled self-driven active switches and inductors in order to reduce the effects of conduction loss in the diodes. | 2010-02-25 |
20100046265 | Separate CAM Core Power Supply For Power Saving - A CAM system includes an integrated circuit chip having: logic & control circuitry, a CAM cell array, read/write access circuitry that performs read and write accesses to the CAM cell array, comparison access circuitry that performs comparison operations to the CAM cell array, a first voltage supply pad coupled to the read/write access circuitry; and a second voltage supply pad coupled to the comparison access circuitry. A first voltage supply, external to the integrated circuit chip, provides a first supply voltage to the first voltage supply pad, wherein the logic & control circuitry is powered by the first supply voltage. A second voltage supply, external to the integrated circuit chip, provides a second supply voltage to the second voltage supply pad, wherein at least a portion of the comparison access circuitry is powered by the second supply voltage, wherein the second supply voltage is less than the first supply voltage. | 2010-02-25 |
20100046266 | High Speed Memory Architecture - Memory devices and memory modules are disclosed. In one embodiment, a memory device includes a semiconductor substrate having a first edge and a second edge opposed to the first edge. A plurality of memory banks is disposed at a central portion of the semiconductor substrate, each memory bank including a plurality of memory cells. A plurality of input/output contacts is disposed between the first edge and the memory banks. Delay locked loop circuitry is disposed adjacent the first edge. A plurality of address and command contacts is disposed between the second edge and the memory banks. | 2010-02-25 |
20100046267 | MEMORY SYSTEM WITH SECTIONAL DATA LINES - A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. The blocks are grouped into bays. The storage system includes array lines of a first type in communication with storage elements, array lines of a second type in communication with storage elements, and sense amplifiers. Each block is geographically associated with two sense amplifiers and all blocks of a particular bay share a group of sense amplifiers associated with the blocks of the particular bay. The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay. | 2010-02-25 |
20100046268 | MAGNETIC RACETRACK WITH CURRENT-CONTROLLED MOTION OF DOMAIN WALLS WITHIN AN UNDULATING ENERGY LANDSCAPE - A method for use with a magnetic racetrack device includes placing domain walls having a first structure and domain walls having a second, different structure along the racetrack at stable positions corresponding to different regions within the device. The domain walls having the first structure and the domain walls having the second structure occupy alternating positions along the racetrack. A current pulse is applied to the racetrack, so that each of the domain walls moves to an adjacent region. This results in a transformation of the domain walls having the first structure into domain walls having the second structure, and vice versa. The first structure may be a vortex structure and the second structure may be a transverse structure. | 2010-02-25 |
20100046269 | Programmable read only memory - An array of memory cells is disclosed. The memory cell includes a fuse and at least one transistor. The transistor is used to control the programming or sensing of the fuse. A program voltage is applied to a stack of first and second conductive layers. A first portion of the stack couples the program voltage to a terminal of the transistor in a cell. A second portion of the stack couples the program voltage to a terminal of the transistor in another cell. | 2010-02-25 |
20100046270 | RESISTANCE VARIABLE MEMORY APPARATUS - A resistance variable memory apparatus ( | 2010-02-25 |
20100046271 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND METHOD OF WRITING DATA INTO SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a semiconductor memory device including a ferroelectric random access memory serving as a ROM, the method comprising: writing data into the ferroelectric random access memory, the data having a polarity opposite to that of ROM data; performing bake processing for a predetermined time period; and writing the ROM data into the ferroelectric random access memory. | 2010-02-25 |
20100046272 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprising a memory cell array of cross-point type having memory cells each composed of a variable resistive element for storing information in the form of variation of the electrical resistance. The operating current in the programming operation is reduced. Main data lines (GDL | 2010-02-25 |
20100046273 | RESISTANCE CHANGE NONVOLATILE MEMORY DEVICE - Memory cells (MC) are formed at intersections of bit lines (BL) extending in the X direction and word lines (WL) extending in the Y direction. A plurality of basic array planes sharing the word lines (WL), each formed for a group of bit lines (BL) aligned in the Z direction, are arranged side by side in the Y direction. In each basic array plane, bit lines in even layers and bit lines in odd layers are individually connected in common. Each of selection switch elements ( | 2010-02-25 |
20100046274 | RESISTANCE CHANGE MEMORY - A resistance change memory includes two memory cell arrays each including a plurality of memory cells, the memory cells including variable resistive elements, two reference cell arrays provided to correspond to the two memory cell arrays, respectively, and each including a plurality of reference cells, the reference cells having a reference value, and a sense amplifier shared by the two memory cell arrays and detecting data in an accessed memory cell by use of a reference cell array corresponding to a second memory cell array different from a first memory cell array including the accessed memory cell. In reading the data, a particular reference cell in one reference cell array is always activated for an address space based on one memory cell array as a unit. | 2010-02-25 |
20100046275 | NONVOLATILE SEMICONDUCTOR STORAGE APPARATUS AND DATA PROGRAMMING METHOD THEREOF - The semiconductor storage apparatus includes a memory cell array including memory cells each having a rectifying element and a variable resistive element connected in series, the memory cells being arranged in crossing portions of a plurality of first wires and a plurality of second wires, and a control circuit configured to control charging to the first wire. The control circuit charges the first wire connected to a selected memory cell up to a first potential, and then set the first wire in a floating state. Then it charges another first wire adjacent to the first wire connected to the selected memory cell to a second potential. The potential of the first wire connected to the selected memory cell is thereby caused to rise to a third potential by coupling. | 2010-02-25 |
20100046276 | Systems and Methods for Handling Negative Bias Temperature Instability Stress in Memory Bitcells - A system and method reduce stress caused by NBTI effects by determining if a trigger event has occurred and if so inverting all input data values to the memory and all output data values from the memory during a period of time defined by the determined trigger event. In one embodiment, the trigger event is an alternate memory power-up. | 2010-02-25 |
20100046277 | Implementing Local Evaluation of Domino Read SRAM With Enhanced SRAM Cell Stability - A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, a single write data propagation input, a precharge signal, and a precharge write signal. A passgate device is connected between the complement bitline and the write data propagation input. A transistor stack is connected in series with the precharge device between the true bitline and ground. The precharge write signal disables the passgate device connected between the complement bitline and the write data propagation input during a read operation. During write operations, the precharge write signal enables the passgate device connected between the complement bitline and the write data propagation input and activates the transistor stack. | 2010-02-25 |
20100046278 | Implementing Local Evaluation of Domino Read SRAM With Enhanced SRAM Cell Stability and Enhanced Area Usage - A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, true and complement write data propagation inputs, a precharge signal, and a precharge write signal. A respective precharge device is connected between a voltage supply VDD and the true bitline and the complement bitline. A first passgate device is connected between the complement bitline and the true write data propagation input. A second passgate device is connected between the true bitline and the complement write data propagation input. The precharge write signal disables the passgate devices during a read operation. During write operations, the precharge write signal enables the passgate devices. | 2010-02-25 |
20100046279 | SEMICONDUCTOR MEMORY DEVICE AND TRIMMING METHOD THEREOF - The first power supply terminal is connected to source electrodes of the first and third transistors. The second power supply terminal is connected to source electrodes of the second and fourth transistors. | 2010-02-25 |
20100046280 | SRAM Yield Enhancement by Read Margin Improvement - A sense margin is improved for a read path in a memory array. Embodiments improve the sense margin by using gates with a lower threshold voltage in a read column multiplexer. A cross coupled keeper can further improve the sense margin by increasing a voltage level on a bit line storing a high value, thereby counteracting leakage on the “high” bit line. | 2010-02-25 |
20100046281 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cells | 2010-02-25 |
20100046282 | Cross-point magnetoresistive memory - A ferromagnetic thin-film based digital memory system having memory cells interconnected in a grid that are selected through voltage values supplied coincidently on interconnections made thereto for changing states thereof and determining present states thereof through suitable biasing of grid interconnections. | 2010-02-25 |
20100046283 | MAGNETIC RANDOM ACCESS MEMORY AND OPERATION METHOD OF THE SAME - A magnetic random access memory of the present invention includes: a plurality of first wirings and a plurality of second wirings extending in a first direction; a plurality of third wirings and a plurality of fourth wirings extending in a second direction; and a plurality of memory cells provided at intersections of the plurality of first wirings and the plurality of third wirings, respectively. Each of the plurality of memory cells includes: a first transistor and a second transistor connected in series between one of the plurality of first wirings and one of the plurality of second wirings and controlled in response to a signal on one of the plurality of third wirings, a first magnetic resistance element having one end connected to a write wiring through which the first transistor and the second transistor are connected, and the other end grounded; and a second magnetic resistance element having one end connected to the write wiring, and the other end connected to the fourth wiring. | 2010-02-25 |
20100046284 | MRAM - An MRAM comprises: a plurality of magnetic memory cells each having a magnetoresistive element; and a magnetic field application section. The magnetic field application section applies an offset adjustment magnetic field in a certain direction to the plurality of magnetic memory cells from outside the plurality of magnetic memory cells. Respective data stored in the plurality of magnetic memory cells become the same when the offset adjustment magnetic field is removed. | 2010-02-25 |
20100046285 | MULTIPLE PHASE CHANGE MATERIALS IN AN INTEGRATED CIRCUIT FOR SYSTEM ON A CHIP APPLICATION - Integrated circuits are described along with methods for manufacturing. An integrated circuit as described herein includes a plurality of memory cells on a substrate. The plurality of memory cells comprise a first set of memory cells comprising a first memory material, and a second set of memory cells comprising a second memory material. The first and second memory materials have different properties such that the first and second sets of memory cells have different operational memory characteristics. | 2010-02-25 |
20100046286 | RESISTIVE MEMORY DEVICES USING ASSYMETRICAL BITLINE CHARGING AND DISCHARGING - A nonvolatile memory device includes a plurality of memory banks, each including a plurality of nonvolatile resistive memory cells (e.g. PRAM cells). The device also includes a write global bitline shared by the memory banks and a read global bitline shared by the memory banks. The device further includes a control circuit configured to write data to a selected nonvolatile memory cell in a first memory bank using the write global bitline while reading data from a selected nonvolatile memory cell in a second memory bank using the read global bitline such that a discharge time period of the write global bitline is longer than a quenching time period of a write current which flows through the nonvolatile memory cell of the first memory bank. | 2010-02-25 |
20100046287 | SEMICONDUCTOR MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE FUNCTIONALITY INCLUDING RESISTANCE CHANGE MATERIAL AND METHOD OF OPERATING - Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described. | 2010-02-25 |
20100046288 | MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME - An MRAM according to the present invention has a pinned layer | 2010-02-25 |
20100046289 | METHOD OF READING NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING NONVOLATILE MEMORY DEVICE - A method of reading a nonvolatile memory device may include, after an n | 2010-02-25 |
20100046290 | FLASH MEMORY DEVICE AND MEMORY SYSTEM - A flash memory device includes a first switch connecting one of a first cell string and a second cell string to a first bit line selectively, a second switch connecting the second cell string to a second bit line, and a control logic circuit providing bias voltages to the first and second cell strings through the first and second bit lines respectively and controlling the first and second cell stings to be simultaneously programmed. | 2010-02-25 |
20100046291 | Process and Temperature Tolerant Non-Volatile Memory - A nonvolatile memory comprising an array of memory cells and sense amplifiers, each sense amplifier using a keeper circuit to provide an amount of current to compensate for bit line leakage current in the memory array. The amount of current from the keeper depends on the temperature of the memory and the speed of the process used to make the memory. | 2010-02-25 |
20100046292 | Non-volatile memory device and bad block remapping method - A non-volatile memory device and a bad block remapping method use some of main blocks as remapping blocks to replace a bad block in a main cell block and selects remapping blocks using existing block address signals. Thus, separate bussing of remapping block address signals is not needed. The bad block remapping includes comparing an external block address input from an external source to a stored bad block address, generating a bad block flag signal when the external block address is identical to the stored bad block address, generating a remapping block address selecting the remapping blocks in response to a remapping address corresponding to the bad block address, selecting one of the external block address and the remapping block address in response to the bad block flag signal to create a selected address, and outputting a row address signal in accordance with the selected address. | 2010-02-25 |
20100046293 | MEMORY CELL BLOCK OF NONVOLATILE MEMORY DEVICE AND METHOD OF MANAGING SUPPLEMENTARY INFORMATION - A nonvolatile memory device of a nonvolatile memory device includes a memory cell unit comprising sets of memory cells, a first supplementary information repository comprising source-side dummy cells respectively connected between source select transistors and first memory cells of the sets of the memory cells, and a second supplementary information repository comprising drain-side dummy cells respectively connected between drain select transistors and second memory cells of the sets of the memory cells. | 2010-02-25 |
20100046294 | NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A non-volatile memory device includes first and second strings memory cell transistors, related first and second word lines respectively connected to gates of the first string memory cell transistors, wherein respective first and second word lines are connected to commonly receive a bias voltage. The non-volatile memory device also includes dummy cell transistors connected to the first and second strings, and first and second dummy word lines configured to receive different bias voltages. | 2010-02-25 |
20100046295 | FAST DATA ACCESS MODE IN A MEMORY DEVICE - A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access mode, a clock delay circuit uses the clock frequency setting bits to select a delay to be added to the input clock. The higher the clock frequency, the less the added delay. The delayed clock generates FIFO control signals to control a data FIFO register. During the fast data access mode, the data is output from the data FIFO register at a faster rate than in the standard clock mode. | 2010-02-25 |
20100046296 | METHOD FOR READING AND PROGRAMMING A MEMORY - A method for programming a memory is provided. The memory includes a number of cells and has a preset PV level for a target cell. The method includes programming a first-side of the target cell to have a Vt level not lower than the preset PV level; reading a Vt level of a second-side of the target cell and accordingly obtaining a corrected PV level corresponding to the first-side; and programming the first-side of the target cell to have a Vt level not lower than the corresponding corrected PV level. | 2010-02-25 |
20100046297 | NON-VOLATILE MEMORY AND METHOD FOR RAMP-DOWN PROGRAMMING - A ramp-down programming voltage is used to program a group of nonvolatile memory cells in parallel, step by step from a highest step to a lowest step. Overall programming time is improved when a conventional setup for program inhibit together with a verify after each program step are avoided. A program voltage estimate is provided for each cell indicating the programming voltage expected to program the cell to its target. Initially, all but those cells having estimates at or above the current program voltage step will be program-inhibited. Thereafter, with each descending program voltage step, additional cells will be un-inhibited. Once un-inhibited, a cell need not be re-inhibited even if programmed to its target. This is because subsequent program steps are at lower voltages and ineffective in programming the cell beyond its target. The un-inhibit operation in one implementation amounts to simply pulling the associated bit lines to ground. | 2010-02-25 |
20100046298 | Non-volatile semiconductor memory circuit - Provided is a non-volatile semiconductor memory circuit capable of improving data retention characteristics and decreasing an area thereof by connecting a constant current circuit ( | 2010-02-25 |
20100046299 | PROGRAMMING RATE IDENTIFICATION AND CONTROL IN A SOLID STATE MEMORY - Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement of the respective threshold voltage) of the memory cells and biasing the corresponding bit line with a programming rate control voltage that is greater than the bit line enable voltage and less than the inhibit voltage. This voltage can be adjusted to change the speed of programming. A capacitor coupled to the bit line stores the programming rate control voltage in order to maintain the proper bit line bias for the duration of the programming operation or until it is desired to change the programming rate. | 2010-02-25 |
20100046300 | REDUCTION OF QUICK CHARGE LOSS EFFECT IN A MEMORY DEVICE - Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being programmed. A negative voltage pulse is applied to the word line after the programming pulse to force any electrons trapped in the tunnel oxide of memory cells being programmed back into the tunnel region. After the negative pulse, a program verify operation is performed. | 2010-02-25 |
20100046301 | INTELLIGENT CONTROL OF PROGRAM PULSE FOR NON-VOLATILE STORAGE - To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of the programming pulses stops increasing and the programming pulses are applied in a manner to provide varying time duration of the programming signal between verification operations. In one embodiment, for example, after the pulses reach the maximum magnitude the pulse widths are increased. In another embodiment, after the pulses reach the maximum magnitude multiple program pulses are applied between verification operations. | 2010-02-25 |
20100046302 | Complementary Reference method for high reliability trap-type non-volatile memory - Methods of complementary pairing of memory cells are described. These methods include two physical memory cells in a complementary pair, a complementary pair of reference cells for each erase block, and a physical complementary pair storing multiple data bits. | 2010-02-25 |
20100046303 | PROGRAM-VERIFY METHOD - Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading the value from the one or more memory cells in read operations. | 2010-02-25 |
20100046304 | NON-VOLATILE MEMORY DEVICE AND ERASE METHOD - Provided is a non-volatile memory device including first and second, vertically stacked semiconductor substrates, a plurality of non-volatile memory cell transistors formed in a row on the first and second semiconductor substrates, and a plurality of word lines connected to gates of the plurality of non-volatile memory cell transistors. The plurality of non-volatile memory cell transistors are grouped into two or more memory cell blocks, such that a first voltage is applied to the first semiconductor substrate including a first memory cell block to be erased, and either (1) a second voltage less than the first voltage and greater than 0V is applied to the second semiconductor substrate not including the first memory cell block, or (2) the second semiconductor substrate not including the first memory cell block is allowed to electrically float. | 2010-02-25 |
20100046305 | ERASE OPERATION IN A FLASH DRIVE MEMORY - A method for erasing a non-volatile memory device performs a block erase operation. The cells are then soft programmed and erase verified to determine if the threshold voltages indicate erased cells. A target cell is programmed to a first threshold voltage and verified. Adjacent cells are programmed and verified. The parasitic capacitance between the target cells and the adjacent cells causes the threshold voltage of the target cell to increase to a new threshold voltage with the programming of the adjacent cells. A difference between the new threshold voltage and the first threshold voltage is determined. If the difference is greater than or equal to a predetermined threshold, the target cell is soft programmed until the difference is less than the predetermined threshold. | 2010-02-25 |
20100046306 | Semiconductor storage device - It has been conventionally difficult to make circuits operate faster. The present invention is a semiconductor storage device including a reference voltage circuit that supplies a reference voltage, and first and second memory circuits, that performs a read/write operation when one of the first and second memory circuits is selected, wherein the first and second memory circuits each include a plurality of memory cells, a plurality of bit line pairs, a precharge circuit that connects a reference voltage circuit to a plurality of bit lines, a sense amplifier circuit that amplifies, when making a selection, a plurality of bit line pairs and a pull-down circuit that lowers any one of the plurality of bit line pairs below the reference voltage, the pull-down circuit of the second memory circuit lowers the bit line pair for a read/write operation period during which the first and second memory circuits are selected or non-selected and the precharge circuits of the first and second memory circuits connect a plurality of bit line pairs to the reference voltage circuit respectively during a precharge period. | 2010-02-25 |
20100046307 | SEMICONDUCTOR MEMORY AND SYSTEM - A word driver supplies a high level voltage to a word line when a memory cell is accessed and supplies low level voltage which is a negative voltage to the word line when the memory cell isn't accessed. A precharge circuit lowers a precharge voltage-supplying capacity to a bit line at least during a standby period when the memory cell is not accessed. A substrate voltage of an nMOS transistor with source or drain connected to the bit line is set to the low level voltage or lower of the word line. Therefore, when the word line and the bit line fails short and the voltage of the bit line changes to the low level voltage of the word line during the standby period, a substrate current can be prevented from flowing between the source of the nMOS transistor and a substrate or the drain and the substrate. | 2010-02-25 |
20100046308 | ONE-TRANSISTOR TYPE DRAM - A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element, formed in a region where the source line, the word line and the bit line are crossed and configured to output a reference current having a plurality of levels, a plurality of reference voltage generating units connected to the reference bit lines and configured to generate a plurality of reference voltages corresponding to the reference current having a plurality of levels, and a sense amplifier and a write driving unit connected to the bit line and configured to receive the plurality of reference voltages. | 2010-02-25 |
20100046309 | RESET CIRCUIT FOR TERMINATION OF TRACKING CIRCUITS IN SELF TIMED COMPILER MEMORIES - A method and circuit for termination of internal cycle and its associated tracking circuits in high performance self timed compiler memories is disclosed. In one embodiment, a method of timing the precharging of BLs in a self timed compiler memory array includes initiating an internal clock during the start of a read/write cycle by a control block, triggering DWL and WLs to go high upon initiating the internal clock by the control block, triggering DBL and BLs to go low upon the DWL and WLs going high by the control block, generating a reset BL signal upon the DWL going high and the DBL going low by the tracking circuit, disabling the DBL from going further low upon receiving the reset BL signal by the tracking circuit, and precharging the DBL to go high upon receiving the reset BL signal by the precharge circuit. | 2010-02-25 |
20100046310 | Semiconductor memory device including memory cell array having dynamic memory cell, and sense amplifier thereof - A semiconductor memory device and a sense amplifier thereof are provided. The semiconductor memory device includes a memory cell array and a plurality of sense amplifiers. The memory cell array includes a memory cell array block having a plurality of memory cells. Each of the plurality of sense amplifiers is configured to apply, based on a restore signal, a first voltage to a corresponding bit line to restore a first data value in a selected memory cell of the plurality of memory cells if a read value in the selected memory cell is the first data value and apply a second voltage based on the restore signal to the corresponding bit line to prevent a second data value from being restored in the selected memory cell if the read value in the selected memory cell is the second data value. | 2010-02-25 |
20100046311 | ON-CHIP TEMPERATURE SENSOR - A temperature invariant reference voltage and a temperature variant physical quantity, such as a voltage or current, are generated. The temperature variant physical quantity changes in response to a temperature of the integrated circuit. A temperature sensor circuit generates a voltage that is linearly dependent on the temperature. A level generator circuit generates 2 | 2010-02-25 |
20100046312 | Dynamic and Non-Volatile Random Access Memories with an Increased Stability of the MOS Memory Cells - In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. Random access memories with a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for DRAM and NVM devices. | 2010-02-25 |
20100046313 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a period of time that the activated wordline is driven to a high voltage level. | 2010-02-25 |
20100046314 | Memory Device Having a Read Pipeline and a Delay Locked Loop - A memory device having a memory core is described. The memory device includes a clock receiver circuit, a control interface, a data interface, a delay locked loop circuit, a read pipeline circuit and a circuit to provide an internal clock signal. The clock receiver circuit receives an external clock signal. The control interface receives a command that specifies a read operation to the memory device. The data interface transfers data between the memory device and an external set of signal lines. The delay locked loop circuit, coupled to the clock receiver circuit, to generate the internal clock signal using the external clock signal. The read pipeline circuit provides read data accessed from the memory core to the data interface. The circuit provides the internal clock signal to the read pipeline circuit in response to receipt of the command that specifies the read operation. | 2010-02-25 |
20100046315 | BONE CEMENT MIXING CARTRIDGE AND METHOD OF USE - A container for bone cement includes a first member defining a chamber, which contains a first ingredient. The chamber also includes a second member movably coupled to the first member. The second member includes a mixing device that is movably disposed within the first chamber, and the second member defines a second chamber containing a second ingredient. The container additional includes an opening device that selectively opens the second chamber and allows the second ingredient to enter from the second chamber into the first chamber. The mixing device is movable within the first chamber to promote mixing of the first ingredient and the second ingredient to prepare the bone cement. A corresponding method of preparing bone cement is also disclosed. | 2010-02-25 |