08th week of 2010 patent applcation highlights part 23 |
Patent application number | Title | Published |
20100045315 | DIAGNOSTIC PROBE ASSEMBLY FOR PRINTHEAD INTEGRATED CIRCUITRY - The invention provides for a diagnostic probe assembly for a tester which is used to diagnose printhead integrated circuits. The probe assembly includes a support assembly and a controller board mounted on the support assembly and having a processor configured to generate test signals for testing a printhead integrated circuit. A routing board is in operative signal communication with the controller board and is configured to multiplex the generated test signals for respective dies of the printhead integrated circuits. The probe assembly also includes a probe interface in signal communication with the routing board and configured for relaying the multiplexed test signals to and from the respective dies. | 2010-02-25 |
20100045316 | METHOD FOR INSPECTING ELECTROSTATIC CHUCKS WITH KELVIN PROBE ANALYSIS - A method of inspecting an electrostatic chuck (ESC) is provided. The ESC has a dielectric support surface for a semiconductor wafer. The dielectric support surface is scanned with a Kelvin probe to obtain a surface potential map. The surface potential map is compared with a reference Kelvin probe surface potential map to determine if the ESC passes inspection. | 2010-02-25 |
20100045317 | HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF - The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer. | 2010-02-25 |
20100045318 | HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF - The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer. | 2010-02-25 |
20100045319 | WAFER AND TEST METHOD THEREOF - A wafer and a test method thereof are provided. The invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer. | 2010-02-25 |
20100045320 | HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF - The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer. | 2010-02-25 |
20100045321 | HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF - The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer. | 2010-02-25 |
20100045322 | Probe Head Apparatus for Testing Semiconductors - One embodiment is a probe head for contacting microelectronic devices substantially lying in a test plane, the probe head including: (a) one or more substrate tiles having one or more probe tips disposed on a top surface thereof; and (b) a registration-alignment apparatus that holds the one or more substrate tiles: (i) in position so that the one or more probe tips are held in the test plane, and (ii) aligned so that the one or more probe tips are substantially coplanar to the test plane, which registration-alignment apparatus includes: (i) one or more capture elements affixed, directly or indirectly, to a frame; (ii) three or more posts mechanically supporting each of the one or more substrate tiles; and (iii) alignment actuators affixed, directly or indirectly, to the frame and the posts, which alignment actuators may be actuated to enable the posts to move in response to forces applied thereto from the one or more substrate tiles, and may be actuated to prevent the posts from moving. | 2010-02-25 |
20100045323 | TEST HEAD POSITIONING SYSTEM AND METHOD - An apparatus for supporting a device, comprising a base assembly, a plurality of carrier columns extending from the base unit, and a plurality of vertical support plates, each vertically movable along a respective carrier column and including a pivotal device mounting bracket. A pneumatic unit including a piston rod is associated with each vertical support plate such that vertical motion of the piston rod controls vertical motion of the respective vertical support plate. | 2010-02-25 |
20100045324 | HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF - The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer. | 2010-02-25 |
20100045325 | Test Pad Design for Reducing the Effect of Contact Resistances - An integrated circuit structure includes a semiconductor wafer; integrated circuit devices in the semiconductor wafer; and a plurality of test pads on a top surface of the semiconductor wafer and connected to the integrated circuit devices. Test pads are grouped in pairs, with the test pads in a same pair are interconnected. | 2010-02-25 |
20100045326 | THERMAL MONITORING AND MANAGEMENT OF INTEGRATED CIRCUITS - The invention, in one aspect, provides a semiconductor device ( | 2010-02-25 |
20100045327 | TEST CIRCUIT AND TEST METHOD FOR POWER SWITCH - For on-chip testing an on-chip power switch coupled to a core logic and to a decoupling capacitance, after the power switch enters a test mode, the decoupling capacitance is pre-charged or discharged; the power switch is turned ON or OFF according to test patterns; and a voltage level at the decoupling capacitance is analyzed or a leakage current flowing the power switch is measured. So that, whether the power switch is passed or failed is identified. | 2010-02-25 |
20100045328 | CIRCUIT FOR DETECTING BONDING DEFECT IN MULTI-BONDING WIRE - An integrated circuit for detecting a bonding defect in a multi-bonding wire. The integrated circuit includes a plurality of pads each connectable by a bonding wire to a lead terminal. Voltage supplied to the lead terminal is applied in common to the plurality of pads. A detection circuit is operably connected to the plurality of pads. The detection circuit detects breakage of the bonding wires based on potentials at the plurality of pads. | 2010-02-25 |
20100045329 | Probeless DC testing of CMOS I/O circuits - A method and implementation is described by which I/O input and output circuitry of a CMOS chip are measured without the need to probe the chip. Output driver transistors are used to provide marginal voltages to test input circuits, and the output driver transistors are segmented into portions where a first portion is used to provide a representative “on” current, which is coupled to a test bus that is further connected to a current comparator circuit contained within the chip. Both leakage and “on” current of the driver transistors is measured using segmented driver transistors. The output of the current comparator circuit is connected to a test scan register or to a test output from which test results are obtained digitally. The testing techniques are also applicable for other semiconductor devices. | 2010-02-25 |
20100045330 | APPARATUS FOR TESTING INTEGRATED CIRCUITRY - A testing apparatus for testing integrated circuits mounted in a carrier includes a support assembly. A controller is mounted in the support assembly. The controller is programmed to process test signals from the integrated circuits. A retaining assembly is arranged on the support assembly and is configured to receive and retain the carrier during testing. A displacement mechanism is arranged on the support assembly for displacing the retaining assembly relative to the support assembly into and out of an operative condition. Testing circuitry is operatively connected to the controller and has at least test signal generation and measurement circuitry and adaptor circuitry for operative engagement with the integrated circuits being tested, the adaptor circuitry being configured to provide both a physical and an electrical interface with the integrated circuits. | 2010-02-25 |
20100045331 | Method of locating failure site on semiconductor device under test - In an analysis of a semiconductor device under test (DUT) using a Thermal Induced Voltage Alteration (TIVA) tool, the TIVA is connected to an output of the DUT and the DC component on the output is decoupled from the TIVA. The remaining AC component from the output is analyzed by the TIVA while scanning the DUT with a scanning laser to identify locations on the DUT that produce signal anomalies at the DUT output. | 2010-02-25 |
20100045332 | TEST CIRCUIT, METHOD, AND SEMICONDUCTOR DEVICE - It is possible to provide a circuit and method for carrying out a parallel test using BOST (Built Out Self Test). The circuit includes first transfer circuits ( | 2010-02-25 |
20100045333 | GENERATING TEST BENCHES FOR PRE-SILICON VALIDATION OF RETIMED COMPLEX IC DESIGNS AGAINST A REFERENCE DESIGN - This invention ( | 2010-02-25 |
20100045334 | DIRECT DETECT SENSOR FOR FLAT PANEL DISPLAYS - Each sensor of a linear array of sensors includes, in part, a sensing electrode and an associated feedback circuit. The sensing electrodes are adapted to be brought in proximity to a flat panel having formed thereon a multitude of pixel electrodes in order to capacitively measure the voltage of the pixel electrodes. Each feedback circuit is adapted to actively drive its associated electrode via a feedback signal so as to maintain the voltage of its associated electrode at a substantially fixed bias. Each feedback circuit may include an amplifier having a first input terminal coupled to the sensing electrode and a second input terminal coupled to receive a biasing voltage. The output signal of the amplification circuit is used to generate the feedback signal that actively drives the sensing electrode. The biasing voltage may be the ground potential. | 2010-02-25 |
20100045335 | METHODS AND SYSTEMS FOR EVALUATING PERMANENT MAGNET MOTORS - A method for evaluating a permanent magnet motor, which includes a rotor with a plurality of magnets mounted thereon, and a stator with a plurality of windings in proximity to the rotor and coupled to an inverter, includes spinning the motor such that a voltage is induced in the windings of the stator and the inverter; measuring the voltage on the inverter; calculating the voltage constant from the motor from the measured voltage; comparing the voltage constant to accepted voltage constants; and identifying the motor as not acceptable if the voltage constant is outside of a range of the accepted voltage constants. | 2010-02-25 |
20100045336 | Method and Device for Programmable Power Supply with Configurable Restrictions - The invention involves a programmable power supply device with configurable restrictions to the programmability of the power supply device, wherein the programmable power supply device comprises a number of freeze/programmability levels, each freeze/programmability defining a dedicated access restriction to the programmability of the power supply device. | 2010-02-25 |
20100045337 | Methods, apparatuses, and products for a secure circuit - Methods, systems, apparatuses and products are disclosed for providing security circuits. Exemplary embodiments including semiconductor chips on circuit boards are shown, together with application in a movie stick/movie player pair. | 2010-02-25 |
20100045338 | Semiconductor device and data processing system including the same - There is provided a semiconductor device that includes: an output buffer capable of adjusting an impedance based on an impedance adjustment signal, and a through-rate control circuit that adjusts a through rate of the output buffer based on at least the impedance adjustment signal, wherein the through-rate control circuit sets a relatively high through rate when the impedance adjustment signal designates a relatively low impedance, and sets a relatively low through rate when the impedance adjustment signal designates a relatively high impedance. | 2010-02-25 |
20100045339 | WIRELINE TRANSMISSION CIRCUIT - A wireline transmission circuit includes a first circuit that produces a first variable current, a second circuit that produces a first static current, a trans-impedance amplifier that outputs a first analog signal at a first output node in response to the first variable current and the first static current received at a first input node, and a first feedback resistor connected to the first input node and the first output node. | 2010-02-25 |
20100045340 | CONTROL CIRCUIT FOR CONTROLLING ON-DIE TERMINATION IMPEDANCE - The present invention relates to an ODT control circuit which is controlled in synchronization with an external clock during power-down mode. An ODT control circuit according to the present invention includes a clock control circuit which receives a synchronized internal clock signal and a DLL clock signal, and selects either one of the internal clock signal or the DLL clock signal according to the power mode to output a plurality of delayed clock signals; and an ODT control signal generation circuit which receives an ODT command, and controls the ODT command with the internal clock signal and a plurality of the delayed clock signals to generate and output an ODT control signal. According to the present invention, an ODT control signal for controlling an on-die termination resistor is synchronized with an external clock even during power-down mode, thereby more effectively controlling the ODT control signal. | 2010-02-25 |
20100045341 | Method and Apparatus for High Resolution ZQ Calibration - A method is disclosed for controlling an output impedance of an electronic device of the type having an impedance control terminal to which an external load is to be connected such that a predetermined value of the voltage at the impedance control terminal controls the output impedance of the device. The method is comprised of comparing a reference voltage to a voltage at the impedance control terminal. A variable count signal representing a count value is produced in response to the comparing. The impedance of a variable impedance circuit is varied in response to the count signal, wherein the impedance of the variable impedance circuit controls the voltage at the impedance control terminal. A device connected in parallel with the variable impedance circuit is periodically operated to change (increase/decrease) the impedance of the variable impedance circuit. An apparatus for performing the method is also disclosed. Because of the rules governing abstracts, this abstract should not be used to construe the claims. | 2010-02-25 |
20100045342 | LEVEL TRANSLATOR CIRCUIT - A voltage-level translator circuit including two pairs of branches in parallel, each pair including a low-impedance branch, where the low-impedance branches can be activated or deactivated. A possible application is the voltage level switching of data originating from an integrated circuit. | 2010-02-25 |
20100045343 | Current Limited Voltage Supply - A current limited voltage supply including a transistor and a capacitor is provided for powering digital logic cells of an integrated circuit. The transistor is connected in a current mirror configuration, such that a constant reference current is mirrored through the transistor to create a first supply current. The transistor is coupled to the digital logic cells and the capacitor. The first supply current is used to charge the capacitor while the digital logic cells are not switching. While the digital logic cells are switching, the capacitor discharges to the digital logic cells, thereby providing the digital logic cells with sufficient energy to implement high-speed switching. The capacitor minimizes voltage fluctuations within in the current limited voltage supply, such that analog circuitry can be reliably powered from a different branch of the same current mirror circuit. | 2010-02-25 |
20100045344 | DUAL RAIL DOMINO CIRCUIT, DOMINO CIRCUIT, AND LOGIC CIRCUIT - In a dual rail domino circuit | 2010-02-25 |
20100045345 | AC DIFFERENTIAL CONNECTION ASSEMBLY BETWEEN A TRANS-IMPEDANCE AMPLIFIER AND A POST AMPLIFIER FOR BURST MODE RECEIVING - An AC differential connection assembly between a trans-impedance amplifier and a post amplifier for burst mode receiving comprising means for coupling a differential output of the trans-impedance amplifier to a differential input of the post amplifier, the means for coupling comprises a coupling capacitor assembly; and a switching circuit coupled across the differential input of the post amplifier, the switching circuit having an ‘on’ state with low impedance and an ‘off’ state with high impedance; wherein during burst mode receiving, the switching circuit is in the ‘off’ state and the coupling capacitor assembly having a time constant to maintain a stable DC level such that a payload is received accurately by the differential input of the post amplifier; and during an idle period, the switching circuit is in the ‘on’ state and the coupling capacitor assembly having a time constant to recover a DC level of the differential output of the trans-impedance amplifier. | 2010-02-25 |
20100045346 | ZERO-CROSSING DETECTING DEVICE AND IMAGE FORMING DEVICE - A zero-crossing detecting device that detects a zero-crossing point of AC voltage, the device has a full-wave rectifier that rectifies the AC voltage and outputs a full-wave rectified voltage, a charger that is charged at a predetermined charging voltage by application of the full-wave rectified voltage, wherein the charger outputs a charging current when the full-wave rectified voltage falls below the charging voltage, and a signal output part that outputs a zero-crossing detecting signal. The signal output part outputs the zero-crossing detecting signal when the charging current flows to the signal output part. | 2010-02-25 |
20100045347 | Power On Control Device and Method - A power on control device and method are used at an adaptor providing a constant voltage. The power on control device includes a first voltage converting circuit, a second voltage converting circuit, a third voltage converting circuit, and a comparison module. The first voltage converting circuit receives the constant voltage and generates a reference voltage. The second voltage converting circuit receives the constant voltage and generates operating voltages. The third voltage converting circuit receives the operating voltages and generates preparatory voltages corresponding to the operating voltages according to the operating voltages. The comparison module outputs a power good signal when all the preparatory voltages are larger than the reference voltage. | 2010-02-25 |
20100045348 | OSCILLATOR, TRANSMITTER-RECEIVER AND FREQUENCY SYNTHESIZER - An output terminal | 2010-02-25 |
20100045349 | PROGRAMMABLE HIGH-SPEED INTERFACE - Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application. | 2010-02-25 |
20100045350 | Semiconductor Device and Amplification Device Generating Triangular Wave Synchronized with Clock Signal - A semiconductor device includes a current control circuit for outputting and sinking a current in synchronization with a received clock signal; and a current/voltage conversion circuit having a first capacitor charged and discharged by the current control circuit outputting and sinking the current, respectively, and outputting a triangular wave based on the charge stored in the first capacitor. | 2010-02-25 |
20100045351 | INTEGRATED CIRCUIT AND PROGRAMMABLE DELAY - Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell. The first inputs of any delay cells are configured to receive an input signal to be delayed. The delay cells out of the plurality of delay cells is configured to constitute a starting point of a signal path including any of the delay cells arranged downstream of the starting point. The first output of the last delay cell in the chain forms an output of the programmable delay element. | 2010-02-25 |
20100045352 | METHOD AND APPARATUS FOR PULSE WIDTH MODULATION - An apparatus and method of providing a pulse width modulated signal that is responsive to a current are disclosed. A circuit according to aspects of the present invention includes a capacitor to convert a first current to a first voltage on the capacitor during a first time duration and to discharge a second current from the capacitor to change the first voltage to a second voltage during a second time duration. A comparator is also included and is coupled to an output of the capacitor to compare a voltage on the capacitor to a reference voltage during the second time duration to change a pulse width of a periodic output signal in response to an input current. | 2010-02-25 |
20100045353 | SELECTIVE EDGE PHASE MIXING - Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and memory device configured to perform operations in synchronization with transitions of an externally provided clock signal. A selective edge phase mixing unit for the memory device may include a first logic gate that receives the clock signal at an input port and receives first control signals, and pull-up circuits in communication with an output of the first logic gate and first control signals. A second logic gate receives the clock signal at the input port and receives second control signals. Pull-down circuits are coupled to the second logic gate and the second control signals, wherein the pull-up circuits and the pull-down circuits are coupled to the output port to provide a duty cycle corrected clock signal to the memory device. Additional apparatus, systems, and methods are disclosed. | 2010-02-25 |
20100045354 | DELAY-LOCK LOOP AND METHOD ADAPTING ITSELF TO OPERATE OVER A WIDE FREQUENCY RANGE - A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a voltage-controlled delay line generating a plurality of delayed clock signals having different phases. A plurality of the delayed clock signals are combined to generate a plurality of output signals. During an initialization period, an initialization circuit sets the delay of the delay line to a minimum delay value and then compares this delay value to the period of the input clock signal. Based on this comparison, the initialization circuit programs the programmable divider and adjusts the number of delayed clock signals combined to generate the output signals. More specifically, as the frequency of the reference clock signal increases, the divider is programmed to divide by a greater number, and a larger number of delay clock signals are combined to generate the output signals. | 2010-02-25 |
20100045355 | CLOCK SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE - In a semiconductor device capable of radio communication, a stable clock signal is generated even if a reference clock signal for generating a clock signal has varied frequencies in each cycle. A clock signal generation circuit includes an edge detection circuit that detects an edge of an input signal and generates a synchronization signal, a reference clock signal generation circuit that generates a clock signal which functions as reference, a counter circuit that counts the number of edges of rise of the reference clock signal in accordance with the synchronization signal, a duty ratio selection circuit that selects a duty ratio of a clock signal from a count value, and a frequency division circuit that generates the clock signal having the selected duty ratio. | 2010-02-25 |
20100045356 | DATA PROCESSING SYSTEM FOR CLIPPING CORRECTION | 2010-02-25 |
20100045357 | Clamp Circuit for Clamping Inrush Voltage Induced by Hot Plugging and Related Chip - An inrush voltage clamping circuit for an electronic device for clamping an inrush voltage induced by hot plugging is disclosed. The clamp circuit includes a buffer unit and a clamp unit. The buffer unit is coupled to an input power end for receiving an inrush current of the inrush voltage. The clamp unit is coupled to the input power end and the buffer unit for controlling the buffer unit to receive the inrush current according to an input voltage of the input power end. | 2010-02-25 |
20100045358 | LEVEL SHIFT CIRCUIT - The present invention provides a level shift circuit capable of operating at low input voltage. The level shift circuit comprises: a first switch element coupled to a first output terminal, a second switch element coupled to a second output terminal, a third switch element coupled to the second output terminal and the first output terminal, a fourth switch element coupled to the first output terminal and the second output terminal, a first current source module for letting a current passing through the third switch element smaller than a current passing through the first switch element when the first switch element and the third switch element are conducted, and a second current source module for let a current passing through the fourth switch element smaller than a current passing through the second switch element when the second switch element and the fourth switch element are conducted. | 2010-02-25 |
20100045359 | CALIBRATION CIRCUIT - To include a first replica buffer that has substantially the same circuit configuration as a pull-up circuit which constitutes an output buffer and a second replica buffer that has substantially the same circuit configuration as a pull-down circuit which constitutes the output buffer. When a first calibration command ZQCS is issued, either a control signal ACT | 2010-02-25 |
20100045360 | DETECTOR - A device for measuring the position of a first body relative to a second body comprising: a first body which further comprises an electrical intermediate device; a second body which further comprises at least two inductors energised with an alternating current and at least one of which is formed by a planar spiral winding on a printed circuit board normal to the measurement axis and attached to the second body; arranged such that displacement of the electrical intermediate device causes a change in inductance of the planar spiral winding and whereby measurement of the ratio of the inductances indicates the position of the first body relative to the second. | 2010-02-25 |
20100045361 | POWER CIRCUIT - A power circuit. One embodiment provides a circuit for driving a power transistor having a control electrode and a load path. The circuit includes a driver circuit configured to change the power transistor to a completely on or off state with the aid of a control signal supplied to the control electrode. A series circuit includes a semiconductor switching element and a capacitor. The series circuit is connected in parallel with the load path and the capacitor provides a supply voltage for the driver circuit. | 2010-02-25 |
20100045362 | Temperature-gradient cancelation technique and device - A system, device, and method for minimizing x-axis and/or y-axis offset shift due to internally produced as well as externally produced on chip temperature imbalances. At least one temperature gradient canceling device is disposed on a substrate including a temperature gradient sensitive device having at least one pair of sensors. Voltage signals generated by the temperature gradient canceling devices can be combined with voltage signals generated by each of the pair of sensors to account for the offset. | 2010-02-25 |
20100045363 | DEVICE AND METHOD FOR SHARING CHARGE | 2010-02-25 |
20100045364 | ADAPTIVE VOLTAGE BIAS METHODOLOGY - The present disclosure provides an integrated circuit. The integrated circuit includes a frequency detector coupled with a logic circuit; a supply voltage regulator coupled with the frequency detector and designed to provide an adaptive voltage supply to the logic circuit based on a frequency error from the frequency detector; and a substrate bias regulator coupled with the frequency detector and designed to provide an adaptive body bias voltage to the logic circuit based on the frequency error. | 2010-02-25 |
20100045365 | TWO TERMINAL QUANTUM DEVICE USING MOS CAPACITOR STRUCTURE - A gated quantum well device formed as an MOS capacitor is disclosed. The quantum well is an inversion region less than 20 nanometers wide under the MOS gate. The device may be fabricated in either polarity, and integrated into a CMOS IC, configured as a quantum dot device or a quantum wire device. The device may be operated as a precision charge pump, with a minority carrier injection region added to speed well filling. | 2010-02-25 |
20100045366 | MEASURING INSTRUMENT IN TWO-CONDUCTOR TECHNOLOGY - In a two-conductor technology circuit the use of certain ASIC components is made possible which, for instance, allow for the supply of contact-free rotational angle sensors, although said ASIC components have a high current consumption. | 2010-02-25 |
20100045367 | LOW-VOLTAGE OPERATION CONSTANT-VOLTAGE CIRCUIT - According to a preferred embodiment of the present invention, a low-voltage operation constant-voltage circuit includes a band-gap reference voltage circuit including a resistor-diode series circuit as a main component. A resistor and a diode-connected bipolar transistor are connected in series to create a constant current. It also includes an output circuit connected in parallel to the resistor-diode series circuit and formed so that the same constant current as the current flowing through the resistor-diode series circuit flows. The output circuit includes a diode-connected MOS transistor, and is configured to cancel the positive temperature coefficient of the current flowing through the output circuit by the MOS transistor. With this, a stable output low-voltage of, e.g., about 0.6 V, excellent in temperature characteristics can be obtained regardless of the ambient temperature changes. | 2010-02-25 |
20100045368 | Semiconductor Integrated Circuit - An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized. | 2010-02-25 |
20100045369 | REFERENCE CURRENT GENERATING CIRCUIT USING ON-CHIP CONSTANT RESISTOR - Provided is a reference current generating circuit capable of maintaining a constant output level regardless of a temperature variation by the use of a reference resistor having a constant resistance regardless of the temperature variation. The reference current generating circuit includes a reference voltage circuit supplying a reference voltage having a constant level regardless of a temperature variation, and a reference resistor circuit comprising a resistor having a positive temperature coefficient and a resistor having a negative temperature coefficient that are connected in series, the reference resistor circuit having a constant total resistance regardless of the temperature variation. Herein, a reference current having a constant level regardless of the temperature variation is generated by the reference voltage and the resistance of the reference resistor circuit. | 2010-02-25 |
20100045370 | TESTING OF TRANSIMPEDANCE AMPLIFIERS - Testing is performed on an amplifier wafer housing a transimpedance amplifier prior to packaging the transimpedance amplifier with an external photodetector, wherein the transimpedance amplifier includes a small, auxiliary, integrated silicon photodetector provided at the input of the transimpedance, in parallel with external photodetector attachment points. To test the transimpedance amplifier, the transimpedance amplifier is stimulated by optically exciting the small auxiliary photodetector, wherein the small auxiliary photodetector is excited using short wavelength light, whereby advantages such as higher efficiency may be obtained. The testing method includes placing the amplifier wafer in a testing system, probing the power and ground connections on the amplifier wafer, illuminating the small auxiliary photodetector on the amplifier wafer, and detecting the output of the transimpedance amplifier housed on the amplifier wafer. | 2010-02-25 |
20100045371 | AMPLIFICATION CONTROL DEVICE, TEST SIGNAL GENERATION MODULE, TEST DEVICE, AMPLIFICATION CONTROL METHOD, PROGRAM, AND RECORDING MEDIUM - An amplification control device for controlling a variable-gain amplifier the amplification factor of which is controlled based on an analog control signal, and which amplifies an analog input signal and outputs an analog output signal, includes component acquisition means that transforms, by the discrete Fourier transform, a digital output signal converted from the analog output signal into digital form by an A/D converter, thereby acquiring a desired frequency component of the digital output signal, differentiating means that acquires a difference between the electric power of the frequency component acquired by the component acquisition means and a target value of the electric power of the frequency component, and digital control signal output means that outputs a digital control signal, based on the difference acquired by the differentiating means, for controlling the amplification factor of the variable-gain amplifier, in which the analog control signal is obtained by converting the digital control signal into analog form by the D/A converter. | 2010-02-25 |
20100045372 | AMPLIFICATION CIRCUIT, AMPLIFICATION CIRCUIT NOISE REDUCING METHOD AND PROGRAM THEREOF - [Problems] to provide a CMOS low-noise amplification circuit which can reduce a chip area and design time, and which is easy to be digital-controlled from outside. | 2010-02-25 |
20100045373 | AMPLIFIER CIRCUIT - An extraction circuit is connected to an input path of an output amplifier. When the power is turned on, the extraction circuit extracts current on the basis of a difference between the normal rise of the supply voltage and a delayed supply voltage. Therefore, a steep rise in the input of the output amplifier when the power is turned on can be removed. | 2010-02-25 |
20100045374 | GAIN ADJUSTMENT DEVICE AND METHOD THEREOF - A gain adjustment device and a method thereof are provided. The device includes a first processing module, a gain adjustment circuit, a second processing module, and a gain control module. The first processing module receives an input signal and generates a first signal. An operating voltage of the first processing module is a first voltage. The gain adjustment circuit receives the first signal and adjusts a gain of the first signal according to a gain control signal to output a third signal. The second processing module receives the third signal and generates a second signal. An operating voltage of the second processing module is a second voltage. The gain control module generates the gain control signal according to the first voltage and the second voltage. | 2010-02-25 |
20100045375 | DEVICE FOR THE LOW-DISTORTION TRANSFORMATION, PARTICULARLY AMPLIFICATION OF SIGNALS - The invention describes a device for the low-distortion conversion, especially amplification, of signals. In one embodiment, the device comprises a digital-to-analog converter having adjustable reference voltages to which an analog-to-digital converter having adjustable reference voltages may be connected upstream. In a further embodiment, the device has a unit, which predistorts a digitized signal, or a digital signal, corresponding to the characteristic transfer line of the amplifier. In a further embodiment, the device has a unit, which equalizes a distorted digitized signal corresponding to the characteristic transfer line of the amplifier stored in the unit. In yet a further embodiment, the device has a digital-to-analog converter operating on the basis of the summation of weighted currents. | 2010-02-25 |
20100045376 | CLASS D AMPLIFIER CONTROL CIRCUIT AND METHOD - Circuit and method for a Class D amplifier. In one exemplary embodiment, an audio amplifier is disclosed. A closed loop configuration for driving high and low side driver transistors is provided, each circuit is compatible with advanced sub micron semiconductor processes. The analog time varying input is coupled to one input of a sigma delta analog to digital converter. A feedback signal from the output is also input to the analog to digital converter. A bit stream is output by the analog to digital converter. A decimator receives this bit stream and downconverts the samples to digital values at a lower frequency. A digital filter with adaptable coefficients is used to filter that signal and a digital pulse width modulator then develops an analog differential PWM signal. A predriver inputs the PWM signal and derives the output gating signals to control the high and low side drivers of a Class D amplifier. | 2010-02-25 |
20100045377 | Switching Amplifier - A switching amplifier includes a modulator, which includes a pulse generator. The pulse generator generates positive and negative pulses, in response to an input signal, and the frequency of the negative pulses can be controlled independently of the frequency of the positive pulses. The positive pulses and negative pulses are combined to form a composite pulse stream, which can be low-pass filtered such that the filter output is an amplified version of the input signal. | 2010-02-25 |
20100045378 | COMMUTATING AUTO ZERO AMPLIFIER - A commutating auto zero amplifier system, comprises a first amplifier (A | 2010-02-25 |
20100045379 | METHOD OF INDICATION OF SYSTEM INFORMATION UPDATING - An amplifier amplifying an input signal and the method thereof. The amplifier comprises first and second transconductor circuits. The first transconductor circuit, coupled to the first transistor, receives the first noise voltage to generate a first noise current. The second transconductor circuit, coupled in parallel to the first transconductor circuit, receives the second noise voltage to generate a second noise current such that the first and second noise currents cancel each other out to reduce a noise component in the output current when summing up together, and the first and second transconductor circuits are operated in a current mode. | 2010-02-25 |
20100045380 | LOW DROP VOLTAGE REGULATOR WITH INSTANT LOAD REGULATION AND METHOD - An LDO regulator ( | 2010-02-25 |
20100045381 | LIMITING AMPLIFIERS - A limiting amplifier with an input stage with dc offset cancellation, identical gain stages, an output buffer and a feedback filter. The input stage receives a differential input signal and outputs a first intermediate differential signal. The gain stages are cascaded to amplify the first intermediate differential signal and generate a second intermediate differential signal, amplified by the output buffer to produce an output signal. The feedback filter provides a dc offset voltage of the output signal to the input stage for the dc offset cancellation. The input stage comprises a resistor network coupled between a pair of input nodes and a power line and comprising a common resistor, a pair of load resistors and a shunt resistor. The load resistors share a common terminal connected to the common resistor that is connected to the power line. The shunt resistor has two terminals respectively connected to the load resistors. | 2010-02-25 |
20100045382 | BIAS CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE BIAS CIRCUIT - A plurality of analog signals are input to input terminals of an analog signal processing circuit ANA | 2010-02-25 |
20100045383 | Variable gain circuit - Provided is a variable gain circuit in which it is not necessary to provide a plurality of phase compensation capacities while stability of a circuit is maintained regardless of a set variable gain. A variable gain circuit comprises a precedent stage amplifier circuit for amplifying an external input signal, a subsequent stage amplifier circuit for amplifying an output signal of the precedent stage amplifier circuit, a phase compensation circuit having a fixed capacitative element and connected between an output terminal and an input terminal of the subsequent stage amplifier circuit, and a gain setting circuit adapted to be capable of setting a gain value of the whole of the precedent stage amplifier circuit and the subsequent stage amplifier circuit to a plurality of values, wherein one of the gain value and a transconductance value of the precedent stage amplifier circuit can be set in conjunction with the other. | 2010-02-25 |
20100045384 | System And Method For Pre-Charging A Current Mirror - A system for pre-charging a current mirror includes a controller configured to provide a first current and an additional current to a current mirror to rapidly charge a capacitance associated with the current mirror based on a reference voltage or control signals. A power amplifier module includes at least one current mirror and a controller. A capacitor is coupled to the current mirror. The controller provides a bias current in an amount proportional to an input to a voltage-to-current converter. The controller receives a control signal that directs the controller to apply one of a pre-charge voltage and a nominal voltage to the voltage-to-current converter. | 2010-02-25 |
20100045385 | INTEGRATED CIRCUIT WITH PARALLEL SETS OF TRANSISTOR AMPLIFIERS HAVING DIFFERENT TURN ON POWER LEVELS - A power amplifier circuit includes a power splitter that splits an input signal into a plurality of component input signals. At least two sets of transistor amplifiers are each coupled in parallel to the power splitter to receive and amplify different ones of the component input signals to generate amplified component output signals. The two transistor amplifiers of each set of transistor amplifiers are configured to turn on at different power levels of the input signal relative to each other. A combiner is configured to receive and combine the amplified component output signals from the at least two sets of transistor amplifiers into an output signal. An integrated circuit package encloses the power splitter, the at least two sets of transistor amplifiers, and the combiner. | 2010-02-25 |
20100045386 | AMPLIFIER CIRCUIT - The invention relates to a circuit arrangement ( | 2010-02-25 |
20100045387 | OPTICAL RECEIVER-AMPLIFIER - There is provided an optical receiver-amplifier wherein the need for a large capacitance capacitor for AC coupling is eliminated to thereby enable miniaturization of a receiver in whole, and output waveforms of a differential limiter amp can be rendered symmetrical with high precision while a transimpedance amp and a limiter amp can be integrated on one chip. The optical receiver-amplifier comprises a photodiode, a transimpedance amp for amplifying an output signal of the photodiode, and a DC current compensating circuit connected in parallel with the transimpedance amp for compensating for a DC-current component of an output current of the differential amp. | 2010-02-25 |
20100045388 | Accuracy on-chip clock generator for multi-clock driven single chip solution - A mixed-signal chip is described. The mixed-signal chip comprises a first portion of analog circuit and second portion of digital circuit, an on-chip precision oscillator residing on the first analog portion, the precision oscillator has a precision frequency; a first on-chip non-precision tunable oscillator from a first clock domain residing on the first analog portion, the first non-precision tunable oscillator has a first adjustable frequency; a noise detector for detecting a first noise in the first clock domain; a frequency adjusting register for storing a first desired frequency value of the first on-chip non-precision tunable oscillator, wherein the first desired frequency value is determined based on the first detected noise; a control circuit for adjusting the adjustable frequency of the first non-precision tunable oscillator to the first desired frequency value by using the precision frequency of the on-chip precision oscillator as a reference. | 2010-02-25 |
20100045389 | RING OSCILLATOR - A ring oscillator is disclosed for generating one or more clock signals. In some embodiments, the ring oscillator includes a first set of n series coupled inverters, a second set of n series coupled inverters, a first reset switch configured to couple a last inverter of the first set of inverters to a first inverter of the second set of inverters and to generate a first signal edge, a second reset switch configured to couple a last inverter of the second set of inverters to a first inverter of the first set of inverters, and a cross-coupling circuit coupled between an output of an inverter of the first set of inverters to a corresponding output of an inverter of the second set of inverters. In some embodiments, 2n clock signals separated in phase by 360°/2n may be generated. | 2010-02-25 |
20100045390 | CIRCUIT AND METHOD FOR MEASURING THE PERFORMANCE PARAMETERS OF TRANSISTORS - An integrated circuit may include an inverter which may include a first transistor of a first conductivity type and a second transistor of a second conductivity type connected in parallel with the first transistor. An input of the inverter may be capable of receiving an oscillating input signal, and which may include an output of the inverter, which is connected to a capacitive device capable of being charged and discharged depending on the state of the first and second transistors being on or off. The inverter may be capable of delivering an oscillating output signal at its output. The integrated circuit may include a selector for transmitting the oscillating output signal and for masking the charging and/or discharging of the capacitive device. | 2010-02-25 |
20100045391 | FREQUENCY LOCKING STRUCTURE APPLIED TO PHASE-LOCKED LOOPS - A frequency locking structure applied to phase-locked loops (PLL) utilizes a common factor to reduce the difference between an output signal of oscillation and an input signal of reference for the jitter reduction of the input signal of reference. Moreover, a count value of clock signal is an input of a greatest-common-factor calculator to acquire an adaptive value and a feedback adaptive value for the common factor of a divider. Such a frequency locking structure both prevents the PLL from being in error about outputting frequency and dynamically adjusts the common factors for different purposes. | 2010-02-25 |
20100045392 | ELECTROMAGNETIC-WAVE OSCILLATOR - An electromagnetic-wave oscillator includes a substrate, an EMW oscillating unit including a gain portion, an EMW resonance portion, an EMW radiating portion, and a ground (GND) portion, and a supplying unit for supplying electric power to the EMW oscillating unit. The ground portion regulates a predetermined reference electric potential for the gain portion, the EMW resonance portion, and the EMW radiating portion. The EMW oscillating unit is disposed on a first surface of the substrate. The supplying unit is disposed on a second surface of the substrate extending on an opposite side to the first surface. The EMW oscillating unit and the supplying unit are electrically connected via a penetrating electrode formed in the substrate. | 2010-02-25 |
20100045393 | Crystal oscillator - A crystal oscillator is provided to secure a space for housing the IC and electronic components, even if the vibrator is small in size. In this crystal oscillator, there is not a hindrance to the wire connections between the IC and the electronic components, and the limitation on the vibrator and oscillator design is reduced. Also, the influence of the heat from the IC and the electronic components is made smaller. Thus, desired characteristics can be readily achieved with this crystal oscillator. In this crystal oscillator, the IC and the electronic components are housed in a concave portion formed in the ceramic package. A pedestal formed with a crystal plate made of the same material as the vibrator is provided to cover almost the entire opening of the concave portion, and the vibrator is placed on the pedestal. | 2010-02-25 |
20100045394 | Method, System and Apparatus for Accurate and Stable LC-Based Reference Oscillators - A substantially temperature-independent LC-based oscillator is achieved using an LC tank that generates a tank oscillation at a phase substantially equal to a temperature null phase. The temperature null phase is a phase of the LC tank at which variations in frequency of an output oscillation of the LC-based oscillator with temperature changes are minimized. The LC-based oscillator further includes frequency stabilizer circuitry coupled to the LC tank to cause the LC tank to oscillate at the phase substantially equal to the temperature null phase. | 2010-02-25 |
20100045395 | FREQUENCY ADJUSTMENT FOR CLOCK GENERATOR - A fractional-N divider receives an input signal and supplies a divided signal divided in accordance with an integer divide control signal determined from a divide ratio. A phase interpolator is coupled to the fractional-N divider to adjust a phase of the divided signal according to a fractional portion of the divide ratio. The apparatus, responsive to a request for a frequency adjustment of the generated signal in a programmable number of steps, is configured to adjust the frequency of the generated signal from a beginning frequency to an ending frequency in the programmable number of steps by adjusting the supplied divide ratio at each step. | 2010-02-25 |
20100045396 | Thin film balun - The present invention provides a thin film balun according to an embodiment of the present invention includes: an unbalanced transmission line which includes two coils; a balanced transmission line which includes two coils and is electromagnetically coupled to the unbalanced transmission line; a capacitor having one end connected to the balanced transmission line; and a ground terminal | 2010-02-25 |
20100045397 | Resonator Filter Working With Surface Acoustic Waves - A resonator filter working with surface acoustic waves is disclosed. The transfer function of this filter features a phase rotation of at least 400° within a passband. | 2010-02-25 |
20100045398 | Miniaturized Wide-Band Baluns for RF Applications - A wide-band balun device includes a first metallization deposited over a substrate and oriented in a first coil. The first coil extends horizontally across the substrate while maintaining a substantially flat vertical profile. A second metallization is deposited over the substrate and oriented in a second coil. The second coil is magnetically coupled to the first coil and a portion of the second coil oriented interiorly of the first coil. A third metallization is deposited over the substrate and oriented in a third coil. The third coil is magnetically coupled to the first and second coils. A first portion of the third coil is oriented interiorly of the second coil. The third coil has a balanced port connected to the third coil between second and third portions of the third coil. | 2010-02-25 |
20100045399 | BALANCED ACOUSTIC WAVE FILTER DEVICE AND COMPOSITE FILTER - An acoustic wave filter device which attains improved balancing between transmission characteristics of first and second balanced terminals includes first and second 3-IDT longitudinally coupled resonator type acoustic wave filter elements that are connected to an unbalanced terminal in parallel, and one terminal of a first IDT and one terminal of a fourth IDT are connected to each other and further connected to the unbalanced terminal, second and third IDTs are connected to each other and further connected to a first balanced terminal, fifth and sixth IDTs are connected to each other and further connected to a second balanced terminal, and a first ground line which electrically connects the second IDT which is nearer to a first ground terminal than the third IDT to the second ground terminal is longer than a second ground line which electrically connects the fifth IDT which is nearer to the first ground terminal than the sixth IDT to the first ground terminal. | 2010-02-25 |
20100045400 | Marchand Balun With Air Bridge - A microwave or millimeter-wave balun is provided. The balun uses three edge-coupled lines along with a plurality of air bridges instead of two edge-coupled lines used in a conventional planar Marchand balun. The first edge-coupled line and the second edge-coupled line are substantially parallel, and the third edge-coupled line is disposed also substantially in parallel between the first edge-coupled line and the second edge-coupled line. The plurality of air bridges are transmission lines between the first edge-coupled line and the second edge-coupled line. The air bridges have total width longer than one half of the total length of the first edge-coupled line or the second edge-coupled line. By combining three edge-coupled-lines and a plurality of air bridges, the Marchand balun has a higher coupling coefficient and increases the operation bandwidth. The microwave monolithic integrated circuit (MMIC) mixer based on the balun can provide compact size compared to conventional ones. | 2010-02-25 |
20100045401 | Thin film balun - The present invention provides a thin film balun according to an embodiment of the present invention includes: an unbalanced transmission line which includes two coils; a balanced transmission line which includes two coils and is electromagnetically coupled to the unbalanced transmission line; a first electrode which is connected to the balanced transmission line and constitutes a capacitor | 2010-02-25 |
20100045402 | APPARATUSES AND A METHOD FOR CONTROLLING ANTENNA SYSTEMS IN A TELECOMMUNICATIONS SYSTEM - The present invention relates to a method and an apparatus ( | 2010-02-25 |
20100045403 | MINIATURE 180 DEGREE HYBRID COUPLER - A 180° hybrid coupler ( | 2010-02-25 |
20100045404 | PHASE ERROR CANCELLATION FOR DIFFERENTIAL SIGNALS - In one embodiment, the present invention includes an electronic circuit comprising a first stage having a first differential inductive element and a second differential inductive element, and a second stage coupled to an output of the first stage, the second stage having a first differential inductive element and a second differential inductive element, wherein the first and second differential inductive elements of the first stage couple magnetically to generate a first phase error, wherein the first and second differential inductive elements of the second stage couple magnetically to generate a second phase error, and wherein the second phase error cancels the first phase error. | 2010-02-25 |
20100045405 | MULTI-LAYERED DEVICE AND ELECTRONIC EQUIPMENT USING THEREOF - A multi-layered device includes an inductor electrode layer connected between one end of a first viahole inductor conductor and a side-surface ground electrode, and arranged substantially in parallel to a dielectric sheet, when the first and second viahole inductor conductors are arranged in such a positional relation that a distance between the first and second viahole inductor conductors is smaller than 1.5 times a length of the first viahole inductor conductor. | 2010-02-25 |
20100045406 | RF FILTER MODULE - The present invention relates to a RF filter module adapted to be connected between an electric circuit and a least one antenna element. The filter module comprises a cavity within a filter housing having a housing wall, and at least one resonator being provided inside said cavity. The housing wall of the filter housing is provided with at least one aperture allowing RF signals to be coupled between an externally arranged non penetrating coupling part and the resonator (s) provided inside said cavity. The invention also relates to a RF filter arrangement and a system for communicating RF signals. | 2010-02-25 |
20100045407 | ELECTROMAGNETICALLY COUPLED INTERCONNECT SYSTEM ARCHITECTURE - An electromagnetic interconnect method and apparatus effects contactless, proximity connections between elements in an electronics system. Data to be communicated between elements in an electronic system are modulated into a carrier signal and transmitted contactlessly by electromagnetic coupling. The electromagnetic coupling may be directly between elements in the system or through an intermediary transmission medium. | 2010-02-25 |
20100045408 | Resonant Frequency Shifted Connector - A connector has data signal conductors for communicating data signals and voltage reference (power and ground) conductors for the signals' return currents. Voltage reference conductors carrying the same voltage level are coupled together at one or more points between the ends of the connector to shift the connector's resonant frequency beyond an operating frequency range of the data signals. Decoupling capacitors may alternatively or additionally be inserted between pairs of voltage reference conductors carrying high and low voltage levels at one or more points between the ends of the connector to shift the connector's resonant frequency beyond an operating frequency range of the data signals. | 2010-02-25 |
20100045409 | SUPERCONDUCTIVE MAGNET SYSTEM FOR A MAGNETIC RESONANCE EXAMINATION SYSTEM - A superconductive magnet system with a super conductive magnet is provided with a cooling system. A thermal switch is configured to thermally (de)couple the superconductive magnet from/to the cooling system so that the magnet can be decoupled from the cooling system e.g. in the event of a quench. | 2010-02-25 |
20100045410 | PLANAR-HELICAL UNDULATOR - A planar-helical undulator for emitting 360° electrically variable photo radiation, including a first coil and a second coil disposed relative to an undulator axis, an axis of the first coil and an axis of the second coil and the undulator axis being parallel to each other, and the undulator axis forming a portion of a synchrotron beam axis. Further, each of the first and second coils includes a helical section and a planar section. The windings of each respective section are connected in series, so that the planar section generates, when energized, a first magnetic field, and so that the helical section generates, when energized, a second magnetic field. Each planar section is disposed around the corresponding helical section, and at least one of the helical section and the planar section of at least one of the coils includes variable windings changing symmetrically over a length of the respective section towards a middle of the respective section. | 2010-02-25 |
20100045411 | R-T-B SINTERED MAGNET AND METHOD FOR PRODUCING THE SAME - An R-T-B based sintered magnet includes both a light rare-earth element R | 2010-02-25 |
20100045412 | SYSTEM AND METHOD FOR PRODUCING BIASED CIRCULAR FIELD EMISSION STRUCTURES - An improved field emission system and method is provided that involves field emission structures having electric or magnetic field sources. The magnitudes, polarities, and positions of the magnetic or electric field sources are configured to have desirable correlation properties, which may be in accordance with a code. The correlation properties correspond to a desired spatial force function where spatial forces between field emission structures correspond to relative alignment, separation distance, and the spatial force function. | 2010-02-25 |
20100045413 | SYSTEM AND METHOD FOR PRODUCING CIRCULAR FIELD EMISSION STRUCTURES - An improved field emission system and method is provided that involves field emission structures having electric or magnetic field sources. The magnitudes, polarities, and positions of the magnetic or electric field sources are configured to have desirable correlation properties, which may be in accordance with a code. The correlation properties correspond to a desired spatial force function where spatial forces between field emission structures correspond to relative alignment, separation distance, and the spatial force function. | 2010-02-25 |
20100045414 | METHOD FOR CODING FIELD EMISSION STRUCTURES USING A CODING COMBINATION - An improved field emission system and method is provided that involves field emission structures having electric or magnetic field sources. The magnitudes, polarities, and positions of the magnetic or electric field sources are configured to have desirable correlation properties, which may be in accordance with a code. The correlation properties correspond to a desired spatial force function where spatial forces between field emission structures correspond to relative alignment, separation distance, and the spatial force function. | 2010-02-25 |