08th week of 2011 patent applcation highlights part 62 |
Patent application number | Title | Published |
20110047340 | Proxy Backup of Virtual Disk Image Files on NAS Devices - A system and method for backing up a virtual machine executing on a virtualization server computer are described. A snapshot of a virtual disk image file of the virtual machine may be created on a network-attached storage (NAS) device coupled to the virtualization server computer. The snapshot may be used to backup the virtual disk image file from the NAS device to a backup storage device without transferring the virtual disk image file through the virtualization server computer. Mapping information useable to access the plurality of files stored in the virtual disk image file on an individual basis may be created and stored together with the backup copy of the virtual disk image file on the backup storage device. | 2011-02-24 |
20110047341 | REMOTE DATA BACKUP METHOD AND REMOTE DATA BACKUP SYSTEM USING THE SAME - A remote data backup method and a remote data backup system using the same are provided. The remote data backup system includes a data generating device which transmits data based on communication status, a data transmitting device which transmits the received data to outside, and a remote backup device which backs up the received data on real-time basis. As a result, images are transmitted to outside and backed up on real-time basis. | 2011-02-24 |
20110047342 | SIMULTANEOUS DATA BACKUP IN A COMPUTER SYSTEM - A data processing system using a client-server configuration includes a method and apparatus for simultaneously generating multiple copies of data sets in multiple storage pools. Simultaneous copies of data sets may be made for storage pools having LAN-free paths in addition to storage pools having only access from a LAN path. | 2011-02-24 |
20110047343 | DATA STORAGE SYSTEM FOR FAST REVERSE RESTORE - Techniques are provided for performing a copy operation. A fast reverse restore command indicating a new source and a new target is received, wherein the new source is an original target and the new target is an original source. A synchronous scan is performed on the new target. A new target structure associated with the new target is updated using a new source structure associated with the new source. Techniques are also provided for performing a copy operation in which a fast reverse restore command is received after an instant virtual copy has been performed from a new target to a new source and wherein the fast reverse restore command is performed before a background copy has been performed by the instant virtual copy. | 2011-02-24 |
20110047344 | STORAGE SYSTEM FOR A STORAGE POOL AND VIRTUAL VOLUMES - This invention provides a storage system to store data used by computers. A storage system coupled to a computer and a management apparatus, includes storage devices accessed by the computer and a control unit that controls the storage devices, in which the control unit performs the following operations: setting, in the storage devices, a first virtual device including a first logical device; setting a second virtual device which including a second logical device, which is a virtual volume accessed by the computer; allocating an address of the first logical device to the second logical device; and changing the allocation to change storage areas of the virtual volume. | 2011-02-24 |
20110047345 | STORAGE AREA NETWORK (SAN) FORECASTING IN A HETEROGENEOUS ENVIRONMENT - The present invention provides an approach for SAN forecasting in a heterogeneous environment. Specifically, under the present invention capacity data on the heterogeneous environment is gathered. Capacity management techniques will then be used to analyze the SAN utilization, identify growth trends and patterns. Proactively, plans are made to account for these changes. Thereafter, a Capacity Planning Margin (CPM) will be applied to the forecast to reflect actual customer usage. The CPM adjusted forecasts will then be reviewed. Then, the SAN environment can be monitored by comparing actual vs. planned and return to adjust the forecast accordingly. | 2011-02-24 |
20110047346 | EFFICIENT INTERLEAVING BETWEEN A NON-POWER-OF-TWO NUMBER OF ENTITIES - Some embodiments of the present invention provide a system that maps an address to an entity, wherein the mapping interleaves addresses between a number of entities. During operation, the system receives an address A from a set of X consecutive addresses, wherein the address A is to be mapped to an entity E in a set of Y entities, and wherein Y need not be a power of two. Next, the system obtains F=floor(log | 2011-02-24 |
20110047347 | MAPPING ALIGNMENT - In general, this disclosure is directed to techniques for adjusting a mapping between a logical block address (LBA) space and a physical block address (PBA) space based on offset data associated with a plurality of access requests. According to one aspect, a method includes defining a translation map between a plurality of LBAs and a plurality of PBAs for a data storage device. Each PBA is associated with a sequence of storage slots. The translation map maps each of the LBAs to a PBA and to an index of a storage slot associated with the PBA. The method further includes obtaining offset data for a plurality of access requests associated with the plurality of LBAs. The offset data includes information relating to the indices to which starting LBAs of the access requests are mapped. The method further includes adjusting the translation map based on the offset data. | 2011-02-24 |
20110047348 | PROCESSING ELEMENTS, MIXED MODE PARALLEL PROCESSOR SYSTEM, PROCESSING METHOD BY PROCESSING ELEMENTS, MIXED MODE PARALLEL PROCESSOR METHOD, PROCESSING PROGRAM BY PROCESSING ELEMENTS AND MIXED MODE PARALLEL PROCESSING PROGRAM - Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N÷S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, which S memories inherently belong to the PEs, where P2011-02-24 | |
20110047349 | PROCESSOR AND PROCESSOR CONTROL METHOD - A processor includes a plurality of subfunctional units provided corresponding to respective slots of one or more pieces of operation result data including a plurality of slots for an SIMD operation; and an enable generating unit configured to, in each of the one or more pieces of the operation result data, compare a value of a predetermined slot with a value of a slot other than the predetermined slot, and disable one or more subfunctional units to which the value equal to the value of the predetermined slot is inputted, and the processor outputs the value of the predetermined slot as the value of the one or more subfunctional units which have been disabled. | 2011-02-24 |
20110047350 | PARTITION LEVEL POWER MANAGEMENT USING FULLY ASYNCHRONOUS CORES WITH SOFTWARE THAT HAS LIMITED ASYNCHRONOUS SUPPORT - A partition that is executed by multiple processing nodes. Each node includes multiple cores and each of the cores has a frequency that can be set. A first frequency range is provided to the cores. Each core, when executing the identified partition, sets its frequency within the first frequency range. Frequency metrics are gathered from the cores running the partition by the nodes. The gathered frequency metrics are received and analyzed by a hypervisor that determines a second frequency range to use for the partition, with the second frequency range being different from the first frequency range. The second frequency range is provided to the cores at the nodes executing the identified partition. When the cores execute the identified partition, they use a frequencies within the second frequency range. | 2011-02-24 |
20110047351 | ROUTING IMAGE DATA ACROSS ON-CHIP NETWORKS - A network of switches may be adapted to route image data to one or more processor cores based on tags associated with data samples, where each tag includes at least one reference-space coordinate value. When image data is received by the network, the image data may be spatially transformed to a reference space, e.g., the physical space that is represented by the image data, to generate the data samples and each data sample may be tagged with a corresponding reference space coordinate value and routed through the network to one or more of the processors according to the tag. | 2011-02-24 |
20110047352 | MEMORY COHERENCE DIRECTORY SUPPORTING REMOTELY SOURCED REQUESTS OF NODAL SCOPE - A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node. | 2011-02-24 |
20110047353 | RECONFIGURABLE DEVICE | 2011-02-24 |
20110047354 | Processor Cluster Architecture and Associated Parallel Processing Methods - A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device. | 2011-02-24 |
20110047355 | Offset Based Register Address Indexing - A circuit arrangement and method support offset based register address indexing, wherein register addresses to be used by an instruction are calculated using offsets to the full target register address, and the offsets are contained in the instruction and occupy less instruction space than the full address widths. An instruction may include at least one offset value that identifies a register address. During decoding of the instruction, an offset and a full target address are retrieved from the instruction, and then a register address is calculated by addition of the offset to the full target address. | 2011-02-24 |
20110047356 | APPARATUS,SYSTEM,AND METHOD FOR MANAGING COMMANDS OF SOLID-STATE STORAGE USING BANK INTERLEAVE - An apparatus, system, and method are disclosed for efficiently managing commands in a solid-state storage device that includes a solid-state storage arranged in two or more banks. Each bank is separately accessible and includes two or more solid-state storage elements accessed in parallel by a storage input/output bus. The solid-state storage includes solid-state, non-volatile memory. The solid-state storage device includes a bank interleave that directs one or more commands to two or more queues, where the one or more commands are separated by command type into the queues. Each bank includes a set of queues in the bank interleave controller. Each set of queues includes a queue for each command type. The bank interleave controller coordinates among the banks execution of the commands stored in the queues, where a command of a first type executes on one bank while a command of a second type executes on a second bank. | 2011-02-24 |
20110047357 | Methods and Apparatus to Predict Non-Execution of Conditional Non-branching Instructions - Efficient techniques are described for not executing an issued conditional non-branch instruction. A conditional non-branch instruction is identified as being eligible for a prediction, the prediction indicating that the eligible conditional non-branch (ECNB) instruction would not execute. The ECNB instruction executes as a no operation (NOP) instruction in response to the prediction that the ECNB instruction would not execute. A source operand required for the ECNB instruction to execute is not fetched in response to the prediction to not execute. | 2011-02-24 |
20110047358 | In-Data Path Tracking of Floating Point Exceptions and Store-Based Exception Indication - Mechanisms are provided for tracking exceptions in the execution of vectorized code. A speculative instruction is executed on a vector element of a vector. An exception condition is detected in association with the vector element based on a result of executing the speculative instruction on the vector element. A special exception value is stored in the vector element in a vector register corresponding to the vector, indicative of the exception condition, without invoking an exception handler for the exception condition. The special exception value is propagated with the vector element of the vector through a processor architecture of the processor, without invoking the exception handler for the exception condition. An exception corresponding to the exception condition indicated by the special exception value is generated only in response to a non-speculative instruction being executed that performs a non-speculative operation on the vector element. | 2011-02-24 |
20110047359 | Insertion of Operation-and-Indicate Instructions for Optimized SIMD Code - Mechanisms are provided for inserting indicated instructions for tracking and indicating exceptions in the execution of vectorized code. A portion of first code is received for compilation. The portion of first code is analyzed to identify non-speculative instructions performing designated non-speculative operations in the first code that are candidates for replacement by replacement operation-and-indicate instructions that perform the designated non-speculative operations and further perform an indication operation for indicating any exception conditions corresponding to special exception values present in vector register inputs to the replacement operation-and-indicate instructions. The replacement is performed and second code is generated based on the replacement of the at least one non-speculative instruction. The data processing system executing the compiled code is configured to store special exception values in vector output registers, in response to a speculative instruction generating an exception condition, without initiating exception handling. | 2011-02-24 |
20110047360 | PROCESSOR - The present application provides a method of randomly accessing a compressed structure in memory without the need for retrieving and decompressing the entire compressed structure. | 2011-02-24 |
20110047361 | Load/Move Duplicate Instructions for a Processor - A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register. | 2011-02-24 |
20110047362 | Version Pressure Feedback Mechanisms for Speculative Versioning Caches - Mechanisms are provided for controlling version pressure on a speculative versioning cache. Raw version pressure data is collected based on one or more threads accessing cache lines of the speculative versioning cache. One or more statistical measures of version pressure are generated based on the collected raw version pressure data. A determination is made as to whether one or more modifications to an operation of a data processing system are to be performed based on the one or more statistical measures of version pressure, the one or more modifications affecting version pressure exerted on the speculative versioning cache. An operation of the data processing system is modified based on the one or more determined modifications, in response to a determination that one or more modifications to the operation of the data processing system are to be performed, to affect the version pressure exerted on the speculative versioning cache. | 2011-02-24 |
20110047363 | Microprogrammable Device Code Tracing - A microprogrammable electronic device has a first code memory storing instructions, and is configured to execute each instruction in the first code memory at a respective instruction cycle. The system comprises binary code generating means, and a tracing device. The binary code generating means form part of the device , and are configured to generate and output on a single pin of the device binary codes, each of which indicates a corresponding execution-related event, is generated and outputted at a corresponding instruction cycle, and has N bits, where N is an integer >=2. The tracing device is coupled with the single pin to receive the binary codes, and has a second code memory in which the instructions are stored. The tracing device is configured to trace instructions executed by the device, on the basis of the received binary codes and of the instructions stored in the second code memory. | 2011-02-24 |
20110047364 | Recovering from an Error in a Fault Tolerant Computer System - A leading thread and a trailing thread are executed in parallel. Assuming that no transient fault occurs in each section, a system is speculatively executed in the section, with the leading thread and the trailing thread preferably being assigned to two different cores. At this time, the leading thread and the trailing thread are simultaneously executed, performing a buffering operation on a thread local area without performing a write operation on a shared memory. When the respective execution results of the two threads match each other, the content buffered to the thread local area is committed and written to the shared memory. When the respective execution results of the two threads do not match each other, the leading thread and the trailing thread are rolled back to a preceding commit point and re-executed. | 2011-02-24 |
20110047365 | System and Method to Manipulate a System Setting When Booting an Information Handling System - A method of manipulating a system setting when booting an information handling system can include providing an update request repository that includes a plurality of entries. Each of the plurality of entries can correspond to a particular system setting. A system setting value associated with each entry can be included in a handoff block (HOB) of a plurality of handoff blocks associated with a cache. The method also includes receiving a command from a PEI module (PEIM) indicating a change to be made to a particular system setting at the information handling system. The method also includes creating or changing a particular entry of the update request repository based on the command. | 2011-02-24 |
20110047366 | BOOTING IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION - The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments include a host and a number of devices coupled to the host in a chained configuration, wherein at least one of the number of devices is a bootable device and the at least one bootable device is not directly coupled to the host. | 2011-02-24 |
20110047367 | Combining Resources of Multiple Bios Roms and Managing Them As A Single Entity - A method and related computer program product for combining resources of multiple RAID controllers and managing them as a single entity, comprising searching the RAID controllers for the most appropriate version of the firmware to be executed, determining whether a more appropriate version of the firmware was previously loaded into system memory, unloading inappropriate versions of the firmware, loading the most appropriate version of the firmware and initializing all RAID controllers as a commonly managed entity having combined resources. | 2011-02-24 |
20110047368 | Application Display on a Locked Device - A user request to display an application while the device is locked is received. In response to this user request, one or more images generated by the application are obtained and displayed while the device is locked. Additionally, an indication of an application to be displayed upon resuming operation from a power-saving mode can be received, and an image generated by the application is displayed in response to resuming operation from the power-saving mode. | 2011-02-24 |
20110047369 | Configuring Software Agent Security Remotely - A device, method, computer program product, and network subsystem are described for receiving information from a remote agent locally and responding to the information from the remote agent by deciding whether to signal a change of a security configuration of the remote agent. | 2011-02-24 |
20110047370 | SYSTEMS AND METHODS FOR RE-COMMISSIONING A CONTROLLED DEVICE IN A HOME AREA NETWORK - Systems and methods for preparing and re-commissioning a controlled device in a home area network are described. A utility meter is communicated with. An authentication key and encryption data for communicating with the utility meter may be determined. The authentication key and encryption data are sent to a controlled device. A set of translation rules for a message are determined. The translation rules are sent to the controlled device. The controlled device establishes a secure communication link with the utility meter using the authentication key and the encryption data. The controlled device receives a request to change power usage from the utility meter over the secure communication link. The controlled device translates the request to change power usage into control instructions using the translation rules. | 2011-02-24 |
20110047371 | SYSTEM AND METHOD FOR SECURE DATA SHARING - A system and method for providing secure data storage and retrieval is disclosed. The system utilizes a protocol for distributing authentication tokens amongst potential recipients of information. Digital information is then disseminated via the system to authorized recipients. Various types of hardware and software authentication devices may be utilized to provide additional security during the storage and retrieval processes. | 2011-02-24 |
20110047372 | MASHAUTH: USING MASHSSL FOR EFFICIENT DELEGATED AUTHENTICATION - The present invention provides a method that allows the MashSSL protocol to be used to provide a secure and efficient way for delegated authentication. The invention allows services which already have an SSL infrastructure to reuse that infrastructure for delegated authentication, and to do so in a fashion where the cryptographic overhead is amortized across multiple users, and which provides the user with greater control of what information is shared on their behalf. | 2011-02-24 |
20110047373 | USER AUTHENTICATION SYSTEM AND METHOD FOR THE SAME - At the user authentication apparatus | 2011-02-24 |
20110047374 | METHOD AND APPARATUS FOR A CONFIGURABLE ONLINE PUBLIC KEY INFRASTRUCTURE (PKI) MANAGEMENT SYSTEM - A method and apparatus are provided for generating identity data to be provisioned in product devices that are a part of a project. The method includes establishing a template associated with each CA in a hierarchical chain of CAs having a root CA at a highest level in the chain and a signing CA at a lowest level in the chain. The template associated with the signing CA inherits mandatory attribute fields specified in the root CA and any intermediate CA in the hierarchical chain. The mandatory attribute fields are user-specifiable fields to be populated with PKI data. A configuration file is generated upon receipt of an order for digital certificates using PKI data provided by a user to populate the mandatory attribute fields of the template associated with the signing CA. The digital certificates requested in the order are generated using the PKI data in the configuration file. | 2011-02-24 |
20110047375 | COMMUNICATION METHOD FOR MULTISUBSCRIBER NETWORKS, WHICH IS PROTECTED FROM DECEPTION, EAVESDROPPING AND HACKING - The invention relates to a P2P communication method for multi-subscriber networks, which is protected from deception, eavesdropping and hacking, and wherein the communication carried out in an interval is predominantly carried out in separate rooms, allocated to the P2P communication, and with separate reference data allocated to the P2P communication. At least part of the separate random reference data and/or random data is generated in at least one unit that participates in the P2P communication and is exchanged within the P2P communication in the form of relative data. The separate P2P communication is initiated with respect to at least one global random reference date valid for the time of the P2P communication, the random reference date being valid for a randomly determined time range and being stored in all units that carry out the P2P communications in a secret and non-deceivable manner. | 2011-02-24 |
20110047376 | METHOD AND APPARATUS FOR SECURE EXECUTION USING A SECURE MEMORY PARTITION - A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code. | 2011-02-24 |
20110047377 | SECURE DIGITAL COMMUNICATIONS VIA BIOMETRIC KEY GENERATION - Systems and methods for secure communications in a communications network ( | 2011-02-24 |
20110047378 | SYSTEM AND METHOD FOR IDENTIFYING ACCOUNT AND PERIPHERAL DEVICE THEREOF - An account identification system, an account identification method, and a peripheral device thereof are provided, wherein the peripheral device has a private key. When a user is about to log into an identification server, besides identifying an account and a password of the user, the identification server further authenticates the peripheral device used by the user so as to identify the user and prevent the user's account from being misappropriated. | 2011-02-24 |
20110047379 | APPARATUS AND METHOD FOR TRANSMITTING DIGITAL MULTIMEDIA BROADCASTING DATA, AND METHOD AND APPARATUS FOR RECEIVING DIGITAL MULTIMEDIA BROADCASTING DATA - Provided are a method and apparatus for transmitting digital multimedia broadcasting data, and a method and apparatus for receiving digital multimedia broadcasting data. A basic audio signal and a multichannel audio signal are encoded to generate a basic audio stream and a multichannel audio stream, and a first data stream describing property and position data of the basic audio stream and a second data stream describing property and position data of the multichannel audio stream are transmitted as independent streams. According to the performance of the receiving apparatus, an audio signal may be decoded by using just the first data stream only or both the first data stream and the second stream. | 2011-02-24 |
20110047380 | PEER-TO-PEER NETWORK INFORMATION STORAGE - In a typical peer-to-peer network, any user of the peer-to-peer network may request a lookup of a key and its associated value. To limit access to a stored key-value pair, a user node may register a key-value pair in a peer-to-peer network associated with an access list listing those user nodes which are authorized to access the key-value pair. The access list may include one or more retrieval identifiers. To further secure the information, the retrieval identifiers and/or the payload may be encrypted. To allow the retrieving user to decrypt an encrypted payload, the payload may be encrypted using a group key associated with the stored key-value pair. The group key may be encrypted using a key known to the retrieving user. | 2011-02-24 |
20110047381 | SAFEMASHUPS CLOUD TRUST BROKER - The present invention provides a new method for policy enforcement in a virtualized or cloud environment. We break down the environment into layers, which are further sub-divided into security units. Each security unit has a security profile based on its own security properties and those of the layers below. The security profile also reflects the floor, ceiling and wall security properties. Each security unit has an agent which is used to establish communications with other security units. Such communication is mediated by a cloud trust broker which determines if the communication is permitted based on access control list or else retrieves the security profiles and applies pre-defined rules. If the communications are allowed the cloud trust broker runs a mutual authentication and key distribution protocol that results in the two security units obtaining a session key which they can then use for further communications which can proceed directly. | 2011-02-24 |
20110047382 | FAST AUTHENTICATION BETWEEN HETEROGENEOUS WIRELESS NETWORKS - A method for preparing for handover of an apparatus from a first wireless network to a second, different wireless network, a master session key (MSK) having been generated during establishment of a connectivity of the apparatus to the first wireless network includes detecting signals of the second wireless network. In response thereto, establishing a connectivity of the apparatus to the second wireless network, using a pairwise master key (PMK) derived from the MSK generated during establishment of the connectivity to the first wireless network, one or more encryption keys being derivable from the PMK to support secure communication over the second wireless network. | 2011-02-24 |
20110047383 | SECURE PEER-TO-PEER MESSAGING INVITATION ARCHITECTURE - First and second communication devices respectively have first and second personal identification numbers (PINs). The first communication device transmits to the second communication device a first encryption key, and receives from the second communication device the second PIN that has been encrypted by the second communication device using the first encryption key. The first communication device receives from the second communication device a second encryption key, decrypts the encrypted second PIN, and encrypts the first PIN using the second encryption key, and transmits the encrypted first PIN to the second communication device. The first communication device conducts, with the second communication, device a peer-to-peer messaging session by transmitting to the second communication device peer-to-peer messages that contain the second PIN and receiving from the second communication device peer-to-peer messages that contain the first PIN. Each message is routed by a routing server based on the respective first and second PINs. | 2011-02-24 |
20110047384 | ESTABLISHING AN AD HOC NETWORK USING FACE RECOGNITION - Ad hoc network formation is provided in connection with using face recognition and simple device pairing to build a network. Upon determining the identity of an individual using, for instance, a software recognition program, various protocols may be used to implement the formation of the ad hoc network. | 2011-02-24 |
20110047385 | Methods and Systems for Digitally Signing a Document - Methods and systems according to various embodiments provide a voice-based digital signature to a digital document. For example, a user can access a website to fill in or compete a digital document such as an insurance application (e.g., an application for Medicare supplement insurance), and can call an interactive voice response (“IVR”) system to provide a voice-based (or oral or aural) digital signature to the digital document. The digital signature can then be attached, related, or appended to that digital document in place of a traditional signature. Thus, the digital document need not be printed and sent to the user for a signature. | 2011-02-24 |
20110047386 | SIGNING METHOD, APPARATUS, AND SYSTEM - A signing method, apparatus, and system, which relate to the information security field. The present invention overcomes the problem of signature counterfeit in prior art. The client host generates a transaction message and determines the key information of the message after receiving transaction information entered by a user, forms a data packet for signing, and transmits the data packet to the USB key, which will then extract the key information and output it for confirmation by the user, and if a confirmation is received, the USB key signs the data packet and transmits a signature to the client host; after receiving the signature and the transaction message from the client host, the server extracts the key information from the transaction message to form a data packet for signing and verifies the signature against the data packet. The embodiments of the present invention are mainly applicable to the field of information security. | 2011-02-24 |
20110047387 | Method of Access Control and Corresponding Device - A computing device which includes an access control mechanism which is used to control access to keys which are used in cryptographic processes. Any application wishing to gain access to a key must first obtain authorisation from the access control mechanism. Authorised applications may access keys directly, without having to pass data through the access control mechanism. | 2011-02-24 |
20110047389 | Trusted Infrastructure Support Systems, Methods and Techniques for Secure Electronic Commerce Electronic Transactions and Rights Management - An integrated, modular array of administrative and support services are provided for electronic commerce and electronic rights and transaction management. These administrative and support services supply a secure foundation for conducting transaction-related capabilities over electronic networks, and can also be adapted to the specific needs of electronic commerce value chains. In one embodiment a Distributed Commerce Utility having a secure, programmable, distributed architecture provides these administrative and support services. The Distributed Commerce Utility may comprise a number of Commerce Utility Systems. These Commerce Utility Systems provide a web of infrastructure support available to, and reusable by, the entire electronic community and/or many of its participants. Different support functions can be collected together in hierarchical and/or networked relationships to suit various business models or other objectives. Modular support functions can be combined in different arrays to form different Commerce Utility Systems for different design implementations and purposes. | 2011-02-24 |
20110047390 | Power Restoration To Blade Servers - Power restoration to blade servers including maintaining a list of blade server identifications and a value of power saving for each capped blade server; identifying losing power to the capped blade servers; restoring power to the previously capped blade servers in order of the values of power savings. | 2011-02-24 |
20110047391 | ELECTRONIC DEVICE AND MOTHERBOARD THEREOF - An electrical device includes a motherboard and a daughter board. The daughter board includes a plurality of signal pins to output signals for denoting a type of the daughter board. The motherboard includes a controller and a voltage adjusting unit. The controller receives the signals from the signal pins of the daughter board to identify the type of the daughter board and outputs control signals according to the signals received from the daughter board. The voltage adjusting unit receives the control signals and adjusts a voltage from a voltage source into a work voltage according the control signal, and outputs the work voltage to the electrical element. | 2011-02-24 |
20110047392 | DEVICE AND METHOD FOR DETECTING MOTHERBOARD VOLTAGE - A voltage detecting device is provided to detect voltage value of a voltage identification (VID) module on a motherboard. The VID module has a plurality of VID module pins. The voltage detecting device includes a signal transforming module and a main control circuit. The signal transforming module is couple with the VID module. The main control circuit is connected to the signal transforming module. The main control circuit is capable of causing the signal transforming module to read voltage signal at each VID module pin, transforming each voltage signal to a group of binary data, decrypting each group of binary data to a corresponding binary level code, constructing a binary level code combination, and determining actual voltage value corresponding to the binary level code combination. | 2011-02-24 |
20110047393 | External Device Charging While Notebook Is Off - A computer comprises a power supply that provides operating power for the computer and a connector on the computer through which an external device can be coupled to the computer. The power supply powers an auxiliary power rail even when the computer is otherwise off. The auxiliary power rail is provided to the connector to thereby provide power to the external device even when the computer is off. | 2011-02-24 |
20110047394 | ELECTRICAL POWER SAVING SYSTEM - An electrical power saving system that achieves efficient electricity consumption of apparatuses connected via a communication network includes at least first and second apparatuses connected via the communication network. The first and second apparatuses each include: a transmission and reception unit that transmits and receives a control command via the communication network, the control command being a command by which one apparatus controls another apparatus; and an operation state switching unit that switches an operation state according to the control command. The first and second apparatuses each have, as operation states of different electricity consumption, a first OFF operation mode in which the apparatus is in a power-OFF state but a part of the apparatus is supplied with power, and a second OFF operation mode of lower electricity consumption than the first OFF operation mode. The operation state switching unit in the second apparatus switches the operation state of the second apparatus from the first OFF operation mode to the second OFF operation mode in the case where, when the second apparatus is in the first OFF operation mode, the transmission and reception unit in the second apparatus receives a control command instructing to switch the operation state, from the first apparatus. | 2011-02-24 |
20110047395 | Platform Communication Protocol - A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state. | 2011-02-24 |
20110047396 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD AND PROGRAM - An information processing apparatus including (a) a storage section storing AC adapter capacity identification, (b) a first section for outputting the AC adapter capacity information, (c) a setting section for setting threshold values used to control power consumption of the apparatus, (d) a detection section for detecting the power consumption of the apparatus, and (e) a control section for controlling power consumption based on whether the power consumption exceeds one of the thresholds. | 2011-02-24 |
20110047397 | POWER GATING DEVICE - A power gating device may include a control unit that generates a first interrupt signal based on a mode change signal when a mode of a system is changed from a normal operation mode to a stand-by mode, and generates a second interrupt signal based on the mode change signal when the mode is changed from the stand-by mode to the normal operation mode, a memory unit that stores data of a function block based on the first interrupt signal, and restores the stored data to the function block based on the second interrupt signal, and a power source unit that provides a normal operation power to the function block and the memory unit based on a power down signal in the normal operation mode, and provides a stand-by power to the memory unit based on the power down signal in the stand-by mode. | 2011-02-24 |
20110047398 | POWER SUPPLY UNIT, PROCESSING SYSTEM, AND ID ASSIGNMENT METHOD - A power supply unit includes a communication unit and a control unit. The communication unit is capable of performing communication with a first processing unit group constituted of a plurality of processing units connected thereto. The control unit controls powers to the plurality of processing units through the communication so that the powers are turned on in an order corresponding to an order of connection and assigns, to the plurality of processing units, respectively, IDs of numbers corresponding to the order of turning-on of the powers each time the power is turned on. | 2011-02-24 |
20110047399 | METHOD AND SYSTEM FOR MANAGING ELECTRICAL POWER SUPPLY OUTAGES ON BOARD AN AIRCRAFT - A method of managing an electrical power supply outage on board an aircraft, including the following operations: —detection of an electrical power supply outage, —measurement of a duration of the power supply outage by measuring a discharge time of a capacitor and comparing this measured duration with a threshold duration, —saving a long outage indication when the duration of the outage is greater than a threshold duration. The disclosed embodiments also relates to a system implementing this method and including: —a circuit for detecting an electrical power supply outage, —a circuit for measuring a duration of the power supply outage, and—a circuit for managing indications able to manage emissions of signals according to the measured duration of the power supply outage. | 2011-02-24 |
20110047400 | Systems and Methods to Efficiently Schedule Commands at a Memory Controller - Systems and methods to respond to schedule commands at a memory controller are disclosed. A transmission error between a first memory controller port and a first redrive device may be detected. A first corrective action may be initiated at the first memory controller port in response to the detection of the transmission error. A particular method may include determining that a second memory controller port initiated a second corrective action. Incoming read commands may be distributed based on a comparison of the first corrective action and the second corrective action. | 2011-02-24 |
20110047401 | Providing Adaptive Frequency Control For A Processor - In one embodiment, the present invention includes a method for receiving utilization data from thread units of one or more processor cores, determining an operating frequency for a core clock signal based on the utilization data, a target utilization value, and an operating mode of the processor, and generating the core clock signal based on the determined operating frequency. Other embodiments are described and claimed. | 2011-02-24 |
20110047402 | DYNAMIC PROGRAMMABLE DELAY SELECTION CIRCUIT AND METHOD - A controller may include a measurement circuit configured to generate a proxy signal representing delay variations in the controller. The measurement circuit may also generate a measurement value from the proxy signal. A control circuit may be configured to convert the measurement value into a control value. A delay circuit may be adjusted by the control value to alter an amount of delay of a signal. | 2011-02-24 |
20110047403 | IMAGE FORMING APPARATUS - This invention provides an image forming apparatus that suppresses a control error between CPUs when the CPUs operate in cooperation with each other in distributed control by the CPUs. To accomplish this, the image forming apparatus utilizes a distributed control system. Respective CPUs measure time interval concerning image formation processing using their built-in clock oscillators, and perform operations in cooperation with each other. Correction coefficients are calculated based on the time interval measured by the respective CPUs to correct a measurement error generated by the operation an error of the respective clock oscillators. Clock count values each indicating a timing to drive a load is corrected based on the correction coefficients. | 2011-02-24 |
20110047404 | ANALYSIS AND PREDICTION SYSTEMS AND METHODS FOR RECOVERY BASED SOCIAL NETWORKING - Systems and methods for recovery based social networking are presented. An analysis module analyzes past and current activity of users on the social networking platform. The analysis module predicts, based on user activity, when particular users will need support from user identified supporters and healthcare professionals. The analysis module sends alert messages to the pre-determined supporters and healthcare professionals soliciting support responsive to the predictions. | 2011-02-24 |
20110047405 | System and Method for Implementing an Intelligent Backup Technique for Cluster Resources - Method and system for implementing a backup in a cluster comprising a plurality of interconnected nodes, at least one of the nodes comprising a cluster resource manager (CRM), and at least one of the nodes comprising a policy engine (PE), the PE maintaining at least one dependency associated with at least a first resource executing on at least one of the nodes. For example, the method comprises, receiving by the CRM a backup request for the first resource from an administrator; responsive to the request, updating by the CRM the cluster configuration; communicating by the CRM to the PE a cluster status and the updated configuration; providing by the PE to the CRM an instruction sequence for carrying out the backup, the instruction sequence based on the dependency associated with the first resource; and responsive to the instruction sequence, carrying out by the CRM the backup of the first resource. | 2011-02-24 |
20110047406 | SYSTEMS AND METHODS FOR SENDING, RECEIVING AND MANAGING ELECTRONIC MESSAGES - Systems and methods for electronic message may include receiving information from a sending device. The information may include a prioritization determination, initial receiving device destinations, alternate receiving device destinations, and a determination of a plurality of responses to message delivery failures from the sending device. Data may be attached to the message before encrypting and sending. Status information about the message may be received, provided to the sending device, and updated. If message delivery failure occurs, the message may be sent to one or more alternate receiving device destinations. Status information about the message may again be received, provided to the sending device, and updated. Message and status information may be stored in a database. | 2011-02-24 |
20110047407 | POWER AND DATA REDUNDANCY IN A SINGLE WIRING CLOSET - Redundancy of data and/or Inline Power in a wired data telecommunications network from a first network device and a second network device configured as power sourcing equipment (PSE) devices and coupled together and to a third network device (such as a PD) via a Y device is provided by providing redundant signaling to/from each of the pair of network devices, and coupling a port of each of the network devices to the Y device and from there to a third port where a third network device such as a PD may be coupled. Because the Y device is essentially passive, communications paths between the PSE devices and the PD are provided for negotiating master/slave status and other status and related information among the respective network devices. Dynamic impedance matching is provided to handle situations where not all devices are plugged in and as a communications technique among the devices. | 2011-02-24 |
20110047408 | Handling of hard errors in a cache of a data processing apparatus - A data processing apparatus and method are provided for handling hard errors. The data processing apparatus comprises processing circuitry for performing data processing operations, and cache storage having a plurality of cache records for storing data values for access by the processing circuitry when performing the data processing operations. A cache record error storage having at least one error record, and a hard error storage having at least one hard error record, are provided for keeping track of errors detected when accessing cache records of the cache storage. In particular, when an error is first detected for a particular cache record, one of the error records in the cache record error storage is allocated to store a cache record identifier for that cache record, and an associated count value is set to a first value. Further, if an error is detected when accessing a cache record, a correction operation is performed in respect of that currently accessed cache record, and access to that currently accessed cache record is then re-performed. Each time an error is detected for subsequent accesses to that cache record, the count value is incremented, and each time an error is not detected when that cache record is accessed, the count value is decremented. If the count value reaches a predetermined threshold value, then the cache record identifier is moved from the cache record error storage to an error record of the hard error storage. Any cache record whose cache record identifier is stored in the hard error storage is logically excluded from the plurality of cache records of the cache storage for the purposes of subsequent operation of the cache storage. Such an approach provides a hardware mechanism that automatically identifies and corrects hard and soft errors, but only masks from further use those cache records affected by hard errors. | 2011-02-24 |
20110047409 | STORAGE DEVICE SUPPORTING AUTO BACKUP FUNCTION - A storage device having an automatic backup function, which is connected to a host apparatus to store user data, is provided. The storage device includes a storage medium which stores the user data, and a controller which controls data writing and reading of the storage medium. The controller backs up at least a portion of the user data stored in the storage medium in an available region of the storage medium when the storage device is in an idle mode. | 2011-02-24 |
20110047410 | REDUNDANT CONFIGURATION METHOD OF A STORAGE SYSTEM MAINTENANCE/MANAGEMENT APPARATUS - Provided is a method of managing a computer system including a plurality of storage systems and a plurality of management appliances for managing the plurality of storage systems. A first management appliance and a second management appliance hold an identifier of a first storage system and management data obtained from the first storage system. The method includes the steps of selecting a third management appliance from the plurality of management appliances when a failure occurs in the first management appliance; transmitting the identifier held in the second management appliance from the second management appliance to the selected third management appliance; and holding the identifier transmitted from the second management appliance in the selected third management appliance. Thus, it is possible to prevent, after failing-over due to an abnormality of a maintenance/management appliance, a single point of failure from occurring to reduce reliability of the maintenance/management appliance. | 2011-02-24 |
20110047411 | Handling of errors in a data processing apparatus having a cache storage and a replicated address storage - A data processing apparatus and method are provided for handling errors. The data processing apparatus comprises processing circuitry for performing data processing operations, a cache storage having a plurality of cache records for storing data values for access by the processing circuitry when performing the data processing operations, and a replicated address storage having a plurality of entries, each entry having a predetermined associated cache record within the cache storage and being arranged to replicate the address indication stored in the associated cache record. On detecting a cache record error when accessing a cache record of the cache storage, a record of a cache location avoid storage is allocated to store a cache record identifier for the accessed cache record. On detection of an entry error when accessing an entry of the replicated address storage, use of the address indication currently stored in that accessed entry of the replicated address storage is prevented, and a command is issued to the cache location avoid storage. In response to the command, a record of the cache location avoid storage is allocated to store the cache record identifier for the cache record of the cache storage associated with the accessed entry of the replicated address storage. Any cache record whose cache record identifier is stored in the cache location avoid storage is logically excluded from the plurality of cache records of the cache storage for the purposes of subsequent operation of the cache storage. Such an approach enables errors to be correctly handled, prevents errors from spreading in a system, and minimises communication necessary on detection of an error in a data processing apparatus having both a cache storage and a replicated address storage. | 2011-02-24 |
20110047412 | PARALLEL PROGRAMMING ERROR CONSTRUCTS - A system receives a program, allocates the program to a first software unit of execution (UE) and a second software UE, executes a first portion of the program with the first and second software UEs in parallel, and determines whether an error is detected during execution of the first portion of the program by the first and second software UEs. The system also sends a signal, between the first and second software UEs, to execute a second portion of the program when the error is detected in the first portion of the program, executes the second portion of the program with the first and second software UEs when the error is detected, and provides for display information associated with execution of the first portion and the second portion of the program by the first and second software UEs. | 2011-02-24 |
20110047413 | METHODS AND DEVICES FOR DETECTING SERVICE FAILURES AND MAINTAINING COMPUTING SERVICES USING A RESILIENT INTELLIGENT CLIENT COMPUTER - Intelligent client computing devices track and record the changes they make to data, applications, and services. Systems, devices, and computer readable media for detecting service tier failures and maintaining application services provide a resilient client architecture that allows a client application on an intelligent client to automatically detect the unavailability of server tiers or sites and re-route requests and updates to secondary sites to maintain application services at the client tier in a manner that is transparent to a user. The resilient client architecture understands the level of currentness of secondary sites in order to select the best secondary site and to automatically and transparently bring this secondary site up to date to ensure no data updates are missing from the secondary site. | 2011-02-24 |
20110047414 | METHOD AND APPARATUS FOR CAUSE ANALYSIS INVOLVING CONFIGURATION CHANGES - A technique determines which configuration change(s) caused an application invocation failure of a computer application without the need for a knowledge database. To determine which configuration change is the most likely cause, the cause analysis program ( | 2011-02-24 |
20110047415 | DEBUGGING OF BUSINESS FLOWS DEPLOYED IN PRODUCTION SERVERS - Facilitating debugging of business flows deployed on a production server. An aspect of the present invention processes some service requests (received from a client system) in a normal mode and some other service requests in a debug mode concurrently, all according to a business flow. According to another aspect, the debug mode supports a single step debug operation, in which each step corresponds to a single activity of the business flow. Accordingly, an administrator of the production server is enabled to better determine, the problems in the execution of business flows deployed on a production server at runtime. | 2011-02-24 |
20110047416 | Method and Apparatus for Using a One-Time or Few-Time Programmable Memory with a Host Device Designed for Erasable-Rewriteable Memory - The embodiments described herein can be used to enable one-time or few-time programmable memories to work with existing consumer electronic devices (such as those that work with flash—an erasable, non-volatile memory) without requiring a firmware upgrade, thereby providing backwards compatibility while minimizing user impact. As such, these embodiments are a viable way to bridge one-time or few-time programmable memories with existing consumer electronic devices that have flash card slots. These embodiments also allow future consumer electronic devices to be designed without updating firmware to include a file system customized for a one-time or few-time programmable memory. | 2011-02-24 |
20110047417 | METHOD AND SYSTEM FOR ERROR DETECTION IN PATTERN DEFINITIONS - A method and system for detecting errors in stored pattern definitions. The method describes structuring a pattern definition into a specified format and creating a pattern definition file. The structured pattern definition contents are hashed to generate a filename for the pattern definition file. This filename, along with a corresponding identifier, is added to an identifier document. Each filename in the identifier document is compared with all other filenames to determine a degree of overlap. A potential error is indicated if a filename substantially matches any of the other filenames in the identifier document. | 2011-02-24 |
20110047418 | SYSTEMS AND METHODS FOR USING RULE-BASED FAULT DETECTION IN A BUILDING MANAGEMENT SYSTEM - A controller for a building management system includes a system of rules for detecting faults in the building management system. The rules include content conditions and trigger conditions. The content conditions are not checked until one or more of the trigger conditions are met. A rule-based fault detection engine may be implemented by a low level building equipment controller. One or more thresholds for a rule may be automatically or manually adjusted. | 2011-02-24 |
20110047419 | Secure Method for Reconstructing a Reference Measurement of a Confidential Datum on the Basis of a Noisy Measurement of this Datum, Notably for the Generation of Cryptographic Keys - The present invention relates to a secure method for reconstructing a reference measurement of a confidential datum on the basis of a noisy measurement of this datum. The method proposes a phase of enrolling a reference datum w having n digits, comprising at least the following steps:
| 2011-02-24 |
20110047420 | METHOD AND SYSTEM FOR TESTING CHIPS - A chip operating method is provided which includes enabling a transmission mechanism or a receiving mechanism of the chip while normally operating the chip. The method further includes enabling both of the transmission mechanism and the receiving mechanism of the chip while testing the chip. | 2011-02-24 |
20110047421 | NAND FLASH-BASED STORAGE DEVICE WITH BUILT-IN TEST-AHEAD FOR FAILURE ANTICIPATION - A test-ahead feature for non-volatile memory-based mass storage devices to anticipate device failure. The test-ahead feature includes a method performed with a solid-state mass storage device having a controller, a cache memory, and at least one non-volatile memory device. At least a first block is reserved on the at least one non-volatile memory device as a wear-indicator block and a plurality of second blocks are used for data storage. Information is stored corresponding to the number of write and erase cycles encountered by the second blocks during usage of the mass storage device, and the information is accessed to perform wear leveling among the second blocks. The wear-indicator blocks are subjected to an offset number of write and erase cycles in excess of the number of write and erase cycles encountered by the second blocks, after which an integrity check of the first block is performed. | 2011-02-24 |
20110047422 | NON-VOLATILE MEMORY CELL READ FAILURE REDUCTION - The present disclosure includes various method, device, and system embodiments for reducing non-volatile memory cell read failures. One such method embodiment includes performing a first read operation, using an initial read potential, to determine a state of a selected memory cell in a string of non-volatile memory cells. This method includes determining whether the state of the selected memory cell is an incorrect state by performing a first check using a data checking technique, and if the incorrect state is determined, performing a number of subsequent read operations using read potentials stepped to a higher and a lower read potential to a particular count of read operations. | 2011-02-24 |
20110047423 | Integrated Circuit Including a Programmable Logic Analyzer with Enhanced Analyzing and Debugging Capabilities and a Method Therefor - An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile. | 2011-02-24 |
20110047424 | INTEGRATED CIRCUIT INCLUDING A PROGRAMMABLE LOGIC ANALYZER WITH ENHANCED ANALYZING AND DEBUGGING CAPABILITES AND A METHOD THEREFOR - An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile. | 2011-02-24 |
20110047425 | On-Chip Logic To Log Failures During Production Testing And Enable Debugging For Failure Diagnosis - On-chip logic includes a shadow register cross-coupled with a multiple input shift/signature register (MISR). The shadow register facilitates debugging by shifting out a test signature while resetting the MISR with a fault-free signature. The on-chip logic may further include comparator circuitry to produce an output signal by comparing the test signature with the fault-free signature or by first compressing the test signature and then comparing the compressed test signature with the compressed fault-free signature. | 2011-02-24 |
20110047426 | METHOD AND APPARATUS FOR LOW-PIN-COUNT SCAN COMPRESSION - A low-pin-count scan compression method and apparatus for reducing test data volume and test application time in a scan-based integrated circuit. The scan-based integrated circuit contains one or more scan chains, each scan chain comprising one or more scan cells coupled in series. The method and apparatus includes a programmable pipelined decompressor comprising one or more shift registers, a combinational logic network, and an optional scan connector. The programmable pipelined decompressor decompresses a compressed scan pattern on its compressed scan inputs and drives the generated decompressed scan pattern at the output of the programmable pipelined decompressor to the scan data inputs of the scan-based integrated circuit. Any input constraints imposed by said_combinational logic network are incorporated into an automatic test pattern generation (ATPG) program for generating the compressed scan pattern for one or more selected faults in one-step. | 2011-02-24 |
20110047427 | Integrated Circuit Including a Programmable Logic Analyzer with Enhanced Analyzing and Debugging Capabilities and a Method Therefor - An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment, an integrated circuit includes a logic analyzer having a first input receiving a plurality of signals and an output for providing an indication of a detection, by the logic analyzer, of at least one trigger event; and a built in self test block having a first input for receiving one or more of the signals appearing at the first input of the logic analyzer, a second input coupled to the output of the logic analyzer for selectively enabling the BIST block, the BIST block generating and maintaining a signature based upon the first and second inputs thereof. | 2011-02-24 |
20110047428 | ON-DEVICE CONSTRAINED RANDOM VERIFICATION FOR DEVICE DEVELOPMENT - A method of functionally verifying a device under test having at least one processor and at least one memory is disclosed. The method includes creating verification data for the device under test using a constrained random verification data creation process executed on the at least one processor. The verification data includes input data and expected output data. The method further includes storing the verification data in the at least one memory. The method further includes processing the input data with the at least one processor to produce actual output data. The method further includes comparing the actual output data to the expected output data. When the actual output data does not equal the expected output data, the method further includes storing at least one inconsistency between the actual output data and the expected output data. | 2011-02-24 |
20110047429 | METHOD AND APPARATUS FOR PROVIDING IMPLICIT NEGATIVE ACKNOWLEDGEMENT - An approach is provided for utilizing implicit negative acknowledgement. A determination is made that a user equipment is out of synchronization (e.g., with respect to the uplink). A control signal specifying timing alignment information is generated for transmission to the user equipment. An implicit negative acknowledgement corresponding to retransmission of data is declared if an acknowledgement is not received within a predetermined time interval. | 2011-02-24 |
20110047430 | IMPROVED HARQ PROCESS MANAGEMENT - The invention relates to a method for receiving data units when using one HARQ process of an HARQ protocol. The memory associated to the HARQ process is divided into several sub-areas, which are addressable by an identifier. Then, when data is received, same is stored in one of the sub-areas. By providing more than one sub-area for one HARQ process, it is possible to actually use one HARQ process for two (or more) different received data units, being from the same data flow or from a different data flow. The actual sub-area of the HARQ process for storing data units can be either freely selected at the receiving end or is indicated by an identifier associated with the data. Furthermore, persistent scheduled data is transmitted in units, scheduled at fixed time intervals. Thus, a control signaling field, usually used for indicating new units, can be used to store the identifier. | 2011-02-24 |
20110047431 | Verification device, verification method, and verification program - A verification device includes a data verifying unit that verifies whether data in a packet has an error using a first or a second verification mode, a packet generating unit that generates a packet in accordance with a first packet generation mode or a second packet generation mode respectively corresponding to the first and the second verification modes, a failure monitoring unit that monitors a failure of a transmission line that requires a switching of the verification mode, a switching packet transmitting unit that transmits to a destination device, a switching packet for informing the switching of the verification mode used by the data verifying unit when the failure monitoring unit detects a failure or a removal of a failure, a generation mode switching unit that switches the generation mode, and a verification mode switching unit that switches the verification mode to the one informed by the switching packet. | 2011-02-24 |
20110047432 | APPARATUS AND METHOD FOR CODING IN COMMUNICATION SYSTEM - Disclosed is a method and apparatus for coding in a communication system. The coding method includes generating an information codeword vector from an information vector, generating a first vector in the information vector from an information part of a parity check matrix, generating a first parity codeword vector by performing an exclusive OR operation of the first vector and a second vector corresponding to a cyclically shifted version of the first vector, and generating a second parity codeword vector by performing an exclusive OR operation of the first vector, the first parity codeword vector, and a third vector. The third vector is a cyclically shifted version of a vector resulting from the exclusive OR operation of the first vector, the first parity codeword vector, and a fed-back third vector. | 2011-02-24 |
20110047433 | SYSTEM AND METHOD FOR STRUCTURED LDPC CODE FAMILY WITH FIXED CODE LENGTH AND NO PUNCTURING - A family of low density parity check (LDPC) codes is generated based on a mother code having a highest code rate. The low density parity check (LDPC) codes include a codeword size of at least 1344. The LDPC codes also include a plurality of parity bits in a lower triangular form. The mother code is constructed by: selecting m number of rows and n number of columns; setting maximum column weights and row weights; designing a protograph matrix based on the set column weights and row weights and selected m and n; and selecting circulant blocks based on the protograph matrix. | 2011-02-24 |
20110047434 | WIRELESS COMMUNICATION OF TURBO CODED ATSC M/H DATA WITH TIME DIVERSITY - In an ATSC M/H wireless broadcast system, data for transmission is turbo encoded into turbo-encoded data blocks. The turbo-coded data blocks are processed for transmission by scheduling a plurality of portions of the block for transmission during respectively corresponding transmit intervals that are temporally separated from one another. The portions of the turbo-encoded blocks may then be transmitted during the respectively corresponding transmit intervals according to the schedule. The turbo-encoded blocks may be interleaved before portions of the blocks are scheduled for transmission. | 2011-02-24 |
20110047435 | METHOD AND SYSTEM FOR PROVIDING SHORT BLOCK LENGTH LOW DENSITY PARITY CHECK (LDPC) CODES - An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a short LDPC code by shortening longer mother codes. The short LDPC code has an outer Bose Chaudhuri Hocquenghem (BCH) code. According to another aspect, for an LDPC code with code rate of ⅗ utilizing 8-PSK (Phase Shift Keying) modulation, an interleaver provides for interleaving bits of the output LDPC code by serially writing data associated with the LDPC code column-wise into a table and reading the data row-wise from right to left. The above approach has particular application in digital video broadcast services over satellite. | 2011-02-24 |
20110047436 | Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors - Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform decoding of a turbo coded signal while still using a selected embodiment of an ARP (almost regular permutation) interleave. The desired number of decoding processors is selected, and very slight modification of an information block (thereby generating a virtual information block) is made to accommodate that virtual information block across all of the decoding processors during all decoding cycles except some dummy decoding cycles. In addition, contention-free memory mapping is provided between the decoding processors (e.g., a plurality of turbo decoders) and memory banks (e.g., a plurality of memories). | 2011-02-24 |
20110047437 | APPARATUS, SYSTEM, AND METHOD FOR GRACEFUL CACHE DEVICE DEGRADATION - An apparatus, system, and method are disclosed for graceful cache device degradation. The method may include determining the risk of data loss on the cache device, which may increase (as with Flash memory) with use and age. If the risk of data loss on the cache devices exceeds a threshold risk level, a modified cache policy may be implemented for the cache device to reduce the risk of data loss below the threshold level. This process may iterate until the cache device cannot guarantee performance sufficient to merit continued use of the cache device, and the cache device is logically removed from the system. The changes in cache policy and in the risk of data loss may be hidden from clients that make use of the cache device. The cache policies may transition, for example, in the following order: write back; write through; write around; read only; and bypass. | 2011-02-24 |
20110047438 | COMPUTER AND DATA STORAGE METHOD - A computer and a method for accessing data in the computer are provided. The computer comprises a mainboard chipset, a conventional hard disk, a flash memory and a controller. The controller is connected with the flash memory and selectively stores data to the hard disk or the flash memory according to the command from the mainboard chipset. The mainboard chipset is the south bridge chipset. The controller comprises a data interface unit in communication with the south bridge chipset, a controlling unit configured to receive the command through the data interface unit, and a flash memory accessing unit connected with the flash memory. The controlling unit controls the flash memory accessing unit to exchange the data with the south bridge chipset through the data interface unit according to the received command. | 2011-02-24 |
20110047439 | SOFT ERROR RATE PROTECTION FOR MEMORIES - Methods and apparatus for performing parity and/or ECC operations are disclosed. An example method includes determining that an opcode is being transmitted on a bus and determining if the transmitted opcode is a memory operation. In the event the transmitted opcode is a memory write operation, the example method includes calculating a parity bit for data associated with the opcode, writing the calculated parity bit to a parity table and writing the data to a memory. The example method also includes, in the event the transmitted opcode is the memory read operation, recovering data from a previously written memory, calculating a parity bit for the recovered data, recovering a previously stored parity bit for the recovered data, comparing the parity bit for the recovered data with the previously stored parity bit and, in the event the recovered data parity bit does not match the previously stored parity bit, providing an error notification. | 2011-02-24 |
20110047440 | Systems and Methods to Respond to Error Detection - Systems and methods to respond to error detection are provided. First data may be received at a first memory controller port in response to a read command issued from the first memory controller port. The read command may be issued as a second read command from a second memory controller port after determining that the first data contains a first uncorrectable error. Second data may be received at the second memory controller port in response to the second read command. A repair write command may be issued from the first memory controller port after determining that the second data does not contain any errors. The repair write command may initiate writing the second data from the first memory controller port. | 2011-02-24 |