08th week of 2012 patent applcation highlights part 35 |
Patent application number | Title | Published |
20120045832 | MULTIPOTENT NEURAL STEM CELLS - An isolated multipotent neural stem cells has a phenotype identified by expression of the protein β-tubulin IV and Olig2 and the absence of the proteins NG2, PLP, and GFAP. | 2012-02-23 |
20120045833 | Bioreactor, control system and control method thereof - A bioreactor includes a cylinder, a mandrel and a filter film. The cylinder includes two end walls and a circumferential wall interconnected with the both end walls; the two end walls and circumferential wall define together a reaction chamber. The mandrel is disposed between the two end walls. The mandrel has an inlet path and an outlet path provided on its both ends; the filter film wraps the mandrel to prevent passage of the first kind of substance while permit the passage of the second kind of substance; a gap is defined between the filter film and mandrel; at least one portion of the filter film is tied so as to divide the gap into multiple separate and isolated gap regions to prevent the second fluid from direct exiting from the outlet path through the gap. Also disclosed are control system and method for the bioreactor. | 2012-02-23 |
20120045834 | METHOD AND APPARATUS FOR MAINTAINING MICROCARRIER BEADS IN SUSPENSION - The invention relates to an impeller for growing adherent mammalian cells on microcarrier beads. In other aspects, the invention relates to methods of using the impeller and to bioreactors or cell separators comprising the impeller. | 2012-02-23 |
20120045835 | PORTABLE DEVICE BASED ON IMMOBILIZED CELLS FOR THE DETECTION OF ANALYTES - The present invention relates to a portable device for the detection of analytes, in particular toxic substances, comprising at least a whole-cell biosensor with cells immobilized onto a transparent and inert matrix that allows the maintenance of cell vitality. The matrix comprises a mixture of collagen and/or its enzyme degradation derivatives, a proteoglycan and a mixture of vinyl polymer and an optionally modified polysiloxane, and an orthosilicate. The biosensor can be a genetically modified cell that expresses luciferase as reporter gene. | 2012-02-23 |
20120045836 | Enzyme-Based Fed-Batch Technique In Liquid Cultures - The present invention is generally in the field of continuous and high-cell-density cultivation in laboratory- or large-scale liquid shaken cultures. More particularly it relates to a method of enzyme-based fed-batch (EnBase) for liquid microbial prokaryotic or eukaryotic cell cultivation having the possibility to manipulate the growth rate of the cultured organisms by a controlled enzymatic release of the growth-limiting substrate-monomer from substrate-polymers or substrate-oligomers. | 2012-02-23 |
20120045837 | PROCESS FOR PREPARING AN INDICATOR COMPOSITION - Indicator inks, indicators formed by printing or otherwise utilizing the inks and host products utilizing the indicators are disclosed. Reactivity-enhancing adjuvants stimulate enhanced thermal reactivity of diacetylenic or other indicator agents capable of responding to ambient thermal conditions with a visual change signaling an end point. The diacetylenic or other agents may be sensitive or relatively insensitive to ambient temperatures. Use of a reactivity-enhancing adjuvant provides a useful means for adapting the reactivities of indicator agents to the response characteristics of prospective host products, for example perishables such as vaccines or fresh fish and maturables such as fruit, cheese and wine. Some exemplary adjuvants include low-temperature polymerization initiators, for example methyl ethyl ketone peroxide and polymerization accelerators, for example cobalt compounds. Such initiators and accelerators can also be used in combination. | 2012-02-23 |
20120045838 | CUSTOMIZED MOLECULARLY IMPRINTED POLYMER (MIP) UNITS - A method of manufacturing at least one customized MIP unit including: (a) providing at least one MIP unit having a surface including at least one target binding site configured to resemble a target molecule and surface-bound chargeable groups; (b) contacting the MIP unit(s) from the step (a) with at least one template molecule in a first solvent allowing the template molecule(s) to bind to the MIP unit(s); (c) passivating the surface-bound chargeable groups on the MIP unit(s) by adding a passivating agent; and (d) removing the template molecule(s) by washing in a second solvent, wherein the passivating agent binds to the surface of the unit(s) through bonds which remain stable upon washing in the second solvent. | 2012-02-23 |
20120045839 | METHOD OF MARKING A PRODUCT, MARKED PRODUCT RESULTING THEREOF, AND METHOD OF IDENTIFYING SAME - A method and means for identifying the authenticity and the genuine nature of a solid or liquid bulk material, by incorporating a marking composition containing at least one trace ion into the said bulk material, whereby the total concentration of the incorporated trace ions in the market bulk material is chosen to be lower than the corresponding concentration of the same ions in standard sea water. The authenticity and the genuine nature or the adulteration level of the marked bulk material can be tested in-the-field using electrochemical sensors, and confirmed in the laboratory using a method such as atomic absorption spectroscopy, ion chromatography or mass spectrometry. | 2012-02-23 |
20120045840 | CHROMOPHORE AND POLYMER CAPABLE OF DETECTING THE PRESENCE OF VARIOUS NEUROTOXINS AND METHOD OF USE - Applicants have produced a chromophore and a polymer that are highly sensitive to the presence of various agents, including organophosphates, pesticides, neurotoxins, metal ions, some explosives, and biological toxins. The detection is accomplished by detecting a change in the fluorescence characteristics of the chromophore or polymer when in the presence of the agent to be detected. The chromophore and polymer may be incorporated into sensors of various types, and they are adaptable for potential field use in areas where detection of these types of agents is desired. | 2012-02-23 |
20120045841 | SYSTEM AND METHOD FOR GENERATION OF AUTOMATED DENATURATION GRAPHS - A system and method for creating a plurality of denaturation curves is disclosed. In accordance with certain embodiments, one variable, such as salt content, pH or another parameter, is varied to create a plurality of different buffer solutions. Each is then used to create a denaturation graph. The plurality of denaturation graphs allows analysis of the effect of that variable on protein stability. | 2012-02-23 |
20120045842 | ANALYSIS SYSTEM WITH CODING RECOGNITION - An analysis system for detecting at least one analyte in a sample is proposed, in particular for detecting glucose in a bodily fluid. The analysis system is designed to detect the analyte using at least one test element. The test element has at least one analysis zone for detecting the analyte. The test element furthermore comprises at least one coding with at least one test element specific item of information and/or at least one position specific item of information. The analysis system comprises a detector and furthermore at least one transfer device which is designed to afford the detector the possibility of acquiring the analysis zone in at least a first position and to afford the detector the possibility of acquiring the coding in at least a second position which differs from the first position. | 2012-02-23 |
20120045843 | TEST ELEMENT FOR DETERMINING A BODY FLUID AND MEASUREMENT METHOD - A test element for determining a body fluid, in particular for determining the blood glucose level, comprises a detection region which is charged with a reagent sensitive to the body fluid. A function element is arranged in and/or adjacent to the detection region for detecting at least one status parameter for the detection region, wherein said functional element can be evaluated by means of a status measurement. A method for measuring the test element is also disclosed. | 2012-02-23 |
20120045844 | METHODS AND APPARATUS FOR MEASURING ANALYTES USING LARGE SCALE FET ARRAYS - Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis. | 2012-02-23 |
20120045845 | SYSTEM AND METHOD FOR CODING INFORMATION ON A BIOSENSOR TEST STRIP - The present invention provides a test strip for measuring a concentration of an analyte of interest in a biological fluid, wherein the test strip may be encoded with information that can be read by a test meter into which the test strip is inserted. | 2012-02-23 |
20120045846 | SYSTEM AND METHOD FOR pH FORMULATIONS - A system and method for creating a buffer solution having a desired pH value is disclosed. The method uses two known buffer solutions, each with predetermined pH values, and determines a mathematical relationship which defines the amount of each known buffer solution needed to create the buffer solution with the desired pH. This method can then be used to create one or more denaturation graphs, which demonstrate the stability of a protein at a given pH level. | 2012-02-23 |
20120045847 | ASSAY FOR ANALYTES USING MULTIPLE RECEPTORS - A method for determining an analyte in a sample suspected of containing the analyte comprises providing in combination a medium, the sample, and two or more different receptors. Each different receptor binds to at least two different epitopic sites. One of the epitopic sites is a common binding site and one of the epitopic sites is non-common binding site. The non-common epitopic sites are different for each different receptor. The receptors exhibit mono-molecular binding. The medium is incubated under conditions for binding of the receptors to the epitopic sites. The medium is examined for the presence and/or amount of complexes comprising the epitopic sites and the receptors. The presence and/or amount of the complexes indicate the presence and/or amount of the analyte in the sample. | 2012-02-23 |
20120045848 | PYRENYLOXYSULFONIC ACID FLUORESCENT AGENTS - The invention provides a novel class of reactive fluorescent agents that are based on a pyrene sulfonic acid nucleus. The agents are readily incorporated into conjugates with other species by reacting the reactive group with a group of complementary reactivity on the other species of the conjugate. Also provided are methods of using the compounds of the invention to detect and/or quantify an analyte in a sample. In an exemplary embodiment, the invention provides multi-color assays incorporating the compounds of the invention. | 2012-02-23 |
20120045849 | SYSTEM AND METHOD TO MEASURE DISSOCIATION CONSTANTS - A system and method for determining the dissociation constant for a particular ligand is disclosed. In accordance with certain embodiments, the method creates a chemical denaturation curve of a protein in the absence of the ligand. A particular point is selected from this curve, such as the point at which 90% of the protein is unfolded. The molarity of chemical denaturant is determined for this selected point. A one point test is then performed for the protein with a predetermined concentration of the particular ligand. The fraction of protein which is unfolded at this point is then used to determine the dissociation constant for the ligand. This constant is used to quickly determine whether a particular ligard is well suited to be considered a potential drug candidate against that protein target. | 2012-02-23 |
20120045850 | SILICA NANOPARTICLE EMBEDDING QUANTUM DOTS, PREPARATION METHOD THEREOF AND BIOSUBSTANCE LABELING AGENT BY USE THEREOF - Disclosed is a quantum dot-embedded silica nanoparticle having plural quantum dots embedded within the silica nanoparticle, wherein the number of quantum dots existing in a concentric area within 10% of a radius from a center of the silica nanoparticle accounts for 10 to 70% of the number of total quantum dots embedded in the silica nanoparticle. | 2012-02-23 |
20120045851 | LABELS, THEIR PRODUCTION PROCESS AND THEIR USES - Labels are disclosed capable of forming a covalent or non-covalent bond with a target molecule, particularly a biological molecule. The structure of these labels may consist of a dye covalently bound by one or more carbons on its chemical structure to one or more [FUNC] group(s), and optionally one or more [SOL] group(s). The structure of these labels allow selection of dyes from a wide variety of different excitation and emission wavelengths and allow easy functionalization of the dye without appreciably altering its spectral characteristics or its solubility characteristics. | 2012-02-23 |
20120045852 | AUTOTUNED SCREEN PRINTING PROCESS - Embodiments of the invention generally provide apparatus and methods of screen printing a pattern on a substrate. In one embodiment, a patterned layer is printed onto a surface of a substrate along with a plurality of alignment marks. The locations of the alignment marks are measured with respect to a feature of the substrate to determine the actual location of the patterned layer. The actual location is compared with the expected location to determine the positional error of the patterned layer placement on the substrate. This information is used to adjust the placement of a patterned layer onto subsequently processed substrates. | 2012-02-23 |
20120045853 | SER Testing for an IC Chip Using Hot Underfill - A method for detecting soft errors in an integrated circuit (IC) due to transient-particle emission, the IC comprising at least one chip and a substrate includes mixing an epoxy with a radioactive source to form a hot underfill (HUF); underfilling the chip with the HUF; sealing the underfilled chip; measuring a radioactivity of the HUF at an edge of the chip; measuring the radioactivity of the HUF on a test coupon; testing the IC for soft errors by determining a current radioactivity of the HUF at the time of testing based on the measured radioactivity; and after the expiration of a radioactive decay period of the radioactive source, using the IC in a computing device by a user. | 2012-02-23 |
20120045854 | INSPECTING METHOD, TEMPLATE MANUFACTURING METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURING METHOD, AND INSPECTING SYSTEM - According to one embodiment, a template for manufacturing a memory cell array comprising a relievable area and a redundant area replaceable with the relievable area is to be inspected. First, based on a defect position of a defect-detected template and position information on a relievable area, a decision is made as to whether the detected defect is positioned within the relievable area. A decision is made as to whether the number of defect-detected relievable areas exceeds the preset permissible number. When the detected defect is positioned outside the relievable area or when the number of defect-detected relievable areas exceeds the permissible number, a notification that the template has failed the inspection is output. | 2012-02-23 |
20120045855 | POSITION-SENSITIVE METROLOGY SYSTEM - A metrology system for analyzing a semiconductor device on a substrate can include a metrology sensor. | 2012-02-23 |
20120045856 | METHOD OF MANUFACTURING ORGANIC EL DEVICE - According to one embodiment, a method of manufacturing an organic EL device is disclosed. The method can arrange an adhesive agent of an ultraviolet curable type between a first substrate on which a plurality of light emitting parts are formed in a predetermined direction and a second substrate arranged to face the first substrate separately so as to surround the light emitting parts. Each of the light emitting parts comprises a plurality of organic EL elements. The method can form a substrate pair by exposing the adhesive agent to ultraviolet rays to bond the first substrate and the second substrate to each other with the adhesive agent. The method can place the substrate pair on a first holding member capable of holding an entire surface of the first substrate or the second substrate. The method can place the substrate pair on a second holding member after a predetermined period of time has passed, the second holding member being capable of holding the substrate pair with at least two supporting members positioned along the first substrate or the second substrate. The method can cut the substrate pair around the adhesive agent with each of the light emitting parts as a unit. | 2012-02-23 |
20120045857 | METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE - A method for manufacturing light emitting device is revealed. Firstly, provide a substrate. Then arrange a light emitting unit on the substrate. Next form at least one electrode and arrange at least one protective layer on the electrode. The protective layer is to prevent a phosphor layer following formed on the light emitting unit from covering the electrode. After forming the phosphor layer, flatten the phosphor layer and the protective layer. That means to remove part of the phosphor layer over the protective layer and the protective layer. Thus the electrode is not affected by the phosphor layer and conductivity of the electrode is improved to resolve phosphor thickness and uniformity problems of the light emitting device. Therefore, the thickness of the light emitting device with LED is effectively reduced and stability of white color temperature control is significantly improved. | 2012-02-23 |
20120045858 | CONTACT FOR A SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region. A p-electrode is disposed on a portion of the p-type region. The p-electrode includes a reflective first material in direct contact with a first portion of the p-type region and a second material in direct contact with a second portion of the p-type region adjacent to the first portion. The first material and second material are formed in planar layers of substantially the same thickness. | 2012-02-23 |
20120045859 | Color Filterless Display Device, Optical Element, and Manufacture - A method of forming liquid crystal cell for a color display device includes forming a liquid crystal layer and a prism structure between top and bottom substrates. Forming the prism structure includes forming a lens shaped die, coating a low refractive index resin on the lens shaped die, pasting the lens shaped die to the top substrate, and irradiating the coated low refractive index resin so as to set the low refractive index resin and form a low refractive index layer. The lens shaped die is removed from the low refractive index layer, a high refractive index resin is coated on the low refractive index layer by use of a planarizing die. The coated high refractive index resin is irradiated so as to set the high refractive index resin and form a high refractive index layer, and the planarizing die is removed from the high refractive index layer. | 2012-02-23 |
20120045860 | LIQUID CRYSTAL DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE - An objective is simplification of a manufacturing method of a liquid crystal display device or the like. In a manufacturing method of a thin film transistor, a stack in which a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked in this order is formed, and the first conductive film is exposed by first etching and a pattern of the second conductive film is formed by second etching. Further, after thin film transistors are formed, a color filter layer is formed so that unevenness caused by the thin film transistors or the like is relieved; thus, the level difference of the surface where the pixel electrode layer is formed is reduced. Alternatively, a color filter layer is selectively formed utilizing the unevenness caused by thin film transistors or the like. | 2012-02-23 |
20120045861 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is fixed to the upper surface of the element formation layer. The element formation layer is transformed through the support base material, and peeling is generated at an interface between the element formation layer and the release layer. Peeling is performed while the liquid is being supplied so that the element formation layer and the release layer which appear sequentially by peeling are wetted with the liquid such as pure water. Electric charge generated on the surfaces of the element formation layer and the release layer can be diffused by the liquid, and discharge by peeling electrification can be eliminated. | 2012-02-23 |
20120045862 | CO-DEPOSITION METHODS FOR THE FABRICATION OF ORGANIC OPTOELECTRONIC DEVICES - A method for fabricating an OLED by preparing phosphorescent metal complexes in situ is provided. In particular, the method simultaneously synthesizes and deposits copper (I) complexes in an organic light emitting device. Devices comprising such complexes may provide improved photoluminescent and electroluminescent properties. | 2012-02-23 |
20120045863 | MICROPLASMA GENERATOR AND METHODS THEREFOR - A low-temperature, atmospheric-pressure microplasma generator comprises at least one strip of metal on a dielectric substrate. A first end of the strip is connected to a ground plane and the second end of the strip is adjacent to a grounded electrode, with a gap being defined between the second end of the strip and the grounded electrode. High frequency power is supplied to the strip. The frequency is selected so that the length of the strip is an odd integer multiple of ¼ of the wavelength traveling on the strip. A microplasma forms in the gap between the second end of the strip and the grounded electrode due to electric fields in that region. A microplasma generator array comprises a plurality of strongly-coupled resonant strips in close proximity to one another. At least one of the strips has an input for high-frequency electrical power. The remaining strips resonate due to coupling from the at least one powered strip. The array can provide a continuous line or ring of plasma. The microplasma generator can be used to alter the surface of a substrate, such as by adding material (deposition), removal of material (etching), or modifying surface chemistry. | 2012-02-23 |
20120045864 | MULTILAYER FILM FORMATION METHOD AND FILM DEPOSITION APPARATUS USED WITH THE METHOD - A multilayer film formation method and film deposition apparatus that suppress fluctuations in thickness, stabilize product quality, and reduce costs. The method employs gas-phase chemical reaction to form a multilayer film having at least three layers using raw material gases of differing compositions. A film formation apparatus is provided having at least first and second film deposition portions along a transfer path of the substrate, and having a supply/recovery portion for the substrate at either end of the transfer path; continuously transferring the substrate along the transfer path at a first speed during a first transfer and film deposition to form a plurality of stacked layers including first and second layers; and continuously transferring the substrate along the transfer path at a second speed during a second transfer and film deposition to form a third layer having the third composition that differs from those of the first and second layers. | 2012-02-23 |
20120045865 | Doped Graphene Films With Reduced Sheet Resistance - Techniques for increasing conductivity of graphene films by chemical doping are provided. In one aspect, a method for increasing conductivity of a graphene film includes the following steps. The graphene film is formed from one or more graphene sheets. The graphene sheets are exposed to a solution having a one-electron oxidant configured to dope the graphene sheets to increase a conductivity thereof, thereby increasing the overall conductivity of the film. The graphene film can be formed prior to the graphene sheets being exposed to the one-electron oxidant solution. Alternatively, the graphene sheets can be exposed to the one-electron oxidant solution prior to the graphene film being formed. A method of fabricating a transparent electrode on a photovoltaic device from a graphene film is also provided. | 2012-02-23 |
20120045866 | METHOD OF FORMING AN ELECTRONIC DEVICE USING A SEPARATION TECHNIQUE - A method of forming an electronic device can include forming a patterned layer adjacent to a side of a substrate including a semiconductor material. The method can also include separating a semiconductor layer and the patterned layer from the substrate, wherein the semiconductor layer is a portion of the substrate. | 2012-02-23 |
20120045867 | ANTI-REFLECTIVE PHOTOVOLTAIC MODULE - An anti-reflective surface on a photovoltaic can reduce optical reflection. | 2012-02-23 |
20120045868 | SEMICONDUCTOR DEVICE CONTACTS - A method of fabrication of electrical contact structures on a semiconductor material is described comprising the steps of: depositing an oxide of a desired contact material by a chemical electroless process on a face of the semiconductor material; and reducing the oxide via a chemical electroless process to produce a contact of the desired contact material. A method of fabrication of a semiconductor device incorporating such electrical contact structures and a semiconductor device incorporating such electrical contact structures are also described. | 2012-02-23 |
20120045869 | FLIP CHIP BONDER HEAD FOR FORMING A UNIFORM FILLET - A low thermal conductivity material layer covers a peripheral portion of the bottom surface of the conductive plate of a chip bonder head. The center portion of the conductive plate is exposed or covered with another conductive plate laterally surrounded by the low thermal conductivity material layer. During bonding, the chip bonder head holds a first substrate upside down and heats the first substrate through the conductive plate. Heating of a fillet, i.e., the laterally extruding portion, of a pre-applied underfill material is reduced because the temperature at the exposed surfaces of the low thermal conductivity material layer is lower than the temperature at the bottom surface of the conductive plate. The longer curing time and the more uniform shape of the fillet in the bonded structure enhance the structural reliability of the bonded substrates. | 2012-02-23 |
20120045870 | Method of Manufacturing Leadless Integrated Circuit Packages Having Electrically Routed Contacts - A method of manufacturing a leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The IC chip, the electrical contacts, and a portion of the metal leadframe are covered with an encapsulation compound, with portions of the electrical contacts exposed on a bottom surface of the encapsulation compound. The electrical contacts of the IC package having metal traces connecting bonding areas on a top surface thereof and contact areas on a bottom surface thereof, wherein at least some of the bonding areas are laterally disposed from the contact areas connected thereto. | 2012-02-23 |
20120045871 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - Provided are a semiconductor package of a semiconductor chip, a semiconductor module, an electronic system, and methods of manufacturing the same. The method includes mounting a semiconductor chip on a package substrate, forming a molding member on the semiconductor chip, forming via holes penetrating the molding member to expose a portion of a top surface of the semiconductor chip, the via holes being arranged in a lattice shape in a plan view, and forming thermally conductive via plugs in the via holes. | 2012-02-23 |
20120045872 | Semiconductor Memory Device - Disclosed herein is a semiconductor memory device for reducing a junction resistance and increasing amount of current throughout the unit cell. A semiconductor memory device comprises plural unit cells, each coupled to contacts formed in different shape at both sides of a word line in a cell array. | 2012-02-23 |
20120045873 | Methods of Forming CMOS Transistors Using Tensile Stress Layers and Hydrogen Plasma Treatment - Methods of forming integrated circuit devices include forming a PMOS transistor having a SiGe channel region therein and then exposing at least a portion of the PMOS transistor to a hydrogen plasma. A tensile stress layer may be formed on the PMOS transistor. The exposing step may include exposing source and drain regions of the PMOS transistor to the hydrogen plasma. | 2012-02-23 |
20120045874 | CMOS INTEGRATION METHOD FOR OPTIMAL IO TRANSISTOR VT - Various embodiments provide methods for fabricating dual supply voltage CMOS devices with a desired I/O transistor threshold voltage. The dual supply voltage CMOS devices can be fabricated in a semiconductor substrate that includes isolated regions for a logic NMOS transistor, a logic PMOS transistor, an I/O NMOS transistor, and an I/O PMOS transistor. Specifically, the fabrication can first set and/or adjust the threshold voltage (V | 2012-02-23 |
20120045875 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: forming first to third gate electrodes in first to third regions, respectively; forming a first mask pattern covering the second region while exposing the first and third regions; forming p-type source drain extensions and p-type pocket regions by ion implantation using the first mask pattern as a mask; forming n-type source drain extensions by ion implantation using the first mask pattern as a mask; forming a second mask pattern covering the first and third regions while exposing the second region; and forming p-type pocket regions by implanting ions of indium into the silicon substrate with the second mask pattern being used as a mask. | 2012-02-23 |
20120045876 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - There is provided a technology capable of preventing the increase in threshold voltages of n channel type MISFETs and p channel type MISFETs in a semiconductor device including CMISFETs having high dielectric constant gate insulation films and metal gate electrodes. When a rare earth element or aluminum is introduced into a Hf-containing insulation film which is a high dielectric constant gate insulation film for the purpose of adjusting the threshold value of the CMISFET, a threshold adjustment layer including a lanthanum film scarcely containing oxygen, and a threshold adjustment layer including an aluminum film scarcely containing oxygen are formed over the Hf-containing insulation film in an nMIS formation region and a pMIS formation region, respectively. This prevents oxygen from being diffused from the threshold adjustment layers into the Hf-containing insulation film and the main surface of a semiconductor substrate. | 2012-02-23 |
20120045877 | FABRICATION METHOD OF POWER SEMICONDUCTOR STRUCTURE WITH REDUCED GATE IMPEDANCE - A fabrication method of a power semiconductor structure with reduced gate impedance is provided. Firstly, a polysilicon gate is formed in a substrate. Then, dopants are implanted into the substrate with the substrate being partially shielded by the polysilicon gate. Afterward, an isolation layer is formed to cover the polysilicon gate. Thereafter, a thermal drive-in process is carried out to form at least a body surrounding the polysilicon gate. Then, the isolation layer is removed to expose the polysilicon gate. Afterward, a metal layer is deposited on the dielectric layer and the polysilicon gate, and a self-aligned silicide layer is formed on the polysilicon gate by using a thermal process. | 2012-02-23 |
20120045878 | MANUFACTURE OF SEMICONDUCTOR DEVICE WITH STRESS STRUCTURE - A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers. | 2012-02-23 |
20120045879 | TUNNEL EFFECT TRANSISTORS BASED ON ELONGATE MONOCRYSTALLINE NANOSTRUCTURES HAVING A HETEROSTRUCTURE - Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents an elongate monocrystalline nanostructure-based TFET with a heterostructure made of a different semiconducting material (e.g. germanium (Ge)) is used. An elongate monocrystalline nanostructure made of a different semiconducting material is introduced which acts as source (or alternatively drain) region of the TFET. The introduction of the heterosection is such that the lattice mismatch between silicon and germanium does not result in a highly defective interface. A dynamic power reduction as well as a static power reduction can result, compared to conventional MOSFET configurations. Multiple layers of logic can therefore be envisioned with these elongate monocrystalline nanostructure Si/Ge TFETs resulting in ultra-high on-chip transistor densities. | 2012-02-23 |
20120045880 | METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer, a polysilicon layer, and a hard mask; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; and forming a conductive layer in the opening for forming a gate. | 2012-02-23 |
20120045881 | METHOD FOR FABRICATING AN INTEGRATED-PASSIVES DEVICE WITH A MIM CAPACITOR AND A HIGH-ACCURACY RESISTOR ON TOP - The present invention relates to a method for fabricating an electronic component, comprising fabricating, on a substrate ( | 2012-02-23 |
20120045882 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes: removing an insulating film on a semiconductor substrate by etching and subsequently oxidizing a surface of the semiconductor substrate by using a liquid oxidation agent without exposing this surface to an atmosphere, thereby forming a first insulating film containing an oxide of a constituent element of the semiconductor substrate on the surface of the semiconductor substrate; forming a second insulating film containing an aluminum oxide on the first insulating film; forming a third insulating film containing a rare earth oxide on the second insulating film; forming a high-k insulating film on the third insulating film; introducing nitrogen into the high-k insulating film to thereby make it a fourth insulating film; and conducting heat treatment to change the first through third insulating films into a insulating film made of a mixture containing aluminum, a rare earth element, the constituent element of the semiconductor substrate, and oxygen. | 2012-02-23 |
20120045883 | METHOD FOR MANUFACTURING SOI SUBSTRATE - An SOI substrate is manufactured by the following method. An insulating layer is formed on a semiconductor substrate; an embrittled region is formed in the semiconductor substrate on which the insulating layer is formed by irradiating the semiconductor substrate with ions; a base substrate is heated to reduce moisture content attaching to a surface of the base substrate, wherein the base substrate after the heating faces and is in contact with the semiconductor substrate in which the embrittled region is formed, so that the base substrate and the semiconductor substrate are bonded to each other; and the bonded base substrate and semiconductor substrate is heated to separate the semiconductor substrate along the embrittled region to form a semiconductor layer over the base substrate. In this manner, the SOI substrate in which bonding defects are be sufficiently reduced can be provided. | 2012-02-23 |
20120045884 | PROTECTIVE THIN FILMS FOR USE DURING FABRICATION OF SEMICONDUCTORS, MEMS, AND MICROSTRUCTURES - A method of protecting a substrate during fabrication of semiconductor, MEMS devices. The method includes application of a protective thin film which typically has a thickness ranging from 3 angstroms to about 1,000 angstroms, wherein precursor materials used to deposit the protective thin film are organic-based precursors which include at least one fluorine-comprising functional group at one end of a carbon back bone and at least one functional bonding group at the opposite end of a carbon backbone, and wherein the carbon backbone ranges in length from 4 carbons through about 12 carbons. In many applications at least a portion of the protective thin film is removed during fabrication of the devices. | 2012-02-23 |
20120045885 | METHOD FOR MAKING NANOWIRE ELEMENT - A method for making a nanowire element includes: providing an imprint mold including a first substrate and a conductive pattern-transferring layer, the pattern-transferring layer includes first conductive strips; electrifying the pattern-transferring layer with an alternating current; applying a nanowire-containing suspension on the pattern-transferring layer; reorienting the nanowires in the nanowire-containing suspension using a dielectrophoresis method, thereby the nanowires connected between two adjacent first conductive strips; providing a pattern-receiving body, the pattern-receiving body including a second substrate and a pattern-receiving layer; pressing the imprint mold onto the pattern-receiving body with the conductive pattern-transferring layer facing the pattern-receiving layer, thereby defining a patterned recess in the pattern-receiving layer and transferring the nanowires to the second substrate; forming a first conductive layer on the second substrate to obtain a conductive pattern layer, the conductive pattern layer including second conductive strips, the nanowires connecting two adjacent second conductive strips; and removing the pattern-receiving layer. | 2012-02-23 |
20120045886 | Methods for Infusing One or More Materials into Nano-Voids of Nanoporous or Nanostructured Materials - A method of forming composite nanostructures using one or more nanomaterials. The method provides a nanostructure material having a surface region and one or more nano void regions within a first thickness in the surface region. The method subjects the surface region of the nanostructure material with a fluid. An external energy is applied to the fluid and/or the nanostructure material to drive in a portion of the fluid into one or more of the void regions and cause the one or more nano void regions to be substantially filled with the fluid and free from air gaps. | 2012-02-23 |
20120045887 | COMPOSITIONS OF DOPED, CO-DOPED AND TRI-DOPED SEMICONDUCTOR MATERIALS - Semiconductor materials suitable for being used in radiation detectors are disclosed. A particular example of the semiconductor materials includes tellurium, cadmium, and zinc. Tellurium is in molar excess of cadmium and zinc. The example also includes aluminum having a concentration of about 10 to about 20,000 atomic parts per billion and erbium having a concentration of at least 10,000 atomic parts per billion. | 2012-02-23 |
20120045888 | MULTILAYER LOW REFLECTIVITY HARD MASK AND PROCESS THEREFOR - A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN). | 2012-02-23 |
20120045889 | INTEGRATING A FIRST CONTACT STRUCTURE IN A GATE LAST PROCESS - A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact. | 2012-02-23 |
20120045890 | Methods Of Forming Non-Volatile Memory Devices Including Dummy Word Lines - A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed. | 2012-02-23 |
20120045891 | Methods Of Forming Patterns, And Methods Of Forming Integrated Circuits - Some embodiments include methods of forming patterns in substrates by utilizing block copolymer assemblies as patterning materials. A block copolymer assembly may be formed over a substrate, with the assembly having first and second subunits arranged in a pattern of two or more domains. Metal may be selectively coupled to the first subunits relative to the second subunits to form a pattern of metal-containing regions and non-metal-containing regions. At least some of the block copolymer may be removed to form a patterned mask corresponding to the metal-containing regions. A pattern defined by the patterned mask may be transferred into the substrate with one or more etches. In some embodiments, the patterning may be utilized to form integrated circuitry, such as, for example, gatelines. | 2012-02-23 |
20120045892 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A gate insulating film is formed on a semiconductor substrate having a first region in which a first conductivity type transistor is formed and a second region in which a second conductivity type transistor is formed. Next, a metal film and a first metal nitride film are sequentially formed on the gate insulating film. Next, part of each of the metal film and the first metal nitride film that is located in the second region is removed, thereby exposing part of the gate insulating film that is located in the second region. Next, a second metal nitride film made of a same metal nitride as the first metal nitride film is formed on the part of the gate insulating film that is located in the second region. | 2012-02-23 |
20120045893 | METHOD OF MAKING INTERCONNECT STRUCTURE - One or more embodiments relate to a method of forming a semiconductor device having a substrate, comprising: providing a Si-containing layer; forming a barrier layer over the Si-containing layer, the barrier layer comprising a compound including a metallic element; forming a metallic nucleation_seed layer over the Si-containing layer, the nucleation_seed layer including the metallic element; and forming a metallic interconnect layer over the nucleation_seed layer, wherein the barrier layer and the nucleation_seed layer are formed without exposing the semiconductor device substrate to the ambient atmosphere. | 2012-02-23 |
20120045894 | Method for Manufacturing Display Device - When a mask layer is formed, a first liquid composition containing a mask-layer-forming material is applied on an outer side of a pattern that is desired to be formed (corresponding to a contour or an edge portion of a pattern) to form a first mask layer having a frame shape. A second liquid composition containing a mask-layer-forming material is applied so as to fill a space inside the first mask layer having a frame shape to form a second mask layer. The first mask layer and the second mask layer are formed to be in contact with each other, and the first mask layer is formed to surround the second mask layer. Therefore, the first mask layer and the second mask layer can be used as one continuous mask layer. | 2012-02-23 |
20120045895 | SEMICONDUCTOR PACKAGE HAVING THROUGH ELECTRODES THAT REDUCE LEAKAGE CURRENT AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package having through electrodes that exhibit a reduced leakage current and a method of making the same are presented. The stacked semiconductor package includes a semiconductor chip, through-holes, and a current leakage prevention layer. The semiconductor chip has opposing first and second surfaces. The through-holes pass entirely through the semiconductor chip and are exposed at the first and second surfaces. A polarized part is formed on at least one of the first and second surfaces of the semiconductor chip. The through-electrodes are disposed within the through-holes. The current leakage prevention layer covers the polarized part and exposes ends of the through-electrodes. | 2012-02-23 |
20120045896 | Methods Of Forming Openings And Methods Of Patterning A Material - Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines. | 2012-02-23 |
20120045897 | Wafer Electroless Plating System and Associated Methods - A dry-in/dry-out system is disclosed for wafer electroless plating. The system includes an upper zone for wafer ingress/egress and drying operations. Proximity heads are provided in the upper zone to perform the drying operations. The system also includes a lower zone for electroless plating operations. The lower zone includes an electroless plating apparatus that implements a wafer submersion by fluid upwelling method. The upper and lower zones of the system are enclosed by a dual-walled chamber, wherein the inner wall is a chemically inert plastic and the outer wall is a structural metal. The system interfaces with a fluid handling system which provides the necessary chemistry supply and control for the system. The system is ambient controlled. Also, the system interfaces with an ambient controlled managed transfer module (MTM). | 2012-02-23 |
20120045898 | Ru CAP METAL POST CLEANING METHOD AND CLEANING CHEMICAL - According to certain embodiments, Ru is removed from the surface of a semiconductor structure by contact with a cleaning solution comprising one or more selected from permanganate ion, orthoperiodic ion and hypochlorous ion, such that Ru is removed from surfaces of the semiconductor substrate where the presence of Ru is undesirable. In some embodiments, a semiconductor structure is formed or provided having at least one metalized layer formed over an underlying layering or semiconductor substrate. The metalized layer contains a dielectric material with one or more metal wires of copper-containing material formed in a trench and/or via in the dielectric material. A cap layer having Ru is formed on the surface of the copper-containing material forming the one or more metal wires. The semiconductor structure is contacted with the cleaning solution comprising one or more selected from permanganate ion, orthoperiodic ion and hypochlorous ion to remove a portion of the Ru present in the semiconductor structure. | 2012-02-23 |
20120045899 | PATTERN REVERSAL FILM FORMING COMPOSITION AND METHOD OF FORMING REVERSED PATTERN - There is provided to a pattern reversal film forming composition that is capable of forming a pattern reversal film which is not mixed with a resist pattern formed on a substrate, and that is only capable of forming a pattern reversal film advantageously covering the pattern, but also irrespective of whether the resist pattern is coarse or fine, capable of forming a planar film excellent in temporal stability on the pattern. A pattern reversal film forming composition including a polysiloxane, an additive and an organic solvent, characterized in that the polysiloxane is a product of a hydrolysis and/or condensation reaction of a silane compound containing a tetraalkoxysilane of Si(OR | 2012-02-23 |
20120045900 | COMPOSITION FOR RESIST UNDERLAYER FILM, PROCESS FOR FORMING RESIST UNDERLAYER FILM, PATTERNING PROCESS, AND FULLERENE DERIVATIVE - The invention provides a composition for a resist underlayer film, the composition for a resist underlayer film to form a resist underlayer film of a multilayer resist film used in lithography, wherein the composition comprises at least (A) a fullerene derivative that is a reaction product of a substance having a fullerene skeleton with a 1,3-diene compound derivative having an electron-withdrawing group and (B) an organic solvent. There can be a composition for a resist underlayer film for a multilayer resist film used in lithography, the composition giving a resist underlayer film having excellent high dry etching resistance, capable of suppressing wiggling during substrate etching with high effectiveness, and capable of avoiding a poisoning problem in upperlayer patterning that uses a chemical amplification resist; a process for forming a resist underlayer film; a patterning process; and a fullerene derivative. | 2012-02-23 |
20120045901 | METHOD OF FORMING A PATTERN STRUCTURE FOR A SEMICONDUCTOR DEVICE - In a method of forming a pattern structure, a cut-off portion of the node-separated line of a semiconductor device is formed by a double patterning process by using a connection portion of the sacrificial mask pattern and the mask pattern to thereby improve alignment margin. The alignment margin between the mask pattern and the sacrificial mask pattern is increased to an amount of the length of the connection portion of the sacrificial mask pattern. The lines adjacent to the node-separated line include a protrusion portion protruding toward the cut-off portion of the separated line. | 2012-02-23 |
20120045902 | SHOWERHEAD ELECTRODES AND SHOWERHEAD ELECTRODE ASSEMBLIES HAVING LOW-PARTICLE PERFORMANCE FOR SEMICONDUCTOR MATERIAL PROCESSING APPARATUSES - Showerhead electrodes for a semiconductor material processing apparatus are disclosed. An embodiment of the showerhead electrodes includes top and bottom electrodes bonded to each other. The top electrode includes one or more plenums. The bottom electrode includes a plasma-exposed bottom surface and a plurality of gas holes in fluid communication with the plenum. Showerhead electrode assemblies including a showerhead electrode flexibly suspended from a top plate are also disclosed. The showerhead electrode assemblies can be in fluid communication with temperature-control elements spatially separated from the showerhead electrode to control the showerhead electrode temperature. Methods of processing substrates in plasma processing chambers including the showerhead electrode assemblies are also disclosed. | 2012-02-23 |
20120045903 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE, AND SUBSTRATE PROCESSING APPARATUS - Provided is a method of forming a tantalum oxide-based film having good step coverage while controlling an oxygen concentration in the film. The method includes forming a tantalum nitride layer on a substrate by supplying a source gas including a tantalum and a nitriding agent into a process chamber wherein the substrate is accommodated under a condition where a chemical vapor deposition (CVD) reaction is caused; oxidizing the tantalum nitride layer by supplying an oxidizing agent into the process chamber under a condition where an oxidation reaction of the tantalum nitride layer by the oxidizing agent is unsaturated; and forming on the substrate a conductive tantalum oxynitride film wherein an oxygen is stoichiometrically insufficient with respect to the tantalum and a nitrogen by alternately repeating forming the tantalum nitride layer on the substrate and oxidizing the tantalum nitride layer a plurality of times. | 2012-02-23 |
20120045904 | METHODS FOR FORMING A HYDROGEN FREE SILICON CONTAINING DIELECTRIC FILM - Embodiments of the disclosure generally provide methods of forming a hydrogen free silicon containing layer in TFT devices. The hydrogen free silicon containing layer may be used as a passivation layer, a gate dielectric layer, an etch stop layer, or other suitable layers in TFT devices, photodiodes, semiconductor diode, light-emitting diode (LED), or organic light-emitting diode (OLED), or other suitable display applications. In one embodiment, a method for forming a hydrogen free silicon containing layer in a thin film transistor includes supplying a gas mixture comprising a hydrogen free silicon containing gas and a reacting gas into a plasma enhanced chemical vapor deposition chamber, wherein the hydrogen free silicon containing gas is selected from a group consisting of SiF | 2012-02-23 |
20120045905 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE AND SUBSTRATE PROCESSING APPARATUS - Provided is a method of manufacturing a semiconductor device. The method includes: loading a substrate into a process vessel; performing a process to form an film on the substrate by alternately repeating: (a) forming a layer containing an element on the substrate by supplying at least two types of source gases into the process vessel, each of the at least two types of source gases containing the element, and (b) changing the layer containing the element by supplying reaction gas into the process vessel, the reaction gas being different from the at least two types of source gases; and unloading the processed substrate from the process vessel. | 2012-02-23 |
20120045906 | Aircraft GPU connection method and apparatus - A GPU connection apparatus for an aircraft towing vehicle comprising a vehicle-mounted ground power unit (GPU). The GPU includes a GPU cable having a first end which is connected to the GPU and a second end which includes a GPU connector that is configured to be plugged into a GPU receptacle on an aircraft to be towed. The GPU connection apparatus includes an intermediate cable having a first end which comprises a cable plug and a second end which comprises a cable receptacle. The cable plug is configured to be plugged into the GPU receptacle. In addition, the cable receptacle is configured to receive the GPU connector. In use of the GPU connection apparatus, the cable plug is plugged into the GPU receptacle and the GPU connector is plugged into the cable receptacle to thereby electrically connect the aircraft to the GPU. | 2012-02-23 |
20120045907 | ELECTRICAL COMPONENT STRUCTURE - An electric component structure is provided with at least two electrical conductive parts, an insulator and a magnetic flux generating structure. The electrical conductive parts are arranged with an electric line of force existing between adjacent ones of the conductive parts. The insulator holds the conductive parts. The magnetic flux generating structure generates a magnetic flux with magnetic flux lines oriented in a direction different from a direction of the electric line of force existing between the adjacent ones of the conductive parts. | 2012-02-23 |
20120045908 | ELECTRICAL CONNECTOR HAVING METALLIC CAGE SHROUDING EMI FROM PASSIVE DEVICE FROM CPU - An electrical connector for electrically connecting a central processing unit (CPU) with a plurality of electronic components assembled thereunder and conductive pins surrounding the electronic components to a printed circuit board (PCB) comprises a base having a plurality of terminals received therein for contacting with the conductive pins of the CPU, a cover mounted on the base, an actuator actuating the cover sliding along the base and a shielding frame mounted on the base. The base has a first opening and a plurality of passageways surrounding the first opening for receiving the terminals. The cover has a second opening corresponding to the first opening. The shielding frame is tightly attached to the sidewalls of the first opening and received in the first and second openings to prevent terminals from electromagnetic interference (EMI) emitted from electronic components assembled under the CPU. | 2012-02-23 |
20120045909 | MULTILEVEL INTERCONNECTION SYSTEM - A male connection component ( | 2012-02-23 |
20120045910 | MOLDING METHOD OF PRINTED CIRCUIT BOARD ASSEMBLY - Disclosed is a printed circuit board assembly PBA on which a connector for electrical connection to an external connection element is mounted. Such an assembly may be formed with a molding method of a PBA which includes applying a polymer resin to the PBA to mold the PBA in order to offer stiffness thereto. The foregoing method of molding the PBA according to the present disclosure is a molding method of a PBA including a PCB and a connector mounted on the PCB to electrically connect the same to an external connection element. The method includes combining the connector with a connector cover, applying a resin to the PBA combined with the connector cover to execute molding of the PBA, and separating the connector cover from the molded PBA to expose the electrode terminal for an external connection element. | 2012-02-23 |
20120045911 | SOCKET CONNECTOR HAVING CARBON NANOTUBE CONTACTS FOR SIGNAL TRANSMISSION AND METALLIC CONTACTS FOR POWER TRANSIMISSION - A socket connector includes a housing having a base and a plurality of sidewalls extending upwardly from the base. The base and the sidewalls define a receiving cavity for receiving an electronic package. A plurality of carbon nanotube contacts for signal transmission and a plurality of metallic contacts for power transmission are mounted within the housing respectively. | 2012-02-23 |
20120045912 | Multi-Contact Connector System - A connector system for Behind-The-Ear (BTE) hearing devices provides a means to detachably connect a variety of accessories to a sound processor, including batteries, earhooks, telecoils, auxiliary microphones, FM receivers, and input jacks for miscellaneous devices. The present invention provides an efficient and economical sealing connection, eliminating the introduction of sweat, body fluid and other contaminants into the connection area, which otherwise would result in corrosion and eventually disable the connected device. A wiping contact formed by a configuration of cam contacts and a flex circuit with a configuration of corresponding contacts is combined with a rotational engagement mechanism to create a vibration-resistant high contact density connector that is moisture proof when engaged. | 2012-02-23 |
20120045913 | SYSTEMS AND METHODS FOR COUPLING INPUT/OUTPUT DEVICES - An input/output (I/O) device for an automation control system includes a base portion configured to communicatively connect the I/O device with at least one other I/O device, an I/O module physically and communicatively connected to the base portion and comprising I/O communication circuitry, a terminal block physically and communicatively connected to the base portion, and an ejection device configured to eject the I/O module or the terminal block from the base portion by pushing the I/O module or the terminal block out of engagement with the base portion when activated. | 2012-02-23 |
20120045914 | TRANSPORTABLE DEVICE - A transportable device includes a housing, a handle portion, a biasing portion, a locking portion, a lever portion, and a link portion. The housing has a power plug insertion opening into which a power plug is inserted. The handle portion can move between the inside and outside of the housing. The biasing portion biases the handle portion in the direction where the handle portion is moved to the outside of the housing. The locking portion locks the handle portion so that the handle portion does not move to the outside of the housing by a biasing force of the biasing portion. The lever portion moves in the insertion direction of the power plug when the power plug is inserted into the opening, while moving in the pull-out direction of the power plug when the power plug is pulled out. The link portion links the locking portion and the lever portion. | 2012-02-23 |
20120045915 | ELECTRICAL POWER CONTACTS AND CONNECTORS COMPRISING SAME - Electrical connectors and contacts for transmitting power are provided. One power contact embodiment includes a first plate that defines a first non-deflecting beam and a first deflectable beam, and a second plate that defines a second non-deflecting beam and a second deflectable beam. The first and second plates are positioned beside one another to form the power contact. | 2012-02-23 |
20120045916 | REPLACEABLE CONNECTION FOR PORTABLE ELECTRONIC DEVICES - Systems and methods electrically connect a first electronic device or electrical component, having a external electrical connector, to a circuit board of a second electronic device. A low-cost, user-installable connection system isolates mechanical stresses imposed on the external electrical connector to within the user-installable connection system, thereby preventing the mechanical stresses from reaching the circuit board in the second electronic device. If the connection becomes faulty, only the low-cost, user-installable connection system must be replaced. | 2012-02-23 |
20120045917 | ELECTRICAL WET CONNECTOR IN DOWNHOLE ENVIRONMENT - An electrical connection for use in boreholes or other remote environment has a a first connection assembly having a first ( | 2012-02-23 |
20120045918 | SUBCUTANEOUS DEVICE FOR ELECTRICAL PERCUTANEOUS CONNECTION - The invention concerns an electrical connection system for a percutaneous electrical connection between an electrical device ( | 2012-02-23 |
20120045919 | CONNECTOR - A connector is configured to be connected to a connecting object. The connector comprises a housing, an actuator, an upper contact and a lower contact. The actuator has a lift-up portion and is held by the housing so as to be pivotable between an open position and a close position. The upper contact and the lower contact are held by the housing. The connecting object is accommodated between the upper contact and the lower contact when the actuator is located at the open position. When the actuator is pivoted and located at the close position, the lift-up portion forces an end of the upper contact to move so that an opposite end of the upper contact presses the connection object downward. Then, the connection object forces an end of the lower contact to move so that an opposite end of the lower contact presses the connection object upward. | 2012-02-23 |
20120045920 | CABLE ASSEMBLY WITH A NEW INTERFACE - A cable assembly ( | 2012-02-23 |
20120045921 | SAFETY SOCKET - A safety socket has an insertion block, a base and a conducting unit. The insertion block has an inner housing and two support frames mounted in the inner housing. The base has an outer housing covered on the inner housing and two guide arms mounted in the outer housing. The conducting unit is mounted between the support arms and between the guide arms. When two blades of a plug are plugged in the insertion block and pushed inwardly, the conducting unit is rotated to electrically connect with the two blades. Each one of the guide arms and the two blades is held between the conducting unit and the corresponding support arm to keep the plug from being unplugged arbitrarily. When the insertion block is pushed again, the conducting unit is rotated and the plug can be easily unplugged. | 2012-02-23 |
20120045922 | FASTENING DEVICE FOR FASTENING A CONNECTOR PLUG TO A BASE HOUSING - A fastening device is described that is arranged on a plug assembly having a connector plug and a base housing, having a fastening element for fastening the connector plug to the base housing, the connector plug having a plug housing with a screw shaft. The fastening element has a first fastening region and a second fastening region, wherein the first fastening region of the fastening element can be fixed to the screw shaft of the plug housing, and the second fastening region of the fastening element can be fixed to an outer surface of the base housing. | 2012-02-23 |
20120045923 | LEVER TYPE ELECTRICAL CONNECTOR - A lever type electrical connector has a case. A connector terminal is provided in the case so as to be slidable in a first direction, and is operable to engage with a mating connector terminal by being moved in the first direction. A handle is connected with the connector terminal. A first lever is pivotably attached to the case, and is connected to the handle. The first lever is operable to be moved so as to move the handle in the first direction. A first lock arm is pivotably attached to the case. A first end of the first lock arm is operable to be come in contact with the mating connector terminal. A second end of the first lock arm opposite to the first end is operable to be disengaged from the handle when the first end is urged from the mating connector terminal. The second end is operable to be engaged with the handle so as to prevent the handle from moving in the first direction when the first end is not urged from the mating connector terminal. | 2012-02-23 |
20120045924 | FLEXIBLE BREAKAWAY CONNECTOR - A connector which has a flexible portion which allows the connector to bend in response to non-axial forces applied thereto. When off-axis forces are applied to the connector or a mating connector, the off-axis forces do not cause oblique loading on the connector or mating connector. | 2012-02-23 |
20120045925 | ELECTRONIC APPARATUS HAVING LIGHT-EMITTING POWER CONNECTOR - A light-emitting power connector is disclosed. The light-emitting power connector includes an insulating plug receiving portion, a shell, and a light emitting diode (LED). The insulating plug receiving portion includes a base from which a light penetrating part and a tongue section extend and a plurality of the conductive terminals. The shell is connected to the insulating plug receiving portion and located outside of the tongue section to define a socket between the shell and the tongue section. The LED is installed at a first predetermined position in the insulating plug receiving portion to ensure the shell and the light penetrating part are located within a viewing angle of the LED. | 2012-02-23 |
20120045926 | IDENTIFIABLE PLUG AND PLUG ASSEMBLY HAVING THE SAME - An identifiable plug and a plug assembly having the same are disclosed. The identifiable plug includes a power input port, a power output port, a storage unit, a signal transmission unit and a processing unit. The power output port is configured to insert into a plug of electronic equipment. The power input port is connected with the power output port. The processing unit is configured to transmit an identification information stored in the storage unit via the signal transmission unit. When the identifiable plug is assembled with an electric socket, the electric socket is capable to read the identification information. | 2012-02-23 |
20120045927 | Cable assembly for protection against undesired signals - A cable assembly for connecting an electronic device to another electronic device and/or to a signal source. The cable assembly comprises a first connector and a second connector and a plurality of conductors connected between the connectors. The first connector may comprise receptacles for receiving a circuit-interrupter that can open a circuit in the cable assembly when an undesired signal (e.g., a over-voltage signal or an over-current signal) is applied to the cable assembly. The circuit-interrupter may comprise a fuse, such as a non-resettable fuse or a resettable fuse. The first connector may be arranged for connection to an automobile and the second connector may be arranged for connection to an electronic device operable for diagnosing and/or servicing the automobile. | 2012-02-23 |
20120045928 | PHYSICAL LAYER MANAGEMENT FOR INTERCONNECT CONFIGURATIONS USING RFID CHIP TECHNOLOGY - An intelligent physical layer management system is provided that includes active electronic hardware, firmware, mechanical assemblies, cables, and software that guide, monitor, and report on the process of connecting and disconnecting patch cords plugs in an interconnect patching environment. RFID tag integrated chips are used to identify which switch port a patch cord is plugged into. The system is capable of monitoring patch cord connections to detect insertions or removals of patch cords or plugs. In addition, the system can map the patch field in interconnect configurations. | 2012-02-23 |
20120045929 | Pals compliant routing system - A PALS compliant routing system includes flexible fabric cabling routed through the webbing of a PALS grid. A first connector or device is coupled to the cabling. Other connectors coupled to the cabling subsystem include a retention mechanism configured to retain them in the channels of the PALS webbing. | 2012-02-23 |
20120045930 | CONNECTOR - Provided is a technique for reducing the depth of a connector. A connector for connecting an FFC to a substrate includes a plurality of signal contacts, a ground contact, and a housing. The signal contacts are arranged to come into contact with signal terminals of the FFC. The ground contact comes into contact with the ground terminal of the FFC. The housing holds the plurality of signal contacts and the ground contact. Assuming that the back surface of the housing in a direction in which the FFC is inserted into or removed from the connector is set as a reference, a first distance to a contact point of the ground contact with respect to the signal terminals is set to be substantially equal to a second distance to a contact point of the ground contact with respect to the ground terminal. | 2012-02-23 |
20120045931 | Connector isolator system - A connector isolator system, having a backstop spaced a fixed distance away from an interface surface; a printed circuit board (PCB) or other connector carrier member that is movable between the backstop and the interface surface, and further comprising one or more in-plane isolators; an electrical connector mounted on the connector carrier member in a position to pass through an aperture in the interface surface; and one or more biasing members arranged between the backstop and the connector carrier member for urging the connector carrier member toward the interface surface and the electrical connector through the aperture. | 2012-02-23 |